Multi-chip packaging structure and packaging method

Abstract

The present invention provides a multi-chip packaging structure and a packaging method. The multi-chip packaging structure includes: a packaging substrate, on which a first conductive wire is arranged; a first chip, which is disposed on the packaging substrate and is electrically connected to the packaging substrate through the first conductive wire; a TVC conversion board, which is disposed on the first chip and is electrically connected to the first chip, and a vertically penetrating TVC conductive via is arranged at a position near the edge of the TVC conversion board; a BCB dielectric film, which is coated on the upper surface of the TVC conversion board; a second chip, which is disposed above the BCB dielectric film and is electrically connected to the TVC conversion board; a third chip, which is disposed above the second chip and is electrically connected to the second chip. The present invention can reduce transmission loss and delay, ensure the integrity of signal transmission, and effectively improve the heat dissipation effect of the multi-chip package.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and particularly to a multi-chip packaging structure and a packaging method. Background Art

[0002] A multi-chip packaging structure refers to a package body that includes at least two chips (the types of chips are not limited and can be arbitrarily combined), and is widely used in various electronic devices, such as mobile phones, tablet computers, laptop computers, etc.; the multi-chip packaging structure plays an important role in modern electronic devices and continues to develop with the continuous progress of technology.

[0003] After retrieval, a Chinese patent with the publication number CN117766501A discloses a multi-chip packaging structure and its packaging method. Among them, the multi-chip packaging structure includes a lead frame, a first chip, a second chip, and a filling material. The lead frame includes a chip carrier and lead pins. The first chip is flip-chip mounted on the chip carrier, and the first chip is electrically connected to the lead pins. The second chip is face-up mounted on the top of the first chip, and the second chip is electrically connected to the lead pins. The filling material is filled between the first chip and the lead frame.

[0004] The above-mentioned multi-chip packaging structure and its packaging method reduce costs, improve versatility, and achieve high density. However, the above-mentioned multi-chip packaging is relatively difficult, and sufficient area and space are required to realize the mounting of stacked chips and wire bonding; moreover, the heat dissipation efficiency of the multi-chip packaging structure is not high, and during long-term use, the chips are easily damaged by temperature, seriously weakening the service life of the chips.

[0005] It should be noted that the information disclosed in the above background art section is only used to strengthen the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] The purpose of the present invention is to provide a multi-chip packaging structure and a packaging method, aiming to solve the technical problem of "relatively difficult multi-chip packaging and low heat dissipation efficiency" in the prior art.

[0007] To achieve the above purpose, an embodiment of the present invention provides a multi-chip packaging structure, which includes:

[0008] A packaging substrate, on which a first conductive wire is arranged;

[0009] A first chip, which is arranged on the packaging substrate, and the first chip is electrically connected to the packaging substrate through the first conductive wire;

[0010] TVC conversion board, the TVC conversion board is disposed on the first chip and electrically connected to the first chip, and a vertically penetrating TVC conductive via hole is provided at a position near the edge of the TVC conversion board;

[0011] BCB dielectric film, the BCB dielectric film is coated on the upper surface of the TVC conversion board;

[0012] Second chip, the second chip is disposed above the BCB dielectric film and electrically connected to the TVC conversion board;

[0013] Third chip, the third chip is disposed above the second chip and electrically connected to the second chip.

[0014] Optionally, an RDL re - wiring layer is formed on the top surface of the TVC conversion board, the BCB dielectric film is coated on the upper surface of the RDL re - wiring layer, and the RDL re - wiring layer is electrically connected to the TVC conductive via hole.

[0015] Optionally, a conductive connecting member is disposed in the TVC conductive via hole, a second conductive wire is connected to the conductive connecting member, and the second conductive wire is electrically connected to the package substrate through the conductive connecting member.

[0016] Optionally, a third conductive wire and a fourth conductive wire are further connected to the upper surface of the conductive connecting member, the second chip is electrically connected to the conductive connecting member through the third conductive wire, and the third chip is electrically connected to the conductive connecting member through the fourth conductive wire.

[0017] Optionally, the conductive connecting member is flush with or exposed from the TVC conversion board, and the cross - section of the conductive connecting member is in a T - shaped structure.

[0018] Optionally, the first chip is face - down mounted on the package substrate, and a filling material for fixing the TVC conversion board is provided between the first chip and the TVC conversion board.

[0019] Optionally, the multi - chip package structure further includes:

[0020] Plastic encapsulation layer, the plastic encapsulation layer is disposed above the package substrate and is used to plastic - encapsulate the first chip, the TVC conversion board, the second chip and the third chip.

[0021] An embodiment of the present invention further provides a multi - chip packaging method, and the multi - chip packaging method includes the following steps:

[0022] S10: Provide a package substrate, which has an upper surface and a lower surface of the package substrate arranged opposite to each other, and a first conductive wire is disposed on the package substrate;

[0023] S20: Mount the first chip face-down on the upper surface of the encapsulation substrate, and connect the first chip to the first conductive wire to achieve electrical connection with the encapsulation substrate;

[0024] S30: Open vertically penetrating TVC conductive through-holes at two positions near the edges of the TVC conversion board, mount the TVC conversion board on the side of the first chip away from the encapsulation substrate, and fill the TVC conductive through-holes with conductive connection components;

[0025] S40: Form an RDL redistribution layer on the surface of the TVC conversion board by patterned electroplating, and the RDL redistribution layer is electrically connected to the TVC conductive through-holes;

[0026] S50: Coat a BCB thin film on the surface of the RDL redistribution layer and perform complete curing in a high-temperature nitrogen atmosphere;

[0027] S60: Mount a second chip on the TVC conversion board, and the second chip is electrically connected to the conductive connection component through a third conductive wire;

[0028] S70: Mount a third chip on the second chip, and the third chip is electrically connected to the conductive connection component through a fourth conductive wire;

[0029] S80: Perform plastic encapsulation on two opposite sides of the encapsulation substrate to form a plastic encapsulation layer covering the first chip, the TVC conversion board, the second chip, and the third chip.

[0030] Optionally, in S20, mounting the first chip face-down on the upper surface of the encapsulation substrate includes:

[0031] Coat an adhesive layer on the bonding surface of the first chip;

[0032] Mount the first chip on the upper surface of the encapsulation substrate through the adhesive layer by chip bonding.

[0033] Optionally, in S30, fill the gap between the first chip and the TVC conversion board with a filling material, and heat and cure the filling material to fix the TVC conversion board on the upper surface of the first chip.

[0034] One or more of the above technical solutions in the multi-chip encapsulation structure and encapsulation method provided by the embodiments of the present invention have at least one of the following technical effects:

[0035] The multi-chip packaging structure and packaging method provided by the present invention. The TVC conversion board can be interconnected with the packaging substrate, and also shortens the distance of wire interconnection between the first chip, the second chip, and the third chip, reducing transmission loss and delay, and ensuring the integrity of signal transmission. Moreover, the first chip, the second chip, and the third chip are located on planes with different heights, thereby realizing three-dimensional packaging between multiple chips. And the surface of the TVC conversion board is coated with a BCB dielectric film, which can effectively improve the heat dissipation effect of the multi-chip package. Brief Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 It is a schematic structural diagram of the multi-chip packaging structure provided by the embodiment of the present invention;

[0038] Figure 2 It is one of the assembly schematic diagrams of the multi-chip packaging structure provided by the embodiment of the present invention;

[0039] Figure 3 It is the second assembly schematic diagram of the multi-chip packaging structure provided by the embodiment of the present invention;

[0040] Figure 4 It is a schematic flowchart of the multi-chip packaging method provided by the embodiment of the present invention.

[0041] Among them, the reference numerals in the drawings are as follows:

[0042] 10. Packaging substrate; 11. First conductive wire;

[0043] 20. First chip;

[0044] 30. TVC conversion board; 31. TVC conductive via; 32. RDL re-wiring layer; 33. Conductive connection; 330. Second conductive wire; 331. Third conductive wire; 332. Fourth conductive wire;

[0045] 40. BCB dielectric film;

[0046] 50. Second chip;

[0047] 60. Third chip;

[0048] 70. Filling material;

[0049] 80. Encapsulation layer. Detailed implementation manners

[0050] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the embodiments of the present invention, and should not be construed as a limitation to the present invention.

[0051] In the description of the embodiments of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0052] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise specifically defined.

[0053] In the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0054] In one embodiment of the present invention, as Figures 1-3 shown, a multi-chip package structure is provided. The multi-chip package structure includes a package substrate 10, a first chip 20, a TVC conversion board 30, a BCB dielectric film 40, a second chip 50, and a third chip 60.

[0055] Specifically, the encapsulation substrate 10 of the present invention has an upper surface and a lower surface of the encapsulation substrate 10 that are oppositely arranged, and the first conductive wire 11 is disposed on the encapsulation substrate 10. In an embodiment of the present invention, the encapsulation substrate 10 may be an organic substrate, an inorganic substrate, a ceramic substrate, a circuit board, a carrier board, a metal substrate, but is not limited thereto, and the present invention does not make specific limitations.

[0056] Specifically, the first chip 20 is disposed on the encapsulation substrate 10, and the first chip 20 is electrically connected to the encapsulation substrate 10 through the first conductive wire 11. In an embodiment of the present invention, the electrical connection manner between the first chip 20 and the encapsulation substrate 10 is not limited to being connected through the first conductive wire 11. Of course, in another embodiment of the present invention, the first chip 20 and the encapsulation substrate 10 may also be electrically connected by wire bonding. In addition, in other embodiments of the present invention, the first chip 20 may also be fixed to the encapsulation substrate 10 by using a die attach film (DAF).

[0057] Specifically, the TVC conversion board 30 is disposed on the first chip 20 and is electrically connected to the first chip 20. The TVC conversion board 30 is provided with a vertically penetrating TVC conductive via 31 near the edge position; in the present invention, the TVC conversion board 30 is a ceramic conversion board, and the TVC conductive via 31 may be laser drilled or drilled by a precision machine on the TVC conversion board 30. Through the TVC conductive via 31, while enabling the stacking of each chip, higher integration and smaller size can be achieved, making the stacked wiring of the chips denser, capable of withstanding high-power usage requirements, and meeting production needs.

[0058] Specifically, the BCB dielectric film 40 is coated on the upper surface of the TVC conversion board 30. By coating the BCB dielectric film 40 on the upper surface of the TVC conversion board 30, the BCB thin film made of the low-dielectric BCB dielectric film 40 can significantly reduce signal delay, reduce signal transmission loss, and ensure the integrity of signal transmission.

[0059] Specifically, the second chip 50 is disposed above the BCB dielectric film 40 and is electrically connected to the TVC conversion board 30. The second chip 50 and the conductive connection member 33 are electrically connected through the third conductive wire 331. Through the setting of the conductive connection member 33, vertical interconnection between the second chip 50 and the encapsulation substrate 10 can be achieved, thereby shortening the connection path.

[0060] Specifically, the third chip 60 is disposed above the second chip 50 and electrically connected to the second chip 50. The third chip 60 and the conductive connection member 33 are electrically connected through the fourth wire 332. By providing the conductive connection member 33, vertical interconnection between the third chip 60 and the package substrate 10 can be achieved, thereby shortening the connection path.

[0061] For the multi-chip package structure provided by the present invention, the TVC conversion board 30 can be interconnected with the package substrate 10, and also shorten the distance of wire interconnection between the first chip 20, the second chip 50 and the third chip 60, reduce the transmission loss and delay, and ensure the integrity of signal transmission; and enable the first chip 20, the second chip 50 and the third chip 60 to be on planes at different heights, thereby achieving three-dimensional packaging between multiple chips; and the surface of the TVC conversion board 30 is coated with a BCB dielectric film 40, and the BCB dielectric film 40 can effectively improve the heat dissipation effect of the multi-chip package.

[0062] It should be noted that the multi-chip package structure provided by the present invention is a three-layer chip. In other embodiments, the multi-chip package structure can also be a four-layer, five-layer, etc. chip. In the three-layer chip multi-chip package structure, the multi-chip package structure includes at least three chips. In this embodiment, three chips are provided. In other embodiments, there can also be four chips, five chips, and the combination of the number of chips of each chip can also be adjusted according to production requirements.

[0063] In an embodiment of the present invention, an RDL re-wiring layer 32 is formed on the top surface of the TVC conversion board. The BCB dielectric film 40 is coated on the upper surface of the RDL re-wiring layer 32, and the RDL re-wiring layer 32 is electrically connected to the TVC conductive via 31. By forming the RDL re-wiring layer 32 on the top surface of the TVC conversion board 30, signal transmission between the TVC conversion board 30 and the second chip 50 can be achieved. In the present invention, the RDL re-wiring layer 32 can be implemented by polyimide, or copper interconnection can be achieved by the damascene process, or aluminum interconnection can also be used. The above materials can reduce the cost of the product and have strong power supply capacity. And in a specific embodiment of the present invention, the RDL re-wiring layer 32 can be single-layer or multi-layer.

[0064] Furthermore, a conductive connection member 33 is provided inside the TVC conductive through-hole 31. A second conductive wire 330 is connected to the conductive connection member 33, and the second conductive wire 330 is electrically connected to the packaging substrate 10 through the conductive connection member 33. By using the conductive connection member 33, the connection between chips can be achieved, the wire bonding connection method can be avoided, and the conductive connection member 33 can shorten the transmission length and the length of the heat conduction path between the first chip 20, the second chip 50, and the third chip 60, reduce signal transmission delay, effectively reduce the parasitic inductance and resistance of the product, and reduce the adverse effects on high-speed signal transmission and timing. Moreover, in this embodiment, the heat dissipation capacity of the multi-chip package is improved by using the arrangement of the conductive connection member 33. In an embodiment of the present invention, the material of the conductive connection member 33 is, for example, gold, silver, tin, copper, or other alloy materials, but is not limited thereto.

[0065] Furthermore, a third conductive wire 331 and a fourth conductive wire 332 are also connected to the upper surface of the conductive connection member 33. The second chip 50 is electrically connected to the conductive connection member 33 through the third conductive wire 331, and the third chip 60 is electrically connected to the conductive connection member 33 through the fourth conductive wire 332. In this embodiment, by using the conductive connection member 33 to electrically connect the second chip 50 to the third conductive wire 331 and the third chip 60 to the fourth conductive wire 332, high-density connection can be achieved, the signal transmission speed can be increased, the signal attenuation can be reduced, and thus the performance of the multi-chip package structure can be improved.

[0066] In an embodiment of the present invention, the conductive connection member 33 is exposed outside the TVC conversion board 30, and the cross-section of the conductive connection member 33 is in a T-shaped structure. Of course, in other embodiments of the present invention, the conductive connection member 33 can be flush with the TVC conversion board 30. The present invention does not make specific limitations. The exposed setting of the conductive connection member 33 in this application is only for illustration and does not represent a limitation. That is, the conductive connection member 33 may not be exposed outside the TVC conversion board 30, and other connection structures can also be adopted, and the specific connection structure is set by those skilled in the art themselves. The present application does not make specific limitations as long as the requirements of the present application can be met.

[0067] Furthermore, a filling material 70 for fixing the TVC conversion board 30 is provided between the first chip 20 and the TVC conversion board 30. By providing the filling material 70 between the first chip 20 and the TVC conversion board 30, the TVC conversion board 30 is fixed on the first chip 20.

[0068] In actual application, the TVC conversion board 30 is placed on the first chip 20. Since there is a gap between the first chip 20 and the TVC conversion board 30, a filling material 70 is injected into the gap between the first chip 20 and the TVC conversion board 30, so as to fix the TVC conversion board 30 on the first chip 20.

[0069] Further, the multi-chip packaging structure further includes:

[0070] A plastic encapsulation layer 80, which is disposed above the packaging substrate 10 and is used to encapsulate the first chip 20, the TVC conversion board 30, the second chip 50, and the third chip 60. In this embodiment, the plastic encapsulation layer 80 is made of epoxy resin. In other embodiments, the plastic encapsulation layer 80 can also be made of phenolic resin. In this embodiment, the plastic encapsulation layer 80 includes a single layer of plastic encapsulation insulating layer. In other embodiments, the plastic encapsulation layer 80 can also be set to two layers of the plastic encapsulation layer 80 or three layers of the plastic encapsulation layer 80, that is, the plastic encapsulation layer 80 can be completed through multiple encapsulations.

[0071] In another embodiment, when the plastic encapsulation layer 80 is set to multiple layers, the chip models can be distinguished by setting multiple layers of plastic encapsulation materials. For example, the first layer is epoxy resin and the second layer is polyimide. This setting is for the first chip model; if the first layer is epoxy resin and the second layer is polyamide resin, this setting is for the second chip model. That is, the chip models are set by pre-setting different layers corresponding to different materials of the plastic encapsulation layer 80. This setting requires chip model identification when the chip is damaged and is applicable to scenarios where it is necessary to distinguish chip models and there is no other distinguishing method.

[0072] In another embodiment of the present invention, as Figure 4 shown, a multi-chip packaging method is further provided. The multi-chip packaging method includes the following steps:

[0073] S10: Provide a packaging substrate 10, which has a packaging substrate 10 upper surface and a packaging substrate 10 lower surface arranged oppositely, and the first conductive wire 11 is arranged on the packaging substrate 10;

[0074] S20: Mount the first chip 20 face up on the upper surface of the packaging substrate 10, and connect the first chip 20 to the first conductive wire 11 to achieve electrical connection with the packaging substrate 10.

[0075] Specifically, the first chip 20 of the present invention and the packaging substrate 10 can be connected not only through the first conductive wire 11. The first chip 20 and the packaging substrate 10 can also be electrically connected by wire bonding. In addition, a die attach film (DAF) can be used to fix the first chip 20 on the packaging substrate 10, and the first chip 20 is connected to the first conductive wire 11 to achieve electrical connection with the packaging substrate 10.

[0076] S30: Vertically penetrating TVC conductive vias 31 are formed at two positions near the edge of the TVC conversion board 30, the TVC conversion board 30 is mounted on the side of the first chip 20 away from the packaging substrate 10, and a conductive connecting member 33 is filled in the TVC conductive vias 31;

[0077] S40: An RDL redistribution layer 32 is formed on the surface of the TVC conversion board 30 by patterned electroplating, and the RDL redistribution layer 32 is electrically connected to the TVC conductive vias 31.

[0078] Specifically, by forming the RDL redistribution layer 32 on the top surface of the TVC conversion board, the electrical connection between the RDL redistribution layer 32 and the TVC conductive vias 31 enables signal transmission between the TVC conversion board 30 and the second chip 50.

[0079] S50: A BCB thin film is coated on the surface of the RDL redistribution layer 32 and completely cured in a high-temperature nitrogen atmosphere. The present invention utilizes the photosensitive characteristics of BCB to fabricate a BCB dielectric film, and then uses a thin film deposition process to fabricate a top layer thin film again. The BCB thin film fabricated using the low-dielectric BCB dielectric film 40 can significantly reduce signal delay, reduce signal transmission loss, and ensure the integrity of signal transmission; and the BCB dielectric film 40 can effectively improve the heat dissipation effect of the multi-chip package.

[0080] S60: A second chip 50 is mounted on the TVC conversion board 30, and the second chip 50 is electrically connected to the conductive connecting member 33 through a third conductive wire 331. Through the arrangement of the conductive connecting member 33, vertical interconnection between the second chip 50 and the packaging substrate 10 can be achieved, thereby shortening the connection path.

[0081] S70: A third chip 60 is mounted on the second chip 50, and the third chip 60 is electrically connected to the conductive connecting member 33 through a fourth conductive wire 332. Through the arrangement of the conductive connecting member 33, vertical interconnection between the third chip 60 and the packaging substrate 10 can be achieved, thereby shortening the connection path.

[0082] S80: Encapsulate on opposite sides of the encapsulation substrate 10 to form an encapsulation layer 80 covering the first chip 20, the TVC conversion board 30, the second chip 50, and the third chip 60.

[0083] Further, in S20, mounting the first chip 20 face up on the upper surface of the encapsulation substrate 10 includes:

[0084] Coat an adhesive layer on the bonding surface of the first chip 20;

[0085] Mount the first chip 20 on the upper surface of the encapsulation substrate 10 through the adhesive layer by chip bonding.

[0086] Further, in S30, fill the void between the first chip 20 and the TVC conversion board 30 with a filling material 70, and heat and cure the filling material 70 to fix the TVC conversion board 30 on the upper surface of the first chip 20.

[0087] In summary, for the multi-chip encapsulation structure and encapsulation method provided by the present invention, the TVC conversion board 30 can be interconnected with the encapsulation substrate 10, and also shortens the distance of wire interconnection between the first chip 20, the second chip 50, and the third chip 60, reduces transmission loss and delay, and ensures the integrity of signal transmission; and enables the first chip 20, the second chip 50, and the third chip 60 to be on planes at different heights, thereby achieving three-dimensional encapsulation between multiple chips; and a BCB dielectric film 40 is coated on the surface of the TVC conversion board 30, and the BCB dielectric film 40 can effectively improve the heat dissipation effect of the multi-chip encapsulation body.

[0088] In another embodiment of the present invention, in S80, the step of encapsulating on opposite sides of the encapsulation substrate includes: encapsulating on opposite sides of the encapsulation substrate with a preset encapsulation material according to a preset weight by a preset encapsulation control device.

[0089] Specifically, the preset weight is set in advance by those skilled in the art. Encapsulation is carried out by setting the preset weight, aiming to make the weight of each of the multi-chip packaging structures after plastic encapsulation consistent. In addition, after plastic encapsulation, the weight of each of the multi-chip packaging structures is measured. If the weights are inconsistent, the plastic encapsulation layer 80 is polished until the weights of each of the multi-chip packaging structures are the same. At this time, when the structures of each of the multi-chip packaging structures are the same, a preset packaging box is used to assemble the preset number of the multi-chip packaging structures according to the preset quantity to form a chip group. Among them, the weight of the preset packaging box is also constant, and the number of multi-chip packaging structures in a preset packaging box is also set and fixed in advance, that is, the preset quantity. Such a setting makes the weight of a chip group determined. Therefore, the chip types in the chip group are distinguished by different weights. That is, in this application scenario, it is applicable to chips that need to be kept confidential and is used in the scenario where the chip model cannot be etched on the multi-chip packaging structure. When the chip model is no longer marked, the manufacturing entity distinguishes the chip model by weight. That is, a chip group of a certain weight corresponds to a certain chip type, which satisfies the confidentiality of the multi-chip packaging structure and can also distinguish the types.

[0090] Based on the above structural design, there are two methods for distinguishing chip types, which are specifically as follows:

[0091] The first is to distinguish by weighing the weight of a single chip. This is applicable when the weighing entity has relatively precise weighing equipment, which is relatively limited. Therefore, there is a second distinguishing method, which is to distinguish by weighing the chip group. The advantage of such a distinction is that it can be distinguished without being limited to relatively precise weighing equipment.

[0092] Of course, not marking the chip model will have some impacts on the entity using the chip later. Therefore, the entity using the chip group later needs to be able to store different chips at a preset position and can use the method of weighing the chip group before use for identification. Of course, other methods can also be used to ensure that there is no confusion during use. The purpose is to achieve confidentiality of the chip model by not marking the chip model and not causing confusion during use. However, after being disassembled by other production entities after being applied to specific products, other production entities cannot distinguish the chip model, thereby realizing the function of chip confidentiality. In this way, the confidentiality of the chip model can be achieved at a relatively low cost. Even if 100% confidentiality cannot be achieved, low-cost confidentiality is also realized.

[0093] In this embodiment, the weights of other structures of the multi-chip package structure are defined to be the same. However, slight deviations may occur in actual production. Therefore, the above steps "if the weights are inconsistent, grind the plastic package layer 80 until the weights of each multi-chip package structure are the same" are required to compensate for the weights.

[0094] In another embodiment, in step S80, after the step of plastic encapsulation on opposite sides of the package substrate, the following steps are further included: etching a marking code on the plastic package layer 80, and the composition of the marking code is "first marking code - second marking code - third marking code"; wherein, the first marking code is a production time mark, specifically the production year, which is marked with numbers from 1 to 100. Among them, 1 represents production in 2001, 2 represents production in 2002, and so on. Among them, 2001 is not the company's establishment year and the production line output year of the company, but a randomly defined starting year. Considering that it is generally guessed that special time nodes such as the production line output year or the company's establishment year are used as the starting year, the starting year is randomly set to play a confidentiality role. The second marking code is the chip model, which is marked with numbers from 01 to 99. 01 represents one chip model, 02 represents another chip model, and so on up to 99. The corresponding chip models are custom-set, and the manufacturer can know the specific chip models by querying the pre-set corresponding relationship. The third marking code is used to represent the production person in charge, which is replaced by English characters. For example, A-Z correspond to different production persons in charge respectively, and the specific corresponding relationship is also pre-set and stored inside the production entity. Therefore, through the setting of "first marking code - second marking code - third marking code", chip model confidentiality different from the prior art is achieved by marking chip models.

[0095] Further, when it is necessary to identify the chip model and other information, the external image of the plastic package layer 80 is obtained, and then the marking code on the external image is identified, specifically identifying the first marking code - second marking code - third marking code, and then parsing the first marking code - second marking code - third marking code according to the pre-stored data, so as to obtain the specific information of the chip.

[0096] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A packaging method for a multi-chip packaging structure, characterized in that: The packaging method includes the following steps: S10: providing a packaging substrate, which has an upper surface and a lower surface of the packaging substrate opposite to each other, and a first conductive line is arranged on the packaging substrate; S20: Mounting the first chip upright on the upper surface of the package substrate, and connecting the first chip to the first conductive wire to achieve electrical connection with the package substrate; S30: vertically penetrating TVC conductive through holes are opened on both sides of the TVC conversion board near the edge, and the TVC conversion board is mounted on the side of the first chip away from the package substrate, and conductive connectors are filled in the TVC conductive through holes; S40: forming an RDL redistribution layer on the surface of the TVC conversion board by patterned electroplating, wherein the RDL redistribution layer is electrically connected to the TVC conductive through-hole; S50: Coat the BCB film on the surface of the RDL redistribution layer and fully cure it in a high-temperature nitrogen atmosphere; S60: Installing a second chip on the TVC conversion board, and electrically connecting the second chip to the conductive connection member via a third conductive line; S70: Mounting a third chip on the second chip, and electrically connecting the third chip to the conductive connecting member via a fourth conductive line; S80: performing plastic encapsulation on opposite sides of the package substrate to form a plastic encapsulation layer covering the first chip, the TVC conversion board, the second chip, and the third chip; In S80, the plastic sealing step includes: Plastic sealing is performed on opposite sides of the packaging substrate using a preset plastic sealing control device according to a preset weight of plastic sealing material; After plastic encapsulation, the weight of each multi-chip package structure is measured. If the weights are inconsistent, the plastic encapsulation layer is polished until the weights of each multi-chip package structure are the same; When the chip model is no longer marked, the manufacturing entity can distinguish the chip model by weight, which ensures the confidentiality of the multi-chip packaging structure while being able to distinguish the type.

2. The packaging method of the multi-chip packaging structure according to claim 1, wherein: In S20, mounting the first chip upright on the upper surface of the packaging substrate includes: coating an adhesive layer on the bonding surface of the first chip; The first chip is attached to the upper surface of the packaging substrate through the adhesive layer.

3. The packaging method of the multi-chip packaging structure according to claim 1, wherein: In S30 , a filling material is filled in the gap between the first chip and the TVC conversion plate, and the filling material is heated and cured to fix the TVC conversion plate to the upper surface of the first chip.

4. A multi-chip package structure prepared by the packaging method of the multi-chip package structure according to any one of claims 1 to 3, characterized in that: The multi-chip package structure includes: a packaging substrate, on which a first conductive line is arranged; a first chip, wherein the first chip is disposed on the packaging substrate and is electrically connected to the packaging substrate via the first conductive line; A TVC conversion board, the TVC conversion board is disposed on the first chip and electrically connected to the first chip, and the TVC conversion board is provided with a vertically penetrating TVC conductive through hole near an edge thereof; A BCB dielectric film, the BCB dielectric film is coated on the upper surface of the TVC conversion plate; a second chip disposed above the BCB dielectric film and electrically connected to the TVC conversion board; a third chip, the third chip being disposed above the second chip and electrically connected to the second chip; An RDL rewiring layer is formed on the top surface of the TVC conversion board, the BCB dielectric film is coated on the upper surface of the RDL rewiring layer, and the RDL rewiring layer is electrically connected to the TVC conductive through hole, and the RDL rewiring layer is used to realize signal transmission between the TVC conversion board and the second chip; A conductive connector is provided in the TVC conductive through hole, a second conductive wire is connected to the conductive connector, and the second conductive wire is electrically connected to the packaging substrate through the conductive connector; The upper surface of the conductive connection member is further connected with a third conductive line and a fourth conductive line. The second chip is electrically connected to the conductive connection member through the third conductive line, and the third chip is electrically connected to the conductive connection member through the fourth conductive line.

5. The multi-chip package structure according to claim 4, wherein: The conductive connecting member is flush with or exposed on the TVC conversion board, and the cross section of the conductive connecting member is a T-shaped structure.

6. The multi-chip package structure according to claim 4, wherein: The first chip is mounted on the packaging substrate, and a filling material for fixing the TVC conversion board is provided between the first chip and the TVC conversion board.

7. The multi-chip package structure according to claim 6, wherein: The multi-chip package structure also includes: A plastic encapsulation layer is provided above the packaging substrate and is used to plastic encapsulate the first chip, the TVC conversion board, the second chip, and the third chip.

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