Array substrate and display device

Abstract

The array substrate comprises a substrate body, a plurality of scanning lines arranged on the substrate body, at least one dummy wire and a scanning driving circuit. The scanning lines are located in the display area and extend in the first direction. The at least one dummy wire is located in the frame area and extends in the second direction. The scanning driving circuit is located in the frame area. At least one scanning line comprises a scanning connecting end extending to the frame area and an extending tail end, and the scanning connecting end is electrically connected with the scanning driving circuit. The at least one dummy wire is broken at the extending tail end of the at least one scanning line, so that the orthographic projection of the at least one dummy wire and the orthographic projection of the extending tail end of the at least one scanning line on the substrate are not overlapped.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Touch and Display Driver Integration (TDDI) products have gradually become the mainstream touch technology due to their advantages of lightness, high integration and high performance. In the field of mobile and touch display products, TDDI technology has been basically adopted. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide an array substrate and a display device.

[0005] On the one hand, an embodiment of the present disclosure provides an array substrate, comprising: a substrate, a plurality of scan lines arranged on the substrate, at least one dummy line and a scan drive circuit. The substrate comprises a display area and a frame area located around the display area. The plurality of scan lines are at least located in the display area and extend along a first direction. At least one dummy line is located in the frame area and extends along a second direction. The scan drive circuit is located in the frame area. At least one scan line comprises a scan connection end and an extension end extending to the frame area, and the scan connection end is electrically connected to the scan drive circuit. At least one dummy line is disconnected at the extension end of at least one scan line, so that the at least one dummy line does not overlap with the extension end of the at least one scan line in the orthographic projection of the substrate. The second direction intersects with the first direction.

[0006] In some exemplary embodiments, the at least one dummy routing line includes: a plurality of dummy routing segments arranged in sequence along the second direction, a first break being provided between adjacent dummy routing segments along the second direction, and a length of the first break along the second direction being greater than a length of an extended end of the at least one scan line along the second direction.

[0007] In some exemplary embodiments, the array substrate further includes: a first common voltage signal line and a second common voltage signal line located in the border area; the first common voltage signal line is electrically connected to the second common voltage signal line, the first common voltage signal line is located on a side of the second common voltage signal line away from the substrate, and the first common voltage signal line and the second common voltage signal line at least partially overlap in their positive projections on the substrate.

[0008] In some exemplary embodiments, at least one dummy routing segment of the at least one dummy routing line is electrically connected to at least one of the second common voltage signal line and the first common voltage signal line.

[0009] In some exemplary embodiments, the array substrate further comprises: a plurality of first connection lines located in the frame region, wherein the scan connection end of the scan line is electrically connected to the scan driving circuit through the first connection lines; and the first connection lines are located on a side of the scan line away from the substrate.

[0010] In some exemplary embodiments, the array substrate further comprises: a plurality of first connection electrodes located in the frame region, wherein the scan connection end of the scan line is electrically connected to the first connection line through the first connection electrode, and the first connection electrode is located on a side of the first connection line away from the substrate.

[0011] In some exemplary embodiments, the first connection electrode and the first common voltage signal line are in the same layer structure, the first common voltage signal line has a plurality of first hollow portions, and the orthographic projection of the first connection electrode on the substrate is located within the first hollow portions.

[0012] In some exemplary embodiments, the array substrate further comprises: a first voltage line located in the frame region, and a plurality of second connection lines. The first voltage line is located on a side of the first common voltage signal line and the second common voltage signal line away from the display region, and is located on a side of the scan drive circuit close to the display region. The first voltage line is electrically connected to the scan drive circuit through the second connection line, and the first voltage line is configured to provide a first voltage signal to the scan drive circuit.

[0013] In some exemplary embodiments, the frame area at least includes: a left frame area and a right frame area located on both sides of the display area along the first direction; the scan drive circuit includes: a first drive circuit located in the left frame area, and a second drive circuit located in the right frame area; the first drive circuit includes: a plurality of cascaded first drive units, and the second drive circuit includes: a plurality of cascaded second drive units. In the left frame area, the 2a-1 level first drive unit and the 2a level first drive unit of the first drive circuit are electrically connected to the first voltage line through the same second connection line. In the right frame area, the 2b-1 level second drive unit and the 2b level second drive unit of the second drive circuit are electrically connected to the first voltage line through the same second connection line; a and b are integers greater than 0.

[0014] In some exemplary embodiments, the array substrate further comprises: a plurality of second connection electrodes located in the border region, the first voltage line being electrically connected to the second connection line through the second connection electrodes; the second connection electrode being located on a side of the first voltage line and the second connection line away from the substrate, the second connection electrode and the first common voltage signal line being in a same layer structure. The edge of the first common voltage signal line away from the display region has a plurality of notches, at least one notch being configured to accommodate a second connection electrode, the orthographic projection of the notch on the substrate covering the orthographic projection of the second connection electrode on the substrate in the first direction.

[0015] In some exemplary embodiments, the plurality of notches and the extending ends of the plurality of scan lines are spaced apart along the second direction.

[0016] In some exemplary embodiments, the frame area includes at least a left frame area and a right frame area located at two sides of the display area along the first direction. The left frame area and the right frame area are each provided with at least one dummy trace.

[0017] In some exemplary embodiments, the border area includes at least: a left border area and a right border area located on both sides of the display area along the first direction; in the left border area or the right border area, the scanning connection ends and the extended ends of the multiple scanning lines are spaced apart along the second direction.

[0018] In some exemplary embodiments, the array substrate further comprises: a plurality of sub-pixels located in the display area, the plurality of sub-pixels being arranged in a plurality of rows, and each row of sub-pixels comprising a plurality of sub-pixels arranged along a first direction. The scan drive circuit comprises: a first drive circuit located in the left border area, and a second drive circuit located in the right border area. The scan connection end of at least one scan line extending to the left border area is electrically connected to the first drive circuit; the first drive circuit is configured to provide a data signal to the 2i-1th row of sub-pixels in the display area. The scan connection end of at least one scan line extending to the right border area is electrically connected to the second drive circuit; the second drive circuit is configured to provide a scan signal to the 2ith row of sub-pixels in the display area; i is an integer greater than 0.

[0019] In some exemplary embodiments, the frame area further includes: a lower frame area located on one side of the display area along the second direction. The array substrate further includes: a plurality of auxiliary scanning lines located in the lower frame area and extending along the first direction, a plurality of first auxiliary driving units located in the left frame area, and a plurality of second auxiliary driving units in the right frame area. The at least one auxiliary scanning line includes: an auxiliary scanning connection end extending to the left frame area and an auxiliary extension end extending to the right frame area; or, an auxiliary scanning connection end extending to the right frame area and an auxiliary extension end extending to the left frame area. The auxiliary scanning connection end of the at least one auxiliary scanning line is electrically connected to the first auxiliary driving unit or the second auxiliary driving unit. In the left frame area or the right frame area, the auxiliary scanning connection ends and the auxiliary extension ends of the plurality of auxiliary scanning lines are spaced apart along the second direction.

[0020] In some exemplary embodiments, the plurality of first auxiliary driving units are configured to provide a reset signal to the first driving circuit; and the plurality of second auxiliary driving units are configured to provide a reset signal to the second driving circuit.

[0021] In some exemplary embodiments, the at least one dummy wiring bypasses an extended end of the at least one scan line from a side away from the display area.

[0022] On the other hand, an embodiment of the present disclosure provides a display device, comprising the array substrate as described above.

[0023] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0025] Figure 1 is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0026] Figure 2 is a schematic diagram of a touch control structure of an array substrate of at least one embodiment of the present disclosure;

[0027] Figure 3 A schematic diagram of a partial structure of a display area of ​​an array substrate according to at least one embodiment of the present disclosure;

[0028] Figure 4 is a schematic diagram of a scan driving circuit according to at least one embodiment of the present disclosure;

[0029] Figure 5 for Figure 1Schematic diagram of local membrane layer in ;

[0030] Fig. 6A A partial plan view of the junction area between the display area and the right frame area of ​​at least one embodiment of the present disclosure;

[0031] Figure 6B It is a partial plan view of the right frame area of ​​at least one embodiment of the present disclosure;

[0032] Fig. 7A for Fig. 6A A schematic diagram of a local cross section along the Q-Q' direction;

[0033] Figure 7B for Fig. 6A A schematic diagram of a local cross section along the R-R' direction;

[0034] Fig. 8A for Fig. 6A A schematic plan view of the array substrate after the first conductive layer is formed;

[0035] Figure 8B for Figure 6B A schematic plan view of the array substrate after the first conductive layer is formed;

[0036] Fig. 9A for Fig. 6A A schematic plan view of an array substrate after a semiconductor layer is formed;

[0037] Fig. 9B for Figure 6B A schematic plan view of an array substrate after a semiconductor layer is formed;

[0038] Fig. 10A for Fig. 6A A schematic plan view of the array substrate after the second conductive layer is formed;

[0039] Fig. 10B for Figure 6B A schematic plan view of the array substrate after the second conductive layer is formed;

[0040] Fig.11A for Fig. 10A A schematic diagram of a second conductive layer in FIG.

[0041] Fig. 11B for Fig. 10B A schematic diagram of a second conductive layer in FIG.

[0042] Fig.12 for Fig. 6A A schematic plan view of the array substrate after the third insulating layer is formed;

[0043] Fig.13 for Fig. 6AA schematic plan view of the array substrate after the first transparent conductive layer is formed;

[0044] Fig.14A for Fig. 6A A schematic plan view of the array substrate after the fourth insulating layer is formed;

[0045] Fig. 14B for Figure 6B A schematic plan view of the array substrate after the fourth insulating layer is formed;

[0046] Fig.15A for Fig. 6A A schematic diagram of a second transparent conductive layer in FIG.

[0047] Fig. 15B for Figure 6B A schematic diagram of a second transparent conductive layer in FIG.

[0048] Fig.16 for Fig. 6A Schematic diagram of the local area in ;

[0049] Fig.17 is another schematic diagram of a scan driving circuit according to at least one embodiment of the present disclosure;

[0050] Fig.18 It is a schematic plan view of the lower right corner of the array substrate of at least one embodiment of the present disclosure;

[0051] Fig.19A for Fig.18 A schematic diagram of an array substrate after a first conductive layer is formed;

[0052] Fig.19B for Fig.18 A schematic diagram of an array substrate after a semiconductor layer is formed;

[0053] Fig.19C for Fig.18 A schematic diagram of an array substrate after a second conductive layer is formed;

[0054] Fig.19D for Fig.19C A schematic diagram of a second conductive layer in FIG.

[0055] Fig.19E for Fig.18 A schematic diagram of an array substrate after a fourth insulating layer is formed;

[0056] Fig.19F for Fig.18 A schematic diagram of a second transparent conductive layer in FIG.

[0057] Fig. 20 is another schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0058] Fig.21 for Fig. 20 Schematic diagram of local membrane layer;

[0059] Fig. 22 FIG. 4 is another schematic diagram of an array substrate according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0061] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0062] The ordinal numbers such as "first", "second", and "third" in the present disclosure are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in the present disclosure means a quantity of two or more than two.

[0063] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0064] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0065] In the present disclosure, a transistor refers to an element including at least three terminals: a gate (gate electrode), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0066] In the present disclosure, in order to distinguish the two poles of the transistor other than the gate electrode, one of the electrodes is called the first pole and the other electrode is called the second pole. The first pole can be a source electrode or a drain electrode, and the second pole can be a drain electrode or a source electrode. In addition, the gate of the transistor is called the control pole. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0067] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0068] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0069] The terms “about” and “substantially” in the present disclosure do not strictly define the limits, but allow for a range of process and measurement errors.

[0070] In some implementations, the array substrate may include: a plurality of scan lines extending along a first direction and a plurality of data lines extending along a second direction in a display area. The plurality of data lines and the plurality of scan lines may cross to form a plurality of sub-pixel areas. A dummy line may be provided in the border area of ​​the array substrate to ensure process uniformity. In the preparation process of the array substrate, there is electrostatic discharge (ESD), and the extended end of the scan line is not electrically connected, and electrostatic discharge will be performed at the extended end of the scan line. Since the scan line and the dummy line are located in different film layers and the extension directions of the two intersect, the static electricity released at the extended end of the scan line will break through the insulating layer between the scan line and the dummy line, causing a short circuit between the scan line and the dummy line. The short circuit between the scan line and the dummy line will affect the stability of the scan signal transmitted by the scan line. For example, the dummy line transmits a common voltage signal, and after the short circuit, the scan signal will be pulled down, causing the scan signal to be abnormal, resulting in poor functionality of horizontal stripes, thereby affecting the display effect.

[0071] The present embodiment provides an array substrate, comprising: a substrate, a plurality of scan lines, at least one dummy line and a scan drive circuit. The substrate comprises a display area and a frame area located around the display area. The plurality of scan lines are at least located in the display area and extend along a first direction. At least one dummy line is located in the frame area and extends along a second direction. The second direction intersects with the first direction, for example, the second direction may be perpendicular to the first direction. The scan drive circuit is located in the frame area. At least one scan line comprises a scan connection end and an extension end extending to the frame area, and the scan connection end is electrically connected to the scan drive circuit. At least one dummy line is disconnected at the extension end of at least one scan line, so that the at least one dummy line and the extension end of the at least one scan line do not overlap in the orthographic projection of the substrate.

[0072] The array substrate provided in this embodiment can avoid the dummy line from crossing the extended end of the scan line by setting the dummy line to be disconnected at the extended end of the scan line, thereby reducing the risk of short circuit between the scan line and the dummy line caused by electrostatic discharge at the extended end of the scan line, and further improving the functional display defects such as horizontal stripes.

[0073] In some exemplary embodiments, at least one dummy routing line may include: a plurality of dummy routing line segments arranged in sequence along the second direction, a first break is provided between adjacent dummy routing line segments in the second direction, and the length of the first break along the second direction may be greater than the length of the extended end of at least one scan line along the second direction. For example, the first break may be corresponding to the extended end of a scan line. In this example, by disconnecting the dummy routing line to form the first break, the dummy routing line may be prevented from crossing the extended end of the scan line.

[0074] In some exemplary embodiments, the array substrate may further include: a first common voltage signal line and a second common voltage signal line located in the border area. The first common voltage signal line is electrically connected to the second common voltage signal line, and the first common voltage signal line may be located on a side of the second common voltage signal line away from the substrate, and the first common voltage signal line and the second common voltage signal line at least partially overlap in their orthographic projections on the substrate. In some examples, at least one dummy routing segment of at least one dummy routing line is electrically connected to at least one of the second common voltage signal line and the first common voltage signal line. For example, at least one dummy routing segment of the dummy routing line may be electrically connected to the second common voltage signal line and the first common voltage signal line, or at least one dummy routing segment of the dummy routing line may be electrically connected to the first common voltage signal line, or at least one dummy routing segment of the dummy routing line may be electrically connected to the second common voltage signal line. In some examples, all dummy routing segments of the dummy routing may be electrically connected to the first common voltage signal line or to the second common voltage signal line; or, a portion of the dummy routing segments may be electrically connected to the first common voltage signal line, and another portion of the dummy routing segments may be electrically connected to the second common voltage signal line. This embodiment is not limited to this. This embodiment transmits a common voltage by setting a dummy routing to be electrically connected to the first common voltage signal line or the second common voltage signal line, thereby avoiding the floating connection of the dummy routing from affecting the surrounding structure.

[0075] The solution of this embodiment is illustrated below through multiple examples.

[0076] Figure 1 is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure. Figure 1 In the example, only the local structure of the display area and the frame area is briefly illustrated. Figure 1 As shown, the array substrate of this example may include: a display area AA and a frame area BB located around the display area AA. The frame area BB may surround the display area AA. In some examples, the display area AA may be a rectangle, and the frame area BB may be a rectangular ring. However, this embodiment is not limited to this. In other examples, the display area AA may be other shapes.

[0077] In some examples, such as Figure 1As shown, the frame area BB may include: a left frame area B1, a right frame area B2, an upper frame area B3 and a lower frame area B4. The left frame area B1 and the right frame area B2 may be located on both sides of the display area AA along the first direction X, and the upper frame area B3 and the lower frame area B4 may be located on both sides of the display area AA along the second direction Y. Wherein, the first direction X and the second direction Y intersect, for example, the first direction X may be perpendicular to the second direction Y. The left frame area B1 may be connected to the upper frame area B3 and the lower frame area B4, and the right frame area B2 may be connected to the upper frame area B3 and the lower frame area B4. The connected area of ​​the left frame area B1 and the upper frame area B3 may form an upper left corner, the connected area of ​​the right frame area B2 and the upper frame area B3 may form an upper right corner, the connected area of ​​the left frame area B1 and the lower frame area B4 may form a lower left corner, and the connected area of ​​the right frame area B2 and the lower frame area B4 may form a lower right corner.

[0078] In some examples, the left frame area B1 and the right frame area B2 may be provided with a scan driving circuit, and the lower frame area B4 may be provided with an integrated chip (eg, a TDDI chip).

[0079] In some examples, the display device including the array substrate may be a liquid crystal display device, for example, a touch display device with an embedded touch structure. For example, the display device may include: an array substrate, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. In some examples, the display device may be an advanced super dimensional field switch (ADS) type touch display device, or may be a high aperture ratio advanced super dimensional field switch (HADS) type touch display device. The array substrate may include pixel electrodes and common electrodes, and the pixel electrodes and the common electrodes may generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer. The opposing substrate may include a base substrate, a color filter layer, and a black matrix.

[0080] Figure 2 FIG. 1 is a schematic diagram of a touch control structure of an array substrate of at least one embodiment of the present disclosure. In some examples, the array substrate of this example may adopt self-capacitive touch control technology. Figure 2 As shown, the touch control structure of the array substrate may include: a plurality of touch control sensing blocks (as self-capacitance electrodes) 17 arranged in an array, and a plurality of touch control signal lines 16 electrically connected to the plurality of touch control sensing blocks 17 respectively. Figure 2The black dots in the middle represent electrical connections. The plurality of touch signal lines 16 may extend along the second direction Y and be arranged along the first direction X. Each touch signal line 16 may be electrically connected to a touch sensing block 17. In some examples, when a touch is performed, a touch object (e.g., a human finger) touches a display device including an array substrate, and the capacitance of the touch sensing block 17 at the touch point changes. The integrated chip may determine the touch position by detecting the change in the self-capacitance of the touch sensing block 17.

[0081] Figure 3 FIG. 1 is a schematic diagram of a partial structure of a display area of ​​an array substrate according to at least one embodiment of the present disclosure. Figure 1 and Figure 3 As shown, the array substrate of this example may at least include: a substrate and a plurality of pixel units disposed on the substrate and located in the display area AA, a plurality of touch signal lines 16, a plurality of data lines 12, and a plurality of scan lines 11. The plurality of data lines 12 may extend along the second direction Y and be arranged along the first direction X; the plurality of scan lines 11 may extend along the first direction X and be arranged in sequence along the second direction Y. The plurality of data lines 12 and the plurality of scan lines 11 may cross to form a plurality of sub-pixel regions. For example, the region defined by the intersection of adjacent data lines 12 and adjacent scan lines 11 may be a sub-pixel region. One sub-pixel may be provided in each sub-pixel region. At least one pixel unit may include three sub-pixels (for example, including a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3) arranged in sequence along the first direction X. The plurality of sub-pixels in the display area are arranged in a plurality of rows and a plurality of columns, a row of sub-pixels includes a plurality of sub-pixels arranged along the first direction X, and a column of sub-pixels includes a plurality of sub-pixels arranged along the second direction Y. For example, after being matched with the opposite substrate, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 can be configured to emit light of different colors.

[0082] In some examples, the sub-pixel area may include: an opening area and a non-opening area surrounding the opening area. In some examples, the non-opening area may be an area blocked by the black matrix of the opposing substrate, and the opening area may be an area not blocked by the black matrix. For example, adjacent scan lines 11 and data lines 12 may be located in the non-opening area. In some examples, the array substrate of this embodiment is used to realize a display function, and the opening area of ​​each sub-pixel area may be configured for display, and the non-opening area surrounds the opening area and does not display. However, this embodiment is not limited to this. In some examples, the array substrate may be used to realize other functions.

[0083] In some examples, such as Figure 3As shown, each sub-pixel may include: a switch transistor 14, a pixel electrode 13 and a common electrode located in the sub-pixel region. The switch transistor 14 may be located in a non-opening region of the sub-pixel region, for example, at the intersection of the data line 12 and the scan line 11. The pixel electrode 13 and the common electrode may be located at least in the opening region of the sub-pixel region. The common electrodes of multiple sub-pixels may be an integrated structure connected to each other.

[0084] In some examples, such as Figure 3 As shown, the switch transistor may be a thin film transistor (TFT). The switch transistor 14 may include: a control electrode, an active layer, a first electrode, and a second electrode. The control electrode of the switch transistor 14 may be electrically connected to the scan line 11, the first electrode may be electrically connected to the data line 12, and the second electrode may be electrically connected to the pixel electrode 13. Under the control of the scan line 11, the switch transistor 14 may provide the data signal transmitted by the data line 12 to the pixel electrode 13.

[0085] In some examples, such as Figure 3 As shown, a touch signal line 16 can be arranged in each pixel unit, and the position of each touch signal line 16 in the corresponding pixel unit can be the same. For example, the touch signal line 16 can be located on one side of the data line 12 connected to the first sub-pixel P1 of the corresponding pixel unit. A column of pixel units can be arranged between two adjacent touch signal lines 16. Three data lines 12 can be arranged between two adjacent touch signal lines 16, and the three data lines 12 can be respectively electrically connected to the switch transistors 14 of the three columns of sub-pixels. However, this embodiment is not limited to this. In other examples, two or three touch signal lines can be arranged in at least one pixel unit. For example, two touch signal lines can be located on the same side of the data line connected to the first sub-pixel of the corresponding pixel unit; or, three touch signal lines can be arranged in correspondence in at least one pixel unit, and the three data lines connected to the three sub-pixels of the pixel unit can be adjacent to the three touch signal lines one by one. In other words, multiple data lines and multiple touch signal lines can be arranged at intervals along the first direction.

[0086] In some examples, the common electrodes of the sub-pixels can be reused as touch sensing blocks. In the display stage, the common voltage is provided to the common electrodes through the touch signal line 16 to realize the display function; in the touch stage, the touch signal detected by the common electrode is transmitted by the touch signal line 16 to realize the touch function. The common electrodes of multiple sub-pixels can be connected to each other to form a touch sensing block. For example, the common electrodes isolated from each other in multiple pixel units can be connected to each other to form a touch sensing block.

[0087] Figure 4FIG. 1 is a schematic diagram of a scan driving circuit according to at least one embodiment of the present disclosure. Figure 1 and Figure 4 As shown, the array substrate may further include: a scan drive circuit located in the border area BB. The scan drive circuit may include: a first drive circuit 24a located in the left border area B1 and a second drive circuit 24b located in the right border area B2. The first drive circuit 24a may include: a plurality of first drive units 241, and the plurality of first drive units 241 may be a plurality of shift register circuits in a cascade relationship; the second drive circuit 24b may include a plurality of second drive units 242, and the plurality of second drive units 242 may be a plurality of shift register circuits in a cascade relationship. The plurality of first drive units 241 may be arranged sequentially in the left border area B1 along the second direction Y, and the plurality of second drive units 242 may be arranged sequentially in the right border area B2 along the second direction Y.

[0088] In some examples, such as Figure 1 and Figure 4 As shown, a first driving unit 241 can be configured to provide a scanning signal to a row of sub-pixels through a scanning line 11, for example, a scanning signal can be provided to the 2i-1th row of sub-pixels in the display area, and a second driving unit 242 can be configured to provide a scanning signal to a row of sub-pixels through a scanning line 11, for example, a scanning signal can be provided to the 2ith row of sub-pixels, wherein i is an integer greater than 0. In other words, the scanning signal of the odd-numbered row sub-pixels in the display area can be provided by the first driving circuit 24a, and the scanning signal of the even-numbered row sub-pixels can be provided by the second driving circuit 24b, thereby realizing a unilateral driving mode of odd-even row crossing. However, this embodiment is not limited to this. In other examples, the scanning signal of the odd-numbered row sub-pixels can be provided by the second driving circuit, and the scanning signal of the even-numbered row sub-pixels can be provided by the first driving circuit. The driving mode of odd-even row crossing in this example can reduce the number of driving units, which is conducive to achieving a narrow frame.

[0089] In some examples, such as Figure 4 As shown, the first driving circuit 24a includes a plurality of first driving units 241 that can be cascaded. For example, the first driving circuit 24a can include a first-stage first driving unit to an N-stage first driving unit, where N is an integer greater than 0. The output end of the a-stage first driving unit can provide an input signal to the a+2-stage first driving unit, and the output end of the a+2-stage first driving unit can provide a reset signal to the a-stage first driving unit; a is an integer greater than 0.

[0090] In some examples, each level of the first driving unit of the first driving circuit 24a can be configured to provide a scanning signal to a sub-pixel row with an odd number. For example, the first level of the first driving unit can be configured to provide a scanning signal to the first row of sub-pixels, the second level of the first driving unit can be configured to provide a scanning signal to the third row of sub-pixels, the third level of the first driving unit can be configured to provide a scanning signal to the fifth row of sub-pixels, the fourth level of the first driving unit can be configured to provide a scanning signal to the seventh row of sub-pixels, and so on.

[0091] In some examples, such as Figure 4 As shown, the plurality of second driving units 242 included in the second driving circuit 24b may be connected in cascade, for example, the second driving circuit 24b may include a first-stage second driving unit to an M-stage second driving unit, where M is an integer greater than 0. The output end of the b-stage second driving unit may provide an input signal to the b+2-stage second driving unit, and the output end of the b+2-stage second driving unit may provide a reset signal to the b-stage second driving unit; b is an integer greater than 0.

[0092] In some examples, each level of the second driving unit of the second driving circuit 24b can be configured to provide a scan signal to a sub-pixel row with an even number. For example, the first level of the second driving unit can be configured to provide a scan signal to the second row of sub-pixels, the second level of the second driving unit can be configured to provide a scan signal to the fourth row of sub-pixels, the third level of the second driving unit can be configured to provide a scan signal to the sixth row of sub-pixels, the fourth level of the second driving unit can be configured to provide a scan signal to the eighth row of sub-pixels, and so on. In some examples, the sum of N and M can be equal to the total number of rows of sub-pixels in the display area.

[0093] In some examples, each of the plurality of first drive units 241 and the plurality of second drive units 242 may include at least: a first control transistor, a second control transistor and a first capacitor. Among them, the control electrode of the first control transistor may be electrically connected to the reset signal line, the first electrode may be electrically connected to the first voltage line, and the second electrode may be electrically connected to the control electrode of the second control transistor. The second electrode of the second control transistor may be electrically connected to the output end of the drive unit. The first electrode of the first capacitor may be electrically connected to the control electrode of the second control transistor, and the second electrode of the first capacitor may be electrically connected to the output end of the drive unit. The connection point between the second electrode of the first control transistor, the first electrode of the first capacitor and the control electrode of the second control transistor may be referred to as a pull-up node PU. For example, taking the first control transistor and the second control transistor as N-type transistors, after the potential of the pull-up node PU is pulled down, the second control transistor cannot be turned on, and the output end of the drive unit stops outputting. The first voltage line may be configured to provide a low-level first voltage signal.

[0094] In some examples, such as Figure 4 As shown, the reset signal line connected to the a-th first driving unit of the first driving circuit 24a can be electrically connected to the output end of the a+2-th first driving unit. The reset signal line connected to the b-th second driving unit of the second driving circuit 24b can be electrically connected to the output end of the b+2-th second driving unit.

[0095] Figure 5 for Figure 1 Schematic diagram of local membrane layers in . In some examples, such as Figure 1 and Figure 5 As shown, the scan line 11 may include: a scan connection end 111 extending to the frame area BB and an extension end 112. Since the array substrate of this example adopts a single-sided driving mode of odd-even row crossing, the scan connection end 111 of the scan line 11 may extend to the left frame area B1 and be electrically connected to the first drive unit 241 of the first drive circuit, or may extend to the right frame area B2 and be electrically connected to the second drive unit 242 of the second drive circuit; the extension end 112 of the scan line 11 may extend to the left frame area B1 or the right frame area B2 as an independently set end. For example, the scan line 11 electrically connected to the sub-pixels in the 2i-1th row may include: a scan connection end 111 extending to the left border area B1 and an extension end 112 extending to the right border area B2, and the scan connection end 111 extending to the left border area B1 can be electrically connected to a first driving unit 241 of the first driving circuit; the scan line 11 electrically connected to the sub-pixels in the 2ith row may include: an extension end 112 extending to the left border area B1 and a scan connection end 111 extending to the right border area B2, and the scan connection end 111 extending to the right border area B2 can be electrically connected to a second driving unit 242 of the second driving circuit.

[0096] In some examples, such as Figure 1 and Figure 5 As shown, in the left frame area B1, the scan connection ends 111 and the extension ends 112 of the plurality of scan lines 11 may be arranged at intervals along the second direction Y. In the right frame area B2, the extension ends 112 and the scan connection ends 111 of the plurality of scan lines 11 may be arranged at intervals along the second direction Y. The arrangement of the scan lines in this example can realize a single-sided driving mode in which odd and even rows are crossed.

[0097] In some examples, such as Figure 1 and Figure 5As shown, the array substrate may further include: a plurality of first connection lines (for example, including a plurality of first connection lines 231 and 232) located in the border area BB. The plurality of first connection lines 231 may be located in the left border area B1, and the first connection lines 231 may be configured to electrically connect the output end of the first drive unit and the scan connection end 111 of the scan line 11 extending to the left border area B1. The plurality of first connection lines 232 may be located in the right border area B2, and the first connection lines 232 may be configured to electrically connect the output end of the second drive unit and the scan connection end 111 of the scan line 11 extending to the right border area B2. The plurality of first connection lines 231 and 232 may be of the same layer structure, and may be located on the side of the plurality of scan lines 11 away from the substrate.

[0098] In some examples, the first connection line 231 (or the first connection line 232) can be directly electrically connected to the scan connection terminal 111 of the scan line 11. For example, the scan line 11 can be located in the first conductive layer, the first connection line 231 or 232 can be located in the second conductive layer, a first insulating layer can be provided between the first conductive layer and the second conductive layer, and the first connection line 231 or 232 located in the second conductive layer can be electrically connected to the scan connection terminal 111 of the scan line 11 located in the first conductive layer through a via hole provided in the first insulating layer. However, this embodiment is not limited to this.

[0099] In some examples, such as Figure 1 and Figure 5 As shown, the array substrate may further include: a first common voltage signal line 21 and a second common voltage signal line 22 located in the border area BB. The first common voltage signal line 21 may be located on a side of the second common voltage signal line 22 away from the substrate. The first common voltage signal line 21 may be a ring-shaped line surrounding the display area AA, for example, a rectangular ring. The second common voltage signal line 22 may be a ring-shaped line surrounding the display area AA, for example, a rectangular ring. The orthographic projection of the first common voltage signal line 21 on the substrate may at least partially overlap with the orthographic projection of the second common voltage signal line 22 on the substrate. For example, the orthographic projection of the first common voltage signal line 21 on the substrate may cover the orthographic projection of the second common voltage signal line 22 on the substrate.

[0100] In some examples, such as Figure 1As shown, the first common voltage signal line 21 can be electrically connected to the second common voltage signal line 22 through a plurality of first vias V1, and the first common voltage signal line 21 and the second common voltage signal line 22 can be configured to transmit a common voltage Vcom. For example, the first common voltage signal line 21 can be located in the second transparent conductive layer, the second common voltage signal line 22 can be located in the first conductive layer, a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer can be provided between the first conductive layer and the second transparent conductive layer, the fourth insulating layer can be provided with a plurality of first vias V1 exposing a portion of the surface of the second common voltage signal line 22, and the first common voltage signal line 21 can be electrically connected to the second common voltage signal line 22 through the plurality of first vias V1.

[0101] In some examples, such as Figure 1 As shown, the plurality of first via holes V1 are divided into a plurality of groups. For example, a group of first via holes V1 may include four first via holes V1 arranged in a 2×2 array. The plurality of groups of first via holes V1 may be arranged in a ring around the display area AA to ensure that a plurality of positions of the first common voltage signal line 21 are electrically connected to the second common voltage signal line 22, thereby ensuring uniform transmission of the common voltage.

[0102] In some examples, such as Figure 1 and Figure 5 As shown, the array substrate may further include: at least one dummy trace 25 located in the border area BB and extending along the second direction Y. In this example, a dummy trace 25 is provided in the left border area B1, and a dummy trace 25 is provided in the right border area B2. In this example, dummy traces are provided in both the left and right border areas to ensure the process uniformity of the array substrate. The number of dummy traces can be determined according to the resolution of the array substrate and the number of touch sensing blocks. This embodiment is not limited to this. In other examples, two dummy traces 25 may be provided in the left border area B1, and two dummy traces 25 may be provided in the right border area B2.

[0103] In some examples, such as Figure 1 and Figure 5 As shown, the dummy wiring 25 can be in the same layer as the data line 12 and the touch signal line 16 of the display area AA. In the left frame area B1 and the right frame area B2, the dummy wiring 25 can be located on the side of the first common voltage signal line 21 and the second common voltage signal line 22 close to the display area AA.

[0104] In some examples, such as Figure 1 and Figure 5As shown, the dummy routing line 25 located in the right frame area B2 may include: a plurality of dummy routing line segments arranged in sequence along the second direction Y and extending along the second direction Y. The plurality of dummy routing line segments may include, for example: two first dummy routing line segments 251 and a plurality of second dummy routing line segments 252, Figure 1 and Figure 5 A second dummy routing segment 252 is used as an example for illustration. A plurality of second dummy routing segments 252 can be sequentially arranged between two first dummy routing segments 251. In this example, the number of second dummy routing segments in the right frame area B2 can be determined according to the number of extended ends of the scan lines in the right frame area B2. For example, if the number of extended ends of the scan lines in the right frame area B2 is N, the number of second dummy routing segments 252 of the dummy routing can be N-1.

[0105] In some examples, such as Figure 1 and Figure 5 As shown, the two first dummy routing segments 251 of the dummy routing line 25 located in the right frame area B2 may not overlap with the orthographic projection of the scanning line 11 of the array substrate on the substrate. The orthographic projection of at least one second dummy routing segment 252 of the dummy routing line 25 on the substrate may overlap with the orthographic projection of the scanning connection end 111 of a scanning line 11 on the substrate.

[0106] In some examples, such as Figure 1 and Figure 5As shown, the first dummy routing segment 251 of the dummy routing line 25 located in the right frame area B2 may be provided with a first dummy connection portion 2511 on a side away from the second dummy routing segment 252, and the first dummy connection portion 2511 and the first dummy routing segment 251 may be an integrated structure connected to each other. The first dummy connection portion 2511 may extend at least along the second direction Y, and be electrically connected to the second common voltage signal line 22 through a plurality of second vias V2. The first dummy routing segment 251 may be provided with a second dummy connection portion 2512 on a side close to one end of the second dummy routing segment 252 and away from the display area AA, and the second dummy connection portion 252 may extend at least along the first direction X, and be electrically connected to the first common voltage signal line 21. The second dummy routing segment 252 may be provided with a third dummy connection portion 2521 and a fourth dummy connection portion 2522 on a side away from the display area AA. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 of the second dummy routing segment 252 may be located on both sides of the scan connection end 111 of a scan line 11 along the second direction Y. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 and the second dummy routing segment 252 may be an integrated structure connected to each other. For example, the third dummy connection portion 2521 is connected to one end of the second dummy routing segment 252, and the fourth dummy connection portion 2522 is connected to the other end of the second dummy routing segment 252. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 may be located on a side of the second common voltage signal line 22 close to the display area AA, and are electrically connected to the first common voltage signal line 21. The first dummy routing segment 251 of the dummy routing in this example is electrically connected to the second common voltage signal line 22 and the first common voltage signal line 21, and the second dummy routing segment 252 is electrically connected to the first common voltage signal line 21, so as to receive the common voltage. This can avoid the floating connection of the dummy routing to generate capacitive coupling and affect the capacitance of the surrounding touch sensing blocks, thereby avoiding affecting the touch effect.

[0107] In some examples, such as Figure 1 and Figure 5As shown, a first break may be provided between adjacent dummy routing segments arranged in sequence along the second direction Y of the dummy routing 25 located in the right frame area B2, for example, a first break K1 may be provided between the first dummy routing segment 251 and the second dummy routing segment 252. The first break K1 corresponds to the position of the extended end 112 of a scanning line 11. The length of the first break K1 along the second direction Y may be greater than the length of the extended end 112 of the scanning line 11 along the second direction Y. By providing the first break, the extended end 112 of the dummy routing 25 and the scanning line 11 may not overlap in the orthographic projection of the substrate, thereby avoiding the cross-arrangement of the dummy routing 25 and the extended end 112 of the scanning line 11, and reducing the risk of electrostatic discharge at the extended end 112 of the scanning line 11 to break through the insulating layer and cause a short circuit between the dummy routing 25 and the scanning line 11, thereby improving the situation of poor functional display of horizontal stripes caused thereby.

[0108] The design of the dummy wiring in the left frame area is similar to that of the dummy wiring in the right frame area, so it will not be repeated here.

[0109] Fig. 6A The diagram is a partial plan view of the boundary area between the display area and the right frame area of ​​at least one embodiment of the present disclosure. Figure 6B It is a partial plan view of the right frame area of ​​at least one embodiment of the present disclosure. Fig. 6A Schematic diagram of the partial structures of the 2b-th level second driving unit, the 2b+1-th level second driving unit and the 2b+2-th level second driving unit in the right frame area B2. Figure 6B 2b-1 second driving unit, 2b second driving unit, 2b+1 second driving unit and 2b+2 second driving unit of the right frame area B2 are shown in FIG. Fig. 7A for Fig. 6A Schematic diagram of the local cross-section along the Q-Q' direction. Figure 7B for Fig. 6A A partial cross-sectional diagram along the RR' direction in FIG. 1 is a schematic diagram of a part of the cross-section of FIG. 1. In this example, a row of dummy sub-pixels may be arranged on one side of the plurality of rows of sub-pixels close to the right frame area B2.

[0110] In some examples, such as Fig. 7A and Figure 7BAs shown, the array substrate may include: a substrate 300, a first conductive layer, a semiconductor layer, a second conductive layer, a first transparent conductive layer, and a second transparent conductive layer sequentially arranged on the substrate 300. A first insulating layer 301 may be arranged between the first conductive layer and the semiconductor layer, a second insulating layer 302 and a third insulating layer 303 may be arranged between the second conductive layer and the first transparent conductive layer, and a fourth insulating layer 304 may be arranged between the first transparent conductive layer and the second transparent conductive layer. The semiconductor layer and the second conductive layer may be in direct contact. Among them, the first insulating layer 301, the second insulating layer 302, and the fourth insulating layer 304 may be inorganic insulating layers, and the third insulating layer 303 may be an organic insulating layer. This embodiment is not limited to this.

[0111] The technical solution of this embodiment is further explained below through the preparation process of the array substrate of this exemplary embodiment. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0112] The "A and B are arranged in the same layer" or "A and B are in the same layer structure" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. In this example, "the shape of A" refers to the shape of the orthographic projection of A on the substrate.

[0113] The preparation process of the array substrate of this embodiment includes the following steps.

[0114] (1) Provide a substrate. In some examples, the substrate may be a transparent substrate, such as a quartz substrate, a glass substrate, or an organic resin substrate. However, this embodiment is not limited thereto.

[0115] (2) Forming a first conductive layer. In some examples, a first conductive film is deposited on a substrate, and the first conductive layer is patterned by a patterning process to form the first conductive layer. In some examples, the first conductive layer may also be referred to as a gate metal layer.

[0116] Fig. 8A for Fig. 6A A plan view of the array substrate after the first conductive layer is formed. Figure 8B for Figure 6B A plan view of the array substrate after the first conductive layer is formed.

[0117] In some examples, such as Fig. 8A and Figure 8B As shown, the first conductive layer may at least include: a plurality of scan lines 11 located in the display area AA and control electrodes 141 of a plurality of switching transistors, a plurality of first dummy control blocks 141a, and a second common voltage signal line 22 located in the right frame area B2, a first voltage line 23, control electrodes of transistors of a plurality of second driving units (for example, including a control electrode 261 of a first control transistor, a control electrode 271 of a second control transistor) and a first electrode 281 of a first capacitor, and a reset signal line 291.

[0118] In some examples, such as Fig. 8A As shown, a plurality of scan lines 11 in the display area AA may extend along the first direction X and be arranged in sequence along the second direction Y. The shape of the scan line 11 may be substantially a straight line extending along the first direction X. The control electrodes 141 of the plurality of switch transistors arranged along the first direction X may be located on the same side of a scan line 11 along the second direction Y, and may be an integral structure interconnected with the scan line 11. The shape of the control electrode 141 of the switch transistor may be substantially a rectangle, and the rectangle may have chamfered or rounded corners.

[0119] In some examples, such as Fig. 8A As shown, the first dummy control block 141a can be located on a side of the control electrode 141 of the plurality of switch transistors arranged along the first direction X close to the right frame area B2. The plurality of first dummy control blocks 141a can be arranged in the boundary area between the display area AA and the right frame area B2 along the second direction Y. The first dummy control block 141a can be an integral structure interconnected with the adjacent scan line 11. The first dummy control block 141a can serve as the control electrode of the switch transistor of the dummy sub-pixel.

[0120] In some examples, such as Fig. 8A and Figure 8BAs shown, in the right frame area B2, the extended ends 112 and the scan connection ends 111 of the plurality of scan lines 11 may be arranged at intervals along the second direction Y and located on a side of the second common voltage signal line 22 close to the display area AA. The distance between the scan connection end 111 and the second common voltage signal line 22 along the first direction X may be smaller than the distance between the extended end 112 and the second common voltage signal line 22 along the first direction X.

[0121] In some examples, such as Fig. 8A and Figure 8B As shown, the second common voltage signal line 22 may extend at least along the second direction Y in the right frame area B2; the first voltage line 23 may extend at least along the second direction Y in the right frame area B2. The first voltage line 23 may be located on a side of the second common voltage signal line 22 away from the display area AA. The first voltage line 23 may be configured to provide a low-level first voltage signal VGL to the plurality of second driving units.

[0122] In some examples, such as Fig. 8A and Figure 8B As shown, the second driving unit may be located on a side of the first voltage line 23 away from the display area AA. The first plate 281 of the first capacitor of the second driving unit may serve as the first electrode of the first capacitor, and the first plates 281 of the first capacitors of the plurality of cascaded second driving units may be arranged in sequence along the second direction Y. The orthographic projection of the first plate 281 of the first capacitor on the substrate may be approximately rectangular.

[0123] In some examples, such as Figure 8B As shown, the first electrode plate 281 of the first capacitor of the second driving unit and the control electrode 271 of the second control transistor can be an integrated structure connected to each other. The control electrode 271 of the second control transistor can be located on the side of the first electrode plate 281 of the first capacitor away from the display area AA. The shape of the control electrode 271 of the second control transistor can be roughly rectangular. The control electrode 271 of the second control transistor can be provided with a control connection block 271-1 on the side away from the display area AA, one end of the control connection block 271-1 is connected to the control electrode 271 of the second control transistor, and the other end extends along the first direction X to the side away from the display area AA. The shape of the control connection block 271-1 of the second driving unit of the 2b-1 level can be roughly 9-shaped, and the shape of the control connection block 271-1 of the second driving unit of the 2b level can be roughly P-shaped. The control connection block 271-1 and the control electrode 271 of the second control transistor can be an integrated structure connected to each other.

[0124] In some examples, such as Figure 8BAs shown, the control electrode 261 of the first control transistor may be located on a side of the control electrode 271 of the second control transistor away from the display area AA along the first direction X. The control electrode 261 of the first control transistor of the second driving unit of the 2b-1 stage may be located on a side of the control connection block 271-1 of the second control transistor in the opposite direction of the second direction Y, and the control electrode 261 of the first control transistor of the second driving unit of the 2b stage may be located on a side of the control connection block 271-1 of the second control transistor in the second direction Y. The shape of the control electrode 261 of the first control transistor may be substantially rectangular. The area of ​​the control electrode 261 of the first control transistor may be smaller than the area of ​​the control electrode 271 of the second control transistor.

[0125] In some examples, such as Figure 8B As shown, the first conductive layer pattern of the second driving unit of the 2b-1th level and the first conductive layer pattern of the second driving unit of the 2bth level can be roughly symmetrical about the midline of the two in the second direction Y. The first conductive layer pattern of the second driving unit of the 2bth level and the first conductive layer pattern of the second driving unit of the 2b+1th level can be roughly symmetrical about the midline of the two in the second direction Y.

[0126] In some examples, such as Figure 8B As shown, the reset signal line 291 may be located at a side of the control electrode 261 of the first control transistor away from the display area AA, and the reset signal line 291 and the control electrode 261 of the first control transistor may be an integrated structure connected to each other. For example, the reset signal line 291 connected to the control electrode 261 of the first control transistor of the second driving unit of the 2b-1 stage may be electrically connected to the output end of the second driving unit of the 2b+1 stage.

[0127] (3) Forming a semiconductor layer. In some examples, a first insulating film and a semiconductor film are sequentially deposited on a substrate, and the semiconductor film is patterned by a patterning process to form a first insulating layer and a semiconductor layer disposed on the first insulating layer.

[0128] Fig. 9A for Fig. 6A A plan view of an array substrate after a semiconductor layer is formed in FIG. Fig. 9B for Figure 6B A plan view of an array substrate after a semiconductor layer is formed in FIG.

[0129] In some examples, such as Fig. 9A and Fig. 9B As shown, the semiconductor layer may include at least: an active layer 140 of multiple switching transistors 14 located in the display area AA, and an active layer of multiple transistors of the second driving unit located in the right frame area B2 (for example, at least including: an active layer 260 of the first control transistor 26 and an active layer 270 of the second control transistor 27).

[0130] In some examples, such as Fig. 9A As shown, the shape of the active layer 140 of the switch transistor 14 may be substantially rectangular, and may have chamfered or rounded corners. The orthographic projection of the control electrode 141 of the switch transistor 14 on the substrate may cover the orthographic projection of the active layer 140 on the substrate.

[0131] In some examples, such as Fig. 9A As shown, at the junction of the display area AA and the right frame area B2, the semiconductor layer may further include: a plurality of first dummy active blocks 140a. The plurality of first dummy active blocks 140a may be arranged in a row along the second direction Y, and located on a side of the active layer 140 of the plurality of switch transistors 14 close to the right frame area B2. The first dummy active block 140a may be used as an active measurement of the switch transistor of the dummy sub-pixel. In this example, the uniformity of the film preparation may be ensured by setting a plurality of first dummy active blocks 140a.

[0132] In some examples, such as Fig. 9A As shown, the shape of the first dummy active block 140a may be substantially rectangular and have chamfered or rounded corners. The orthographic projection of the first dummy active block 140a on the substrate may be located within the orthographic projection range of the first dummy control block 141a on the substrate.

[0133] In some examples, such as Fig. 9B As shown, the shape of the active layer 260 of the first control transistor 26 may be substantially rectangular, and may have chamfered or rounded corners. The orthographic projection of the control electrode 261 of the first control transistor 26 on the substrate may cover the orthographic projection of the active layer 260 on the substrate.

[0134] In some examples, such as Fig. 9B As shown, the shape of the active layer 270 of the second control transistor 27 may be substantially rectangular, and may have chamfered or rounded corners. The orthographic projection of the control electrode 271 of the second control transistor 27 on the substrate may cover the orthographic projection of the active layer 270 on the substrate.

[0135] In some examples, such as Fig. 9B As shown, the semiconductor layer pattern of the second driving unit of the 2b-1th level and the semiconductor layer pattern of the second driving unit of the 2bth level can be roughly symmetrical about the midline of the two in the second direction Y. The semiconductor layer pattern of the second driving unit of the 2bth level and the semiconductor layer pattern of the second driving unit of the 2b+1th level can be roughly symmetrical about the midline of the two in the second direction Y.

[0136] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region between the first region and the second region. The material of the semiconductor layer may include, for example, one or more materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc. The channel region may not be doped with impurities and has semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, doped with impurities, and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors.

[0137] (4) Forming a second conductive layer. In some examples, a second conductive film is deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second conductive layer. In some examples, the second conductive layer may also be referred to as a source-drain metal layer.

[0138] Fig. 10A for Fig. 6A A schematic plan view of the array substrate after the second conductive layer is formed. Fig. 10B for Figure 6B A schematic plan view of the array substrate after the second conductive layer is formed. Fig.11A for Fig. 10A Schematic diagram of the second conductive layer in . Fig. 11B for Fig. 10B Schematic diagram of the second conductive layer in .

[0139] In some examples, such as FIG. 10A to FIG. 11B As shown, the second conductive layer may at least include: multiple data lines 12, multiple touch signal lines 16, second electrodes 142 of multiple switching transistors and virtual data lines 18 located in the display area AA; virtual routing lines 25 located in the right frame area B2, first connecting lines 232, first electrodes and second electrodes of multiple transistors of multiple second driving units (for example, including first electrodes 272 and second electrodes 273 of second control transistors, first electrodes 262 and second electrodes 263 of first control transistors) and the second electrode plate 282 of the first capacitor, and second connecting lines 292.

[0140] In some examples, such as Fig. 10A and Fig.11A As shown, the shape of the data line 12 in the display area AA can be roughly a folded line extending along the second direction Y. The orthographic projection of the data line 12 on the substrate at least partially overlaps with the orthographic projection of the first area of ​​the active layer 140 of the switching transistor on the substrate. The overlapping portion of the data line 12 and the active layer 140 of the switching transistor can serve as the first electrode of the switching transistor.

[0141] In some examples, such as Fig. 10A and Fig.11A As shown, the shape of the second electrode 142 of the switch transistor can be substantially L-shaped. The orthographic projection of the second electrode 142 of the switch transistor on the substrate at least partially overlaps with the orthographic projection of the second region of the active layer 140 of the switch transistor on the substrate.

[0142] In some examples, such as Fig. 10A and Fig.11A As shown, the shape of the touch signal line 16 in the display area AA may be substantially a folded line extending along the second direction Y. Three data lines 12 may be arranged between two adjacent touch signal lines 16 .

[0143] In some examples, such as Fig. 10A and Fig.11A As shown, the dummy data line 18 may be located on a side of the touch signal line 16 close to the right frame area B2. The dummy data line 18 may be connected to a column of dummy sub-pixels. The shape of the dummy data line 18 may be substantially a folded line extending along the second direction Y. The orthographic projection of the dummy data line 18 on the substrate partially overlaps with the orthographic projection of the plurality of first dummy active blocks 140a on the substrate.

[0144] In some examples, such as FIG. 10A to FIG. 11B As shown, a dummy routing line 25 is provided in the right frame area B2. The dummy routing line 25 is located on one side of the dummy data line 18. The dummy routing line 25 may include at least: a plurality of second dummy routing line segments 252. The shape of the second dummy routing line segment 252 may be roughly Σ-shaped. The orthographic projection of the second dummy routing line segment 252 on the substrate overlaps with the orthographic projection of the scanning line extending from the scanning connection end 111 to the right frame area B2 on the substrate. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 of the second dummy routing line segment 252 may be located on both sides of the scanning connection end 111 of a scanning line along the second direction Y. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 of the second dummy routing line segment 252 and the scanning connection end 111 of the scanning line may be aligned in the second direction Y. A first break K1 may be provided between adjacent second dummy routing line segments 252, and the extended end 112 of the scanning line may be inserted into the first break K1.

[0145] In some examples, such as FIG. 10A to FIG. 11BAs shown, the shape of the first connection line 232 can be roughly a fold line extending along the first direction X. The orthographic projection of the first connection line 232 on the substrate overlaps with the orthographic projection of the second common voltage signal line 22 and the first voltage line 23 on the substrate. The orthographic projection of the first end of the first connection line 232 on the substrate overlaps with the orthographic projection of the scanning connection end 111 of the scanning line on the substrate. The second end of the first connection line 232 can be electrically connected to the output end of a second driving unit. For example, the first end of the first connection line 232 and the output end of the second driving unit can be an integrated structure connected to each other.

[0146] In some examples, such as Fig. 10B and Fig. 11B As shown, the first electrode 272 of the second control transistor of the second driving unit overlaps with the orthographic projection of the active layer 270 on the substrate in the orthographic projection of the substrate, and the shape of the first electrode 272 can be roughly comb-shaped. The orthographic projection of the second electrode 273 of the second control transistor overlaps with the orthographic projection of the active layer 270 on the substrate, and the shape of the second electrode 273 can be roughly comb-shaped. The comb-tooth structure of the first electrode 272 and the second electrode 273 of the second control transistor can be cross-arranged. The second electrode 273 of the second control transistor and the second electrode plate 282 of the first capacitor can be an integral structure connected to each other. The second electrode plate 282 of the first capacitor can serve as the second electrode of the first capacitor, and can also serve as the output end of the second driving unit, and is electrically connected to the first connecting line 232. The orthographic projection of the first electrode 262 of the first control transistor of the second driving unit overlaps with the orthographic projection of the active layer 260 on the substrate in the orthographic projection of the substrate, and the shape of the first electrode 262 can be roughly comb-shaped. The orthographic projection of the second electrode 263 of the first control transistor overlaps with the orthographic projection of the active layer 260 on the substrate, and the shape of the second electrode 263 can be roughly comb-shaped. The comb-tooth structure of the first electrode 262 and the second electrode 263 of the first control transistor can be cross-arranged.

[0147] In some examples, such as Fig. 10B and Fig. 11BAs shown, the first electrode 262 of the first control transistor of the second driving unit of the 2b-1 level and the first electrode 262 of the first control transistor of the second driving unit of the 2b level can be electrically connected to the same second connection line 292. For example, the first electrode 262 of the first control transistor of the second driving unit of the 2b-1 level, the first electrode 262 of the first control transistor of the second driving unit of the 2b level, and a second connection line 292 can be an integrated structure connected to each other. The second connection line 292 can be located between the second plate 282 of the first capacitor of the second driving unit of the 2b-1 level and the second plate 282 of the first capacitor of the second driving unit of the 2b level. The orthographic projection of the end of the second connection line 292 on the substrate may overlap with the orthographic projection of the first voltage line 23 on the substrate. In this example, the second driving units of two adjacent levels can be electrically connected to the first voltage line 23 through the same second connection line.

[0148] In some examples, such as Fig. 10B and Fig. 11B As shown, the second conductive layer pattern of the second driving unit of the 2b-1th level and the second conductive layer pattern of the second driving unit of the 2bth level can be substantially symmetrical about the second connecting line 292. The second conductive layer pattern of the second driving unit of the 2bth level and the second conductive layer pattern of the second driving unit of the 2b+1th level can be substantially symmetrical about the midline of the two along the second direction Y. The arrangement of the second driving unit in this example is conducive to circuit arrangement and saves space.

[0149] (5) Forming a second insulating layer and a third insulating layer. In some examples, a second insulating film is deposited on the substrate forming the aforementioned structure, and then a third insulating film is coated, and the third insulating film is patterned by a patterning process to form a third insulating layer, and the second insulating film exposed by the third insulating layer is etched to form a second insulating layer. In some examples, the second insulating layer may also be referred to as a first passivation layer (PVX1).

[0150] Fig.12 for Fig. 6A A schematic plan view of an array substrate after a third insulating layer is formed in FIG. Fig.12 As shown, the third insulating layer of the display area AA may be provided with a plurality of third via holes V3. The third insulating layer and the second insulating layer in the third via holes V3 may be removed to expose a portion of the surface of the second electrode 142 of the switch transistor located in the second conductive layer.

[0151] In some examples, such as Fig.12As shown, the third insulating layer of the right frame area B2 may be provided with a plurality of openings, for example, may include a first opening Q1, a second opening Q2, a third opening Q3 and a fourth opening Q4. The third insulating layer within the first opening Q1 to the fourth opening Q4 may be removed to expose the surface of the second insulating film. The orthographic projection of the first opening Q1 on the substrate at least partially overlaps with the orthographic projection of the third dummy connection portion 2511 or the fourth dummy connection portion 2512 of the second dummy routing segment of the dummy routing on the substrate. The orthographic projection of the second opening Q2 on the substrate at least partially overlaps with the orthographic projection of the first voltage line 23 and the second connection line 292 on the substrate. The orthographic projection of the third opening Q3 on the substrate partially overlaps with the orthographic projection of the scan connection end 111 of the scan line and the first connection line 232 on the substrate. The orthographic projection of the fourth opening Q4 on the substrate may be located within the orthographic projection range of the second common voltage signal line 22 on the substrate.

[0152] (6) Forming a first transparent conductive layer. In some examples, a first transparent conductive film is deposited on the substrate having the aforementioned structure, and the first transparent conductive film is patterned by a patterning process to form a first transparent conductive layer.

[0153] Fig.13 for Fig. 6A A schematic plan view of an array substrate after forming a first transparent conductive layer. Fig.13 As shown, the first transparent conductive layer of the display area AA may include at least: a plurality of pixel electrodes 13 and a plurality of dummy pixel electrodes 13a. The pixel electrode 13 may be electrically connected to the second electrode 142 of the switching transistor through a third via hole V3. The orthographic projection of the pixel electrode 13 on the substrate may be located in a sub-pixel region defined by the intersection of the adjacent data line 12 and the adjacent scan line 11. The orthographic projection of the touch signal line 16 on the substrate may overlap with the orthographic projection portion of the pixel electrode 13 on the substrate. The plurality of dummy pixel electrodes 13a may be arranged in a row along the second direction Y and located on one side of the plurality of pixel electrodes 13 close to the right frame area B2. The orthographic projection of the dummy pixel electrode 13a on the substrate may overlap with the orthographic projection portion of the first dummy active block 140a on the substrate. The dummy pixel electrode 13a may serve as a pixel electrode of a dummy sub-pixel.

[0154] (7) Forming a fourth insulating layer. In some examples, a fourth insulating film is deposited on the substrate forming the aforementioned structure, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer. In some examples, the fourth insulating layer may also be referred to as a second passivation layer (PVX2).

[0155] Fig.14A for Fig. 6A A schematic plan view of the array substrate after the fourth insulating layer is formed. Fig. 14B for Figure 6BA schematic plan view of the array substrate after the fourth insulating layer is formed.

[0156] In some examples, such as Fig.14A and Fig. 14B As shown, the fourth insulating layer may have a plurality of via holes, for example, a first via hole V1, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9 and a tenth via hole V10.

[0157] In some examples, such as Fig.14A and Fig. 14B As shown, the orthographic projection of the first via hole V1 on the substrate can be located within the orthographic projection range of the fourth opening Q4 on the substrate; the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the first via hole V1 can be removed to expose a portion of the surface of the second common voltage signal line 22 located in the first conductive layer. The orthographic projections of the fourth via hole V4 and the fifth via hole V5 on the substrate can be located within the orthographic projection range of the third opening Q3 on the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the fourth via hole V4 can be removed to expose a portion of the surface of the scan connection end 111 of the scan line 11 located in the first conductive layer. The fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 can be removed to expose a portion of the surface of the first end of the first connecting line 232 located in the second conductive layer. The orthographic projection of the sixth via hole V6 on the substrate can be located within the orthographic projection range of the first opening Q1 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth via hole V6 may be removed, exposing a portion of the surface of the third dummy connection portion 2521 or the fourth dummy connection portion 2522 of the second dummy routing segment 252 of the dummy routing line 25 located in the second conductive layer. The orthographic projections of the seventh via hole V7 and the eighth via hole V8 on the substrate may be located within the orthographic projection range of the second opening Q2 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh via hole V7 may be removed, exposing a portion of the surface of the second connection line 292 located in the second conductive layer. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the eighth via hole V8 may be removed, exposing a portion of the surface of the first voltage line 23 located in the first conductive layer. The orthographic projections of the ninth via hole V9 and the tenth via hole V10 on the substrate may be located within the orthographic projection range of an opening of the third insulating layer on the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the ninth via hole V9 may be removed, exposing a portion of the surface of the control connection block 271-1 located in the first conductive layer. The fourth insulating layer, the third insulating layer and the second insulating layer in the tenth via hole V10 may be removed to expose a portion of the surface of the second electrode 263 of the first control transistor.

[0158] In this example, the third insulating layer is firstly dug out at the position where the via hole is formed, so as to avoid the via hole being too deep and thus affecting the electrical connection effect of the conductive film layer.

[0159] (8) Forming a second transparent conductive layer. In some examples, a second transparent conductive film is deposited on the substrate forming the aforementioned structure, and the second transparent conductive film is patterned by a patterning process to form a second transparent conductive layer.

[0160] Fig.15A for Fig. 6A Schematic diagram of the second transparent conductive layer in . Fig. 15B for Figure 6B Schematic diagram of the second transparent conductive layer in .

[0161] In some examples, such as Fig. 6A , Figure 6B , Fig.15A and Fig. 15B As shown, the second transparent conductive layer may include at least: a common electrode 15 located in the display area AA, a first common voltage signal line 21 located in the right frame area B2, and multiple connecting electrodes (for example, including a first connecting electrode 41, a second connecting electrode 42 and a third connecting electrode 43).

[0162] In some examples, such as Fig.15A As shown, the common electrode 15 of the multiple sub-pixels in the display area AA can be an integrated structure connected to each other. The common electrode 15 located in the sub-pixel area can have multiple (for example, three or four) slits. The extension direction of the multiple slits can intersect with the first direction X and the second direction Y. The common electrode 15 can have slits in two different directions to form a dual-domain structure. However, this embodiment is not limited to this. For example, the common electrode can form a single-domain or multi-domain structure.

[0163] In some examples, the common electrodes 15 of multiple sub-pixels are electrically connected to each other to be reused as a touch sensing block. For example, the common electrode can be electrically connected to the touch signal line located in the second conductive layer through the vias opened in the fourth insulating layer, the third insulating layer, and the second insulating layer; or, the common electrode can be electrically connected to the electrode connection block located in the first transparent conductive layer through the vias opened in the fourth insulating layer, and the electrode connection block is electrically connected to the touch signal line located in the second conductive layer through the vias opened in the third insulating layer and the second insulating layer, thereby realizing the electrical connection between the common electrode and the touch signal line. This embodiment is not limited to this. In this example, a common voltage signal is applied to the common electrode in the display stage to realize the display function, and a touch signal is applied to the common electrode in the touch stage to realize the touch function. In this way, there is no need to additionally make the film layer where the touch electrode is located, thereby saving the manufacturing process and reducing the thickness of the array substrate.

[0164] In some examples, such as Fig.15A and Fig. 15B As shown, the first common voltage signal line 21 of the right frame area B2 may have a plurality of first hollow portions 211. The orthographic projection of the first hollow portion 211 on the substrate may be roughly rectangular, and the rectangle may have rounded corners or chamfers. The plurality of first hollow portions 211 may be aligned in the second direction Y. The orthographic projection of the first hollow portion 211 of the first common voltage signal line 21 on the substrate may not overlap with the orthographic projection of the second common voltage signal line 22 on the substrate.

[0165] In some examples, such as Fig.15A and Fig. 15B As shown, the first common voltage signal line 21 of the right frame area B2 may have a first edge close to the display area AA and a second edge away from the display area AA in the first direction X. The first edge may face the common electrode 15 of the display area AA, and the edge shape of the integrated structure of the first edge and the plurality of common electrodes 15 of the display area AA may roughly match, for example, may be roughly in the shape of a broken line extending along the second direction Y. The second edge of the first common voltage signal line 21 may have a plurality of notches 213. The orthographic projection of the notch 213 on the substrate may be roughly rectangular. The plurality of notches 213 may be arranged sequentially along the second direction Y.

[0166] In some examples, such as FIG. 6A to FIG. 15B As shown, the orthographic projection of the first common voltage signal line 21 on the substrate can cover the orthographic projection of the second common voltage signal line 22 on the substrate. The first common voltage signal line 21 can be electrically connected to the second common voltage signal line 22 through multiple groups of first vias V1. For example, each group of first vias V1 may include two first vias V1 arranged along the first direction X. The multiple groups of first vias V1 in the right frame area B2 may be arranged in sequence along the second direction Y. The multiple groups of first vias V1 and the multiple first hollow portions 211 may be spaced apart in the second direction Y, thereby facilitating circuit layout.

[0167] In some examples, such as FIG. 6A to FIG. 15B As shown, the orthographic projection of the first common voltage signal line 21 on the substrate can cover the orthographic projection of the second dummy routing segment 252 of the dummy routing line 25 on the substrate. The second dummy routing segment 252 can be located on the side of the first hollow portion 211 close to the display area AA. The third dummy connection portion 2521 or the fourth dummy connection portion 2522 of the second dummy routing segment 252 can be electrically connected to the first common voltage signal line 21 through two sixth vias V6 arranged along the first direction X.

[0168] In some examples, such as Fig. 7AAs shown, the area where the third dummy connection part 2521 (or the fourth dummy connection part 2522) of the second dummy routing segment 252 is located can form a first opening to remove the third insulating layer 303, and the fourth insulating layer and the second insulating layer are etched away in the first opening to form two sixth vias V6, exposing the third dummy connection part 2521 (or the fourth dummy connection part 2522). The first common voltage signal line 21 can be electrically connected to the third dummy connection part 2521 (or the fourth dummy connection part 2522) through the first opening and the sixth vias V6. In this example, by etching the vias after forming the first opening in the third insulating layer, it is possible to avoid insufficient contact of the conductive film layer due to excessive via depth, and to ensure the effectiveness of the electrical connection between the first common voltage signal line and the second dummy routing segment.

[0169] In some examples, such as FIG. 6A to FIG. 15B As shown, the first connection electrode 41 can be located on the side of the second common voltage signal line 22 close to the display area AA. The first connection electrode 41 can be electrically connected to the scan connection end 111 of the scan line 11 through two fourth vias V4 arranged along the second direction Y, and can also be electrically connected to the first end of the first connection line 232 through two fifth vias V5 arranged along the second direction Y. The orthographic projection of the first connection electrode 41 on the substrate can be located within the orthographic projection range of the first hollow portion 211 of the first common voltage signal line 21 on the substrate. For example, the orthographic projection of each first hollow portion 211 on the substrate can cover the orthographic projection of a first connection electrode 41 on the substrate. The multiple first connection electrodes 41 in the right frame area B2 can be arranged in sequence along the second direction Y. In this example, the first connection electrode is avoided by setting a first hollow portion on the first common voltage signal line, so as to ensure the effectiveness of the electrical connection between the first connection electrode and the scan connection end of the scan line and the first connection line.

[0170] Fig.16 for Fig. 6A Schematic diagram of a local area in . In some examples, such as Fig.16 As shown, the orthographic projection of the first connection electrode 41 on the substrate may be approximately rectangular, for example, the rectangle may have rounded corners or chamfered corners. The length L11 of the first connection electrode 41 along the first direction X may be less than the length L12 along the second direction Y. For example, the length L11 of the first connection electrode 41 along the first direction X may be 25 micrometers (um) to 35um, for example, about 30um; the length L12 of the first connection electrode 41 along the second direction Y may be 36um to 45um, for example, about 40um.

[0171] In some examples, such as Fig.16As shown, in the first direction X, there is a first distance L13 between the edge of the first connection electrode 41 close to the display area AA and the edge of the first hollow portion 211 close to the display area AA, and there may be a second distance L14 between the edge of the first connection electrode 41 away from the display area AA and the edge of the first hollow portion 211 away from the display area AA. The second distance L14 may be greater than or equal to the first distance L13. For example, the first distance L13 and the second distance L14 may both be greater than 6um, for example, the first distance L13 may be approximately 10um, and the second distance L14 may be approximately 15um.

[0172] In some examples, such as Fig.16 As shown, in the second direction Y, there is a third distance L15 between the lower edge of the first connection electrode 41 and the adjacent edge of the first hollow portion 211, and there is a fourth distance L16 between the upper edge of the first connection electrode 41 and the adjacent edge of the first hollow portion 211. The third distance L15 and the fourth distance L16 may be substantially the same. For example, the third distance L15 and the fourth distance L16 may both be approximately 15 um.

[0173] In some examples, such as FIG. 6A to FIG. 15B As shown, the second connection electrode 42 may be located on a side of the second common voltage signal line 22 away from the display area AA. The orthographic projection of the second connection electrode 42 on the substrate may be roughly rectangular, for example, the rectangle may have chamfers or rounded corners. The second connection electrode 42 may be electrically connected to the second connection line 292 located on the second conductive layer through two seventh vias V7 arranged along the second direction Y, and may also be electrically connected to the first voltage line 23 located on the first conductive layer through two eighth vias V8. The two eighth vias V8 may be located on both sides of the two seventh vias V7 along the second direction Y. The orthographic projection of the second connection electrode 42 on the substrate at least partially overlaps with the orthographic projection of the first voltage line 23 on the substrate; for example, the orthographic projection of the first voltage line 23 on the substrate may cover the orthographic projection of the second connection electrode 42 on the substrate.

[0174] In some examples, such as Fig.15A As shown, the orthographic projection of the second connection electrode 42 on the substrate may be located within the orthographic projection range of the notch 213 on the substrate. In the first direction X, the orthographic projection of the notch 213 on the substrate may cover the orthographic projection of the second connection electrode 42 on the substrate. The edge of the second connection electrode 42 away from the display area AA may be flush with the second edge of the first common voltage signal line 21 in the first direction X.

[0175] In some examples, such as Fig.15AAs shown, in the first direction X, there may be a fifth distance L21 between the edge of the second connection electrode 42 close to the display area AA and the bottom surface of the recess 213; in the second direction Y, there may be a sixth distance L22 between the lower edge of the second connection electrode 42 and the side surface of the recess 213, and there may be a seventh distance L23 between the upper edge of the second connection electrode 42 and the side surface of the recess 213. The fifth distance L21, the sixth distance L22, and the seventh distance L23 may be greater than 6um. For example, the fifth distance L21 may be about 8um, the sixth distance L22 may be about 15um, and the seventh distance L23 may be about 15um. In this example, by setting the first common voltage signal line to avoid the second connection electrode, the effectiveness of the electrical connection of the second connection electrode to the first voltage line and the second connection line can be ensured.

[0176] In some examples, such as Figure 7B As shown, a second opening can be formed in the area corresponding to the notch 213 of the first common voltage signal line 21 to remove the third insulating layer 303, and the fourth insulating layer and the second insulating layer are etched away in the second opening to form two seventh vias V7, exposing a portion of the surface of the second connection line 292 located in the second conductive layer, and the fourth insulating layer, the second insulating layer and the first insulating layer are etched away in the second opening to form two eighth vias V8, exposing a portion of the surface of the first voltage line 23 located in the first conductive layer. The second connection electrode 42 can be electrically connected to the second connection line 292 through the seventh via V7, and can also be electrically connected to the first voltage line 23 through the eighth via V8. In this example, by etching the via after forming the second opening in the third insulating layer, it is possible to avoid insufficient contact of the conductive film layer due to excessive via depth, and to ensure the effectiveness of the electrical connection between the first voltage line and the second connection line.

[0177] In some examples, such as Fig. 6A and Figure 6B As shown, in the right frame area B2, the plurality of notches 213 of the first common voltage signal line 21 and the extended ends 112 of the plurality of scan lines 11 can be spaced apart in the second direction Y. Since the two adjacent second drive units can be electrically connected to the first voltage line 23 through the same second connection line and the second connection electrode, and the second connection electrode is located in the notch, the two adjacent second drive units can share the second connection electrode in the notch to be electrically connected to the first voltage line. By arranging the notch and the extended ends of the scan lines to be spaced apart in the second direction, a reasonable circuit layout can be achieved, which is conducive to saving space.

[0178] In some examples, the first insulating layer 301, the second insulating layer 302 and the fourth insulating layer 304 may be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The third insulating layer 303 may be made of an organic insulating material. The first conductive film and the second conductive film may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti. The first transparent conductive film and the second transparent conductive film may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, this embodiment is not limited to this.

[0179] The structure of the array substrate and its preparation process of the embodiment of the present disclosure are merely exemplary. In some examples, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the common electrode can be a sheet electrode structure without slits, so that the touch electrode has a larger area, which is conducive to enhancing the touch performance. However, this embodiment is not limited to this.

[0180] The array substrate of this example can avoid the dummy line from crossing the extended end of the scan line by setting the dummy line to be disconnected at the extended end of the scan line, thereby reducing the risk of short circuit between the scan line and the dummy line caused by electrostatic discharge at the extended end of the scan line, and further improving the functional display defects such as horizontal stripes.

[0181] Fig.17 FIG. 1 is another schematic diagram of a scan driving circuit according to at least one embodiment of the present disclosure. Fig.17 As shown, the array substrate may further include: a plurality of auxiliary driving units (for example, including first auxiliary driving units 35c and 35d, and second auxiliary driving units 35a and 35b). The first auxiliary driving units 35c and 35d may be located in the left frame area, and the second auxiliary driving units 35a and 35b may be located in the right frame area.

[0182] In some examples, such as Fig.17As shown, the second auxiliary driving unit 35c located in the left frame area can be cascaded with the N-1th first driving unit, and the second auxiliary driving unit 35d can be cascaded with the Nth first driving unit. The output end of the Nth first driving unit can be configured to provide an input signal to the first auxiliary driving unit 35d, and the output end of the first auxiliary driving unit 35d can be configured to provide a reset signal to the Nth first driving unit; the output end of the N-1th first driving unit can be configured to provide an input signal to the first auxiliary driving unit 35c, and the output end of the first auxiliary driving unit 35c can be configured to provide a reset signal to the N-1th first driving unit. The second auxiliary driving unit 35a located in the right frame area is cascaded with the M-1th second driving unit, and the second auxiliary driving unit 35b can be cascaded with the Mth second driving unit. The output end of the M-1th level second driving unit can be configured to provide an input signal to the second auxiliary driving unit 35a, and the output end of the second auxiliary driving unit 35a can be configured to provide a reset signal to the M-1th level second driving unit; the output end of the Mth level second driving unit can be configured to provide an input signal to the second auxiliary driving unit 35b, and the output end of the second auxiliary driving unit 35b can be configured to provide a reset signal to the Mth level second driving unit.

[0183] In this example, multiple auxiliary driving units are provided to provide reset signals to the last two first driving units and the last two second driving units, so as to ensure the reset and driving effect of the first driving circuit and the second driving circuit. However, this embodiment is not limited to this. In other examples, separate reset signals can be provided to the last two first driving units and the last two second driving units.

[0184] In some examples, the circuit structure of the auxiliary driving unit is similar to the circuit structure of the first driving unit and the second driving unit. For example, the auxiliary driving unit may include at least: a first auxiliary capacitor, a first plate of the first auxiliary capacitor may be electrically connected to the pull-up node, and a second plate may be electrically connected to the output terminal of the auxiliary driving unit.

[0185] In some examples, such as Fig.17 As shown, the array substrate may further include: a plurality of (e.g., four) auxiliary scanning lines 31 located at the lower frame. The four auxiliary scanning lines 31 may be electrically connected to the four auxiliary driving units in a one-to-one correspondence. In this example, by providing auxiliary scanning lines electrically connected to the auxiliary driving units, not only a release path is provided for the output signals of the auxiliary driving units, but also process uniformity can be ensured.

[0186] Fig.18 It is a schematic plan view of the lower right corner of the array substrate of at least one embodiment of the present disclosure. Fig.19A for Fig.18 Schematic diagram of an array substrate after the first conductive layer is formed. Fig.19B for Fig.18 Schematic diagram of an array substrate after a semiconductor layer is formed. Fig.19C for Fig.18 Schematic diagram of the array substrate after the second conductive layer is formed. Fig.19D for Fig.19C Schematic diagram of the second conductive layer in . Fig.19E for Fig.18 Schematic diagram of the array substrate after the fourth insulating layer is formed. Fig.19F for Fig.18 Schematic diagram of the second transparent conductive layer in .

[0187] In some examples, such as Fig.19A As shown, the first conductive layer may include at least: a first electrode 381 of a first auxiliary capacitor 38 of two second auxiliary driving units 35a and 35b located in the right frame area B2, a second common voltage signal line 22 and a first voltage line 23, four auxiliary scanning lines 31 and a plurality of second dummy control blocks 141b located in the lower frame area B4, and a plurality of data lead lines 321.

[0188] In some examples, such as Fig.19A As shown, the second common voltage signal line 22 may include: a first signal segment 221 located in the right frame area B2 and a second signal segment 222 located in the lower frame area B4. The first signal segment 221 extends along the second direction Y, and the second signal segment 222 extends along the first direction X. The first signal segment 221 and the second signal segment 222 may be an integral structure connected to each other. For example, the first signal segment 221 may extend to the lower frame area B4 and be electrically connected to the integrated chip.

[0189] In some examples, such as Fig.19A As shown, the first electrodes 381 of the first auxiliary capacitors of the two second auxiliary driving units 35a and 35b can be arranged in sequence along the second direction Y and aligned with the first plates 281 of the first capacitors of the second driving units in the second direction Y.

[0190] In some examples, such as Fig.19AAs shown, the four auxiliary scan lines 31 may be located on a side of the second signal segment 222 of the second common voltage signal line 22 close to the display area AA. Each auxiliary scan line 31 may include an auxiliary scan connection end 311 and an auxiliary extension end 312. In the lower right corner area, the auxiliary extension ends 312 and the auxiliary scan connection ends 311 of the four auxiliary scan lines 31 may be arranged at intervals along the second direction Y. Each auxiliary scan line 31 may be electrically connected to a plurality of second dummy control blocks 141b arranged along the first direction X, for example, may be an integrated structure connected to each other. By providing a plurality of second dummy control blocks 141b, the first conductive layer pattern portion of the display area AA and the lower frame area B4 may be consistent, thereby ensuring process uniformity.

[0191] In some examples, such as Fig.19A As shown, the plurality of data lead lines 321 may be located at a side of the second signal segment 222 of the second common voltage signal line 22 away from the display area AA. The plurality of data lead lines 321 may extend to be electrically connected to the integrated chip.

[0192] In some examples, such as Fig.19B As shown, the semiconductor layer of the lower frame area B4 may include at least: a plurality of second dummy active blocks 140b. The plurality of second dummy active blocks 140b may be arranged in four rows and multiple columns. The orthographic projection of the second dummy active block 140b on the substrate may be located within the orthographic projection range of the second dummy control block 141b on the substrate. By setting a plurality of second dummy active blocks 140b, the present example can ensure process uniformity.

[0193] In some examples, such as Fig.19C and Fig.19D As shown, the dummy routing line 25 located in the right frame area B2 may include a first dummy routing line segment 251 and a second dummy routing line segment 252. The first dummy routing line segment 251 may have a first dummy connection portion 2511 and a second dummy connection portion 2512. The second dummy connection portion 2512 may extend to the lower frame area B4, and the orthographic projection of the second dummy connection portion 2512 on the substrate may overlap with the orthographic projection of the second signal segment 222 of the second common voltage signal line 22 on the substrate. The shape and connection method of the first dummy connection portion 2511 are similar to the third dummy connection portion and the fourth dummy connection portion of the second dummy routing line segment 252, so they are not repeated here. The dummy data line 18 in the display area AA may extend to the lower frame area B4 and be electrically connected to the second dummy connection portion 2512. For example, the dummy data line 18 and the second dummy connection portion 2512 may be an integrated structure connected to each other. The orthographic projection of the first dummy routing line segment 251 on the substrate may overlap with the orthographic projection of the auxiliary scanning connection end and the auxiliary extension end of the auxiliary scanning line on the substrate. In this example, the dummy routing line may not need to avoid the auxiliary scanning line.

[0194] In some examples, such as Fig.19C and Fig.19D As shown, the multiple data lines 12 in the display area AA can extend to the lower frame area B4. The multiple touch signal lines 16 can extend to the lower frame area B4 and be electrically connected to the multiple touch lead lines 322 in the lower frame area B4. For example, the touch signal lines 16 and the touch lead lines 322 can be an integrated structure connected to each other.

[0195] In some examples, such as Fig.19C and Fig.19D As shown, the auxiliary scanning line can be electrically connected to the output end of the second auxiliary driving unit through the fourth connecting line 233. A third connecting line 293 can be set between the second auxiliary driving units 35a and 35b. The second auxiliary driving units 35a and 35b can share the third connecting line 293 to be electrically connected to the first voltage line 23.

[0196] In some examples, such as Fig.19E As shown, the fourth insulating layer in the lower right corner area may be provided with a plurality of vias, for example, may include: an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17 and an eighteenth via V18.

[0197] In some examples, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the eleventh via hole V11 may be removed to expose a portion of the surface of the auxiliary scanning connection terminal 312 of the auxiliary scanning line. The fourth insulating layer, the third insulating layer, and the second insulating layer in the twelfth via hole V12 may be removed to expose a portion of the surface of the fourth connecting line 233. The fourth insulating layer, the third insulating layer, and the second insulating layer in the thirteenth via hole V13 may be removed to expose a portion of the surface of the first dummy connection portion 2511 of the first dummy routing segment 251 of the dummy routing line 25. The fourth insulating layer, the third insulating layer, and the second insulating layer in the fourteenth via hole V14 may be removed to expose a portion of the surface of the second dummy connection portion 2512 of the first dummy routing segment 251 of the dummy routing line 25. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the fifteenth via hole V15 may be removed to expose a portion of the surface of the first voltage line 23. The fourth insulating layer, the third insulating layer and the second insulating layer in the sixteenth via hole V16 may be removed to expose a portion of the surface of the third connection line 293. The fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the seventeenth via hole V17 may be removed to expose a portion of the surface of the data lead line 321. The fourth insulating layer, the third insulating layer and the second insulating layer in the eighteenth via hole V18 may be removed to expose a portion of the surface of the data line 12 extending to the lower frame area B4.

[0198] In some examples, such as Figures 18 to 19F As shown, the first common voltage signal line 21 may have a second hollow portion 212 at the lower right corner. The second hollow portion 212 may be aligned with the first hollow portion 211 in the second direction Y. The second hollow portion 212 may be located between the auxiliary drive unit and the auxiliary scan line in the first direction X. The orthographic projection of the second hollow portion 212 on the substrate may be roughly rectangular. The orthographic projection of the second hollow portion 212 on the substrate may cover the orthographic projection of three connection electrodes (for example, including a first connection electrode 41 and two fourth connection electrodes 44) on the substrate. The fourth connection electrode 44 may be electrically connected to the auxiliary scan connection terminal 311 of the auxiliary scan line through two eleventh vias V11 arranged vertically, and may also be electrically connected to the fourth connection line 233 through two twelfth vias V12 to achieve electrical connection with the output end of the second auxiliary drive unit. The first connection electrode and the two fourth connection electrodes 44 in the second hollow portion 212 may be arranged in sequence along the second direction Y.

[0199] In some examples, such as Figures 18 to 19F As shown, the first common voltage signal line 21 can be electrically connected to the first dummy connection portion 2511 of the first dummy routing segment 251 of the dummy routing line 25 through two thirteenth vias V13. The first common voltage signal line 21 can be electrically connected to the second dummy connection portion 2512 of the first dummy routing segment 251 of the dummy routing line 25 through four fourteenth vias V14 arranged in a 2×2 array.

[0200] In some examples, such as Figures 18 to 19F As shown, the fifth connection electrode 45 located in the second transparent conductive layer can be electrically connected to the first voltage line 23 through two fifteenth via holes V15, and can also be electrically connected to the third connection line 293 through two sixteenth via holes V16. The fifth connection electrode 45 can be located in a notch of the first common voltage signal line 21, so that the first common voltage signal line 21 avoids the fifth connection electrode 45, so as to ensure effective electrical connection between the auxiliary driving unit and the first voltage line.

[0201] In some examples, such as Figures 18 to 19F As shown, the sixth connection electrode 46 located in the second transparent conductive layer can be electrically connected to the data lead line 321 through two seventeenth via holes V17, and can also be electrically connected to the data line 12 through two eighteenth via holes V18, thereby realizing data signal transmission from the lower frame area to the display area. The plurality of sixth connection electrodes 46 can be located on the side of the first common voltage signal line 21 away from the display area AA.

[0202] The structure of the lower left corner of the array substrate of this example can refer to the structure of the lower right corner, and the remaining structures of the display area and the right frame area of ​​the array substrate of this example can refer to the description of the aforementioned embodiment, so it is not repeated here. Among them, the auxiliary scanning connection end of the auxiliary scanning line extending to the left frame area can be electrically connected to the first auxiliary driving unit.

[0203] The array substrate of this example can ensure the reset and driving effects of the first driving circuit and the second driving circuit by providing the auxiliary driving unit and the auxiliary scanning line, and can also ensure process uniformity.

[0204] Fig. 20 FIG. 4 is another schematic diagram of an array substrate according to at least one embodiment of the present disclosure. Fig.21 for Fig. 20 Schematic diagram of local film layer. In some examples, such as Fig. 20 and Fig.21 As shown, multiple dummy routing segments (including a first dummy routing segment 251 and a second dummy routing segment 252 ) of the dummy routing 25 located in the left frame area B1 and the right frame area B2 may all be electrically connected to the second common voltage signal line 22 .

[0205] The remaining structures of the array substrate of this example can be referred to the description of the aforementioned embodiment, so they will not be described again here.

[0206] Fig. 22 is another schematic diagram of an array substrate according to at least one embodiment of the present disclosure. Fig. 22 As shown, the dummy trace 25 located in the left frame area B1 and the right frame area B2 can be bent around the extended end 112 of the scan line, and the orthographic projections of the dummy trace 25 and the extended end 112 of the scan line on the substrate may not overlap. This example can avoid the dummy trace from crossing the extended end of the scan line, thereby reducing the risk of short circuit between the scan line and the dummy trace caused by electrostatic discharge at the extended end of the scan line, and further improve the horizontal stripe type functional display defect.

[0207] The remaining structures of the array substrate of this example can be referred to the description of the aforementioned embodiment, so they will not be described again here.

[0208] In other examples, the dummy traces provided in the left frame area (or right frame area) of the array substrate may adopt a disconnection design to avoid the extended ends of the scan lines, and the dummy traces provided in the right frame area (or left frame area) may adopt a bypassing design to avoid the extended ends of the scan lines. In other examples, the dummy traces provided in the left frame area or the right frame area of ​​the array substrate may adopt both a disconnection design and a bypassing design to avoid the extended ends of multiple scan lines. This embodiment is not limited to this.

[0209] At least one embodiment of the present disclosure further provides a display device, comprising the array substrate as described above.

[0210] In some examples, the display device may include: an array substrate, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. The pixel electrodes and common electrodes (reused as touch electrodes) included in the array substrate are used to generate an electric field for controlling the deflection of liquid crystal molecules in the liquid crystal layer. In some examples, the opposing substrate may include a base substrate, and a black matrix and a color filter layer disposed on the base substrate. However, this embodiment is not limited to this.

[0211] In some exemplary embodiments, the display device may be: a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with touch and display functions.

[0212] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures may refer to the usual design. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those of ordinary skill in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and should be included in the scope of the claims of the present disclosure.

Claims

1. An array substrate, characterized in that: include: A substrate, comprising a display area and a frame area located around the display area; A plurality of scan lines, at least located in the display area and extending along a first direction; at least one dummy trace, located in the frame region and extending along a second direction, wherein the second direction intersects the first direction; A scanning driving circuit is located in the frame area; At least one of the plurality of scan lines comprises: a scan connection end extending to the frame area and an extension end, the scan connection end being electrically connected to the scan driving circuit; The at least one dummy routing line is disconnected at an extended end of the at least one scan line, so that the at least one dummy routing line and the extended end of the at least one scan line have no overlap in an orthographic projection on the substrate.

2. The array substrate according to claim 1, characterized in that: The at least one dummy routing line includes: a plurality of dummy routing line segments arranged in sequence along the second direction, a first break is provided between adjacent dummy routing line segments in the second direction, and a length of the first break along the second direction is greater than a length of an extended end of the at least one scanning line along the second direction.

3. The array substrate according to claim 2, characterized in that: The array substrate also includes: a first common voltage signal line and a second common voltage signal line located in the border area; the first common voltage signal line is electrically connected to the second common voltage signal line, the first common voltage signal line is located on a side of the second common voltage signal line away from the substrate, and the first common voltage signal line and the second common voltage signal line at least partially overlap in their positive projections on the substrate.

4. The array substrate according to claim 3, characterized in that: At least one dummy routing segment of the at least one dummy routing line is electrically connected to at least one of the second common voltage signal line and the first common voltage signal line.

5. The array substrate according to claim 3, characterized in that: The array substrate further comprises: a plurality of first connection lines located in the frame area; The scan connection end of the scan line is electrically connected to the scan driving circuit through the first connection line; the first connection line is located on a side of the scan line away from the substrate.

6. The array substrate according to claim 5, characterized in that: The array substrate further comprises: a plurality of first connection electrodes located in the frame area; The scan connection end of the scan line is electrically connected to the first connection line through the first connection electrode, and the first connection electrode is located on a side of the first connection line away from the substrate.

7. The array substrate according to claim 6, characterized in that: The first connection electrode and the first common voltage signal line are in the same layer structure, the first common voltage signal line has a plurality of first hollow parts, and the orthographic projection of the first connection electrode on the substrate is located in the first hollow parts.

8. The array substrate according to claim 3, characterized in that: The array substrate further comprises: a first voltage line located in the frame area, and a plurality of second connection lines; The first voltage line is located at a side of the first common voltage signal line and the second common voltage signal line away from the display area, and is located at a side of the scan driving circuit close to the display area; The first voltage line is electrically connected to the scan driving circuit through the second connecting line, and the first voltage line is configured to provide a first voltage signal to the scan driving circuit.

9. The array substrate according to claim 8, characterized in that: The frame area at least includes: a left frame area and a right frame area located on both sides of the display area along the first direction; The scanning driving circuit comprises: a first driving circuit located in the left frame area, and a second driving circuit located in the right frame area; the first driving circuit comprises: a plurality of cascaded first driving units, and the second driving circuit comprises: a plurality of cascaded second driving units; In the left frame area, the 2a-1 level first driving unit and the 2a level first driving unit of the first driving circuit are electrically connected to the first voltage line through the same second connecting line; In the right frame area, the 2b-1-level second driving unit and the 2b-level second driving unit of the second driving circuit are electrically connected to the first voltage line through the same second connecting line; a and b are integers greater than 0.

10. The array substrate according to claim 8, characterized in that: The array substrate further comprises: a plurality of second connection electrodes located in the frame area, the first voltage line is electrically connected to the second connection line through the second connection electrodes; the second connection electrode is located on a side of the first voltage line and the second connection line away from the substrate, and the second connection electrode and the first common voltage signal line are in the same layer structure; The first common voltage signal line has a plurality of notches at an edge away from the display area, at least one notch is configured to accommodate a second connecting electrode, and the orthographic projection of the notch on the substrate covers the orthographic projection of the second connecting electrode on the substrate in the first direction.

11. The array substrate according to claim 10, characterized in that: The plurality of notches and the extending ends of the plurality of scanning lines are spaced apart along the second direction.

12. The array substrate according to claim 1, characterized in that: The frame area at least includes: a left frame area and a right frame area located on both sides of the display area along the first direction; The left frame area and the right frame area are both provided with at least one dummy wiring.

13. The array substrate according to claim 1, characterized in that: The frame area at least includes: a left frame area and a right frame area located on both sides of the display area along the first direction; In the left frame area or the right frame area, the scanning connection ends and the extending ends of the plurality of scanning lines are arranged at intervals along the second direction.

14. The array substrate according to claim 13, characterized in that: The array substrate further comprises: a plurality of sub-pixels located in the display area, the plurality of sub-pixels are arranged in a plurality of rows, and each row of sub-pixels comprises a plurality of sub-pixels arranged along the first direction; The scanning driving circuit comprises: a first driving circuit located in the left frame area, and a second driving circuit located in the right frame area; The scanning connection end of at least one scanning line extending to the left frame area is electrically connected to the first driving circuit; the first driving circuit is configured to provide a data signal to the 2i-1th row of sub-pixels in the display area; The scan connection end of at least one scan line extending to the right frame area is electrically connected to the second drive circuit; the second drive circuit is configured to provide a scan signal to the 2i-th row of sub-pixels in the display area; i is an integer greater than 0.

15. The array substrate according to claim 14, characterized in that: The frame area further includes: a lower frame area located at one side of the display area along the second direction; The array substrate further comprises: a plurality of auxiliary scanning lines located in the lower frame area and extending along the first direction, a plurality of first auxiliary driving units located in the left frame area, and a plurality of second auxiliary driving units located in the right frame area; The at least one auxiliary scanning line comprises: an auxiliary scanning connection end extending to the left frame area and an auxiliary extension end extending to the right frame area; or an auxiliary scanning connection end extending to the right frame area and an auxiliary extension end extending to the left frame area; The auxiliary scanning connection end of the at least one auxiliary scanning line is electrically connected to the first auxiliary driving unit or the second auxiliary driving unit; In the left frame area or the right frame area, the auxiliary scanning connection ends and the auxiliary extension ends of the plurality of auxiliary scanning lines are arranged at intervals along the second direction.

16. The array substrate according to claim 15, characterized in that: The plurality of first auxiliary driving units are configured to provide a reset signal to the first driving circuit; and the plurality of second auxiliary driving units are configured to provide a reset signal to the second driving circuit.

17. The array substrate according to claim 1, characterized in that: The at least one dummy wiring goes around an extended end of the at least one scan line from a side away from the display area.

18. A display device, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 17.

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