Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a substrate and a driving circuit layer, the driving circuit layer comprises a light shielding layer, a first active layer, a first gate layer and a second active layer, the light shielding layer comprises a first light shielding part, the first gate layer comprises a first gate of a compensation transistor, and the first gate of the compensation transistor and an active pattern of the compensation transistor are correspondingly arranged. The first shading part is arranged corresponding to the active pattern of the first initialization transistor, the first gate layer can be adopted to form the bottom gate of the compensation transistor, the shading layer can be adopted to form the bottom gate of the first initialization transistor, and the distance between the first gate layer and the second active layer is small, so that the electrical property improvement effect on the compensation transistor is good; as the space of the light shielding layer is large, the bottom gate of the first initialization transistor arranged on the light shielding layer does not have a short circuit problem, and the yield of the display panel and the electrical property of the oxide thin film transistor are both considered.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display devices, the requirements of existing display devices for power consumption and screen-to-body ratio are getting higher and higher. In order to reduce power consumption and increase screen-to-body ratio, existing display devices will adopt low-temperature polysilicon oxide (LTPO) technology. LTPO technology refers to the use of low-temperature polysilicon thin-film transistors and oxide thin-film transistors at the same time, so that the driving circuit takes into account the advantages of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, thereby reducing power consumption and leakage current. However, the existing display devices using LTPO technology have a large number of film layers, and the corresponding number of required masks is large, resulting in a more complex process and higher cost. In order to reduce the number of mask plates, existing display devices will remove some gate layers and insulating layers, but this will cause the bottom gate of the oxide thin-film transistor to be missing, and the photosensitivity and electrical properties of the thin-film transistor will deteriorate. In order to improve the electrical properties of the oxide thin-film transistor, the existing technology will use some film layers to form the bottom gate of the oxide thin-film transistor, but there will be some problems. For example, the distance between some film layers and the active layer of the oxide thin-film transistor is too far, resulting in a small bottom gate effect, and the distance between some film layers and the active layer of the oxide thin-film transistor is close, but the space of the film layer is limited, which is easy to cause short-circuit failure problems.

[0003] Therefore, existing display devices using LTPO technology have the technical problem of being unable to take into account both the yield and the electrical properties of oxide thin film transistors. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem that the existing display devices using LTPO technology cannot take into account both the yield and the electrical properties of oxide thin film transistors.

[0005] An embodiment of the present application provides a display panel, which includes a substrate and a driving circuit layer arranged on one side of the substrate, wherein the driving circuit layer includes a pixel driving circuit, and the pixel driving circuit includes a switching transistor, a driving transistor, a compensation transistor and a first initialization transistor, wherein the switching transistor and the driving transistor are connected to a first node; an electrode of the compensation transistor, an electrode of the first initialization transistor and the driving transistor are connected to a second node, and another electrode of the compensation transistor and the driving transistor are connected to a third node; wherein the driving circuit layer includes:

[0006] A light shielding layer, wherein the light shielding layer comprises a first light shielding portion;

[0007] A first active layer is disposed on a side of the light shielding layer away from the substrate;

[0008] A first gate layer, disposed on a side of the first active layer away from the substrate, the first gate layer comprising a first gate of the compensation transistor;

[0009] A second active layer, disposed on a side of the first gate layer away from the substrate, the second active layer comprising an active pattern of the compensation transistor and an active pattern of the first initialization transistor;

[0010] The first gate of the compensation transistor is arranged corresponding to the active pattern of the compensation transistor, and the first light shielding portion is arranged corresponding to the active pattern of the first initialization transistor.

[0011] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0012] Beneficial effects: The present application provides a display panel and a display device; the display panel includes a substrate and a driving circuit layer, the driving circuit layer includes a light shielding layer, a first active layer, a first gate layer and a second active layer, by making the light shielding layer include a first light shielding portion, the first gate layer includes a first gate of a compensation transistor, so that the first gate of the compensation transistor is arranged corresponding to the active pattern of the compensation transistor, and the first light shielding portion is arranged corresponding to the active pattern of the first initialization transistor, then the first gate layer can be used to form the bottom gate of the compensation transistor, and the light shielding layer can be used to form the bottom gate of the first initialization transistor. Since the distance between the first gate layer and the second active layer is small, the electrical property of the compensation transistor is better improved. Since the space of the light shielding layer is large, there will be no short circuit problem when the bottom gate of the first initialization transistor is arranged in the light shielding layer, thereby taking into account both the yield of the display panel and the electrical property of the oxide thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0014] Figure 1 A schematic diagram of a first comparative display device provided in an embodiment of the present application.

[0015] Figure 2 A schematic diagram of a second comparative display device provided in an embodiment of the present application.

[0016] Figure 3 A schematic diagram of a third comparative display device provided in an embodiment of the present application.

[0017] Figure 4 A schematic diagram of a film layer of a display panel provided in an embodiment of the present application.

[0018] Figure 5 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application.

[0019] Figure 6 A stacking diagram of the film layers of the display panel provided in an embodiment of the present application.

[0020] Figure 7 for Figure 6 Exploded view of the light shielding layer of the display panel.

[0021] Figure 8 for Figure 6 Exploded view of the first active layer of the display panel in FIG.

[0022] Fig. 9 for Figure 6 An exploded view of the first gate layer of the display panel in FIG.

[0023] Fig.10 for Figure 6 Exploded view of the second active layer of the display panel in FIG.

[0024] Fig.11 for Figure 6 An exploded view of the second gate layer of the display panel in FIG.

[0025] Fig.12 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG.

[0026] Fig.13 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG.

[0027] Fig.14 for Figure 6 Exploded view of the first via hole of the display panel.

[0028] Fig.15 for Figure 6 Exploded view of the second via hole of the display panel.

[0029] Fig.16 for Figure 6 An exploded view of the third via hole of the display panel in FIG.

[0030] Fig.17 for Figure 6 An exploded view of the fourth via hole of the display panel in FIG. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0032] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0033] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0034] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0035] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0036] Figure 1 A schematic diagram of a first comparative display device provided in an embodiment of the present application. Figure 2 A schematic diagram of a second comparative display device provided in an embodiment of the present application. Figure 3 A schematic diagram of a third comparative display device provided in an embodiment of the present application.

[0037] like Figures 1 to 3 As shown, as an introduction to the embodiments of the present application, some comparative display devices are provided to illustrate the principle of the technical problem to be solved by the embodiments of the present application. Figure 1 As shown, a comparative display device using LTPO technology includes a substrate 101, a light shielding film 102, a barrier film 103, a buffer film 104, a low-temperature polysilicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarizing film 117, a second source-drain film 118, a second planarizing film 119, a third source-drain film 121, a third planarizing film 122, an anode film 123, a pixel definition film 124, and a support film 125. Figure 1 It can be seen that the comparative display device includes three layers of source and drain films and three layers of gate films, so that the comparative display device needs to be formed using 16 mask plates, the process is relatively complex and the cost is relatively high.

[0038] In order to solve the problem of complex process of the comparative display device, another comparative display device removes one layer of the gate film and the insulating film, such as Figure 2 As shown, it can be seen that the second gate film 109 and the second gate insulating film 108 are removed from the comparative display device, so that the number of mask plates can be reduced to 14, but there are still problems such as a large number of mask plates, a complex process, and a high cost.

[0039] In order to further solve the problem of complex process of the comparative display device, another comparative display device further removes a layer of source and drain film and insulating film, such as Figure 3 As shown in FIG. 1 , by removing the third source-drain film 121 and the third planarization film 122, the number of mask plates can be reduced to 13; Figure 2 , Figure 3 It can be seen that there is no shielding under the oxide semiconductor film 112, resulting in the missing bottom gate of the oxide thin film transistor, and the photosensitivity and electrical properties of the thin film transistor are deteriorated.

[0040] To solve Figure 3 Some display devices represented by the comparative display devices shown have the problem of missing bottom gates of oxide thin film transistors. Some comparative display devices use a light shielding film to form the bottom gates of oxide thin film transistors, and make the bottom gates of the oxide thin film transistors transmit the signal of the high potential power supply terminal or the signal of the scanning line connected to each oxide thin film transistor. However, due to the long distance between the light shielding film and the oxide semiconductor film, the bottom gate effect of the oxide thin film transistor is weak, and the electrical properties of the oxide thin film transistor are still poor. In other comparative display devices, the comparative display devices use a first gate film to form the bottom gates of the oxide thin film transistors, but in the comparative display devices, the scanning lines and the gate drive circuit signal lines are all formed by the first gate film, and the number of wirings in the first gate film is large. At this time, it is difficult to increase the bottom gate of the oxide thin film transistor. Since the bottom gate of the compensation transistor needs to be connected to the output end of the gate drive circuit, the wiring is easily short-circuited with other signal lines in the first gate film, resulting in display failure. Therefore, the existing display devices using LTPO technology have the technical problem of not being able to take into account both the yield and the electrical properties of the oxide thin film transistor.

[0041] In view of the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0042] Figure 4 A schematic diagram of a film layer of a display panel provided in an embodiment of the present application. Figure 5 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application. Figure 6 A stacking diagram of the film layers of the display panel provided in an embodiment of the present application. Figure 7 for Figure 6 Exploded view of the light shielding layer of the display panel. Figure 8 for Figure 6 Exploded view of the first active layer of the display panel in FIG. Fig. 9 for Figure 6 An exploded view of the first gate layer of the display panel in FIG. Fig.10 for Figure 6 Exploded view of the second active layer of the display panel in FIG. Fig.11 for Figure 6 An exploded view of the second gate layer of the display panel in FIG. Fig.12 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG. Fig.13 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG. Fig.14 for Figure 6 Exploded view of the first via hole of the display panel. Fig.15 for Figure 6 Exploded view of the second via hole of the display panel. Fig.16 for Figure 6 An exploded view of the third via hole of the display panel in FIG. Fig.17 for Figure 6 An exploded view of the fourth via hole of the display panel in FIG.

[0043] like Figures 4 to 17 As shown, an embodiment of the present application provides a display panel, the display panel 2 includes a substrate 201 and a driving circuit layer 22, the driving circuit layer 22 is arranged on one side of the substrate 201, the driving circuit layer 22 includes a light shielding layer 202, a first active layer 205, a first gate layer 207 and a second active layer 209, the light shielding layer 202 is arranged between the substrate 201 and the first active layer 205, the first active layer 205 is arranged between the light shielding layer 202 and the first gate layer 207, and the driving circuit layer 22 also includes a pixel driving circuit 31;

[0044] The pixel driving circuit 31 includes: a switch transistor T2, a driving transistor T1, a compensation transistor T3 and a first initialization transistor T4, wherein the switch transistor T2 and the driving transistor T1 are connected to a first node A; one electrode of the compensation transistor T3, one electrode of the first initialization transistor T4 and the driving transistor T1 are connected to a second node Q, and the other electrode of the compensation transistor T3 and the driving transistor T1 are connected to a third node B;

[0045] The second active layer 209 includes the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4, the light-shielding layer 202 includes a first light-shielding portion 202a, the first gate layer 207 includes a first gate T3Ga of the compensation transistor T3, the first gate T3Ga of the compensation transistor T3 is arranged corresponding to the active pattern T3A of the compensation transistor T3, and the first light-shielding portion 202a is arranged corresponding to the active pattern of the first initialization transistor T4.

[0046] An embodiment of the present application provides a display panel, which includes a substrate and a driving circuit layer, the driving circuit layer includes a light shielding layer, a first active layer, a first gate layer and a second active layer. The light shielding layer includes a first light shielding portion, and the first gate layer includes a first gate of a compensation transistor, so that the first gate of the compensation transistor is arranged corresponding to the active pattern of the compensation transistor, and the first light shielding portion is arranged corresponding to the active pattern of a first initialization transistor. The first gate layer can be used to form a bottom gate of the compensation transistor, and the light shielding layer can be used to form a bottom gate of the first initialization transistor. Since the distance between the first gate layer and the second active layer is small, the electrical property of the compensation transistor is better improved. Since the space of the light shielding layer is large, there will be no short circuit problem when the bottom gate of the first initialization transistor is arranged in the light shielding layer, thereby taking into account both the yield of the display panel and the electrical property of the oxide thin film transistor.

[0047] Specifically, in the embodiment of the present application, the light shielding portion is set corresponding to the active pattern of the transistor, which means that the light shielding portion is set corresponding to at least the channel portion of the transistor, and the projection of the light shielding portion on the substrate overlaps with the projection of the channel portion of the transistor on the substrate. It can be understood that the active pattern of each transistor includes a doping portion and a channel portion, and the channel portion is easily affected by light, resulting in changes in performance, and the corresponding arrangement of the electrode and the channel portion can improve the gate control capability. Therefore, the light shielding portion can be set corresponding to the channel portion of the transistor. Specifically, for example, the first light shielding portion is set corresponding to the active pattern of the first initialization transistor, which means that the first light shielding portion is set corresponding to at least the channel portion of the first initialization transistor. Similarly, the first gate of the compensation transistor is set corresponding to the active pattern of the compensation transistor, which means that the first gate of the compensation transistor is set corresponding to at least the channel portion of the compensation transistor.

[0048] Specifically, compared with the comparative display device in which a shading film is used to form the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor respectively, and the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor are respectively input with corresponding scanning signals or input with high-potential power supply signal lines, there will be problems such as a long distance between the bottom gates and a weak bottom gate effect; compared with the comparative display device in which a first gate film is used to form the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor respectively, and the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor are respectively input with corresponding scanning signals, there will be problems such as a small space for the first gate film that is difficult to implement and is prone to short circuits. The embodiment of the present application takes into account that the electrical properties of the compensation transistor have a great influence on the display panel, which is specifically related to the afterimage, flicker, life, optical properties and other properties of the display panel, and the function of the first initialization transistor is to reset the second node Q. Therefore, the first gate layer forms the bottom gate of the compensation transistor, the light shielding layer forms the first light shielding portion, and the first light shielding portion is set to correspond to the active pattern of the first initialization transistor. Then, the space between the first gate layer and the light shielding layer can be taken into account to avoid the short circuit problem, and the electrical properties of the compensation transistor are better, so that the various characteristics of the display panel are better, thereby taking into account the yield of the display panel and the electrical properties of the oxide thin film transistor. In order to further avoid the problems such as short circuits caused by too many wirings in each film layer and improve the electrical properties of each wiring and each electrode, the positions of each wiring, each connecting wire and via will be further designed, and the specific design is as shown in the following embodiment.

[0049] Specifically, Figure 4 As shown, it can be seen that the driving transistor T1 uses part of the light shielding layer for light shielding, the compensation transistor T3 uses part of the first gate layer as the bottom gate of the compensation transistor, and the active pattern of the first initialization transistor T4 is set corresponding to the part of the light shielding layer.

[0050] Specifically, the light-shielding layer 202 is disposed on one side of the substrate 201 , the first active layer 205 is disposed on the side of the light-shielding layer 202 away from the substrate 201 , the first gate layer 207 is disposed on the side of the first active layer 205 away from the light-shielding layer 202 , and the second active layer 209 is disposed on the side of the first gate layer 207 away from the first active layer 205 .

[0051] In some embodiments, Figures 4 to 8As shown, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, each of the repeating units 30 includes two symmetrically arranged pixel driving circuits 31, and in the repeating unit 30, the light shielding layer 202 also includes two second light shielding portions 202b and a connecting portion 202c symmetrically arranged in the corresponding regions of the two pixel driving circuits 31, the connecting portion 202c includes a first connecting portion 321 arranged along a first direction X, a second connecting portion 322 arranged along the first direction X, and a third connecting portion 323 arranged along a second direction Y, and the first active layer 2 05 includes an active pattern T1A of a driving transistor T1, the second light-shielding portion 202b is arranged corresponding to the active pattern T1A of the driving transistor T1, the first connecting portion 321 connects the adjacent first light-shielding portion 202a, the second connecting portion 322 connects the adjacent second light-shielding portion 202b, one end of the third connecting portion 323 is connected to the first light-shielding portion 202a, and the other end of the third connecting portion 323 is connected to the second light-shielding portion 202b; an angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By making the light-shielding layer also include a second light-shielding portion and a connecting portion, and making the connecting portion include a first connecting portion, a second connecting portion and a third connecting portion, the first connecting portion connects the adjacent first light-shielding portion, the second connecting portion connects the adjacent second light-shielding portion, one end of the third connecting portion is connected to the first light-shielding portion, and the other end of the third connecting portion is connected to the second light-shielding portion, then the light-shielding layer can be gridded to improve the electrical properties of the light-shielding layer, and the first light-shielding portion can be used as the bottom gate of the first initialization transistor to improve the electrical properties of the first initialization transistor.

[0052] Specifically, it can be understood that the display panel may include a plurality of repeating units arranged in an array, and the pixel driving circuit in each repeating unit may refer to the design in a repeating unit described in the embodiment of the present application.

[0053] Specifically, it can be understood that in the display panel, two adjacent pixel units will be symmetrically arranged to increase the aperture ratio. The embodiment of the present application realizes the connection of the light-shielding parts in each row and column by arranging the light-shielding parts symmetrically and setting the first connecting part, the second connecting part and the third connecting part, thereby realizing the mesh structure of the light-shielding layer. When the signal is input, the voltage drops of various parts of the light-shielding layer are similar or even the same, thereby improving the uniformity of the signal and improving the display effect.

[0054] Specifically, it is understood that in order to illustrate the specific design of a certain film layer or a certain structure, the embodiments of the present application will name each part separately, but it is understood that multiple parts of a certain film layer or a certain structure will be formed at the same time, and when they are connected together, they will transmit the same signal. Multiple parts belonging to the same structure can actually use the same name. For example, Figure 7As shown, the first light shielding portion 202a, the second light shielding portion 202b, the first connecting portion 321, the second connecting portion 322, and the third connecting portion 323 in the light shielding layer 202 are actually multiple parts of the same structure, and the light shielding portions and connecting portions located in two repeating units are also multiple parts of the same structure, and the various parts are connected to each other. Without considering the voltage drop, the multiple parts of this structure transmit the same signal, and they can be named the same, for example, each part can be named as part of the light shielding portion. Similarly, for other film layers and other structures, please refer to the above description, and will not be repeated in the following embodiments.

[0055] Specifically, the second light shielding portion can transmit the signal of the high-potential power line, and the second light shielding portion can be connected to the high-potential power line.

[0056] Specifically, the first light shielding portion may serve as a bottom gate of the first initialization transistor.

[0057] Specifically, Figure 7 As shown, it can be seen that the second light shielding portions 202b in each repeating unit may be connected via the second connecting portion 322, but the first light shielding portions 202a in each repeating unit may not be connected.

[0058] In some embodiments, the light shielding layer 202 further includes a second light shielding portion 202b, the first active layer 205 includes an active pattern T1A of the driving transistor T1, the second light shielding portion 202b is arranged corresponding to the active pattern T1A of the driving transistor T1, and the first light shielding portion 202a and the second light shielding portion 202b are arranged at intervals. By arranging the first light shielding portion and the second light shielding portion at intervals, the first light shielding portion can transmit a signal line of a scanning line connected to the gate of the first initialization transistor, thereby improving the gate control capability of the first initialization transistor.

[0059] Specifically, when the first light shielding portion and the second light shielding portion are provided in the light shielding layer, the first light shielding portion and the second light shielding portion can be spaced apart, and the first light shielding portion and the second light shielding portion transmit different signals. The first light shielding portion transmits the signal of the scanning line connected to the gate of the first initialization transistor. The first light shielding portion serves as the bottom gate of the first initialization transistor to improve the electrical properties of the first initialization transistor. The second light shielding portion shields the active pattern of the driving transistor to prevent the active pattern of the driving transistor from being affected by light.

[0060] Specifically, the first light shielding portion may be connected to the third scanning signal line, the second light shielding portion may transmit the signal of the high potential power line, and the second light shielding portion may be connected to the high potential power line.

[0061] In some embodiments, the driving circuit layer 22 includes a plurality of pixel driving circuits 31 arranged in an array, the first light shielding portion 202a is arranged in a corresponding area of ​​the pixel driving circuit 31 along a first direction X, and the second light shielding portion 202b is arranged in a corresponding area of ​​the pixel driving circuit 31 along the first direction X. In the first direction X, the first light shielding portions 202a located in two adjacent pixel driving circuits 31 are connected, and the second light shielding portions 202b located in two adjacent pixel driving circuits 31 are connected. The driving circuit layer 22 also includes a scanning signal line (for example, a first scanning signal line Pscan), and the first direction X is the same as the setting direction of the scanning signal line. By setting the first light shielding portion along the first direction, connecting the first light shielding portions in two adjacent pixel driving circuits, and setting the second light shielding portion along the first direction, connecting the second light shielding portions in two adjacent pixel driving circuits, the first light shielding portions of each row can be connected, and the second light shielding portions of each row can be connected, so that the connection between the first light shielding portion and the signal terminal can be reduced, the connection between the second light shielding portion and the signal terminal can be reduced, the vias in the display panel can be reduced, and the stability of the display panel can be improved.

[0062] Specifically, the above embodiments are described by taking the connection of shading parts in different pixel driving circuits as an example, but the embodiments of the present application are not limited to this. The shading parts in the corresponding areas of different pixel driving circuits can be independently set and not connected.

[0063] In some embodiments, Figure 5 As shown, the gate of the switching transistor T2 is connected to the first scanning signal line Pscan, the first electrode of the switching transistor T2 is connected to the data line DATA, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at the first node A; the gate of the compensation transistor T3 is connected to the second scanning signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the third scanning signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node Q; the pixel driving circuit 31 also includes:

[0064] a first light emission control transistor T5, wherein a gate of the first light emission control transistor T5 is connected to the light emission control signal line EM, a first electrode of the first light emission control transistor T5 is connected to the high potential power line VDD, and a second electrode of the first light emission control transistor T5 is connected to the first electrode of the driving transistor T1 and a first node A;

[0065] A second light emission control transistor T6, wherein a gate of the second light emission control transistor T6 is connected to the light emission control signal line EM, and a first electrode of the second light emission control transistor T6 and a second electrode of the driving transistor T1 are connected to a third node B;

[0066] a second initialization transistor T7, wherein a gate of the second initialization transistor T7 is connected to a fourth scanning signal line Pscan2, a first electrode of the second initialization transistor T7 is connected to a second initialization signal line VI-ANO, and a second electrode of the second initialization transistor T7 and a second electrode of the second light emission control transistor T6 are connected to a fourth node C;

[0067] a third initialization transistor T8, wherein a gate of the third initialization transistor T8 is connected to the fourth scan signal line Pscan2, a first electrode of the third initialization transistor T8 is connected to the third initialization signal line VI3, and a second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T1 to a first node A;

[0068] A storage capacitor Cst, one plate of the storage capacitor Cst is connected to the high potential power line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1 at a second node Q;

[0069] A boost capacitor Cboost, wherein one plate of the boost capacitor Cboost is connected to the first scanning signal line, and the other plate of the boost capacitor is connected to the second electrode of the first initialization transistor.

[0070] Specifically, Figure 4 , Figure 5 As shown, the display panel 2 also includes a light-emitting layer 23, which includes a light-emitting device LED. The light-emitting device LED is connected to the pixel driving circuit, the positive electrode of the light-emitting device LED is connected to the second electrode of the second initialization transistor T7, and the negative electrode of the light-emitting device LED is connected to the low potential power line VSS.

[0071] In some embodiments, Figure 4As shown, the driving circuit layer 22 further includes a second gate layer 212, a first source-drain electrode layer 214, and a second source-drain electrode layer 216. The second active layer 209 is disposed between the first gate layer 207 and the second gate layer 212. The second gate layer 212 is disposed between the second active layer 209 and the first source-drain electrode layer 214. The first source-drain electrode layer 214 is disposed between the second gate layer 212 and the second source-drain electrode layer 216. By making the driving circuit layer include the first gate layer, the second gate layer, the first source-drain electrode layer, and the second source-drain electrode layer, the process steps of the display panel can be reduced, and the mask plates required to form the display panel can be reduced.

[0072] In some embodiments, Figure 4 , Figure 6 , Figure 8 As shown, the first active layer 205 includes an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, an active pattern T5A of a first light-emitting control transistor T5, an active pattern T6A of a second light-emitting control transistor T6, an active pattern T7A of a second initialization transistor T7, and an active pattern T8A of a third initialization transistor T8, the active pattern T1A of the driving transistor T1 is arranged along a first direction X, and the active pattern T1A of the driving transistor T1 is connected to the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5, and the active pattern T6A of the second light-emitting control transistor T6, the active pattern T2A of the switching transistor T2 is connected to the active pattern T5A of the first light-emitting control transistor T5, and the active pattern T6A of the second light-emitting control transistor T6. T5A is arranged along the second direction Y, the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7 are arranged along the second direction Y, and the active pattern T6A of the second light-emitting control transistor T6 is connected to the active pattern T7A of the second initialization transistor T7, the active pattern T8A of the third initialization transistor T8 is arranged at intervals with the active pattern T1A of the driving transistor T1, the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5, the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7; the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0073] In some embodiments, Figures 4 to 6 , Fig. 9As shown, the first gate layer 207 includes a first scanning signal line Pscan, a first electrode Cst1 of a storage capacitor Cst, a light-emitting control signal line EM, a fourth scanning signal line Pscan2, a first initialization connection line L1, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light-emitting control transistor T5, a gate T6G of a second light-emitting control transistor T6, a gate T7G of a second initialization transistor T7, and a gate T8G of a third initialization transistor T8; the first scanning signal line Pscan, the first gate T3Ga of the compensation transistor T3, the first electrode Cst1 of the storage capacitor Cst, the light-emitting control signal line EM, the fourth scanning signal line Pscan2, and the first initialization connection line L1 are sequentially arranged in intervals along the second direction Y. By arranging the first gate of the compensation transistor in the first gate layer, the first gate of the compensation transistor is arranged between the first electrode of the storage capacitor and the first scanning signal line, so that the first gate of the compensation transistor is spaced apart from other electrodes, thereby avoiding short circuits between the compensation transistor and other electrodes and improving the yield of the display panel.

[0074] Specifically, from Fig. 9 It can be seen that the gate T2G of the switch transistor T2 is a part of the first scan signal line Pscan. It can be understood that since the gates T2G of all the switch transistors T2 in a row of pixel units are connected to the same first scan signal line Pscan, when the first scan signal line Pscan is formed, the portion of the first scan signal line corresponding to the channel of the switch transistor T2 of each pixel unit serves as the gate of the switch transistor T2 of each pixel unit. Therefore, two reference numerals are used to identify the same structure. Similarly, the gate T1G of the drive transistor T1 serves as both the gate and the first gate of the storage capacitor Cst. The electrode plate Cst1, the portion of the channel of the first light-emitting control transistor T5 corresponding to the light-emitting control signal line EM serves as the gate T5G of the first light-emitting control transistor T5, the portion of the channel of the second light-emitting control transistor T6 corresponding to the light-emitting control signal line EM serves as the gate T6G of the second light-emitting control transistor T6, the portion of the channel of the fourth scanning signal line Pscan2 corresponding to the second initialization transistor T7 serves as the gate T7G of the second initialization transistor T7, and the portion of the channel of the third initialization transistor T8 corresponding to the fourth scanning signal line Pscan2 serves as the gate T8G of the third initialization transistor T8.

[0075] In some embodiments, Fig.10As shown, the second active layer 209 further includes a second plate Cst2 of a storage capacitor Cst, the active pattern T3A of the compensation transistor T3 is connected to the active pattern T4A of the first initialization transistor T4, the second plate Cst2 of the storage capacitor Cst is arranged at one side of the active pattern T3A of the compensation transistor T3 along the first direction X, and a through hole 331 is provided on the second plate Cst2 of the storage capacitor Cst. By forming the second plate of the storage capacitor with the second active layer, a storage capacitor can be provided in the pixel driving circuit, and a through hole is provided on the second plate of the storage capacitor, so that the first electrode of the compensation transistor can be normally connected to the gate of the driving transistor.

[0076] Specifically, it can be understood that the second active layer forms the second electrode of the storage capacitor. Therefore, it is necessary to make the second electrode of the storage capacitor have better electrical properties. The second electrode of the storage capacitor can be doped to keep the electrical properties of the second electrode of the storage capacitor consistent with or even higher than the electrical properties of the doped portion of the active pattern, so that the electrical properties of the storage capacitor are better.

[0077] Specifically, by providing a through hole on the second electrode plate of the storage capacitor, the first electrode of the compensation transistor can pass through the second electrode plate of the storage capacitor and be connected to the gate of the driving transistor, so that the pixel driving circuit can work normally.

[0078] Specifically, Fig. 9 , Fig.10 As shown, the first gate layer 207 also includes a first plate Cboost1 of a boost capacitor Cboost, the second active layer 209 also includes a second plate Cboost2 of the boost capacitor Cboost, the overlapping portion of the first scanning signal line Pscan and the active pattern T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping portion of the active pattern T4A of the first initialization transistor T4 and the first scanning signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0079] In some embodiments, Figures 4 to 6 , Fig.11 As shown, the second gate layer 212 includes a second scan signal line Nscan1, a third scan signal line Nscan2, a second initialization signal line VI-ANO, a second gate T3Gb of the compensation transistor T3 and a gate T4G of the first initialization transistor T4, and the third scan signal line Nscan2, the second scan signal line Nscan1 and the second initialization signal line VI-ANO are arranged in sequence along the second direction Y.

[0080] Specifically, the projection of the first light shading portion on the substrate may overlap with the projection of the third scanning signal line on the substrate, thereby reducing the coupling capacitance between the first light shading portion and other signal lines. Even if the first light shading portion is coupled with the third scanning signal line, since the first light shading portion is arranged corresponding to the active pattern of the first initialization transistor, the potential of the first light shading portion can be the potential of the third scanning signal line, thereby improving the gate control capability of the first initialization transistor.

[0081] Specifically, the first light shielding portion can be regarded as the first gate of the first initialization transistor, and correspondingly, the gate of the first initialization transistor located in the second gate layer is the second gate of the first initialization transistor.

[0082] Specifically, the projection of the first gate of the compensation transistor on the substrate may overlap with the projection of the second scanning signal line on the substrate, thereby reducing the coupling capacitance between the first gate of the compensation transistor and other signal lines. When the first gate of the compensation transistor is coupled with the second scanning signal line, both transmit the driving signal of the gate of the compensation transistor, which can improve the gate control capability of the first initialization transistor.

[0083] In some embodiments, Figures 4 to 6 , Fig.12 As shown, the first source-drain layer 214 includes a first initialization signal line VI-G, a first electrode T4S of the switch transistor T2, a second electrode T2D of the switch transistor T2, a first electrode T3S of the compensation transistor T3, a second electrode T3D of the compensation transistor T3, a first electrode T4S of the first initialization transistor T4, a second electrode T4D of the first initialization transistor T4, a first electrode T5S of the first light-emitting control transistor T5, a second electrode T5D of the first light-emitting control transistor T5, a first electrode T6S of the second light-emitting control transistor T6, a second electrode T6D of the second light-emitting control transistor T6, a first electrode T6S of the second initialization transistor T7, The first switching line L2 is connected to the first gate T3Ga of the compensation transistor T3 and the second scanning signal line Nscan1, the second switching line L4 is connected to the second initialization signal line VI-ANO and the first electrode T7S of the second initialization transistor T7, the second electrode T7D of the second initialization transistor T7, the first electrode T8S of the third initialization transistor T8, the second electrode T8D of the third initialization transistor T8, the first switching line L2, the first data connection line L3, the second switching line L4 and the third initialization signal line VI3, the first switching line L2 is connected to the first gate T3Ga of the compensation transistor T3 and the second scanning signal line Nscan1, the second switching line L4 is connected to the second initialization signal line VI-ANO and the first electrode T7S of the second initialization transistor T7, and the third initialization signal line VI3 is connected to the first initialization connection line L1.

[0084] Specifically, the embodiment of the present application forms a first gate of the compensation transistor on the first gate layer, forms a second scanning signal line on the third gate layer, and forms a first transfer line on the first source and drain layer, and uses two close-range drillings to connect the first transfer line to the second scanning signal line and the first gate, thereby saving space, and two sub-pixel units can share the same first transfer line and via, reducing the number of vias, saving space, and improving pixel density.

[0085] Specifically, by forming the third initialization signal line in the first source-drain layer and connecting the third initialization signal line to the first initialization connection line, a row of third initialization signal lines is connected, without requiring multiple input terminals for signal input.

[0086] Specifically, Fig.12 As shown, it can be understood that since the electrodes of each transistor are connected together, in order to improve the aperture ratio in actual design, the electrodes of each transistor share the same structure. Fig.12 In the figure, multiple reference numerals are used to identify the same structure. For example, a structure serves as both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4. Figure 5 As can be seen in , this is the location where the second node Q is connected. Similarly, other structures can also serve as multiple electrodes, and the location of each node can be determined accordingly.

[0087] Specifically, since some electrodes and / or signal lines are connected together, only one electrode or one signal line may be marked on a structure. It is understandable that the structure may also be other electrodes or signal lines connected to the electrode or signal line.

[0088] In some embodiments, Figures 4 to 6 , Fig.13 As shown, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, each of the repeating units 30 includes two symmetrically arranged pixel driving circuits 31, and within the repeating unit 30, the second source and drain layer 216 includes two second data connection lines L5, two data lines DATA, two high potential power lines VDD and a second initialization connection line L6, the two second data connection lines L5 are symmetrically arranged, and a break is provided on the second data connection line L5, the two data lines DATA are symmetrically arranged, the two high potential power lines VDD are symmetrically arranged, and the second initialization connection line L6 is connected to the second initialization signal line VI-ANO.

[0089] Specifically, by arranging the second initialization connection line in the second source-drain layer and connecting the second initialization signal line to the second initialization connection line, the second initialization signal line can be gridded and the voltage drop of the second initialization signal line can be reduced.

[0090] Specifically, it can be understood that due to the design of some pixel driving circuits in the display area shown in the embodiment of the present application, the connection points of some routing lines may be located in other pixel driving circuits or outside the display area. Therefore, some routing lines may not be connected together, but in fact, they will be connected. For example, in order to adopt the technology of setting the fan-out line in the display area (Fanout In AA, FIAA), the data line DATA will be set along the first direction. The first data connection line L3 set along the first direction and the second data connection line L5 set along the second direction will be connected, and will be connected to some data lines. However, the embodiment of the present application shows the design of some pixel driving circuits, and therefore, its connection points are not shown, but in fact, they will be connected.

[0091] Specifically, Figure 6 , Fig.10 , Fig.12 , Fig.13 As shown, the first source-drain electrode layer 214 further includes a first connection terminal K1 and a second connection terminal K2, the high potential power line VDD is connected to the first connection terminal K1, the first connection terminal K1 is connected to the second connection terminal K2, and the second connection terminal K2 is connected to the second electrode plate Cst2 of the storage capacitor Cst and the first electrode T5S of the first light-emitting control transistor T5, thereby realizing the connection between the high potential power line and the second electrode plate of the storage capacitor and the first electrode of the first light-emitting control transistor. In view of the fact that the high potential power line and the first electrode of the first light-emitting control transistor do not overlap, and due to the existence of other signal lines, the high potential power line cannot be directly punched and connected to the second electrode plate of the storage capacitor, the embodiment of the present application sets the first connection terminal and the second connection terminal on the first source-drain electrode layer, and respectively connects the high potential power line and the second electrode plate of the storage capacitor through the first connection terminal and the second connection terminal, so as to realize the connection between the high potential power line, the second electrode plate of the storage capacitor and the first electrode of the first light-emitting control transistor.

[0092] Specifically, Figures 5 to 12 As shown, the first source-drain layer 214 also includes a third connection terminal K3, and the first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1. Therefore, the third connection terminal K3 can be set in the first source-drain layer, and the third connection terminal K3 is connected to the gate T1G of the driving transistor T1 through the through hole 331, thereby realizing the connection between the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0093] Specifically, Figures 5 to 13 As shown, the second source-drain electrode layer 216 further includes a fourth connection terminal K4, and the fourth connection terminal K4 is connected to the second electrode T6D of the second light emitting control transistor T6 and an electrode of the light emitting device.

[0094] Specifically, since the active parts of some transistors are connected together, some nodes and electrodes in the circuit diagram are not marked. For example, the first node A is the connection node of the first electrode of the driving transistor T1, the second electrode of the switching transistor T2 and the second electrode of the first light-emitting control transistor T5, and the active parts of the driving transistor T1, the switching transistor T2 and the first light-emitting control transistor T5 share the same structure. Therefore, there is no need to separately set the first electrode of the driving transistor T1, the second electrode of the switching transistor T2 and the second electrode of the first light-emitting control transistor T5. Accordingly, the first node A does not exist in the exploded view of each film layer. It can be understood that the first node A is located at the connection point of the active parts of the driving transistor T1, the switching transistor T2 and the first light-emitting control transistor T5.

[0095] In some embodiments, Fig.14 As shown, Fig.14 The arrangement position of the first via hole 341 is shown. The first via hole 341 refers to a via hole etched from the first source and drain electrode layer to the first active layer or the first gate layer.

[0096] In some embodiments, Fig.15 As shown, Fig.15 The arrangement position of the second via hole 342 is shown. The second via hole 342 refers to a via hole etched from the first source and drain electrode layer to the second active layer or the second gate layer.

[0097] In some embodiments, Fig.16 As shown, Fig.16 The configuration position of the third via hole 343 is shown. The third via hole 343 refers to a via hole etched from the second source and drain electrode layer to the first source and drain electrode layer.

[0098] In some embodiments, Fig.17 As shown, Fig.17 The fourth via hole 344 is shown as a location where the fourth via hole 344 is etched from the anode of the light emitting layer to the second source and drain layer.

[0099] In some embodiments, the first light shielding portion is connected to the third scanning signal line. By connecting the first light shielding portion to the third scanning signal line, the first light shielding portion can be used as a bottom gate of the first initialization transistor, thereby improving the electrical properties of the first initialization transistor.

[0100] Specifically, the first light shielding portion and the third scanning signal line may be connected via other connecting lines, or may be directly connected via punching.

[0101] Specifically, in the above embodiments, when the transistor has a bottom gate and a top gate, the gate of the transistor refers to the first gate and the second gate of the transistor.

[0102] Specifically, Figure 4 As shown, the driving circuit layer 22 further includes a blocking layer 203 , a buffer layer 204 , a first gate insulating layer 206 , a first interlayer insulating layer 208 , a second gate insulating layer 211 , a second interlayer insulating layer 213 , a first planarizing layer 215 and a second planarizing layer 217 .

[0103] Specifically, Figure 4 As shown, the display panel 2 further includes a light-emitting layer 23 , and the light-emitting layer 23 includes a pixel electrode layer 218 , a pixel definition layer 219 , a light-emitting material layer, a common electrode layer and a support column 221 .

[0104] Specifically, the first electrode of the transistor in the above embodiment is a source, and the second electrode is a drain; or the first electrode of the transistor in the above embodiment is a drain, and the second electrode is a source.

[0105] Specifically, the first scanning signal line Pscan, the second scanning signal line Nscan1, the third scanning signal line Nscan2, the fourth scanning signal line Pscan2 and the light-emitting control signal line EM can be respectively connected to different gate driving circuits. Specifically, five groups of gate driving circuits can be used to output signals to the first scanning signal line Pscan, the second scanning signal line Nscan1, the third scanning signal line Nscan2, the fourth scanning signal line Pscan2 and the light-emitting control signal line EM, respectively. Among them, the gate driving circuit connected to the first scanning signal line Pscan can adopt bilateral driving, and the other gate driving circuits adopt unilateral driving.

[0106] Specifically, the material of the first active layer includes silicon semiconductor material, specifically low temperature polysilicon.

[0107] Specifically, the material of the second active layer includes an oxide semiconductor material, specifically a metal oxide semiconductor material, and more specifically, indium gallium zinc oxide.

[0108] Specifically, the material of the light shielding layer may include metal material.

[0109] Specifically, the driving transistor, the switching transistor, the first light emission control transistor, the second light emission control transistor, the second initialization transistor and the third initialization transistor are P-type transistors, and the first initialization transistor and the compensation transistor are N-type transistors.

[0110] Specifically, the above embodiments respectively describe the display panel in detail from the perspective of the pixel driving circuit, film layer structure, specific structure, material, and potential of each layer in the display panel. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the light-shielding layer also includes a second light-shielding portion, the first active layer includes an active pattern of the driving transistor, the second light-shielding portion is arranged corresponding to the active pattern of the driving transistor, and the first light-shielding portion and the second light-shielding portion are arranged alternately, and the first light-shielding portion is connected to the third scanning signal line.

[0111] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0112] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0113] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a substrate and a driving circuit layer arranged on one side of the substrate, wherein the driving circuit layer comprises a pixel driving circuit, wherein the pixel driving circuit comprises a switching transistor, a driving transistor, a compensation transistor and a first initialization transistor, wherein the switching transistor and the driving transistor are connected to a first node; an electrode of the compensation transistor, an electrode of the first initialization transistor and the driving transistor are connected to a second node, and another electrode of the compensation transistor and the driving transistor are connected to a third node; wherein the driving circuit layer comprises: A light shielding layer, wherein the light shielding layer comprises a first light shielding portion; A first active layer is disposed on a side of the light shielding layer away from the substrate; A first gate layer, disposed on a side of the first active layer away from the substrate, the first gate layer comprising a first gate of the compensation transistor; A second active layer, disposed on a side of the first gate layer away from the substrate, the second active layer comprising an active pattern of the compensation transistor and an active pattern of the first initialization transistor; The first gate of the compensation transistor is arranged corresponding to the active pattern of the compensation transistor, and the first light shielding portion is arranged corresponding to the active pattern of the first initialization transistor.

2. The display panel according to claim 1, wherein: The driving circuit layer includes a plurality of repeating units arranged in an array, each of the repeating units includes two symmetrically arranged pixel driving circuits, within the repeating unit, the light shielding layer also includes two second light shielding portions and a connecting portion symmetrically arranged in the corresponding areas of the two pixel driving circuits, the connecting portion includes a first connecting portion arranged along a first direction, a second connecting portion arranged along the first direction, and a third connecting portion arranged along a second direction, the first active layer includes an active pattern of a driving transistor, the second light shielding portion is arranged corresponding to the active pattern of the driving transistor, the first connecting portion connects adjacent first light shielding portions, the second connecting portion connects adjacent second light shielding portions, one end of the third connecting portion is connected to the first light shielding portion, and the other end of the third connecting portion is connected to the second light shielding portion; An included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

3. The display panel according to claim 1, wherein: The light shielding layer further includes a second light shielding portion, the first active layer includes an active pattern of a driving transistor, the second light shielding portion is arranged corresponding to the active pattern of the driving transistor, and the first light shielding portion and the second light shielding portion are arranged at intervals.

4. The display panel according to claim 3, wherein: The driving circuit layer includes a plurality of pixel driving circuits arranged in an array, the first light shielding portion is arranged in a corresponding area of ​​the pixel driving circuit along a first direction, and the second light shielding portion is arranged in a corresponding area of ​​the pixel driving circuit along the first direction. In the first direction, the first light shielding portions located in two adjacent pixel driving circuits are connected, and the second light shielding portions located in two adjacent pixel driving circuits are connected. The driving circuit layer also includes a scanning signal line, and the first direction is the same as the setting direction of the scanning signal line.

5. The display panel according to any one of claims 1 to 4, characterized in that: The gate of the switch transistor is connected to the first scan signal line, the first electrode of the switch transistor is connected to the data line, and the second electrode of the switch transistor is connected to the first electrode of the drive transistor at a first node; the gate of the compensation transistor is connected to the second scan signal line, the first electrode of the compensation transistor is connected to the gate of the drive transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the drive transistor; the gate of the first initialization transistor is connected to the third scan signal line, the first electrode of the first initialization transistor is connected to the first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate of the drive transistor at a second node; The pixel driving circuit further includes: a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to a light emission control signal line, a first electrode of the first light emission control transistor is connected to a high potential power supply line, and a second electrode of the first light emission control transistor is connected to a first node with a first electrode of the driving transistor; a second light emission control transistor, wherein a gate of the second light emission control transistor is connected to the light emission control signal line, and a first electrode of the second light emission control transistor and a second electrode of the driving transistor are connected to a third node; a second initialization transistor, wherein a gate of the second initialization transistor is connected to a fourth scanning signal line, a first electrode of the second initialization transistor is connected to a second initialization signal line, and a second electrode of the second initialization transistor and a second electrode of the second light emission control transistor are connected to a fourth node; a third initialization transistor, wherein a gate of the third initialization transistor is connected to the fourth scanning signal line, a first electrode of the third initialization transistor is connected to the third initialization signal line, and a second electrode of the third initialization transistor is connected to the first electrode of the driving transistor at a first node; A storage capacitor, wherein one plate of the storage capacitor is connected to the high potential power line, and the other plate of the storage capacitor is connected to the gate of the driving transistor at a second node; A boost capacitor, one plate of the boost capacitor is connected to the first scanning signal line, and the other plate of the boost capacitor is connected to the second electrode of the first initialization transistor.

6. The display panel according to claim 5, wherein: The driving circuit layer also includes a second gate layer, a first source-drain layer, and a second source-drain layer, the second active layer is arranged between the first gate layer and the second gate layer, the second gate layer is arranged between the second active layer and the first source-drain layer, and the first source-drain layer is arranged between the second gate layer and the second source-drain layer.

7. The display panel according to claim 6, wherein: The first active layer includes an active pattern of the driving transistor, an active pattern of the switching transistor, an active pattern of the first light emission control transistor, an active pattern of the second light emission control transistor, an active pattern of the second initialization transistor, and an active pattern of the third initialization transistor, the active pattern of the driving transistor is arranged along a first direction, and the active pattern of the driving transistor is connected to the active pattern of the switching transistor, the active pattern of the first light emission control transistor, and the active pattern of the second light emission control transistor, the active pattern of the switching transistor and the active pattern of the first light emission control transistor are arranged along a second direction, the active pattern of the second light emission control transistor and the active pattern of the second initialization transistor are arranged along the second direction, and the active pattern of the second light emission control transistor is connected to the active pattern of the second initialization transistor, and the active pattern of the third initialization transistor is arranged alternately with the active pattern of the driving transistor, the active pattern of the switching transistor, the active pattern of the first light emission control transistor, the active pattern of the second light emission control transistor, and the active pattern of the second initialization transistor; An included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

8. The display panel according to claim 7, wherein: The first gate layer includes the first scanning signal line, the first electrode plate of the storage capacitor, the light-emitting control signal line, the fourth scanning signal line, the first initialization connection line, the gate of the driving transistor, the gate of the switching transistor, the gate of the first light-emitting control transistor, the gate of the second light-emitting control transistor, the gate of the second initialization transistor and the gate of the third initialization transistor; the first scanning signal line, the first gate of the compensation transistor, the first electrode plate of the storage capacitor, the light-emitting control signal line, the fourth scanning signal line and the first initialization connection line are arranged in sequence along the second direction.

9. The display panel according to claim 8, wherein: The second active layer also includes a second electrode plate of the storage capacitor, the active pattern of the compensation transistor is connected to the active pattern of the first initialization transistor, the second electrode plate of the storage capacitor is arranged on one side of the active pattern of the compensation transistor along the first direction, and a through hole is provided on the second electrode plate of the storage capacitor.

10. The display panel according to claim 9, wherein: The second gate layer includes the second scanning signal line, the third scanning signal line, the second initialization signal line, the second gate of the compensation transistor and the gate of the first initialization transistor, and the third scanning signal line, the second scanning signal line and the second initialization signal line are arranged in sequence along the second direction.

11. The display panel according to claim 10, wherein: The first source-drain layer includes the first initialization signal line, the first electrode of the switch transistor, the second electrode of the switch transistor, the first electrode of the compensation transistor, the second electrode of the compensation transistor, the first electrode of the first initialization transistor, the second electrode of the first initialization transistor, the first electrode of the first light emission control transistor, the second electrode of the first light emission control transistor, the first electrode of the second light emission control transistor, the second electrode of the second light emission control transistor, the first electrode of the second initialization transistor, the second electrode of the second initialization transistor, the first electrode of the third initialization transistor, the second electrode of the third initialization transistor, the first transfer line, the first data connection line, the second transfer line and the third initialization signal line. The first switching line is connected to the first gate of the compensation transistor and the second scanning signal line, the second switching line is connected to the second initialization signal line and the first electrode of the second initialization transistor, and the third initialization signal line is connected to the first initialization connection line.

12. The display panel according to claim 11, wherein: The driving circuit layer includes a plurality of repeating units arranged in an array, each of the repeating units includes two symmetrically arranged pixel driving circuits, within the repeating units, the second source and drain layer includes two second data connection lines, two data lines, two high potential power lines and a second initialization connection line, the two second data connection lines are symmetrically arranged, and a break is provided on the second data connection line, the two data lines are symmetrically arranged, the two high potential power lines are symmetrically arranged, and the second initialization connection line is connected to the second initialization signal line.

13. The display panel according to claim 5, wherein: The first light shielding portion is connected to the third scanning signal line.

14. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 13.

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