Driving backplane and display panel

Abstract

The present application discloses a driving backplane and a display panel. The driving backplane includes a substrate, a metal oxide thin film crystal disposed on the substrate, and a hydrogen barrier. The metal oxide thin film transistor includes an oxide semiconductor portion; the hydrogen barrier portion includes a first hydrogen barrier portion and a second hydrogen barrier portion; the first hydrogen barrier portion is disposed on the side of the oxide semiconductor portion close to the substrate, and the orthographic projection of the oxide semiconductor portion on the substrate and the orthographic projection of the first hydrogen barrier portion on the substrate at least partially overlap; the second hydrogen barrier portion is disposed on the outside of the oxide semiconductor portion, and on a plane perpendicular to the substrate, the orthographic projection of the oxide semiconductor portion and the orthographic projection of the second hydrogen barrier portion at least partially overlap. The present application improves the stability of the metal oxide thin film transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving backplane and a display panel. Background Art

[0002] With the rapid development and innovation of display technology, display terminals have a demand for reducing power consumption of mainstream LCD (Liquid Crystal Display) and AMOLED (Active-matrix organic light-emitting diode) display panels to achieve the goal of green energy saving.

[0003] In order to achieve low power consumption, in related technologies, based on the existing LTPS (Low Temperature Poly-Silicon) backplane technology, the advantages of low leakage current of metal oxide thin-film transistors such as IGZO thin-film transistors are utilized to combine LTPS and IGZO to create a LTPO (Low Temperature Polycrystalline-Si Oxide) technology.

[0004] However, in terms of process complexity and device stability, LTPO technology often encounters the problem of satisfying the performance of one set of devices at the expense of the performance of another set of devices. For example: in order to achieve better picture quality at low grayscale on the screen, it is generally required that the current change rate of the driving thin film transistor in the subthreshold region cannot be too large, which requires that the subthreshold swing of the driving thin film transistor with LTPS as the active layer material cannot be too small. In order to achieve this performance, it is usually necessary to perform a high-temperature baking process on the LTPS device, but the above-mentioned high-temperature baking process has a greater impact on the stability of the threshold voltage of the oxide thin film transistor, especially the metal oxide thin film transistor with high mobility materials such as IGZO as the active layer material, which is more susceptible to the influence of the high-temperature baking process, thereby reducing the stability of the metal oxide thin film transistor. Summary of the Invention

[0005] The embodiments of the present application provide a driving backplane and a display panel, which can reduce the impact of high-temperature processes on metal oxide thin film transistors and improve the stability of metal oxide thin film transistors.

[0006] To solve the above technical problems, an embodiment of the present application provides a driving backplane, which includes:

[0007] substrate;

[0008] a metal oxide thin film transistor disposed on one side of the substrate, the metal oxide thin film transistor including an oxide semiconductor portion; and

[0009] A hydrogen barrier portion is arranged on the substrate, and the hydrogen barrier portion includes a first hydrogen barrier portion and a second hydrogen barrier portion; wherein the first hydrogen barrier portion is arranged on a side of the oxide semiconductor portion close to the substrate, and the orthographic projection of the oxide semiconductor portion on the substrate and the orthographic projection of the first hydrogen barrier portion on the substrate at least partially overlap; the second hydrogen barrier portion is arranged on the outside of the oxide semiconductor portion, and on a plane perpendicular to the substrate, the orthographic projection of the oxide semiconductor portion and the orthographic projection of the second hydrogen barrier portion at least partially overlap.

[0010] Optionally, in some embodiments of the present application, the driving backplane also includes a low-temperature polycrystalline silicon thin film transistor arranged on the substrate, and the low-temperature polycrystalline silicon thin film transistor includes a low-temperature polycrystalline silicon semiconductor part, a first gate insulating layer, a first gate and a first source and drain arranged in sequence, the low-temperature polycrystalline silicon semiconductor part, the first gate insulating layer and the first gate are all located on the side of the oxide semiconductor part close to the substrate, the first source and drain are connected to the low-temperature polycrystalline silicon semiconductor part; the first gate is reused as the first hydrogen barrier part.

[0011] Optionally, in some embodiments of the present application, the orthographic projection of the oxide semiconductor portion on the substrate is located within the orthographic projection of the first hydrogen barrier portion on the substrate.

[0012] Optionally, in some embodiments of the present application, the driving backplane further comprises an insulating stack, wherein the insulating stack is provided on a side of the first hydrogen barrier portion away from the substrate, and the oxide semiconductor portion is located in the insulating stack;

[0013] A connection hole is opened in the insulating stack, exposing the first hydrogen barrier portion. The second hydrogen barrier portion is arranged on the surface of the insulating stack and fills the connection hole. The second hydrogen barrier portion is connected to the first hydrogen barrier portion.

[0014] Optionally, in some embodiments of the present application, the metal oxide thin film transistor also includes a second gate, which is arranged on the side of the oxide semiconductor portion away from the substrate and located on the surface of the insulating stack away from the substrate; the second hydrogen barrier portion is located on the surface of the insulating stack and is insulated from the second gate.

[0015] Optionally, in some embodiments of the present application, the insulating stack includes a first interlayer insulating layer and a second gate insulating layer, the first interlayer insulating layer is located between the first hydrogen barrier portion and the oxide semiconductor portion, and the second gate insulating layer is located between the oxide semiconductor portion and the second gate;

[0016] The connection hole passes through the second gate insulating layer and the first interlayer insulating layer in sequence, the second hydrogen barrier is arranged on the surface of the second gate insulating layer and fills the connection hole, and the second hydrogen barrier is located on the surface of the second gate insulating layer in the same layer as the second gate and is insulated.

[0017] Optionally, in some embodiments of the present application, the metal oxide thin film transistor also includes a second source and drain, which are arranged on the surface of the insulating stack away from the substrate and connected to the oxide semiconductor part; the second hydrogen barrier part is located on the surface of the insulating stack and is insulated from the same layer as the second source and drain.

[0018] Optionally, in some embodiments of the present application, the metal oxide thin film transistor further includes a second gate, the second gate being located on a side of the oxide semiconductor portion away from the substrate; the insulating stack includes a first interlayer insulating layer, a second gate insulating layer, and a second interlayer insulating layer sequentially provided on the substrate, the first interlayer insulating layer being located between the first hydrogen barrier portion and the oxide semiconductor portion, the second gate insulating layer being located between the oxide semiconductor portion and the second gate, and the second interlayer insulating layer being located between the second gate and the first source and drain;

[0019] The connection hole passes through the second interlayer insulating layer, the second gate insulating layer and the first interlayer insulating layer in sequence, the second hydrogen barrier portion is arranged on the surface of the second interlayer insulating layer and filled in the connection hole, and the second hydrogen barrier portion is located on the surface of the second interlayer insulating layer in the same layer as the second source and drain and is insulated.

[0020] Optionally, in some embodiments of the present application, the metal oxide thin film transistor further includes a second gate, the second gate is arranged on a side of the oxide semiconductor portion away from the substrate, and the second hydrogen barrier portion and the second gate are in the same layer and are insulated.

[0021] Optionally, in some embodiments of the present application, the second hydrogen barrier portion is arranged around the circumference of the oxide semiconductor portion, and the second hydrogen barrier portion has a gap in at least a region corresponding to the second gate, and the second gate extends into the gap and toward the oxide semiconductor portion to cover the oxide semiconductor portion.

[0022] Optionally, in some embodiments of the present application, the driving backplane also includes a low-temperature polycrystalline silicon thin film transistor arranged on the substrate, and the low-temperature polycrystalline silicon thin film transistor includes a low-temperature polycrystalline silicon semiconductor part, a first gate insulating layer, a first gate and a first source and drain arranged in sequence, the low-temperature polycrystalline silicon semiconductor part, the first gate insulating layer and the first gate are all located on the side of the oxide semiconductor part close to the substrate, and the first source and drain are connected to the low-temperature polycrystalline silicon semiconductor part; the first hydrogen barrier part and the first gate are in the same layer and are arranged at intervals.

[0023] Optionally, in some embodiments of the present application, the metal oxide thin film transistor further includes a second gate and a second source and drain, the second gate being arranged on a side of the oxide semiconductor portion away from the substrate, and the second source and drain being arranged on a surface of the second gate away from the substrate and connected to the oxide semiconductor portion;

[0024] The first source and drain and the second gate are arranged in the same layer; or the first source and drain and the second source and drain are arranged in the same layer.

[0025] The present application also provides a display panel, which includes a driving backplane and a light-emitting unit arranged on the driving backplane, and the driving backplane is the driving backplane described in any of the aforementioned embodiments.

[0026] Compared to the driving backplane in the prior art, the driving backplane provided in the present application provides a hydrogen barrier portion below and on the side of the oxide semiconductor portion of the metal oxide thin film transistor, and uses the hydrogen barrier portion to block hydrogen below and on the side of the oxide semiconductor portion, such as in the vertical direction. Specifically, the first hydrogen barrier portion in the hydrogen barrier portion is used to block hydrogen below the oxide semiconductor portion, and the second hydrogen barrier portion in the hydrogen barrier portion is used to block hydrogen on the side of the oxide semiconductor portion. This reduces the probability of hydrogen below and on the side of the oxide semiconductor portion diffusing into the interior of the oxide semiconductor portion during the high-temperature baking process in the driving backplane manufacturing process, thereby improving the stability of the metal oxide thin film transistor and the driving performance of the driving backplane. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. The drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 It is a schematic diagram of the cross-sectional structure of the driving backplane provided in the first embodiment of the present application.

[0029] Figure 2a yes Figure 1 The first planar structural schematic diagram of the driving backplane is shown.

[0030] Figure 2b yes Figure 1 The second planar structure schematic diagram of the driving backplane is shown.

[0031] Figure 2c yes Figure 1 The third planar structure schematic diagram of the driving backplane is shown.

[0032] Figure 3a yes Figure 1 The fourth planar structure schematic diagram of the driving backplane is shown.

[0033] Figure 3b yes Figure 1 The fifth planar structural diagram of the driving backplane is shown.

[0034] Figure 3c yes Figure 1 The sixth planar structural schematic diagram of the driving backplane is shown.

[0035] Figure 4 It is a schematic diagram of the cross-sectional structure of the driving backplane provided in the second embodiment of the present application.

[0036] Figure 5 It is a schematic diagram of the cross-sectional structure of the driving backplane provided in the third embodiment of the present application.

[0037] Figure 6 It is a schematic diagram of the cross-sectional structure of the driving backplane provided in the fourth embodiment of the present application.

[0038] Figure 7a yes Figure 6 The first planar structural diagram of the driving backplane is shown.

[0039] Figure 7b yes Figure 6 The second planar structure schematic diagram of the driving backplane is shown.

[0040] Figure 7c yes Figure 6 The third planar structure schematic diagram of the driving backplane is shown.

[0041] Figure 8a yes Figure 6 The fourth planar structure schematic diagram of the driving backplane is shown.

[0042] Figure 8b yes Figure 6 The fifth planar structural diagram of the driving backplane is shown.

[0043] Figure 8c yes Figure 6The sixth planar structural schematic diagram of the driving backplane is shown.

[0044] Figure 9 This is a schematic diagram of the cross-sectional structure of the display panel provided in Example 1 of this application.

[0045] Figure 10 This is a schematic diagram of the cross-sectional structure of the display panel provided in Example 2 of this application.

[0046] Figure 11 This is a schematic diagram of the cross-sectional structure of the display panel provided in Example 3 of this application.

[0047] Figure 12 This is a schematic diagram of the cross-sectional structure of the display panel provided in Example 4 of this application. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0049] The present application provides a driving backplane, which includes a substrate, a metal oxide thin film crystal, and a hydrogen barrier. The metal oxide thin film transistor is arranged on one side of the substrate and includes an oxide semiconductor portion; the hydrogen barrier portion is arranged on the substrate and includes a first hydrogen barrier portion and a second hydrogen barrier portion. The first hydrogen barrier portion is arranged on the side of the oxide semiconductor portion close to the substrate, and the orthographic projection of the oxide semiconductor portion on the substrate and the orthographic projection of the first hydrogen barrier portion on the substrate at least partially overlap; the second hydrogen barrier portion is arranged on the outside of the oxide semiconductor portion, and on a plane perpendicular to the substrate, the orthographic projection of the oxide semiconductor portion and the orthographic projection of the second hydrogen barrier portion at least partially overlap.

[0050] Therefore, the driving backplane provided by the present application provides a hydrogen barrier portion below and on the side of the oxide semiconductor portion of the metal oxide thin film transistor, and uses the hydrogen barrier portion to block hydrogen below and on the side of the oxide semiconductor portion, such as in the vertical direction. Specifically, the first hydrogen barrier portion in the hydrogen barrier portion is used to block hydrogen below the oxide semiconductor portion, and the second hydrogen barrier portion in the hydrogen barrier portion is used to block hydrogen on the side of the oxide semiconductor portion. This reduces the probability of hydrogen below and on the side of the oxide semiconductor portion diffusing into the interior of the oxide semiconductor portion during the high-temperature baking process in the driving backplane manufacturing process, thereby improving the stability of the metal oxide thin film transistor and the driving performance of the driving backplane.

[0051] The driver backplane provided by the present application is described in detail below through specific embodiments. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0052] It should be noted that the driving backplane provided in the present application can be applicable to a driving backplane that only contains metal oxide thin film transistors, and can also be applicable to a driving backplane that simultaneously contains metal oxide thin film transistors and another type of thin film transistors, such as a driving backplane that simultaneously contains metal oxide thin film transistors and low-temperature polycrystalline silicon thin film transistors; the following embodiments of the present application only use the structure of the driving backplane as an example when it is a driving backplane that simultaneously contains metal oxide thin film transistors and low-temperature polycrystalline silicon thin film transistors, but are not limited to this.

[0053] Please refer to Figure 1 、 Figures 2a to 2c as well as Figures 3a to 3c The first embodiment of the present application provides a driving backplane 100 . The driving backplane 100 includes a substrate 10 , a buffer layer 20 disposed on the substrate 10 , a low-temperature polysilicon thin film transistor 30 and a metal oxide thin film transistor 40 disposed on the buffer layer 20 .

[0054] In this embodiment, the low-temperature polysilicon thin film transistor 30 and the metal oxide thin film transistor 40 are disposed in the display region, serving as the driving thin film transistor and the switching thin film transistor, respectively, in the pixel driving circuit. In some embodiments, the low-temperature polysilicon thin film transistor 30 and the metal oxide thin film transistor 40 may also be disposed in the GOA region, which will not be further described here.

[0055] Specifically, the substrate 10 can be a rigid substrate, such as a glass substrate; or, the substrate 10 can be a flexible substrate, such as a polyimide substrate; or, the substrate 10 can be a stacked structure including both a rigid substrate and a flexible substrate, and so on; this application does not specifically limit the material of the substrate 10.

[0056] The buffer layer 20 is disposed on one side of the substrate 10. The material of the buffer layer 20 may include, but is not limited to, at least one of silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride. It should be noted that this embodiment only uses the structure of the buffer layer 20 as a single inorganic layer as an example. In some embodiments, the buffer layer 20 may also have a double-layer structure or a multi-layer structure, which will not be further described here.

[0057] The low-temperature polysilicon thin film transistor 30 includes a low-temperature polysilicon semiconductor portion 31 , a first gate insulating layer 32 , a first gate 33 , and a first source and drain 34 .

[0058] Specifically, the low-temperature polysilicon semiconductor portion 31 is disposed on a side of the buffer layer 20 away from the substrate 10. The material of the low-temperature polysilicon semiconductor portion 31 includes low-temperature polysilicon.

[0059] The first gate insulating layer 32 is disposed on a side of the low-temperature polysilicon semiconductor portion 31 away from the buffer layer 20. The first gate insulating layer 32 covers the low-temperature polysilicon semiconductor portion 31 and the buffer layer 20. The material of the first gate insulating layer 32 may include, but is not limited to, at least one of silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride. The first gate insulating layer 32 may be a single-layer structure or a composite film layer including two or more inorganic layers.

[0060] The first gate 33 is arranged on the side of the first gate insulating layer 32 away from the low-temperature polycrystalline silicon semiconductor part 31. The orthographic projection of the first gate 33 on the substrate 10 is located within the orthographic projection of the low-temperature polycrystalline silicon semiconductor part 31 on the substrate 10. Among them, the driving backplane 100 also includes a light-emitting control signal line (not marked in the figure) arranged on the same layer as the first gate 33, and the light-emitting control signal line is located in the line change area adjacent to the display area, and is used to transmit the signal of the GOA area to the display area. The relevant technologies are all existing technologies and are not repeated here. Specifically, the material of the first gate 33 may include at least one of metals such as copper, aluminum, molybdenum and titanium, and may also include an alloy composed of at least two of the above metals. The first gate 33 can be a single-layer structure, a double-layer structure or a three-layer structure formed by any of the above materials.

[0061] In this embodiment, the driving backplane 100 further includes an insulating stack 50, which is disposed on a side of the first gate 33 away from the first gate insulating layer 32. The insulating stack 50 includes a first interlayer insulating layer 51 and a second gate insulating layer 52 sequentially disposed on the first gate 33. The first source and drain electrodes 34 are disposed on a side of the second gate insulating layer 52 away from the substrate 10. The first source and drain electrodes 34 are connected to the low-temperature polysilicon semiconductor portion 31 through contact holes (not shown in the figure) that sequentially penetrate the second gate insulating layer 52, the first interlayer insulating layer 51, and the first gate insulating layer 32. Specifically, the first source and drain electrodes 34 include a first source electrode 341 and a first drain electrode 342, and the first source electrode 341 and the first drain electrode 342 are respectively connected to the end of the low-temperature polysilicon semiconductor portion 31 through a contact hole. In this embodiment, the material of the first source and drain electrode 34 may include at least one of metals such as copper, aluminum, molybdenum and titanium, or may include an alloy composed of at least two of the above metals; the first source and drain electrode 34 may be a single-layer structure, a double-layer structure or a triple-layer structure formed by any of the above materials.

[0062] The first interlayer insulating layer 51 is disposed on the side of the first gate 33 away from the first gate insulating layer 32. The material of the first interlayer insulating layer 51 may include, but is not limited to, at least one of silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride. Preferably, the material of the first interlayer insulating layer 51 is silicon oxide or aluminum oxide. This configuration can reduce the hydrogen content in the first interlayer insulating layer 51, thereby reducing the probability of hydrogen diffusion during high-temperature processes. Furthermore, the first interlayer insulating layer 51 may be a single-layer structure or a composite film layer comprising two or more inorganic layers.

[0063] In this embodiment, the metal oxide thin film transistor 40 includes an oxide semiconductor portion 41 , a second gate 42 , and a second source and drain 43 .

[0064] Specifically, the oxide semiconductor portion 41 is disposed on a side of the first interlayer insulating layer 51 away from the first gate 33. The material of the oxide semiconductor portion 41 may include, but is not limited to, at least one of IGZO, IGZTO, IZTO, IGTO, ITO, and IZO. In this embodiment, the material of the oxide semiconductor portion 41 is IGZO. The oxide semiconductor portion 41 includes a channel and a source contact portion and a drain contact portion, respectively, disposed on opposite sides of the channel. The relevant technologies are all prior art and will not be further described here.

[0065] The second gate insulating layer 52 is disposed on the side of the oxide semiconductor portion 41 away from the first interlayer insulating layer 51. The material of the second gate insulating layer 52 may include, but is not limited to, at least one of silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride. In addition, the second gate insulating layer 52 may be a single-layer structure or a composite film layer including two or more inorganic layers. In this embodiment, the second gate insulating layer 52 is disposed on the entire surface, that is, the second gate insulating layer 52 covers the oxide semiconductor portion 41 and the first interlayer insulating layer 51. In some embodiments, the second gate insulating layer 52 may also be a patterned structure. In this case, the second gate insulating layer 52 may be disposed corresponding to the channel of the oxide semiconductor portion 41, which will not be described in detail here.

[0066] The second gate 42 is arranged on the side of the oxide semiconductor portion 41 away from the substrate 10, and is located on the surface of the insulating stack 50 away from the substrate 10. Specifically, the second gate 42 is arranged on the side of the second gate insulating layer 52 away from the oxide semiconductor portion 41, and is arranged in the same layer as the first source and drain 34. The orthographic projection of the second gate 42 on the substrate 10 is located within the orthographic projection of the oxide semiconductor portion 41 on the substrate 10, wherein the orthographic projection of the second gate 42 on the substrate 10 at least overlaps with the orthographic projection of the channel of the oxide semiconductor portion 41 on the substrate 10. The material of the second gate 42 may include metals such as at least one of copper, aluminum, molybdenum and titanium, and may also include an alloy composed of at least two of the above metals. It should be noted that the driving backplane 100 also includes a scanning line (not shown in the figure) arranged in the same layer as the second gate 42, which will not be repeated here.

[0067] Furthermore, the driving backplane 100 further includes a second interlayer insulating layer 53, which is disposed on a side of the second gate 42 away from the second gate insulating layer 52. The material of the second interlayer insulating layer 53 may include, but is not limited to, at least one of silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride; in addition, the second interlayer insulating layer 53 may be a single-layer structure or a composite film layer including two or more inorganic layers.

[0068] The second source and drain electrodes 43 are arranged on a side of the second interlayer insulating layer 53 away from the second gate electrode 42. The second source and drain electrodes 43 are connected to the oxide semiconductor portion 41 through a contact hole (not marked in the figure) that penetrates the second interlayer insulating layer 53 and the second gate insulating layer 52. Specifically, the second source and drain electrodes 43 include a second source electrode 431 and a second drain electrode 432, and the second source electrode 431 and the second drain electrode 432 are respectively connected to the end of the oxide semiconductor portion 41 through a contact hole. The material of the second source and drain electrodes 43 may include at least one of metals such as copper, aluminum, molybdenum and titanium, and may also include an alloy composed of at least two of the above metals; the second source and drain electrodes 43 may be a single-layer structure, a double-layer structure or a triple-layer structure formed by any of the above materials.

[0069] In this embodiment, the driving backplane 100 further includes a signal transmission electrode 433 disposed in the same layer as the second source and drain electrodes 43. The signal transmission electrode 433 is connected to the first source and drain electrodes 34 through a via (not shown) in the second interlayer insulating layer 53. The signal transmission electrode 433 can be used to transmit data signals.

[0070] Furthermore, in this embodiment, the driving backplane 100 further includes a hydrogen barrier 60. The hydrogen barrier 60 includes a first hydrogen barrier 61 and a second hydrogen barrier 62. The first hydrogen barrier 61 is disposed on a side of the oxide semiconductor portion 41 close to the substrate 10, and the orthographic projection of the oxide semiconductor portion 41 on the substrate 10 and the orthographic projection of the first hydrogen barrier 61 on the substrate 10 at least partially overlap, thereby blocking hydrogen below the oxide semiconductor portion 41. The second hydrogen barrier 62 is disposed outside the oxide semiconductor portion 41, and on a plane perpendicular to the substrate 10, the orthographic projection of the oxide semiconductor portion 41 and the orthographic projection of the second hydrogen barrier 62 at least partially overlap, thereby blocking hydrogen on the side of the oxide semiconductor portion 41, such as in the vertical direction.

[0071] Therefore, the driving backplane 100 provided in this embodiment sets a hydrogen barrier portion 60 below and on the side of the oxide semiconductor portion 41 of the metal oxide thin film transistor 40, and uses the hydrogen barrier portion 60 to block the hydrogen below and on the side of the oxide semiconductor portion 41, such as in the vertical direction, so that during the high-temperature baking process in the process of the driving backplane 100, the probability of hydrogen below and on the side of the oxide semiconductor portion 41 diffusing into the interior of the oxide semiconductor portion 41 can be reduced, thereby improving the stability of the metal oxide thin film transistor 40 and improving the driving performance of the driving backplane 100.

[0072] The structure of the hydrogen barrier 60 provided in this embodiment is described in detail below.

[0073] In this embodiment, the first gate 33 is reused as the first hydrogen barrier 61. In this configuration, the top gate of the low-temperature polysilicon thin-film transistor 30 is used as the hydrogen barrier layer below the oxide semiconductor portion 41, thereby preventing the diffusion of hydrogen without adding additional processing steps. The orthographic projection of the oxide semiconductor portion 41 on the substrate 10 is located within the orthographic projection of the first hydrogen barrier 61 on the substrate 10, further enhancing the hydrogen barrier effect of the first hydrogen barrier 61.

[0074] In addition, since the material of the first interlayer insulating layer 51 is silicon oxide or aluminum oxide, compared with the case where silicon nitride or silicon oxynitride is used as the insulating material, the first interlayer insulating layer 51 in this embodiment contains only a small amount of hydrogen or even no hydrogen. Therefore, when the first gate 33 is reused as a hydrogen barrier layer under the oxide semiconductor portion 41, even in a high-temperature process, the oxide semiconductor portion 41 will not be affected by the diffusion of hydrogen in the first interlayer insulating layer 51, so that the first hydrogen barrier portion 61 has a good blocking effect on the hydrogen-containing film layers under the oxide semiconductor portion 41, such as the first gate insulating layer 32, the low-temperature polysilicon semiconductor portion 31 and the buffer layer 20.

[0075] It can be understood that since the orthographic projection of the first gate 33 on the substrate 10 is located within the orthographic projection of the low-temperature polysilicon semiconductor portion 31 on the substrate 10, that is, the low-temperature polysilicon thin-film transistor 30 and the metal oxide thin-film transistor 40 at least partially overlap, this arrangement can save the space occupied by the thin-film transistor and is conducive to the design of high-resolution display products.

[0076] Furthermore, in this embodiment, the first gate 33 can serve as the top gate of the low-temperature polysilicon thin film transistor 30 and also as the bottom gate of the metal oxide thin film transistor 40, so that the metal oxide thin film transistor 40 is formed into a dual-gate structure including the first gate 33 and the second gate 42, thereby improving the switching performance of the metal oxide thin film transistor 40.

[0077] In this embodiment, a connection hole 50A is defined in the insulating stack 50. The connection hole 50A penetrates the insulating stack 50 and exposes the first hydrogen barrier 61. A second hydrogen barrier 62 is disposed on the surface of the insulating stack 50 and fills the connection hole 50A. The second hydrogen barrier 62 is connected to the exposed portion of the first hydrogen barrier 61. With this arrangement, the second hydrogen barrier 62 serves as a hydrogen barrier on the side surfaces of the oxide semiconductor portion 41, thereby reducing the effects of hydrogen diffusion on the side surfaces of the oxide semiconductor portion 41, such as in the vertical direction, during high-temperature processes.

[0078] The portion of the second hydrogen barrier 62 located on the surface of the insulating stack 50 is in the same layer as the second gate 42 and is insulated therefrom. Specifically, the connection hole 50A sequentially penetrates the second gate insulating layer 52 and the first interlayer insulating layer 51. The second hydrogen barrier 62 is disposed on the surface of the second gate insulating layer 52 and fills the connection hole 50A. The portion of the second hydrogen barrier 62 located on the surface of the second gate insulating layer 52 is in the same layer as the second gate 42 and is insulated therefrom. Because the second hydrogen barrier 62 and the second gate 42 are disposed in the same layer and are connected to the first hydrogen barrier 61, i.e., the second hydrogen barrier 62 is connected to the first gate 33, this arrangement can prevent signal crosstalk caused by conduction between the second gate 42 and the first gate 33.

[0079] In this embodiment, the second hydrogen barrier 62 and the second gate 42 can be manufactured using the same process, thereby avoiding an additional increase in the number of manufacturing processes for the driving backplane 100 .

[0080] Further, taking the structure of the driving backplane 100 applied to the OLED display panel as an example, please continue to refer to Figures 2a to 2c as well as Figures 3a to 3c In this embodiment, the orthographic projection of the second hydrogen barrier 62 on the substrate 10 partially overlaps with the orthographic projection of the first hydrogen barrier 61 on the substrate 10 , and the overlapping area of ​​the second hydrogen barrier 62 and the first hydrogen barrier 61 is the connection area A of the second hydrogen barrier 62 and the first hydrogen barrier 61 .

[0081] It should be noted that Figures 2a to 2c as well as Figures 3a to 3c The structures are all partial structures of the pixel compensation circuit in the driving backplane when the driving backplane is applied to the OLED display panel. The above structures are only schematic and are used to facilitate the description of this embodiment, but should not be understood as limiting the present application.

[0082] In this embodiment, the second hydrogen barrier 62 is disposed around the oxide semiconductor portion 41 and has a notch 621 at least in a region corresponding to the second gate 42. The second gate 42 extends into the notch 621 and extends toward the oxide semiconductor portion 41 until it covers the oxide semiconductor portion 41. The orthographic projection area of ​​the portion of the second gate 42 extending into the notch 621 on the substrate 10 is smaller than the opening area of ​​the notch 621.

[0083] Please refer to Figures 2a to 2c Taking the orthographic projection of the second hydrogen barrier 62 on the substrate 10 as a rectangular ring-shaped structure as an example, this embodiment provides three configurations of the hydrogen barrier 60. The structure of the first hydrogen barrier 61 in the following three configurations is the same, and the only difference lies in the structure of the second hydrogen barrier 62.

[0084] In the first structure, Figure 2a As shown, there is one notch 621 in the second hydrogen barrier 62, which exposes a portion of the second gate 42. This arrangement prevents signal crosstalk between the first hydrogen barrier 61 (first gate 33) and the second gate 42 while maximizing the second hydrogen barrier 62's ability to block hydrogen from the sides of the oxide semiconductor portion 41, thereby improving the stability of the metal oxide thin film transistor 40. The specific size of the notch 621 can be set based on actual product design requirements and is not limited in this application.

[0085] In the second structure, Figure 2b As shown, Figure 2aThe difference in the structure is that there are two notches 621 in the second hydrogen barrier 62. One of the notches 621 (hereinafter referred to as the first notch 621a) exposes a portion of the second gate 42, and the other notch 621 (hereinafter referred to as the second notch 621b) is arranged on the opposite side of the first notch 621a. The first notch 621a and the second notch 621b can be symmetrically arranged to reduce the difficulty of process manufacturing. Among them, the first notch 621a and the second notch 621b divide the second hydrogen barrier 62 into two parts, that is, the first hydrogen barrier 61 and the second hydrogen barrier 62 have two connection areas A, and the two parts of the second hydrogen barrier 62 are connected to the first hydrogen barrier 61 through corresponding connection holes 50A, which will not be repeated here.

[0086] It is understandable that when the interior of the oxide semiconductor portion 41 is completely free of hydrogen, the metal oxide thin film transistor 40 may experience excessive negative bias. To address this technical issue, in the second structure, while the size of the notches 621 remains unchanged, the number of notches 621 in the second hydrogen barrier portion 62 is increased, thereby partially weakening the hydrogen barrier effect of the second hydrogen barrier portion 62 to a certain extent. This allows a small amount of hydrogen that diffuses laterally to remain inside the oxide semiconductor portion 41, thereby preventing the metal oxide thin film transistor 40 from experiencing excessive negative bias.

[0087] In the third structure, Figure 2c As shown, Figure 2b The difference in structure is that the second hydrogen barrier 62 further includes a third notch 621c and a fourth notch 621d, which are symmetrically arranged. The first notch 621a, the second notch 621b, the third notch 621c, and the fourth notch 621d divide the second hydrogen barrier 62 into four parts. That is, the first hydrogen barrier 61 and the second hydrogen barrier 62 have four connection areas A, and the four parts of the second hydrogen barrier 62 are connected to the first hydrogen barrier 61 through corresponding connection holes 50A. Details are omitted here.

[0088] Please refer to Figures 3a to 3c Taking the orthographic projection of the second hydrogen barrier 62 on the substrate 10 as an "elliptical ring structure" as an example, this embodiment provides three configurations of the hydrogen barrier 60. The structure of the first hydrogen barrier 61 in the following three configurations is the same, and the only difference lies in the structure of the second hydrogen barrier 62.

[0089] like Figure 3a As shown, the arrangement of the notch 621 in the fourth structure can refer to the description of the notch 621 in the first structure; Figure 3b As shown, the arrangement of the notch 621 in the fifth structure can refer to the description of the notch 621 in the second structure; Figure 3cAs shown, the arrangement of the notch 621 in the sixth structure can refer to the description of the notch 621 in the third structure, and will not be repeated here.

[0090] It should be noted that the configuration of the hydrogen barrier 60 in the first through sixth structures described above is merely exemplary and is provided to facilitate the description of this embodiment. In particular, the specific number, location, and size of the notches 621 in the second hydrogen barrier 62 can be determined based on actual application requirements, and this embodiment is not to be construed as limiting the present application.

[0091] In summary, in the driving backplane 100 provided in the first embodiment of the present application, the top gate of the low-temperature polysilicon thin-film transistor 30 is reused as a hydrogen barrier layer under the oxide semiconductor portion 41, and a second hydrogen barrier portion 62 is provided which is prepared by the same process as the top gate of the metal oxide thin-film transistor 40. The second hydrogen barrier portion 62 is used as a hydrogen barrier layer on the side of the oxide semiconductor portion 41, such as in the vertical direction. The "semi-enclosed structure" formed by the first hydrogen barrier portion 61 and the second hydrogen barrier portion 62 is used to block hydrogen below and in the vertical direction of the oxide semiconductor portion 41. Therefore, during the high-temperature baking process in the manufacturing process of the driving backplane 100, the probability of hydrogen below and in the vertical direction diffusing into the interior of the oxide semiconductor portion 41 can be reduced, thereby improving the stability of the metal oxide thin-film transistor 40 and improving the driving performance of the driving backplane 100.

[0092] Please refer to Figure 4 The second embodiment of the present application provides a driving backplane 200. The driving backplane 200 provided in the second embodiment of the present application differs from the first embodiment in that the second hydrogen barrier 62 is located on the surface of the insulating stack 50 and is in the same layer as the second source and drain 43 and is insulated therefrom.

[0093] Specifically, the insulating stack 50 includes a first interlayer insulating layer 51, a second gate insulating layer 52 and a second interlayer insulating layer 53. The connection hole 50A sequentially penetrates the second interlayer insulating layer 53, the second gate insulating layer 52 and the first interlayer insulating layer 51. The second hydrogen barrier portion 62 is arranged on the surface of the second interlayer insulating layer 53 and filled in the connection hole 50A. The portion of the second hydrogen barrier portion 62 located on the surface of the second interlayer insulating layer 53 is in the same layer as the second source and drain 43 and is insulated.

[0094] In this embodiment, the second hydrogen barrier 62 and the second source and drain 43 can be manufactured using the same process, thereby avoiding an additional increase in the number of manufacturing processes for the driving backplane 200 .

[0095] Please refer to Figure 5The third embodiment of the present application provides a driving backplane 300. The driving backplane 300 provided in the third embodiment of the present application is different from that in the first embodiment in that the first source-drain 34 and the second source-drain 43 are provided in the same layer.

[0096] Specifically, the first source and drain electrodes 34 are connected to the low-temperature polysilicon semiconductor portion 31 via contact holes (not shown) that sequentially penetrate the second interlayer insulating layer 53, the second gate insulating layer 52, the first interlayer insulating layer 51, and the first gate insulating layer 32. In this embodiment, the first source and drain electrodes 34 and the second source and drain electrodes 43 are fabricated using the same process.

[0097] Please refer to Figure 6 , reference Figures 7a to 7c as well as Figures 8a to 8c The fourth embodiment of the present application provides a driving backplane 400. The driving backplane 400 provided in the fourth embodiment of the present application differs from the first embodiment in that the first hydrogen barrier 61 and the first gate 33 are in the same layer and spaced apart from each other, the second hydrogen barrier 62 located on the surface of the insulating stack 50 is in the same layer and spaced apart from the second source and drain 43, and the first source and drain 34 and the second source and drain 43 are in the same layer.

[0098] In this embodiment, the low-temperature polysilicon thin-film transistor 30 is spaced apart from the metal oxide thin-film transistor 40. The insulating stack 50 includes a first interlayer insulating layer 51, a second gate insulating layer 52, and a second interlayer insulating layer 53. A connection hole 50A sequentially penetrates the second interlayer insulating layer 53, the second gate insulating layer 52, and the first interlayer insulating layer 51. A second hydrogen barrier 62 is disposed on the surface of the second interlayer insulating layer 53 and fills the connection hole 50A. The portion of the second hydrogen barrier 62 located on the surface of the second interlayer insulating layer 53 is in the same layer as the second source and drain electrodes 43 and is insulated therefrom. The first source and drain electrodes 34 are connected to the low-temperature polysilicon semiconductor portion 31 via contact holes (not shown) that sequentially penetrate the second interlayer insulating layer 53, the second gate insulating layer 52, the first interlayer insulating layer 51, and the first gate insulating layer 32.

[0099] In this embodiment, the first source-drain electrode 34 , the second source-drain electrode 43 and the second hydrogen barrier 62 are manufactured by the same process.

[0100] Further, taking the structure of the driving backplane 400 applied to the OLED display panel as an example, please continue to refer to Figures 7a to 7c as well as Figures 8a to 8c In this embodiment, the orthographic projection of the second hydrogen barrier 62 on the substrate 10 is located within the orthographic projection of the first hydrogen barrier 61 on the substrate 10 . The area where the second hydrogen barrier 62 is located is the connection area A between the second hydrogen barrier 62 and the first hydrogen barrier 61 .

[0101] It should be noted that Figures 7a to 7c as well as Figures 8a to 8c The structures are all partial structures of the pixel compensation circuit in the driving backplane when the driving backplane is applied to the OLED display panel. The above structures are only schematic and are used to facilitate the description of this embodiment, but should not be understood as limiting the present application.

[0102] It can be understood that since the first hydrogen barrier portion 61 and the low-temperature polycrystalline silicon semiconductor portion 31 are arranged at intervals, the orthographic projections of the two on the substrate 10 do not overlap. Therefore, the above arrangement makes it possible to not be restricted by the size of the low-temperature polycrystalline silicon semiconductor portion 31 when setting the first hydrogen barrier portion 61, and thus the size of the first hydrogen barrier portion 61 can be increased to improve the hydrogen barrier effect under the oxide semiconductor portion 41; at the same time, under the above arrangement, the connection area between the second hydrogen barrier portion 62 and the first hydrogen barrier portion 61 can be increased, thereby further improving the overall hydrogen barrier effect of the hydrogen barrier portion 60.

[0103] Taking the orthographic projection shape of the first hydrogen barrier 61 on the substrate 10 as a rectangle as an example, the orthographic projection shape of the second hydrogen barrier 62 on the substrate 10 is designed according to the first hydrogen barrier 61. Figures 7a to 7c Taking the orthographic projection of the second hydrogen barrier 62 on the substrate 10 as a rectangular ring-shaped structure as an example, this embodiment provides three configurations of the hydrogen barrier 60. The structure of the first hydrogen barrier 61 in the following three configurations is the same, and the only difference lies in the structure of the second hydrogen barrier 62.

[0104] like Figure 7a As shown, the arrangement of the second hydrogen barrier 62 in the first structure can refer to Figure 2a Description in Figure 7b As shown, the arrangement of the second hydrogen barrier 62 in the second structure can refer to Figure 2b Description in Figure 7c As shown, the arrangement of the second hydrogen barrier 62 in the third structure can refer to Figure 2c The description in , will not be repeated here.

[0105] Please refer to Figures 8a to 8c Taking the example of an elliptical orthographic projection of the first hydrogen barrier 61 on the substrate 10, and the orthographic projection of the second hydrogen barrier 62 on the substrate 10 being a similar "elliptical ring structure," this embodiment provides three configurations for the hydrogen barrier 60. The first hydrogen barrier 61 in each of the following three configurations has the same structure; the only difference lies in the structure of the second hydrogen barrier 62.

[0106] like Figure 8a As shown, the arrangement of the second hydrogen barrier 62 in the fourth structure can refer to Figure 3a Description in Figure 8b As shown, the arrangement of the second hydrogen barrier 62 in the fifth structure can refer to Figure 3b Description in Figure 8c As shown, the arrangement of the second hydrogen barrier 62 in the sixth structure can refer to Figure 3c The description in , will not be repeated here.

[0107] It should be noted that in the first to sixth structures described above, the portion of the second hydrogen barrier 62 where the notches 621 are not provided is the connection area A between the second hydrogen barrier 62 and the first hydrogen barrier 61, thereby maximizing the hydrogen barrier effect of the hydrogen barrier 60. In addition, the configuration of the hydrogen barrier 60 in the above structures is merely an example to facilitate the description of this embodiment. The shape and size of the first hydrogen barrier 61, the specific number, position, and size of the notches 621 in the second hydrogen barrier 62, etc. can all be set according to actual application requirements, and this embodiment should not be construed as a limitation of this application.

[0108] Furthermore, the present application also provides a display panel, comprising a driver backplane and a light-emitting unit disposed on the driver backplane. The display panel may be a liquid crystal display panel, an organic light-emitting diode display panel, a miniature light-emitting diode display panel, or a micro light-emitting diode display panel. Taking an organic light-emitting diode display panel as an example, the display panel provided by the present application is described in detail below through specific examples.

[0109] Please refer to Figure 9 In Example 1 of the present application, a display panel 1000 is provided. The display panel 1000 includes a driving backplane 101 and a light-emitting unit disposed on the driving backplane 101 .

[0110] Specifically, the display panel 1000 further includes a first planarization layer 102, a connection electrode 103, a second planarization layer 104, an anode 105, a pixel definition layer 106, a light-emitting layer (not shown), and a cathode (not shown) sequentially disposed on the driving backplane 101. The anode 105, the light-emitting layer, and the cathode constitute a light-emitting unit.

[0111] It should be noted that the structure of the driving backplane 101 in this example is the same as the structure of the driving backplane 100 provided in the aforementioned first embodiment. The structure of the driving backplane 101 can refer to the description of the driving backplane 100 in the aforementioned first embodiment and will not be repeated here.

[0112] One end of the connecting electrode 103 is connected to the first drain electrode 342 via the signal transmission electrode 433, and the other end of the connecting electrode 103 is connected to the second drain electrode 432. Specifically, the material of the connecting electrode 103 may include a metal such as at least one of copper, aluminum, molybdenum, and titanium, or an alloy composed of at least two of the aforementioned metals. Furthermore, the anode 105 is connected to the connecting electrode 103, and an opening is defined in the pixel definition layer 106 to expose the anode 105. The related technologies are all prior art and will not be further described here.

[0113] Please refer to Figure 10 Example 2 of the present application provides a display panel 2000. The difference between the display panel 2000 provided in Example 2 of the present application and the display panel 1000 provided in Example 1 is that the structure of the driving backplane 101 is the same as that of the driving backplane 200 provided in the second embodiment.

[0114] Please refer to Figure 11 Example 3 of the present application provides a display panel 3000. The display panel 3000 provided in Example 3 of the present application differs from the display panel 1000 provided in Example 1 in that: the structure of the driving backplane 101 is the same as that of the driving backplane 300 provided in the aforementioned third embodiment; one end of the connecting electrode 103 is directly connected to the first drain electrode 342, and the other end of the connecting electrode 103 is connected to the second drain electrode 432.

[0115] Please refer to Figure 12 Example 4 of the present application provides a display panel 4000. The difference between the display panel 4000 provided in Example 4 of the present application and the display panel 3000 provided in Example 3 is that the structure of the driving backplane 101 is the same as that of the driving backplane 400 provided in the fourth embodiment.

[0116] The above is a detailed introduction to a driving backplane and display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A driving backplane, characterized in that: include: substrate; a metal oxide thin film transistor, disposed on one side of the substrate, the metal oxide thin film transistor including an oxide semiconductor portion; as well as a hydrogen barrier portion disposed on the substrate, the hydrogen barrier portion comprising a first hydrogen barrier portion and a second hydrogen barrier portion; wherein the first hydrogen barrier portion is disposed on a side of the oxide semiconductor portion close to the substrate, and an orthographic projection of the oxide semiconductor portion on the substrate and an orthographic projection of the first hydrogen barrier portion on the substrate at least partially overlap; The second hydrogen barrier portion is provided outside the oxide semiconductor portion, and an orthographic projection of the oxide semiconductor portion and an orthographic projection of the second hydrogen barrier portion at least partially overlap on a plane perpendicular to the substrate.

2. The driving backplane according to claim 1, characterized in that: The driving backplane also includes a low-temperature polysilicon thin film transistor arranged on the substrate, and the low-temperature polysilicon thin film transistor includes a low-temperature polysilicon semiconductor part, a first gate insulating layer, a first gate and a first source and drain arranged in sequence. The low-temperature polysilicon semiconductor part, the first gate insulating layer and the first gate are all located on the side of the oxide semiconductor part close to the substrate, and the first source and drain are connected to the low-temperature polysilicon semiconductor part; the first gate is reused as the first hydrogen barrier part.

3. The driving backplane according to claim 1, characterized in that: An orthographic projection of the oxide semiconductor portion on the substrate is located within an orthographic projection of the first hydrogen barrier portion on the substrate.

4. The driving backplane according to claim 2, characterized in that: The driving backplane further includes an insulating stack, the insulating stack being arranged on a side of the first hydrogen barrier away from the substrate, and the oxide semiconductor portion being located in the insulating stack; A connection hole is opened in the insulating stack, exposing the first hydrogen barrier portion. The second hydrogen barrier portion is arranged on the surface of the insulating stack and fills the connection hole. The second hydrogen barrier portion is connected to the first hydrogen barrier portion.

5. The driving backplane according to claim 4, characterized in that: The metal oxide thin film transistor also includes a second gate, which is arranged on a side of the oxide semiconductor portion away from the substrate and located on a surface of the insulating stack away from the substrate; a portion of the second hydrogen barrier portion located on the surface of the insulating stack is in the same layer as the second gate and is insulated.

6. The driving backplane according to claim 5, characterized in that: The insulating stack includes a first interlayer insulating layer and a second gate insulating layer, the first interlayer insulating layer is located between the first hydrogen barrier portion and the oxide semiconductor portion, and the second gate insulating layer is located between the oxide semiconductor portion and the second gate; The connection hole passes through the second gate insulating layer and the first interlayer insulating layer in sequence, the second hydrogen barrier is arranged on the surface of the second gate insulating layer and fills the connection hole, and the second hydrogen barrier is located on the surface of the second gate insulating layer in the same layer as the second gate and is insulated.

7. The driving backplane according to claim 4, characterized in that: The metal oxide thin film transistor also includes a second source and drain, which are arranged on the surface of the insulating layer away from the substrate and connected to the oxide semiconductor part; the second hydrogen barrier part is located on the surface of the insulating layer and is in the same layer as the second source and drain and is insulated.

8. The driving backplane according to claim 7, characterized in that: The metal oxide thin film transistor further includes a second gate, the second gate being located on a side of the oxide semiconductor portion away from the substrate; the insulating stack includes a first interlayer insulating layer, a second gate insulating layer, and a second interlayer insulating layer sequentially disposed on the substrate, the first interlayer insulating layer being located between the first hydrogen barrier portion and the oxide semiconductor portion, the second gate insulating layer being located between the oxide semiconductor portion and the second gate, and the second interlayer insulating layer being located between the second gate and the first source and drain; The connection hole passes through the second interlayer insulating layer, the second gate insulating layer and the first interlayer insulating layer in sequence, the second hydrogen barrier portion is arranged on the surface of the second interlayer insulating layer and filled in the connection hole, and the second hydrogen barrier portion is located on the surface of the second interlayer insulating layer in the same layer as the second source and drain and is insulated.

9. The driving backplane according to claim 1, characterized in that: The metal oxide thin film transistor further includes a second gate, which is arranged on a side of the oxide semiconductor portion away from the substrate. The second hydrogen barrier portion and the second gate are in the same layer and are insulated from each other.

10. The driving backplane according to claim 9, characterized in that: The second hydrogen barrier portion is disposed around the oxide semiconductor portion and has a notch at least in a region corresponding to the second gate. The second gate extends into the notch and toward the oxide semiconductor portion to cover the oxide semiconductor portion.

11. The driving backplane according to claim 1, characterized in that: The driving backplane also includes a low-temperature polycrystalline silicon thin film transistor arranged on the substrate, and the low-temperature polycrystalline silicon thin film transistor includes a low-temperature polycrystalline silicon semiconductor part, a first gate insulating layer, a first gate and a first source and drain arranged in sequence. The low-temperature polycrystalline silicon semiconductor part, the first gate insulating layer and the first gate are all located on the side of the oxide semiconductor part close to the substrate, and the first source and drain are connected to the low-temperature polycrystalline silicon semiconductor part; the first hydrogen barrier part and the first gate are in the same layer and are arranged at intervals.

12. The driving backplane according to claim 2, characterized in that: The metal oxide thin film transistor further includes a second gate and a second source and drain, the second gate being arranged on a side of the oxide semiconductor portion away from the substrate, and the second source and drain being arranged on a surface of the second gate away from the substrate and connected to the oxide semiconductor portion; The first source and drain and the second gate are arranged in the same layer; or the first source and drain and the second source and drain are arranged in the same layer.

13. A display panel, characterized in that: The invention comprises a driving backplane and a light-emitting unit arranged on the driving backplane, wherein the driving backplane is the driving backplane according to any one of claims 1 to 12.

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