A half-bridge drive control circuit

Abstract

The present invention provides a half-bridge drive control circuit, comprising: a high-side power transistor, a low-side power transistor, a logic module, a high-side power transistor drive module, a high-side power transistor turn-off module, and a low-side power transistor drive module; the logic module is configured to convert a PWM input signal into a high-side power transistor control signal and a low-side power transistor control signal; the high-side power transistor drive module controls the conduction of the high-side power transistor according to the input high-side power transistor control signal; the high-side power transistor turn-off module controls the turn-off of the high-side power transistor according to the input high-side power transistor control signal; the low-side power transistor drive module controls the conduction and turn-off of the low-side power transistor according to the input low-side power transistor control signal; the high-side power transistor control signal and the low-side power transistor control signal have opposite levels at the same time; when the high-side power transistor conducts, the low-side power transistor turns off, and when the high-side power transistor turns off, the low-side power transistor conducts.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a half-bridge drive control circuit. Background Art

[0002] DC motors are small in size, large in torque, and high in speed, making their applications very extensive, ranging from small devices such as pop-up cameras in mobile phones, toy cars, and floor-sweeping robots to large-scale applications such as automobiles, industrial automation robots, and numerical control machines. Especially in recent years, with the popularization of automotive electronic control, H-bridge driver chips have been increasingly widely used in automobiles. Since automotive-grade chips have extremely high requirements for the input voltage range and electromagnetic radiation characteristics, it has increased the difficulty of designing automotive-grade full-bridge drive chips.

[0003] The full-bridge motor power stage drive is as Figure 1 shown, which is composed of two half-bridge circuits, Q1+Q2 and Q3+Q4 respectively. Among them, Q1 / Q3 are high-side drive power transistors, and Q2 / Q4 are low-side drive power transistors.

[0004] The existing high-voltage automotive-grade half-bridge drive circuit is as Figure 2 shown. In the figure, HSMN and LSMN are the high-side and low-side power transistors of the half-bridge circuit respectively. The inverter INV1, INV2, and the AND gates NAND2, NAND3 form the logic control module of the half-bridge drive. The function of the Level shift module is to convert the logic signals in the low-voltage VDD-GND domain into logic signals in the high-voltage VBST-OUT domain. When PWM_IN = 0, EN_LS_ON = 1, EN_HS_ON = 0. At this time, the high-side power transistor HSMN is turned off, and the low-side power transistor LSMN is turned on. The OUT terminal is pulled down to a low level. At this time, the voltage VDD charges the off-chip bootstrap capacitor CBST through the on-chip diode D1, making VBST-OUT ≈ VDD. When PWM_IN = 1, EN_HS_ON = 1, EN_LS_ON = 0. At this time, the high-side power transistor HSMN is turned on, and the low-side power transistor LSMN is turned off. The OUT terminal is pulled up to the voltage VIN. At this time, the diode D1 is cut off, and the voltage of the off-chip bootstrap capacitor CBST cannot change suddenly. During the conduction stage of the high-side power transistor HSMN, VBST ≈ VDD + OUT, supplying power to the high-voltage domain power drive module.

[0005] From the above analysis, the existing half-bridge drive circuit has two problems in automotive applications: 1. Poor EMI characteristics, and the EMI characteristics cannot be optimized by adjusting the turn-on speed of the upper transistor; 2. This drive circuit requires an off-chip self-bootstrapping capacitor CBST, which undoubtedly increases the system application cost and further deteriorates the EMI characteristics.

[0006] Therefore, how to improve the electromagnetic radiation characteristics and save the overall system cost is the problem that needs to be solved currently. Summary of the Invention

[0007] The object of the present invention is to provide a half - bridge drive control circuit, which can improve the electromagnetic radiation characteristics and save the overall system cost.

[0008] To achieve the above object, the present invention provides a half - bridge drive control circuit, comprising:

[0009] A high - side power transistor, a low - side power transistor, a logic module, a high - side power transistor drive module, a high - side power transistor turn - off module, and a low - side power transistor drive module;

[0010] The logic module is used to convert the PWM input signal into a high - side power transistor control signal and a low - side power transistor control signal;

[0011] The high - side power transistor drive module controls the high - side power transistor to turn on according to the input high - side power transistor control signal;

[0012] The high - side power transistor turn - off module controls the high - side power transistor to turn off according to the input high - side power transistor control signal;

[0013] The low - side power transistor drive module controls the low - side power transistor to turn on and off according to the input low - side power transistor control signal;

[0014] The high - side power transistor control signal and the low - side power transistor control signal have opposite levels at the same time; when the high - side power transistor is on, the low - side power transistor is off, and when the high - side power transistor is off, the low - side power transistor is on;

[0015] The input signal of the high - side power transistor drive module further includes: a clock signal and the output signal of the half - bridge drive control circuit, and the high - side power transistor drive module outputs a high - side power transistor voltage drive signal;

[0016] When the high - side power transistor control signal changes from low level to high level, the high - side power transistor drive module starts to work. Under the control of the clock signal, the output high - side power transistor voltage drive signal is gradually increased, so as to control the high - side power transistor to turn on, and at the same time the low - side power transistor is off;

[0017] When the high - side power transistor control signal changes from high level to low level, the high - side power transistor turn - off module pulls down the high - side power transistor voltage drive signal, so that the high - side power transistor is off, and at the same time the low - side power transistor is on.

[0018] In an alternative embodiment, the input signal of the high - side power transistor drive module includes a slope adjustment signal, and the slope adjustment signal is used to adjust the rising speed of the voltage of the drive signal.

[0019] In an alternative solution, the high-side power transistor driving module includes: a first NAND gate, a second NAND gate, a third NAND gate, a first inverter, a second inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, and a second capacitor;

[0020] One input terminal of the first NAND gate is used for inputting the high-side power transistor control signal, and the other input terminal is used for inputting the clock signal. The output terminal is connected to the input terminal of the first inverter; the output terminal of the first inverter is connected to the input terminal of the second inverter and one input terminal of the second NAND gate; the other input terminal of the second NAND gate is connected to the output terminal of the third NAND gate; the output terminal of the second inverter is connected to one input terminal of the third NAND gate, and the other input terminal of the third NAND gate is connected to the output terminal of the second NAND gate;

[0021] The output terminal of the second NAND gate is connected to the gate of the first NMOS transistor and the gate of the first PMOS transistor; the source of the first PMOS transistor is connected to the power supply voltage, and the drain is connected to the drain of the first NMOS transistor and one end of the first capacitor; the source of the first NMOS transistor is grounded through the first resistor, connected to the drain of the fourth NMOS transistor through the second resistor, connected to the drain of the third NMOS transistor through the third resistor, and connected to the drain of the second NMOS transistor through the fourth resistor; the sources of the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all grounded; the gates of the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are used for inputting the slope adjustment signal;

[0022] The output terminal of the third NAND gate is connected to the gates of the fifth NMOS transistor and the second PMOS transistor; the source of the second PMOS transistor is connected to the power supply voltage, and the drain is connected to the drain of the fifth NMOS transistor and one end of the second capacitor; the source of the fifth NMOS transistor is grounded through the fifth resistor, connected to the drain of the sixth NMOS transistor through the sixth resistor, connected to the drain of the seventh NMOS transistor through the seventh resistor, and connected to the drain of the eighth NMOS transistor through the eighth resistor; the sources of the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are all grounded; the gate of the sixth NMOS transistor is connected to the gate of the fourth NMOS transistor; the gate of the seventh NMOS transistor is connected to the gate of the third NMOS transistor; the gate of the eighth NMOS transistor is connected to the gate of the second NMOS transistor;

[0023] The other end of the first capacitor is connected to the gate of the third PMOS transistor, the gate of the ninth NMOS transistor, the drain of the fourth PMOS transistor, and the drain of the tenth NMOS transistor; the sources of the ninth NMOS transistor and the tenth NMOS transistor are connected to the high-side power transistor turn-off module and serve as the output terminal of the half-bridge drive control circuit; the drain of the ninth NMOS transistor is connected to the gate of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate of the tenth NMOS transistor, and the other end of the second capacitor; the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the gate of the high-side power transistor and output the drive signal of the high-side power transistor.

[0024] In an alternative embodiment, the high-side power transistor drive module further includes a first buffer and a second buffer;

[0025] The first buffer is connected between the output terminal of the second NAND gate and the gate of the first PMOS transistor;

[0026] The second buffer is connected between the output terminal of the third NAND gate and the gate of the second PMOS transistor.

[0027] In an alternative embodiment, the logic module includes: a fourth inverter, a fifth inverter, a fourth NAND gate, and a fifth NAND gate;

[0028] The input terminal of the fourth inverter is used to input the PWM input signal, and the output terminal is connected to the input terminal of the fifth inverter and one input terminal of the fifth NAND gate; the other input terminal of the fifth NAND gate is connected to the output terminal of the fourth NAND gate; the output terminal of the fifth inverter is connected to one input terminal of the fourth NAND gate; the other input terminal of the fourth NAND gate is connected to the output terminal of the fifth NAND gate;

[0029] The output terminal of the fourth NAND gate is used to output the low-side power transistor control signal; the output terminal of the fifth NAND gate is used to output the high-side power transistor control signal.

[0030] In an alternative solution, the high-side power transistor turn-off module includes: a third inverter, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a first high-voltage transistor, and a second high-voltage transistor;

[0031] The input terminal of the third inverter is connected to the gate of the first high-voltage transistor for inputting the high-side power transistor control signal. The output terminal of the third inverter is connected to the gate of the second high-voltage transistor. The source of the second high-voltage transistor is connected to the drain of the thirteenth NMOS transistor. The gate of the thirteenth NMOS transistor is connected to the gate of the twelfth NMOS transistor, the gate and drain of the eleventh NMOS transistor, and is connected to the power supply voltage. The drain of the twelfth NMOS transistor is connected to the source of the first high-voltage transistor. The sources of the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are all grounded;

[0032] The drain of the first high-voltage transistor is connected to the gate and drain of the fifth PMOS transistor, the gate of the sixth PMOS transistor, the drain of the seventh PMOS transistor, and the gate of the ninth PMOS transistor. The drain of the sixth PMOS transistor is connected to the drain and gate of the eighth PMOS transistor, the gate of the seventh PMOS transistor, the drain of the ninth PMOS transistor, the gate of the tenth PMOS transistor, and the drain of the second high-voltage transistor;

[0033] The drain of the tenth PMOS transistor is connected to the high-side power transistor driving module and serves as the output terminal of the half-bridge driving control circuit;

[0034] The sources of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor are connected to the gate of the high-side power transistor and output the driving signal of the high-side power transistor.

[0035] In an alternative solution, the high-side power transistor turn-off module includes a third buffer and a fourth buffer; the high-side power transistor control signal is input to the gate of the first high-voltage transistor through the third buffer; the fourth buffer is connected between the third inverter and the second high-voltage transistor.

[0036] In an alternative embodiment, the low-side power transistor driving module is a buffer or a combination of buffers connected in series; the input terminal of the buffer is connected to the output terminal of the fourth NAND gate, and the output terminal of the buffer is connected to the gate of the low-side power transistor.

[0037] In an alternative embodiment, the drain of the high-side power transistor is connected to the input voltage, the source is connected to the drain of the low-side power transistor and the output of the half-bridge driving control circuit, and the source of the low-side power transistor is grounded.

[0038] The beneficial effects of the present invention are as follows:

[0039] The present invention can improve the electromagnetic radiation performance of half-bridge and full-bridge driving chips, and at the same time enable the driving chips to eliminate off-chip bootstrap capacitors, reducing the system cost. Specifically, by integrating a high-side power transistor driving module in the chip as the driving circuit of the high-side power transistor, the off-chip bootstrap capacitor is eliminated. At the same time, by adjusting the turn-on speed of the high-side power transistor driving module, the conduction slope of the high-side power transistor can be controlled, thereby facilitating the optimization of electromagnetic radiation characteristics from the system level. Description of the Drawings

[0040] By describing the exemplary embodiments of the present invention in more detail in conjunction with the drawings, the above and other objects, features, and advantages of the present invention will become more apparent. In the exemplary embodiments of the present invention, the same reference numerals generally represent the same components.

[0041] Figure 1 It is a schematic diagram of the full-bridge motor power stage drive.

[0042] Figure 2 It is an existing automotive half-bridge drive circuit.

[0043] Figure 3 It is a schematic diagram of the architecture of the half-bridge driving control circuit according to an embodiment of the present invention.

[0044] Figure 4 It is a schematic diagram of the implementation of the half-bridge driving control circuit according to an embodiment of the present invention. Detailed Embodiments

[0045] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will be clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in many different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0046] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, or part discussed below may be denoted as the second element, component, region, layer, or part.

[0047] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0049] Embodiment 1

[0050] Referring to Figure 3 and Figure 4 , this embodiment provides a half-bridge drive control circuit, comprising:

[0051] High-side power transistor HSMN, low-side power transistor LSMN, logic module LOGIC_CTR, high-side power transistor driving module CHARGE_PUMP, high-side power transistor turn-off module HS_OFF_CTR, and low-side power transistor driving module LS_DRV;

[0052] The logic module LOGIC_CTR is used to convert the PWM input signal PWM_IN into a high-side power transistor control signal EN_HS_ON and a low-side power transistor control signal EN_LS_ON;

[0053] The high-side power transistor driving module CHARGE_PUMP controls the conduction of the high-side power transistor according to the input high-side power transistor control signal EN_HS_ON;

[0054] The high-side power transistor turn-off module HS_OFF_CTR controls the turn-off of the high-side power transistor according to the input high-side power transistor control signal EN_HS_ON;

[0055] The low-side power transistor driving module LS_DRV controls the conduction and turn-off of the low-side power transistor according to the input low-side power transistor control signal EN_LS_ON;

[0056] The high-side power transistor control signal EN_HS_ON and the low-side power transistor control signal EN_LS_ON have opposite levels at the same time; when the high-side power transistor conducts, the low-side power transistor turns off, and when the high-side power transistor turns off, the low-side power transistor conducts.

[0057] That is, the high-side power transistor control signal EN_HS_ON controls the conduction of the high-side power transistor through the high-side power transistor driving module CHARGE_PUMP and controls the turn-off of the high-side power transistor through the high-side power transistor turn-off module HS_OFF_CTR. The low-side power transistor control signal EN_LS_ON controls the conduction and turn-off of the low-side power transistor through the low-side power transistor driving module LS_DRV. And when the high-side power transistor turns off, the low-side power transistor conducts, and when the low-side power transistor turns off, the high-side power transistor conducts.

[0058] Specifically, in this embodiment, the input signals of the high-side power transistor driving module CHARGE_PUMP further include: a slope adjustment signal TRIM_HS_SR<2:0>, a clock signal CLK_IN, and an output signal OUT of the half-bridge driving control circuit. The high-side power transistor driving module CHARGE_PUMP outputs a high-side power transistor voltage driving signal HS_GATE_DRV. When the high-side power transistor control signal EN_HS_ON changes from a low level to a high level, the high-side power transistor driving module CHARGE_PUMP starts to operate. Under the control of the clock signal CLK_IN, the output high-side power transistor voltage driving signal HS_GATE_DRV is gradually increased, thereby controlling the conduction of the high-side power transistor, and at the same time, the low-side power transistor is turned off. When the high-side power transistor control signal EN_HS_ON changes from a high level to a low level, the high-side power transistor turn-off module HS_OFF_CTR pulls down the high-side power transistor voltage driving signal, turning off the high-side power transistor, and at the same time, the low-side power transistor is turned on. The slope adjustment signal is used to adjust the rising speed of the voltage of the driving signal HS_GATE_DRV. The drain of the high-side power transistor HSMN is connected to the input voltage VIN, the source is connected to the drain of the low-side power transistor LSMN and the output OUT of the half-bridge driving control circuit, and the source of the low-side power transistor LSMN is grounded.

[0059] In this embodiment, the high-side power transistor driving module CHARGE_PUMP includes: a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a first inverter INV1, a second inverter INV2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, and a second capacitor C2; One input terminal of the first NAND gate NAND1 is used to input the high-side power transistor control signal EN_HS_ON, and the other input terminal is used to input the clock signal CLK_IN, and the output terminal is connected to the input terminal of the first inverter INV1; The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2 and one input terminal of the second NAND gate NAND2; The other input terminal of the second NAND gate NAND2 is connected to the output terminal of the third NAND gate NAND3; The output terminal of the second inverter INV2 is connected to one input terminal of the third NAND gate NAND3, and the other input terminal of the third NAND gate NAND3 is connected to the output terminal of the second NAND gate NAND2; The output terminal of the second NAND gate NAND2 is connected to the gate of the first NMOS transistor MN1 and the gate of the first PMOS transistor MP1; The source of the first PMOS transistor MP1 is connected to the power supply voltage VDD, and the drain is connected to the drain of the first NMOS transistor MN1 and one end of the first capacitor C1; The source of the first NMOS transistor MN1 is grounded through the first resistor R1, connected to the drain of the fourth NMOS transistor MN4 through the second resistor R2, connected to the drain of the third NMOS transistor MN3 through the third resistor R3, and connected to the drain of the second NMOS transistor MN2 through the fourth resistor R4; The sources of the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all grounded; The gates of the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are used to input the slope adjustment signal; The output terminal of the third NAND gate NAND3 is connected to the gate of the fifth NMOS transistor MN5 and the gate of the second PMOS transistor MP2; The source of the second PMOS transistor MP2 is connected to the power supply voltage VDD, and the drain is connected to the drain of the fifth NMOS transistor MN5 and one end of the second capacitor C2;The source of the fifth NMOS transistor MN5 is grounded through the fifth resistor R5, connected to the drain of the sixth NMOS transistor MN6 through the sixth resistor R6, connected to the drain of the seventh NMOS transistor MN7 through the seventh resistor R7, and connected to the drain of the eighth NMOS transistor MN8 through the eighth resistor R8; the sources of the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 are all grounded; the gate of the sixth NMOS transistor MN6 is connected to the gate of the fourth NMOS transistor MN4; the gate of the seventh NMOS transistor MN7 is connected to the gate of the third NMOS transistor MN3; the gate of the eighth NMOS transistor MN8 is connected to the gate of the second NMOS transistor MN2; the other end of the first capacitor C1 is connected to the gate of the third PMOS transistor MP3, the gate of the ninth NMOS transistor MN9, the drain of the fourth PMOS transistor MP4, and the drain of the tenth NMOS transistor MN10; the sources of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are connected to the high-side power transistor turn-off module and serve as the output terminal of the half-bridge drive control circuit; the drain of the ninth NMOS transistor MN9 is connected to the gate of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4, the gate of the tenth NMOS transistor MN10, and the other end of the second capacitor C2; the sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the gate of the high-side power transistor and output the drive signal HS_GATE_DRV of the high-side power transistor.

[0060] In this embodiment, the high-side power transistor drive module CHARGE_PUMP further includes a first buffer BUF1 and a second buffer BUF2; the first buffer BUF1 is connected between the output terminal of the second NAND gate NAND2 and the gate of the first PMOS transistor MP1; the second buffer BUF2 is connected between the output terminal of the third NAND gate NAND3 and the gate of the second PMOS transistor MP2.

[0061] In this embodiment, the logic module LOGIC_CTR includes: a fourth inverter INV4, a fifth inverter INV5, a fourth NAND gate NAND4, and a fifth NAND gate NAND5; the input terminal of the fourth inverter INV4 is used to input the PWM input signal, and the output terminal is connected to the input terminal of the fifth inverter INV5 and one input terminal of the fifth NAND gate NAND5; the other input terminal of the fifth NAND gate NAND5 is connected to the output terminal of the fourth NAND gate NAND4; the output terminal of the fifth inverter INV5 is connected to one input terminal of the fourth NAND gate NAND4; the other input terminal of the fourth NAND gate NAND4 is connected to the output terminal of the fifth NAND gate NAND5; the output terminal of the fourth NAND gate NAND4 is used to output the low-side power transistor control signal EN_LS_ON; the output terminal of the fifth NAND gate NAND5 is used to output the high-side power transistor control signal EN_HS_ON. It should be noted that the function of the logic module LOGIC_CTR is to generate the low-side power transistor control signal EN_LS_ON and the high-side power transistor control signal EN_HS_ON. However, the generation method of the low-side power transistor control signal EN_LS_ON and the high-side power transistor control signal EN_HS_ON is not limited to this. In other embodiments, it can also be independently controlled by the host respectively.

[0062] The high-side power transistor turn-off module HS_OFF_CTR includes: a third inverter INV3, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a first high-voltage transistor HVMN1, and a second high-voltage transistor HVMN2; the input terminal of the third inverter INV3 is connected to the gate of the first high-voltage transistor HVMN1 for inputting the high-side power transistor control signal EN_HS_ON, the output terminal of the third inverter INV3 is connected to the gate of the second high-voltage transistor HVMN2, the source of the second high-voltage transistor HVMN2 is connected to the drain of the thirteenth NMOS transistor MN13, the gate of the thirteenth NMOS transistor MN13 is connected to the gate of the twelfth NMOS transistor MN12, the gate and drain of the eleventh NMOS transistor MN11, and is connected to the power supply voltage VDD; the drain of the twelfth NMOS transistor MN12 is connected to the source of the first high-voltage transistor HVMN1; the sources of the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, and the thirteenth NMOS transistor MN13 are all grounded; the drain of the first high-voltage transistor HVMN1 is connected to the gate and drain of the fifth PMOS transistor MP5, the gate of the sixth PMOS transistor MP6, the drain of the seventh PMOS transistor MP7, and the gate of the ninth PMOS transistor MP9; the drain of the sixth PMOS transistor MP6 is connected to the drain and gate of the eighth PMOS transistor MP8, the gate of the seventh PMOS transistor MP7, the drain of the ninth PMOS transistor MP9, the gate of the tenth PMOS transistor MP10, and the drain of the second high-voltage transistor HVMN2; the drain of the tenth PMOS transistor MP10 is connected to the high-side power transistor drive module CHARGE_PUMP and serves as the output terminal of the half-bridge drive control circuit; the sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10 are connected to the gate of the high-side power transistor HSMN and output the drive signal HS_GATE_DRV of the high-side power transistor.

[0063] In this embodiment, the high-side power transistor turn-off module HS_OFF_CTR includes a third buffer BUF3 and a fourth buffer BUF4; the high-side power transistor control signal EN_HS_ON is input to the gate of the first high-voltage transistor HVMN1 through the third buffer BUF3; the fourth buffer BUF4 is connected between the third inverter INV3 and the second high-voltage transistor HVMN2.

[0064] The low-side power transistor driving module LS_DRV is a buffer or a combination of buffers connected in series; the input end of the buffer is connected to the output end of the fourth NAND gate NAND4, and the output end of the buffer is connected to the gate of the low-side power transistor LSMN. Refer to Figure 4 , in this embodiment, the low-side power transistor driving module LS_DRV includes a fifth buffer BUF5 and a sixth buffer BUF6; the input end of the fifth buffer BUF5 is connected to the output end of the fourth NAND gate NAND4, and the output end of the fifth buffer BUF5 is connected to the input end of the sixth buffer BUF6 which is connected to the output end of the fifth buffer BUF5, and the output end of the sixth buffer BUF6 is connected to the gate of the low-side power transistor LSMN.

[0065] The working principle of this half-bridge driving control circuit is described below:

[0066] The function of the logic module LOGIC_CTR is to convert the PWM input signal PWM_IN into the enable signals of the high-side power transistor HSMN and the low-side power transistor LSMN. When PWM_IN = H, EN_HS_ON = H, EN_LS_ON = L. At this time, the high-side power transistor driving module CHARGE_PUMP is enabled to turn on the high-side power transistor HSMN, and at the same time, the low-side power transistor LSMN is turned off. When PWM_IN = L, EN_HS_ON = L, EN_LS_ON = H. At this time, the high-side power transistor driving module CHARGE_PUMP is turned off, the high-side power transistor HSMN is turned off, and at the same time, the low-side power transistor LSMN is turned on.

[0067] The function of the high-side power transistor driving module CHARGE_PUMP is to control the high-side power transistor HSMN to turn on. Its input signals are the high-side power transistor control signal EN_HS_ON, the slope adjustment signal TRIM_HS_SR<2:0>, the high-frequency clock signal CLK_IN and the output signal OUT of the control circuit, and its output signal is the driving signal HS_GATE_DRV of the high-side power transistor. When EN_HS_ON changes from low level to high level, the high-side power transistor driving module CHARGE_PUMP starts to work. Under the control of the high-frequency clock signal CLK_IN, the third PMOS transistor MP3, the ninth NMOS transistor MN9, the first PMOS transistor MP1, the first NMOS transistor MN1, the fourth PMOS transistor MP4, the tenth NMOS transistor MN10, the second PMOS transistor MP2, and the fifth NMOS transistor MN5 charge and discharge the first capacitor C1 and the second capacitor C2 in sequence, and raise the voltage of the driving signal HS_GATE_DRV of the high-side power transistor from V OUT gradually, and finally reach V HS_GATE_DRV = V OUT+V DD . The first capacitor C1 and the second capacitor C2 are integrated capacitors inside the chip. In this module, the function of the slope adjustment signal TRIM_HS_SR<2:0> is to adjust the equivalent impedance to ground of nodes S1 and S2 by controlling the on and off of the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8, so as to adjust the rising speed of the driving signal HS_GATE_DRV of the high-side power transistor. The slope adjustment signal TRIM_HS_SR<2:0> is generated by a digital control register, a host interface, etc., which is a conventional technology in this field. Considering symmetry, the aspect ratios of the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 are kept the same. At the same time, the resistance values R1 = R5, R2 = R6, R3 = R7, and R4 = R8. For example, when the driving signal TRIM_HS_SR<2:0> of the high-side power transistor = 111, the equivalent impedance R to ground of node S1 (the intersection of the source of the first NMOS transistor and the fourth resistor) S1 = R1 / / R2 / / R3 / / R4 (in parallel), and the equivalent impedance R to ground of node S2 (the intersection of the source of the fifth NMOS transistor and the eighth resistor) S2 = R5 / / R6 / / R7 / / R8. At this time, the equivalent resistance is the smallest, and the turn-on slope of the high-side power transistor HSMN is the fastest; when TRIM_HS_SR<2:0> = 000, the equivalent impedance R to ground of node S1 S1 = R1, and the equivalent impedance R to ground of node S2 S2 = R5. At this time, the equivalent resistance is the largest, and the turn-on slope of the high-side power transistor HSMN is the slowest.

[0068] The function of the high-side power transistor turn-off module HS_OFF_CTR is that when PWM_IN = L, EN_HS_ON = L, and EN_LS_ON = H, when the low-side power transistor LSMN starts to conduct, the driving signal HS_GATE_DRV of the high-side power transistor is pulled to the same potential as the OUT terminal, so that V GS_HSMN = 0 (the gate-source voltage of the high-side power transistor), and the high-side power transistor HSMN is completely turned off. The first high-voltage transistor HVMN1 and the second high-voltage transistor HVMN2 are high-voltage transistors. The high-voltage transistor in this embodiment refers to a MOS transistor whose input drain-source voltage is allowed to be above 5V. When EN_HS_ON = L, the first high-voltage transistor HVMN1 is cut off, the G9 node is at a high level, the second high-voltage transistor HVMN2 is turned on, and the G10 node (the intersection of the drain of the eighth PMOS transistor and the gate of the tenth PMOS transistor) is pulled down so that the tenth MOS transistor MP10 is turned on, so that V HS_GATE_DRV = VOUT When PWM_IN = H, EN_HS_ON = H, and EN_LS_ON = L, when the low-side power transistor LSMN is turned off, at this time, the first high-voltage transistor HVMN1 is turned on, and the G9 node (the intersection of the drain of the fifth PMOS transistor and the gate of the ninth PMOS transistor) is pulled down, causing the ninth PMOS transistor MP9 to be turned on and the tenth PMOS transistor MP10 to be turned off, so that the high-side power transistor HSMN is gradually controlled to be turned on by the high-side power transistor driving module CHARGE_PUMP module.

[0069] In this embodiment, the high-side power transistor driving module CHARGE_PUMP in the chip is used as the driving circuit for the high-side power transistor, eliminating the bootstrap capacitor outside the chip, saving the overall system cost. At the same time, without an external bootstrap capacitor on the chip, it helps to improve its electromagnetic radiation characteristics. By adjusting the charge and discharge speed of the high-side power transistor driving module CHARGE_PUMP in this embodiment, the turn-on slope of the high-side power transistor can be flexibly controlled, facilitating further optimization of the electromagnetic radiation characteristics from the system level. The half-bridge drive control circuit proposed in this embodiment has the characteristics of low system cost and good electromagnetic interference characteristics, and this half-bridge drive control circuit can be widely applied to in-vehicle motor drive chips and various full-bridge drive chips.

[0070] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A half-bridge drive control circuit, characterized in that: include: High-side power tube, low-side power tube, logic module, high-side power tube driver module, high-side power tube shutdown module and low-side power tube driver module; The logic module is used to convert the PWM input signal into a high-side power tube control signal and a low-side power tube control signal; The high-side power tube driving module controls the high-side power tube to be turned on according to the input high-side power tube control signal; The high-side power tube shutdown module controls the high-side power tube to shut down according to the input high-side power tube control signal; The low-side power tube driving module controls the low-side power tube to be turned on and off according to the input low-side power tube control signal; The high-side power tube control signal and the low-side power tube control signal are at opposite levels at the same time; when the high-side power tube is turned on, the low-side power tube is turned off, and when the high-side power tube is turned off, the low-side power tube is turned on; The input signal of the high-side power tube driving module also includes: a clock signal and an output signal of the half-bridge driving control circuit, and the high-side power tube driving module outputs a high-side power tube voltage driving signal; When the high-side power tube control signal changes from a low level to a high level, the high-side power tube driving module starts to work, and under the control of the clock signal, the output high-side power tube voltage driving signal is gradually increased, thereby controlling the high-side power tube to be turned on, and the low-side power tube to be turned off; When the high-side power tube control signal changes from a high level to a low level, the high-side power tube shutdown module pulls down the high-side power tube voltage drive signal to shut down the high-side power tube, while turning on the low-side power tube.

2. The half-bridge drive control circuit according to claim 1, characterized in that: The input signal of the high-side power tube driving module includes a slope adjustment signal, and the slope adjustment signal is used to adjust the voltage increase speed of the driving signal.

3. The half-bridge drive control circuit according to claim 2, characterized in that: The high-side power tube driving module includes: A first NAND gate, a second NAND gate, a third NAND gate, a first inverter, a second inverter, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, and a second capacitor; One input end of the first NAND gate is used to input the high-side power tube control signal, the other input end is used to input the clock signal, and the output end is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter and one input end of the second NAND gate; the other input end of the second NAND gate is connected to the output end of the third NAND gate; the output end of the second inverter is connected to one input end of the third NAND gate, and the other input end of the third NAND gate is connected to the output end of the second NAND gate; The output end of the second NAND gate is connected to the gate of the first NMOS tube and the gate of the first PMOS tube; the source of the first PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the first NMOS tube and one end of the first capacitor; the source of the first NMOS tube is grounded through the first resistor, connected to the drain of the fourth NMOS tube through the second resistor, connected to the drain of the third NMOS tube through the third resistor, and connected to the drain of the second NMOS tube through the fourth resistor; the sources of the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are all grounded; the gates of the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are used to input the slope adjustment signal; The output end of the third NAND gate is connected to the gate of the fifth NMOS tube and the gate of the second PMOS tube; the source of the second PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the fifth NMOS tube and one end of the second capacitor; the source of the fifth NMOS tube is grounded through the fifth resistor, connected to the drain of the sixth NMOS tube through the sixth resistor, connected to the drain of the seventh NMOS tube through the seventh resistor, and connected to the drain of the eighth NMOS tube through the eighth resistor; the sources of the sixth NMOS tube, the seventh NMOS tube, and the eighth NMOS tube are all grounded; the gate of the sixth NMOS tube is connected to the gate of the fourth NMOS tube; the gate of the seventh NMOS tube is connected to the gate of the third NMOS tube; the gate of the eighth NMOS tube is connected to the gate of the second NMOS tube; The other end of the first capacitor is connected to the gate of the third PMOS tube, the gate of the ninth NMOS tube, the drain of the fourth PMOS tube and the drain of the tenth NMOS tube; the source of the ninth NMOS tube and the source of the tenth NMOS tube are connected to the high-side power tube shutdown module and serve as the output end of the half-bridge drive control circuit; the drain of the ninth NMOS tube is connected to the gate of the third PMOS tube, the gate of the fourth PMOS tube, the gate of the tenth NMOS tube and the other end of the second capacitor; the source of the third PMOS tube and the source of the fourth PMOS tube are connected to the gate of the high-side power tube and output the drive signal of the high-side power tube.

4. The half-bridge drive control circuit according to claim 3, characterized in that: The high-side power tube driving module also includes a first buffer and a second buffer; The first buffer is connected between the output end of the second NAND gate and the gate of the first PMOS tube; The second buffer is connected between the output terminal of the third NAND gate and the gate of the second PMOS tube.

5. The half-bridge drive control circuit according to claim 1, characterized in that: The logic module includes: a fourth inverter, a fifth inverter, a fourth NAND gate and a fifth NAND gate; The input end of the fourth inverter is used to input the PWM input signal, and the output end is connected to the input end of the fifth inverter and one input end of the fifth NAND gate; the other input end of the fifth NAND gate is connected to the output end of the fourth NAND gate; the output end of the fifth inverter is connected to one input end of the fourth NAND gate; the other input end of the fourth NAND gate is connected to the output end of the fifth NAND gate; The output end of the fourth NAND gate is used to output the low-side power tube control signal; the output end of the fifth NAND gate is used to output the high-side power tube control signal.

6. The half-bridge drive control circuit according to claim 1, characterized in that: The high-side power tube shutdown module includes: a third inverter, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a first high-voltage tube, and a second high-voltage tube; The input end of the third inverter is connected to the gate of the first high-voltage tube, and is used to input the high-side power tube control signal. The output end of the third inverter is connected to the gate of the second high-voltage tube. The source of the second high-voltage tube is connected to the drain of the thirteenth NMOS tube. The gate of the thirteenth NMOS tube is connected to the gate of the twelfth NMOS tube and the gate and drain of the eleventh NMOS tube and connected to the power supply voltage. The drain of the twelfth NMOS tube is connected to the source of the first high-voltage tube. The sources of the eleventh NMOS tube, the twelfth NMOS tube, and the thirteenth NMOS tube are all grounded. The drain of the first high-voltage tube is connected to the gate and drain of the fifth PMOS tube, the gate of the sixth PMOS tube, the drain of the seventh PMOS tube and the gate of the ninth PMOS tube; the drain of the sixth PMOS tube is connected to the drain and gate of the eighth PMOS tube, the gate of the seventh PMOS tube, the drain of the ninth PMOS tube, the gate of the tenth PMOS tube and the drain of the second high-voltage tube; The drain of the tenth PMOS tube is connected to the high-side power tube driving module and serves as the output end of the half-bridge driving control circuit; The sources of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are connected to the gate of the high-side power tube and output the driving signal of the high-side power tube.

7. The half-bridge drive control circuit according to claim 6, characterized in that: The high-side power tube shutdown module includes a third buffer and a fourth buffer; the high-side power tube control signal is input to the gate of the first high-voltage tube through the third buffer; and the fourth buffer is connected between the third inverter and the second high-voltage tube.

8. The half-bridge drive control circuit according to claim 1, characterized in that: The low-side power tube driving module is a buffer or a combination of buffers connected in series; the input end of the buffer is connected to the output end of the fourth NAND gate, and the output end of the buffer is connected to the gate of the low-side power tube.

9. The half-bridge drive control circuit according to claim 1, characterized in that: The drain of the high-side power tube is connected to the input voltage, the source is connected to the drain of the low-side power tube and the output of the half-bridge drive control circuit, and the source of the low-side power tube is grounded.

Images