A sampling grid voltage bootstrap switch capable of avoiding overvoltage

Abstract

The application provides a sampling grid voltage bootstrap switch capable of avoiding overpressure, and relates to the technical field of power electronics, and comprises a voltage multiplication module, a sampling voltage division module and a switch tube module; the voltage multiplication module is connected with the sampling voltage division module and the switch tube module respectively, and the sampling voltage division module is connected with the switch tube module. The application reduces the parasitic capacitance on the pump pressure path and eliminates the nonlinearity of the parasitic capacitance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, and particularly relates to a sampling gate voltage bootstrap switch capable of avoiding overvoltage. BACKGROUND

[0002] In modern electronic systems, the precision and speed of an analog-to-digital converter (ADC) have a crucial impact on the overall performance. As a key component in an ADC, the performance of a sampling switch directly determines the accuracy of a sampling signal and the overall efficiency of a circuit. Traditional sampling switches, such as single-tube switches or transmission gate switches, although simple in structure, have drawbacks such as large on-resistance and strong nonlinearity, which significantly affect the accuracy of a sampling signal.

[0003] In order to overcome these drawbacks, gate voltage bootstrap switches are widely used in analog-to-digital converter circuits. Gate voltage bootstrap technology uses a charge pump to raise the gate voltage of a sampling switch to a level one power supply voltage higher than an input signal, thereby achieving a constant gate-source voltage (VGS) of the sampling switch as a power supply voltage. This technology significantly reduces the on-resistance and nonlinearity, and improves the sampling speed and accuracy. However, in the process of raising the gate voltage, many devices on the path of the traditional gate voltage bootstrap switch may face overvoltage problems, causing the transistor to work in an overvoltage state for a long time, accelerating its aging process and greatly reducing the service life of the product.

[0004] Therefore, a sampling gate voltage bootstrap switch capable of avoiding overvoltage is proposed. SUMMARY

[0005] The present application provides a sampling gate voltage bootstrap switch capable of avoiding overvoltage, which reduces the parasitic capacitance on the pump pressure path and eliminates the nonlinearity of the parasitic capacitance.

[0006] The present application provides a sampling gate voltage bootstrap switch capable of avoiding overvoltage, which includes:

[0007] a voltage multiplication module, a sampling voltage division module, and a switch tube module; the voltage multiplication module is connected with the sampling voltage division module and the switch tube module, and the sampling voltage division module is connected with the switch tube module.

[0008] Optionally, the voltage multiplication module comprises an inverter I1 and an inverter I2, the inverter I1 is connected with a pump capacitor C3 and the inverter I2 respectively, the pump capacitor C3 is connected with a switch tube MN3, the switch tube MN3 is connected with a switch tube MN2 and a switch tube MP4 respectively, the switch tube MN2 is connected with a switch tube MN1 and a pump capacitor C2 respectively, the pump capacitor C2 is connected with the inverter I2; the switch tube MP4 is connected with a switch tube MP3, a switch tube MN9 and a power supply voltage AVDD respectively, the switch tube MP3 is connected with the switch tube MN9, the switch tube MN1 is connected with the switch tube module and the sampling voltage division module respectively.

[0009] Optionally, the voltage multiplication module comprises an inverter I1 and an inverter I2, the inverter I1 is connected with a pump capacitor C3 and the inverter I2 respectively, the pump capacitor C3 is connected with a Deep-Nwell tube, the Deep-Nwell tube is connected with a pump capacitor C2, the switch tube module and the sampling voltage division module, the pump capacitor C2 is connected with the inverter I2.

[0010] Optionally, the switch tube module comprises a pump capacitor C1, the pump capacitor C1 is connected with a switch tube MN0 and a switch tube MP1 respectively, the switch tube MN0 is connected with a switch tube MN4, the switch tube MN4 is connected with a switch tube MN5 and the switch tube MP0 respectively, the switch tube MP0 is connected with the switch tube MP1, the switch tube MP1 is connected with the sampling voltage division module, the switch tube MN5 is connected with a switch tube MN6, the switch tube MN6 is connected with a sampling tube MNS, the sampling tube MNS is connected with a capacitor CS.

[0011] Optionally, the sampling voltage division module comprises a switch tube MP2, the switch tube MP2 is connected with a switch tube MN7 and a switch tube MN8 respectively.

[0012] Optionally, comprising:

[0013] When the power supply voltage AVDD is powered on, the body-source diode of the switch tube MN2 and the switch tube MN3 is positively biased, and the node of the switch tube MN2 and the switch tube MN3 is charged to the power supply voltage AVDD.

[0014] Optionally, comprising:

[0015] When the reset stage CLK is low and CLKB is high, the switch tube MN2, the switch tube MN1, the switch tube MN0 and the switch tube MN8 are turned on, vin_track and CLK_BS are 0, CLKBB is low, the switch tube MP0 is turned on, the switch tube MP1 is turned off, and the sampling tube MNS is turned off.

[0016] Optionally comprising:

[0017] When the sampling stage CLK is high and CLKBB is high, the switch tube MN1 and the switch tube MN2 are off, the switch tube MN4 is on, CLKBB is low, the switch tube MN0 and the switch tube MN8 are off, the switch tube MP2 is on, the switch tube MN7 gate voltage is high, the switch tube MN5 and the switch tube MN6 are on, vin_track and N4 node are charged to vin; the switch tube MN1 is off, the switch tube MP1 is on, the switch tube MN7 is disconnected, so as to realize that the VGS of the sampling tube MNS is AVDD.

[0018] In the application, the body terminal of the switch tube MN2 and the switch tube MN3 is connected to AVDD, which changes the body terminal potential of the NMOS tube for charging the pump capacitor, and avoids the overvoltage problem. Meanwhile, the body terminal of the switch tube MN1 is connected to vin_track, which reduces the parasitic capacitance on the pump path and eliminates the nonlinearity of the parasitic capacitance. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 The schematic diagram of the sampling gate voltage bootstrap switch which can avoid overvoltage;

[0021] Figure 2 The waveform diagram of each node and signal in the circuit.

[0022] FIG. 10 is a voltage multiplication module; 20, a sampling voltage division module; 30, a switch tube module. DETAILED DESCRIPTION

[0023] The following description is used to disclose the present application so that those skilled in the art can implement the present application. The preferred embodiments in the following description are only as examples, and other obvious modifications can be thought by those skilled in the art. The basic principles of the present application defined in the following description can be applied to other embodiments, modifications, improvements, equivalents and other technical solutions without departing from the spirit and scope of the present application.

[0024] The following description is used to disclose the present application so that those skilled in the art can implement the present application. The preferred embodiments in the following description are only as examples, and other obvious modifications can be thought by those skilled in the art. The basic principles of the present application defined in the following description can be applied to other embodiments, modifications, improvements, equivalents and other technical solutions without departing from the spirit and scope of the present application. Figures 1-2Exemplary embodiments of the present application are described more fully hereinafter with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art. Like reference numerals refer to like elements throughout the specification. Repetitive descriptions of like elements will be omitted for sake of brevity.

[0025] In the case of a certain specific embodiment, the features, structures, characteristics or other details described do not exclude that they can be combined in a suitable manner in one or more other embodiments, in accordance with the technical concept of the present application.

[0026] In the description of the specific embodiments, the features, structures, characteristics or other details described are intended to enable a person skilled in the art to fully understand the embodiments. However, it does not exclude that a person skilled in the art can practice the technical solution of the present application without one or more of the specific features, structures, characteristics or other details.

[0027] The flowcharts shown in the drawings are only exemplary illustrations, and do not necessarily include all the contents and operations / steps, nor do they have to be executed in the order described. For example, some operations / steps can be further decomposed, and some operations / steps can be combined or partially combined, so the actual execution order can be changed according to the actual situation.

[0028] The block diagrams shown in the drawings are only functional entities, and do not necessarily have to correspond to physically independent entities. That is, these functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0029] The term "and / or" or "and / or" includes all combinations of one or more of the associated listed items.

[0030] The embodiment of the present application provides a sampling grid voltage bootstrap switch capable of circumventing overvoltage, which comprises: Figure 1As shown, the voltage multiplication module, the sampling voltage division module, and the switch tube module; the voltage multiplication module is connected with the sampling voltage division module and the switch tube module, and the sampling voltage division module is connected with the switch tube module. The voltage multiplication module is used to charge the upper plate of the pump capacitor C1 by opening the switch tube MN1 in the reset stage. The voltage multiplication module includes an inverter I1 and an inverter I2, and the inverter I1 and the inverter I2 are used to generate the CLKB and the CLKBB signals to control the working state of the sampling voltage division module and the switch tube module. The inverter I1 is connected with the pump capacitor C3 and the inverter I2, the pump capacitor C3 is connected with the switch tube MN3, and the upper plate of the capacitor is pumped to a higher voltage through the pump capacitor C3. The switch tube MN3 is connected with the switch tube MN2 and the switch tube MP4, and the preliminary voltage is raised by alternately charging and discharging C2 and C3. The switch tube MN2 is connected with the switch tube MN1 and the pump capacitor C2, the pump capacitor C2 is connected with the inverter I2, and the upper plate of the capacitor is pumped to a higher voltage through the pump capacitor C2. The switch tube MP4 is connected with the switch tube MP3, the switch tube MN9, and the power voltage AVDD, the switch tube MP3 is connected with the switch tube MN9, and the switch tube MN1 is connected with the switch tube module and the sampling voltage division module. It is worth noting that the body terminals of the switch tube MN1, the switch tube MN2, and the switch tube MN3 are connected with the P-type substrate (P-sub), because the switch tube N1 is raised to vin+AVDD in the working process, and the switch tube N2 and the switch tube N3 are raised to 2*AVDD in the working process, and the P-sub is grounded, so that the reverse bias voltage of the body-source diode of the switch tube MN1, the switch tube MN2, and the switch tube MN3 is too high, and there is a risk of breakdown. In summary, the voltage multiplication module realizes efficient voltage multiplication by skillfully using the switch tube and the pump capacitor, and has the advantages of high efficiency, low power consumption, small size, flexible design, and high reliability.

[0031] The switch tube MN1 is replaced by a PMOS, the gate end is connected to the N5 node, and the body end is connected to the N1 node. The switch tube MN2, the switch tube MN3, the pumping capacitor C2 and the pumping capacitor C3 are discarded. Although the overvoltage problem is avoided, the body end of the PMOS is an N-well, and there is a large nonlinear capacitor between the N-well and the P-sub. The capacitor is between the N1 node and the ground, which will cause a large nonlinearity in the sampling process. The voltage multiplication module includes an inverter I1 and an inverter I2. The inverter I1 is connected with the pumping capacitor C3 and the inverter I2. The pumping capacitor C3 is connected with a Deep-Nwell tube. The Deep-Nwell tube is connected with the pumping capacitor C2, the switch tube module and the sampling voltage division module. The pumping capacitor C2 is connected with the inverter I2. Under the control of the clock signal, the Deep-Nwell tubes MN2 and MN3 (as switches) are alternately opened to connect the pumping capacitors C2 and C3 to the power supply voltage AVDD or floating. When MN3 is opened, the upper plate of C3 is charged to AVDD. At this time, MN2 is in the off state, so C2 is floating, and the upper plate is pumped up to AVDD. When MN2 is opened, the upper plate of C2 is charged to the power supply voltage. At this time, MN3 is in the off state, so C3 is floating, and the upper plate of C3 is pumped up to AVDD.

[0032] The switch tube module includes a pumping capacitor C1. Since the switch state of MN1 is the same as that of MN2, when the upper plate of C2 is charged to AVDD, the upper plate of C1 is also charged to the same voltage. When the upper plate of C2 is pumped up to AVDD, the upper plate of C1 will also be pumped up to AVDD to realize that the N1 node is higher than vin by one AVDD. The pumping capacitor C1 is connected with a switch tube MN0 and a switch tube MP1. The switch tube MN0 is connected with a switch tube MN4. The switch tube MN4 is connected with a switch tube MN5 and a switch tube MP0. The switch tube MP0 is connected with the switch tube MP1. The switch tube MP1 is connected with the sampling voltage division module. The switch tube MN5 is connected with a switch tube MN6. The switch tube MN6 is connected with a sampling tube MNS. The sampling tube MNS is connected with a capacitor CS.

[0033] The sampling voltage division module includes a switch tube MP2. The switch tube MP2 is connected with a switch tube MN7 and a switch tube MN8.

[0034] As shown in Figure 2 When the power supply voltage AVDD is powered on, the body-source diode of the switch tube MN2 and the switch tube MN3 is forward biased, and the node of the switch tube MN2 and the switch tube MN3 is charged to the power supply voltage AVDD.

[0035] When the reset stage CLK is low and the CKB is high, the N3 voltage is 2*AVDD, the switch tube MN2, the switch tube MN1, the switch tube MN0 and the switch tube MN8 are turned on, the N2, N1 voltage is AVDD, the vin_track and the CLK_BS are 0, the CLKBB is low, the switch tube MP0 is turned on, the switch tube MP1 is turned off, the sampling tube MNS is turned off, and the voltage across the pump capacitor C1 is AVDD.

[0036] When the sampling stage CLK is high and the CLKBB is high, the N2 is 2*AVDD, the N3 is AVDD, the switch tube MN1 and the switch tube MN2 are turned off, the switch tube MN4 is turned on, the CKB is low, the switch tube MN0 and the switch tube MN8 are turned off, the switch tube MP2 is turned on, the N7 node is AVDD, the gate voltage of the switch tube MN7 is high, AVDD charges to the N5 node through the switch tube MP2 and the switch tube MN7, the switch tube MN5 and the switch tube MN6 are turned on, the vin_track and the N4 node are charged to vin; the switch tube MN1 is turned off, the N1 node is a high resistance node, and the N1 voltage is lifted to AVDD+vin due to the charge conservation, the switch tube MP1 is turned on and the VGS is AVDD, the N1 node charges to the N5 node, the switch tube MN7 is disconnected, the CLK_BS is AVDD+vin, so that the VGS of the sampling tube MNS is AVDD.

[0037] In the application, the body terminal of the switch tube MN2 and the switch tube MN3 is connected to AVDD, the body terminal potential of the NMOS tube charging the pump capacitor is changed, and the overvoltage problem is avoided. Meanwhile, the body terminal of the switch tube MN1 is connected to the vin_track, the parasitic capacitance on the pump path is reduced, and the nonlinearity of the parasitic capacitance is eliminated.

[0038] The above-described specific embodiments further illustrate the purpose, technical solutions and advantages of the application. It should be understood that the application is not inherently related to any specific computer, virtual device or electronic equipment, and various general-purpose devices can also implement the application. The above-described specific embodiments are merely examples of the application and are not intended to limit the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application should be included in the protection scope of the application.

[0039] Each embodiment in the specification is described in a progressive manner, and the same or similar parts of each embodiment can be referred to each other. Each embodiment focuses on the difference from other embodiments.

[0040] The above merely provides an example of the present application, but is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application should be included in the scope of claims of the present application.

Claims

1. A gate voltage sampling bootstrap switch capable of avoiding overvoltage, characterized in that: include: A voltage multiplier module (10), a sampling voltage divider module (20), and a switch tube module (30); the voltage multiplier module (10) is connected to the sampling voltage divider module (20) and the switch tube module (30), respectively, and the sampling voltage divider module (20) is connected to the switch tube module (30); The voltage multiplier module (10) comprises an inverter I1 and an inverter I2, wherein the inverter I1 is connected to the pump capacitor C3 and the inverter I2 respectively; The pumping capacitor C3 is connected to the switch tube MN3, the switch tube MN3 is respectively connected to the switch tube MN2 and the switch tube MP4, the switch tube MN2 is respectively connected to the switch tube MN1 and the pumping capacitor C2, and the pumping capacitor C2 is connected to the inverter I2; the switch tube MP4 is respectively connected to the switch tube MP3, the switch tube MN9, and the power supply voltage AVDD, the switch tube MP3 is connected to the switch tube MN9, and the switch tube MN1 is respectively connected to the switch tube module (30) and the sampling voltage divider module (20); Alternatively, the inverter I1 is connected to the pumping capacitor C3 and the inverter I2 respectively, the pumping capacitor C3 is connected to the Deep-Nwell tube, the Deep-Nwell tube is connected to the pumping capacitor C2, the switch tube module (30), and the sampling voltage divider module (20), and the pumping capacitor C2 is connected to the inverter I2.

2. The overvoltage-avoiding gate voltage sampling bootstrap switch according to claim 1, wherein: The switch tube module (30) includes a pumping capacitor C1, the pumping capacitor C1 is respectively connected to the switch tube MN0 and the switch tube MP1, the switch tube MN0 is connected to the switch tube MN4, the switch tube MN4 is respectively connected to the switch tube MN5 and the switch tube MP0, the switch tube MP0 is connected to the switch tube MP1, the switch tube MP1 is connected to the sampling voltage divider module (20), the switch tube MN5 is connected to the switch tube MN6, the switch tube MN6 is connected to the sampling tube MNS, and the sampling tube MNS is connected to the capacitor CS.

3. The overvoltage-avoiding gate voltage sampling bootstrap switch according to claim 2, wherein: The sampling voltage dividing module (20) comprises a switch tube MP2, and the switch tube MP2 is connected to the switch tube MN7 and the switch tube MN8 respectively.

4. The overvoltage-avoiding gate voltage sampling bootstrap switch according to claim 1, wherein: include: When the power supply voltage AVDD is powered on, the body-source diodes of the switch transistor MN2 and the switch transistor MN3 are forward biased, and the node between the switch transistor MN2 and the switch transistor MN3 is charged to the power supply voltage AVDD.

5. The gate voltage sampling bootstrap switch capable of avoiding overvoltage according to claim 3, wherein: include: During the reset phase, when CLK is low and CLKB is high, the switch transistors MN2, MN1, MN0, and MN8 are turned on, vin_track and CLK_BS are 0, CLKBB is low, the switch transistor MP0 is turned on, the switch transistor MP1 is turned off, and the sampling transistor MNS is turned off.

6. The gate voltage sampling bootstrap switch capable of avoiding overvoltage according to claim 3, wherein: include: During the sampling phase, when CLK is high and CLKBB is high, the switches MN1 and MN2 are turned off, the switch MN4 is turned on, CLKB is low, the switches MN0 and MN8 are turned off, the switch MP2 is turned on, the gate voltage of the switch MN7 is high, the switches MN5 and MN6 are turned on, and the vin_track and N4 nodes are both charged to vin; the switch MN1 is turned off, the switch MP1 is turned on, and the switch MN7 is turned off, so that the VGS of the sampling transistor MNS is AVDD.

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