A gate voltage bootstrap switch circuit and control method for a multiplexed analog-to-digital converter

Abstract

The application discloses a gate voltage bootstrap switch circuit and a control method of a multiplexing analog-to-digital converter, and the circuit comprises a gate voltage bootstrap circuit module, a voltage buffer module, a gating switch module and a MOS sampling switch tube module. The method comprises the following steps: controlling the voltage buffer module, the gating switch module and the MOS sampling switch tube module to be in a sampling stage or a holding stage according to a first control clock signal and a second control clock signal; driving the voltage output of the gate voltage bootstrap circuit module to obtain an output voltage signal; controlling the MOS sampling switch tube module to be in a conduction state or a holding state according to a gating switch signal; and performing sampling and holding processing on an input voltage signal. The embodiment of the application can greatly optimize the area and power consumption of the gate voltage bootstrap switch circuit in the front end of a traditional high-precision multi-channel analog-to-digital converter. The application can be widely applied to the technical field of mixed signal circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of mixed signal circuit, and particularly relates to a gate voltage bootstrap switch circuit and control method of a multiplexing analog-to-digital converter. BACKGROUND

[0002] In recent years, under the strong driving of industrial demand, research on wearable biomedical chips is very extensive, and research results emerge in an endless stream. As a key of wearable biomedical chips, analog front-end signal acquisition and processing circuit technology has attracted the attention and research of many institutions and scholars, and is in a rapid development stage. In related circuit design, a multiplexing data acquisition system is basically used. At this time, a multi-channel analog front-end circuit is usually integrated in the chip, each channel of which integrates an LNA and a PGA, and a circuit multiplexing technology is used to make the multi-channel front-end circuit share an ADC. Therefore, a high-precision switch circuit must be designed between the PGA and the ADC to realize the gating function of the channel, but the on-resistance of the traditional MOS switch is directly related to the size of the input voltage, and the linearity of the system is poor, so it is only suitable for a low-precision analog-to-digital converter connected in the back. In a high-precision analog-to-digital converter, a gate voltage bootstrap switch circuit is usually used.

[0003] The gate voltage bootstrap switch circuit keeps the gate-source voltage of the MOS switch constant by connecting a capacitor in parallel between the gate and the source of the MOS tube, so that the on-resistance does not change with the change of the input voltage. In the holding stage, the sampling switch is turned off, the bootstrap capacitor is connected to the ground and the power supply, and the voltage difference across the bootstrap capacitor is charged to the power supply value. In the sampling stage, the bootstrap capacitor is disconnected from both ends and connected to the input signal and the gate of the sampling switch MOS tube. At this time, the top plate voltage value of the bootstrap capacitor is the sum of the input signal and the power supply value, so that the gate-source voltage of the sampling MOS tube remains basically unchanged, improving its linearity. Since the area and power consumption of the gate voltage bootstrap switch circuit are larger than those of a single MOS switch, the gate voltage bootstrap switch circuit occupies a larger circuit area and consumes more power in a multiplexing analog-to-digital converter that needs to use multiple gate voltage bootstrap switches.

[0004] In summary, the technical problems in the related art need to be improved. SUMMARY

[0005] The main purpose of the embodiments of the present application is to provide a gate voltage bootstrap switch circuit and control method of a multiplexing analog-to-digital converter, which can greatly optimize the area and power consumption of the gate voltage bootstrap switch circuit in the front end of a traditional high-precision multi-channel analog-to-digital converter.

[0006] To achieve the above object, one aspect of the embodiment of the present application proposes a gate voltage bootstrap switch circuit of a multiplexing analog-to-digital converter, which comprises a gate voltage bootstrap circuit module, a voltage buffer module, a gating switch module and a MOS sampling switch tube module, the output end of the gate voltage bootstrap circuit module is connected with the input end of the voltage buffer module, the output end of the voltage buffer module is connected with the input end of the gating switch module, the output end of the gating switch module is connected with the input end of the MOS sampling switch tube module, wherein:

[0007] The gate voltage bootstrap circuit module is used to control the voltage buffer module, the gating switch module and the MOS sampling switch tube module to be in a sampling state or a holding state according to a first control clock signal and a second control clock signal;

[0008] The voltage buffer module is used to drive the voltage output of the gate voltage bootstrap circuit module and obtain an output voltage signal;

[0009] The gating switch module is used to control the MOS sampling switch tube module to be in a conducting state or a holding state according to a gating switch signal, and if the MOS sampling switch tube module is in the conducting state, the output voltage signal is transmitted to the MOS sampling switch tube module;

[0010] The MOS sampling switch tube module is used to sample and hold an input voltage signal.

[0011] In some embodiments, the gate voltage bootstrap circuit module comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a bootstrap capacitor, a gate of the first MOS transistor is connected with a gate of the second MOS transistor and receives the first control clock signal, a source of the first MOS transistor, a drain of the third MOS transistor, a gate of the seventh MOS transistor and a source of the eighth MOS transistor are connected, a drain of the first MOS transistor, a drain of the second MOS transistor, a gate of the fifth MOS transistor and a drain of the sixth MOS transistor are connected, a source of the second MOS transistor, a drain of the fourth MOS transistor, a second terminal of the bootstrap capacitor and a source of the sixth MOS transistor are connected, a source of the fourth MOS transistor is grounded, a gate of the fourth MOS transistor receives the second control clock signal, a source of the third MOS transistor, a first terminal of the bootstrap capacitor and a source of the fifth MOS transistor are connected, a gate of the third MOS transistor, a drain of the fifth MOS transistor, a gate of the sixth MOS transistor and a drain of the seventh MOS transistor are connected, a source of the seventh MOS transistor, a drain of the eighth MOS transistor and a drain of the ninth MOS transistor are connected, a gate of the eighth MOS transistor is connected with a gate of the ninth MOS transistor and receives the second control clock signal, and a source of the ninth MOS transistor is grounded.

[0012] In some embodiments, the gate voltage bootstrap circuit module comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a bootstrap capacitor, a gate of the first MOS transistor is connected with a gate of the second MOS transistor and receives the first control clock signal, a source of the first MOS transistor, a drain of the third MOS transistor, a gate of the seventh MOS transistor and a source of the eighth MOS transistor are connected, a drain of the first MOS transistor, a drain of the second MOS transistor, a gate of the fifth MOS transistor and a drain of the sixth MOS transistor are connected, a source of the second MOS transistor, a drain of the fourth MOS transistor, a second terminal of the bootstrap capacitor and a source of the sixth MOS transistor are connected, a source of the fourth MOS transistor is grounded, a gate of the fourth MOS transistor receives the second control clock signal, a source of the third MOS transistor, a first terminal of the bootstrap capacitor and a source of the fifth MOS transistor are connected, a gate of the third MOS transistor, a drain of the fifth MOS transistor, a gate of the sixth MOS transistor and a drain of the seventh MOS transistor are connected, a source of the seventh MOS transistor, a drain of the eighth MOS transistor and a drain of the ninth MOS transistor are connected, a gate of the eighth MOS transistor is connected with a gate of the ninth MOS transistor and receives the second control clock signal, and a source of the ninth MOS transistor is grounded.

[0013] In some embodiments, the first gate-on switch comprises a tenth MOS transistor and an eleventh MOS transistor, the second gate-on switch comprises a fourteenth MOS transistor and a fifteenth MOS transistor, and the third gate-on switch comprises an eighteenth MOS transistor and a nineteenth MOS transistor, wherein:

[0014] The gate of the tenth MOS tube is connected with the gate of the eleventh MOS tube and is connected with a first gate-on switch signal, the drain of the tenth MOS tube is connected with the drain of the eleventh MOS tube and is connected with the first MOS sampling switch tube, the source of the tenth MOS tube is connected with the voltage buffer module, and the source of the eleventh MOS tube is connected with the ground.

[0015] The gate of the fourteenth MOS tube is connected with the gate of the fifteenth MOS tube and is connected with a second gate-on switch signal, the drain of the fourteenth MOS tube is connected with the drain of the fifteenth MOS tube and is connected with the second MOS sampling switch tube, the source of the fourteenth MOS tube is connected with the voltage buffer module, and the source of the fifteenth MOS tube is connected with the ground.

[0016] The gate of the eighteenth MOS tube is connected with the gate of the nineteenth MOS tube and is connected with a third gate-on switch signal, the drain of the eighteenth MOS tube is connected with the drain of the nineteenth MOS tube and is connected with the third MOS sampling switch tube, the source of the eighteenth MOS tube is connected with the voltage buffer module, and the source of the nineteenth MOS tube is connected with the ground.

[0017] In some embodiments, the first MOS sampling switch tube comprises a twelfth MOS tube and a thirteenth MOS tube, the second MOS sampling switch tube comprises a sixteenth MOS tube and a seventeenth MOS tube, and the third MOS sampling switch tube comprises a twentieth MOS tube and a twenty-first MOS tube, wherein:

[0018] The gate of the twelfth MOS tube is connected with the gate of the thirteenth MOS tube and is connected with the first gate-on switch, the drain of the twelfth MOS tube is connected with the source of the thirteenth MOS tube and is connected with a first input voltage signal, the source of the twelfth MOS tube is connected with the gate voltage self-boosting circuit module, and the drain of the thirteenth MOS tube is connected with the second MOS sampling switch tube and the third MOS sampling switch tube respectively.

[0019] The gate of the sixteenth MOS tube is connected with the gate of the seventeenth MOS tube and is connected with the second gate-on switch, the drain of the sixteenth MOS tube is connected with the source of the seventeenth MOS tube and is connected with a second input voltage signal, the source of the sixteenth MOS tube is connected with the gate voltage self-boosting circuit module, and the drain of the seventeenth MOS tube is connected with the first MOS sampling switch tube and the third MOS sampling switch tube respectively.

[0020] The gate of the twentieth MOS tube is connected with the gate of the twenty-first MOS tube and the third gating switch, the drain of the twentieth MOS tube is connected with the source of the twenty-first MOS tube and a third input voltage signal, the source of the twentieth MOS tube is connected with the gate voltage bootstrap circuit module, and the drain of the twenty-first MOS tube is connected with the first MOS sampling switch tube and the second MOS sampling switch tube respectively.

[0021] In some embodiments, further comprising:

[0022] The first gating switch is used for controlling the first MOS sampling switch tube module to be in a conductive state or a holding state according to the first gating switch signal.

[0023] The second gating switch is used for controlling the second MOS sampling switch tube module to be in a conductive state or a holding state according to the second gating switch signal.

[0024] The third gating switch is used for controlling the third MOS sampling switch tube module to be in a conductive state or a holding state according to the third gating switch signal.

[0025] The first MOS sampling switch tube is used for sampling and holding the first input voltage signal.

[0026] The second MOS sampling switch tube is used for sampling and holding the second input voltage signal.

[0027] The third MOS sampling switch tube is used for sampling and holding the third input voltage signal.

[0028] To achieve the above object, another aspect of the embodiment of the present application proposes a control method of a gate voltage bootstrap switch circuit of a multiplexing analog-to-digital converter, which comprises the following steps:

[0029] According to the first control clock signal and the second control clock signal, the voltage buffer module, the gating switch module and the MOS sampling switch tube module are controlled to be in a sampling stage or a holding stage.

[0030] The voltage output of the gate voltage bootstrap circuit module is driven to obtain an output voltage signal.

[0031] According to the gating switch signal, the MOS sampling switch tube module is controlled to be in a conductive state or a holding state, and if the MOS sampling switch tube module is in the conductive state, the output voltage signal is transmitted to the MOS sampling switch tube module.

[0032] The input voltage signal is sampled and held.

[0033] In some embodiments, the second control clock signal is an inverted version of the first control clock signal.

[0034] In some embodiments, in the sampling phase, the self-boosting capacitor in the gate voltage self-boosting circuit module is disconnected from the power supply and the ground by the first control clock signal and the second control clock signal, and the top plate voltage value of the self-boosting capacitor is the sum of the input signal of the gating channel of the gating switch module and the power supply voltage when the corresponding channel is selected by the voltage buffer module and the first gating switch, the second gating switch and the third gating switch.

[0035] In some embodiments, in the holding phase, the self-boosting capacitor in the gate voltage self-boosting circuit module is connected to the ground and the power supply by the first control clock signal and the second control clock signal, and the voltage difference between the two ends of the self-boosting capacitor is charged to the power supply voltage value.

[0036] The embodiments of the present application at least have the following beneficial effects: the present application provides a gate voltage self-boosting switch circuit and a control method of a multiplexing analog-to-digital converter, which introduces a gating switch module and a MOS sampling switch tube module, controls the gate-source voltage of the MOS sampling switch tube to remain basically unchanged by the gating state of the gating switch module, improves the linearity, further simplifies the circuit design without sacrificing the circuit performance, and can greatly optimize the area and power consumption of the front-end gate voltage self-boosting switch circuit in the traditional high-precision multi-channel analog-to-digital converter. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a structural schematic diagram of a gate voltage self-boosting switch circuit of a multiplexing analog-to-digital converter provided by the embodiments of the present application;

[0038] Figure 2 is a step flowchart of a control method of a gate voltage self-boosting switch circuit of a multiplexing analog-to-digital converter provided by the embodiments of the present application;

[0039] Figure 3 is a structural schematic diagram of an existing gate voltage self-boosting switch circuit provided by the embodiments of the present application;

[0040] Figure 4 is a simulation result schematic diagram of a gate voltage self-boosting switch circuit provided by the embodiments of the present application.

[0041] Reference numerals: 1, gate voltage bootstrap circuit module; 2, voltage buffer module; 3, first gating switch; 4, first MOS sampling switch tube; 5, second gating switch; 6, second MOS sampling switch tube; 7, third gating switch; 8, third MOS sampling switch tube. DETAILED DESCRIPTION

[0042] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present examples. They are only examples of systems and methods consistent with some aspects of the present examples as detailed in the appended claims.

[0043] It can be understood that the terms "first", "second", and the like used in the present application can be used herein to describe various concepts, but unless specifically stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the present examples, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determining".

[0044] The terms "at least one", "multiple", "each", "any" and the like used in the present application include one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by those skilled in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0046] Reference Figure 1 , Figure 1 A flowchart of a gate voltage bootstrap switch circuit of a multiplexing analog-to-digital converter according to an embodiment of the present application is shown in FIG. 1. The gate voltage bootstrap switch circuit includes a gate voltage bootstrap circuit module 1, a voltage buffer module 2, a first gating switch 3, a first MOS sampling switch tube 4, a second gating switch 5, a second MOS sampling switch tube 6, a third gating switch 7, and a third MOS sampling switch tube 8. Figure 1The circuit comprises a gate voltage self-boosting circuit module 1, a voltage buffer module 2, a gating switch module and a MOS sampling switch tube module, the output end of the gate voltage self-boosting circuit module is connected with the input end of the voltage buffer module, the output end of the voltage buffer module is connected with the input end of the gating switch module, and the output end of the gating switch module is connected with the input end of the MOS sampling switch tube module.

[0047] The gate voltage self-boosting circuit module is used for controlling the voltage buffer module, the gating switch module and the MOS sampling switch tube module to be in a sampling state or a holding state according to the first control clock signal and the second control clock signal.

[0048] Specifically, the gate voltage self-boosting circuit module comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9 and a self-boosting capacitor C boot , the gate of the first MOS tube is connected with the gate of the second MOS tube and is connected with the first control clock signal, the source of the first MOS tube, the drain of the third MOS tube and the gate of the seventh MOS tube are connected with the source of the eighth MOS tube, the drain of the first MOS tube, the drain of the second MOS tube, the gate of the fifth MOS tube and the drain of the sixth MOS tube are connected, the source of the second MOS tube, the drain of the fourth MOS tube and the second end of the self-boosting capacitor are connected with the source of the sixth MOS tube, the source of the fourth MOS tube is grounded, the gate of the fourth MOS tube is connected with the second control clock signal, the source of the third MOS tube, the first end of the self-boosting capacitor and the source of the fifth MOS tube are connected, the gate of the third MOS tube, the drain of the fifth MOS tube, the gate of the sixth MOS tube and the drain of the seventh MOS tube are connected, the source of the seventh MOS tube, the drain of the eighth MOS tube and the drain of the ninth MOS tube are connected, the gate of the eighth MOS tube and the gate of the ninth MOS tube are connected and are connected with the second control clock signal, and the source of the ninth MOS tube is grounded.

[0049] In the embodiment, the gate voltage self-boosting circuit module is used for, in a sampling phase, the gate voltage self-boosting circuit module being controlled by the first control clock signal CK s and the second control clock signal NCK s , controlling the voltage buffer module, the first gating switch module, the first MOS sampling switch tube, the second gating switch module, the second MOS sampling switch tube, the third gating switch module and the third MOS sampling switch tube to complete sampling, and realizing the gate voltage self-boosting function; in a holding phase, the gate voltage self-boosting circuit module being controlled by the control clock CK s and NCK s , so that the first MOS sampling switch tube, the second MOS sampling switch tube and the third MOS sampling switch tube are all cut off.

[0050] The voltage buffer module is used for driving the voltage output of the gate voltage self-boosting circuit module, and obtaining an output voltage signal.

[0051] In the embodiment, the voltage buffer module is used for further improving the voltage driving capability of the output end of the gate voltage self-boosting circuit module.

[0052] The gating switch module is used for controlling the MOS sampling switch tube module to be in a conducting state or a holding state according to a gating switch signal, and if the MOS sampling switch tube module is in the conducting state, the output voltage signal is transmitted to the MOS sampling switch tube module.

[0053] The MOS sampling switch tube module is used for sampling and holding the input voltage signal.

[0054] Specifically, the gating switch module includes a first gating switch 3, a second gating switch 5 and a third gating switch 7, the MOS sampling switch tube module includes a first MOS sampling switch tube 4, a second MOS sampling switch tube 6 and a third MOS sampling switch tube 8, the output end of the first gating switch is connected to the input end of the first MOS sampling switch tube, the output end of the second gating switch is connected to the input end of the second MOS sampling switch tube, the output end of the third gating switch is connected to the input end of the third MOS sampling switch tube, the output end of the first MOS sampling switch tube, the output end of the second MOS sampling switch tube and the output end of the third MOS sampling switch tube are connected to each other and serve as a total output end of the gate voltage self-boosting switch circuit, the input end of the first gating switch, the input end of the second gating switch and the input end of the third gating switch are all connected to the output end of the voltage buffer module, wherein the first gating switch is used for controlling the first MOS sampling switch tube module to be in a conducting state or a holding state according to a first gating switch signal; the second gating switch is used for controlling the second MOS sampling switch tube module to be in a conducting state or a holding state according to a second gating switch signal; the third gating switch is used for controlling the third MOS sampling switch tube module to be in a conducting state or a holding state according to a third gating switch signal; the first MOS sampling switch tube is used for sampling and holding a first input voltage signal; the second MOS sampling switch tube is used for sampling and holding a second input voltage signal; and the third MOS sampling switch tube is used for sampling and holding a third input voltage signal.

[0055] Further, it needs to be noted that the first gating switch includes a tenth MOS tube M 10 and an eleventh MOS tube M 11 , the second gating switch includes a fourteenth MOS tube M 14 and a fifteenth MOS tube M 15 , and the third gating switch includes an eighteenth MOS tube M 18 and a nineteenth MOS tube M 19The gate of the tenth MOS tube is connected with the gate of the eleventh MOS tube and connected with the first gate-on switch signal, the drain of the tenth MOS tube is connected with the drain of the eleventh MOS tube and connected with the first MOS sampling switch tube, the source of the tenth MOS tube is connected with the voltage buffer module, the source of the eleventh MOS tube is connected with the ground, the gate of the fourteenth MOS tube is connected with the gate of the fifteenth MOS tube and connected with the second gate-on switch signal, the drain of the fourteenth MOS tube is connected with the drain of the fifteenth MOS tube and connected with the second MOS sampling switch tube, the source of the fourteenth MOS tube is connected with the voltage buffer module, the source of the fifteenth MOS tube is connected with the ground, the gate of the eighteenth MOS tube is connected with the gate of the nineteenth MOS tube and connected with the third gate-on switch signal, the drain of the eighteenth MOS tube is connected with the drain of the nineteenth MOS tube and connected with the third MOS sampling switch tube, the source of the eighteenth MOS tube is connected with the voltage buffer module, and the source of the nineteenth MOS tube is connected with the ground.

[0056] Further, it needs to be further explained that the first MOS sampling switch tube includes the twelfth MOS tube M 12 and the thirteenth MOS tube M 13 , the second MOS sampling switch tube includes the sixteenth MOS tube M 16 and the seventeenth MOS tube M 17 , and the third MOS sampling switch tube includes the twentieth MOS tube M 20 and the twenty-first MOS tube M 21 , wherein the gate of the twelfth MOS tube is connected with the gate of the thirteenth MOS tube and connected with the first gate-on switch, the drain of the twelfth MOS tube is connected with the source of the thirteenth MOS tube and connected with the first input voltage signal, the source of the twelfth MOS tube is connected with the gate voltage self-lifting circuit module, the drain of the thirteenth MOS tube is connected with the second MOS sampling switch tube and the third MOS sampling switch tube, the gate of the sixteenth MOS tube is connected with the gate of the seventeenth MOS tube and connected with the second gate-on switch, the drain of the sixteenth MOS tube is connected with the source of the seventeenth MOS tube and connected with the second input voltage signal, the source of the sixteenth MOS tube is connected with the gate voltage self-lifting circuit module, the drain of the seventeenth MOS tube is connected with the first MOS sampling switch tube and the third MOS sampling switch tube, the gate of the twentieth MOS tube is connected with the gate of the twenty-first MOS tube and connected with the third gate-on switch, the drain of the twentieth MOS tube is connected with the source of the twenty-first MOS tube and connected with the third input voltage signal, the source of the twentieth MOS tube is connected with the gate voltage self-lifting circuit module, and the drain of the twenty-first MOS tube is connected with the first MOS sampling switch tube and the second MOS sampling switch tube.

[0057] In this embodiment, the first selection switch is used to transmit the output voltage signal of the voltage buffer module to the gate of the first MOS sampling switch tube when the first channel is selected; and to connect the gate of the first MOS sampling switch tube to the ground to cut off the first channel when the first channel is not selected.

[0058] The first MOS sampling switch is used to input the first voltage signal V in<1> Perform sampling and holding;

[0059] The second selection switch is used to transmit the output voltage signal of the voltage buffer module to the gate of the second MOS sampling switch tube when the second channel is selected; and to connect the gate of the second MOS sampling switch tube to the ground to cut off the second channel when the second channel is not selected.

[0060] The second MOS sampling switch is used to input the second voltage signal V in<2> Perform sampling and holding;

[0061] The third selection switch is used to transmit the output voltage signal of the voltage buffer module to the gate of the third MOS sampling switch tube when the third channel is selected; and to connect the gate of the third MOS sampling switch tube to the ground to cut off the third channel when the third channel is not selected.

[0062] The third MOS sampling switch is used to input the third voltage signal V in<3> Perform sample and hold.

[0063] Furthermore, it should be noted that MOS tube < 12 Drain and MOS tube< 13 The source connection is provided with an input point on the wiring, which is used to connect the input V in<1> MOS tube M 16 The drain and the MOS tube M 17 The source connection is provided with an input point on the wiring, which is used to connect the input V in<2> MOS tube M 20 The drain and the MOS tube M 21 The source connection is provided with an input point on the wiring, which is used to connect the input V in <n>< / n> MOS tube M 13 The drain and the MOS tube M 17 The drain and MOS tube M 21 The drain connection is provided with a lead point on the wiring, which is used to output V out ; The first channel's selection switch signal V CHANNEL<1> At the same time and MOS tube M 10 The gate and MOS tube M 11the gate of the first MOS sampling switch tube M CHANNEL<2> the gate of the second MOS sampling switch tube M 14 the gate of the first MOS sampling switch tube M 15 the gate of the first MOS sampling switch tube M CHANNEL <n>< / n> the gate of the second MOS sampling switch tube M 18 the gate of the first MOS sampling switch tube M 19 the gate of the first MOS sampling switch tube M.

[0064] Please refer to Figure 2 The embodiment of the application further provides a control method of the gate voltage bootstrap switch circuit of the multiplexing analog-to-digital converter, which can realize the above-mentioned gate voltage bootstrap switch circuit of the multiplexing analog-to-digital converter, and the method comprises the following steps:

[0065] S100, controlling the voltage buffer module, the gating switch module and the MOS sampling switch tube module to be in a sampling stage or a holding stage according to the first control clock signal and the second control clock signal.

[0066] It should be noted that in some specific embodiments, the second control clock signal is obtained by inverting the first control clock signal.

[0067] S200, driving the voltage output of the gate voltage bootstrap circuit module to obtain an output voltage signal.

[0068] S300, controlling the MOS sampling switch tube module to be in a conducting state or a holding state according to the gating switch signal, and if the MOS sampling switch tube module is in the conducting state, the output voltage signal is transmitted to the MOS sampling switch tube module.

[0069] S400, sampling and holding the input voltage signal.

[0070] It should be noted that in some embodiments, in the sampling stage, the two ends of the bootstrap capacitor in the gate voltage bootstrap circuit module are disconnected from the power supply and the ground respectively by the first control clock signal and the second control clock signal, and the voltage buffer module and the first gating switch, the second gating switch and the third gating switch are connected to the gate of the first MOS sampling switch tube, the gate of the second MOS sampling switch tube and the gate of the third MOS sampling switch tube respectively in the corresponding channel when being selected, and the top plate voltage value of the bootstrap capacitor is the sum of the input signal of the gating switch module and the power supply voltage of the selected channel, and in the holding stage, the two ends of the bootstrap capacitor in the gate voltage bootstrap circuit module are connected to the ground and the power supply respectively by the first control clock signal and the second control clock signal, and the voltage difference between the two ends of the bootstrap capacitor is charged to the power supply voltage value.

[0071] Specifically, in the holding stage, the control clock CK s and NCK sThe bootstrap capacitor in the gate voltage bootstrap circuit module is connected to the ground and the power supply, and the voltage difference across the bootstrap capacitor is charged to the power supply voltage value; in the sampling phase, the control clock CK s and NCK s The top plate voltage value of the bootstrap capacitor in the gate voltage bootstrap circuit module is disconnected from the power supply and the ground, and is connected to the gate of the first MOS sampling switch tube, the second MOS sampling switch tube and the third MOS sampling switch tube in the corresponding channel when the corresponding channel is selected through the voltage buffer module and the first gating switch module, the second gating switch module and the third gating switch module; at this time, the top plate voltage value of the bootstrap capacitor is the sum of the input signal of the gating channel and the power supply voltage, so that the gate-source voltage of the MOS sampling switch tube in the gating channel is basically maintained as the power supply voltage value, thereby effectively improving the linearity.

[0072] As Figure 4 shown, it is a simulation result of the gate voltage bootstrap switch circuit and control method of the multiplexing analog-to-digital converter proposed in the present application. The number of channels is set to 16, and the number of channels can be increased or decreased according to specific applications. The SFDR of the circuit is 120.09 dBc under the conditions of a single-channel sampling clock frequency of 1 KHz, a total sampling clock frequency of 16 KHz and a load capacitance of 1.8 pF, and the effective number of bits of the 16 channels can reach 17 bits or more, meeting the design requirements.

[0073] Unlike related technologies, as Figure 3 shown, since the area and power consumption of the gate voltage bootstrap switch circuit are larger than those of a single MOS tube switch, the related technologies occupy a larger circuit area and consume more power in the multiplexing analog-to-digital converter that needs to use multiple gate voltage bootstrap switches. Therefore, the present embodiment further simplifies the design of the circuit without sacrificing the performance of the circuit, and can greatly optimize the area and power consumption of the front-end gate voltage bootstrap switch circuit in the traditional high-precision multi-channel analog-to-digital converter.

[0074] It can be understood that the contents in the above method embodiments are applicable to the present system embodiment, the present system embodiment specifically implements the same functions as the above method embodiments, and achieves the same beneficial effects as the above method embodiments.

[0075] The preferred embodiments of the present application are described above with reference to the accompanying drawings, but this does not limit the scope of the present application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the present application should be within the scope of the present application.

Claims

1. A gate voltage bootstrap switch circuit for a multiplexed analog-to-digital converter, characterized by, The circuit comprises a gate voltage self-boosting circuit module, a voltage buffer module, a gating switch module and a MOS sampling switch tube module, an output end of the gate voltage self-boosting circuit module is connected with an input end of the voltage buffer module, an output end of the voltage buffer module is connected with an input end of the gating switch module, and an output end of the gating switch module is connected with an input end of the MOS sampling switch tube module, wherein: The gate voltage self-boosting circuit module is used for controlling the voltage buffer module, the gating switch module and the MOS sampling switch tube module to be in a sampling stage or a holding stage according to a first control clock signal and a second control clock signal. The voltage buffer module is used for driving a voltage output of the gate voltage self-boosting circuit module and obtaining an output voltage signal. The gating switch module is used for controlling the MOS sampling switch tube module to be in a conducting state or a holding state according to a gating switch signal, and the output voltage signal is transmitted to the MOS sampling switch tube module if the MOS sampling switch tube module is in the conducting state. The MOS sampling switch tube module is used for sampling and holding an input voltage signal. In the sampling stage, the self-boosting capacitor in the gate voltage self-boosting circuit module is disconnected from the power supply and the ground respectively through the first control clock signal and the second control clock signal, and the voltage buffer module and the first gating switch, the second gating switch and the third gating switch are connected to the gate of the first MOS sampling switch tube, the gate of the second MOS sampling switch tube and the gate of the third MOS sampling switch tube respectively in the corresponding channel when selected, and the top plate voltage value of the self-boosting capacitor is the sum of the input signal of the gating switch module and the power supply voltage. In the holding stage, the self-boosting capacitor in the gate voltage self-boosting circuit module is connected to the ground and the power supply respectively through the first control clock signal and the second control clock signal, and the voltage difference between the two ends of the self-boosting capacitor is charged to the power supply voltage value.

2. The circuit of claim 1, wherein, The gate voltage bootstrap circuit module comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a bootstrap capacitor, the gate of the first MOS transistor is connected with the gate of the second MOS transistor and receives the first control clock signal, the source of the first MOS transistor, the drain of the third MOS transistor and the gate of the seventh MOS transistor are connected with the source of the eighth MOS transistor, the drain of the first MOS transistor, the drain of the second MOS transistor and the gate of the fifth MOS transistor are connected with the drain of the sixth MOS transistor, the source of the second MOS transistor, the drain of the fourth MOS transistor and the second end of the bootstrap capacitor are connected with the source of the sixth MOS transistor, the source of the fourth MOS transistor is grounded, the gate of the fourth MOS transistor receives the second control clock signal, the source of the third MOS transistor and the first end of the bootstrap capacitor are connected with the source of the fifth MOS transistor, the gate of the third MOS transistor, the drain of the fifth MOS transistor and the gate of the sixth MOS transistor are connected with the drain of the seventh MOS transistor, the source of the seventh MOS transistor, the drain of the eighth MOS transistor and the drain of the ninth MOS transistor are connected, the gate of the eighth MOS transistor is connected with the gate of the ninth MOS transistor and receives the second control clock signal, and the source of the ninth MOS transistor is grounded.

3. The circuit of claim 1, wherein, The gate voltage bootstrap circuit module comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a bootstrap capacitor, the gate of the first MOS transistor is connected with the gate of the second MOS transistor and receives the first control clock signal, the source of the first MOS transistor, the drain of the third MOS transistor and the gate of the seventh MOS transistor are connected with the source of the eighth MOS transistor, the drain of the first MOS transistor, the drain of the second MOS transistor and the gate of the fifth MOS transistor are connected with the drain of the sixth MOS transistor, the source of the second MOS transistor, the drain of the fourth MOS transistor and the second end of the bootstrap capacitor are connected with the source of the sixth MOS transistor, the source of the fourth MOS transistor is grounded, the gate of the fourth MOS transistor receives the second control clock signal, the source of the third MOS transistor and the first end of the bootstrap capacitor are connected with the source of the fifth MOS transistor, the gate of the third MOS transistor, the drain of the fifth MOS transistor and the gate of the sixth MOS transistor are connected with the drain of the seventh MOS transistor, the source of the seventh MOS transistor, the drain of the eighth MOS transistor and the drain of the ninth MOS transistor are connected, the gate of the eighth MOS transistor is connected with the gate of the ninth MOS transistor and receives the second control clock signal, and the source of the ninth MOS transistor is grounded.

4. The circuit of claim 3, wherein, The first gate switch comprises a tenth MOS transistor and an eleventh MOS transistor, the second gate switch comprises a fourteenth MOS transistor and a fifteenth MOS transistor, and the third gate switch comprises an eighteenth MOS transistor and a nineteenth MOS transistor, wherein: the gate of the tenth MOS transistor is connected with the gate of the eleventh MOS transistor and receives a first gate switch signal, the drain of the tenth MOS transistor is connected with the drain of the eleventh MOS transistor and receives the first MOS sampling switch tube, the source of the tenth MOS transistor is connected with the voltage buffer module, and the source of the eleventh MOS transistor is grounded. The gate of the fourteenth MOS tube is connected with the gate of the fifteenth MOS tube and is connected with a second gate-on switch signal, the drain of the fourteenth MOS tube is connected with the drain of the fifteenth MOS tube and is connected with the second MOS sampling switch tube, the source of the fourteenth MOS tube is connected with the voltage buffer module, and the source of the fifteenth MOS tube is connected with the ground. The gate of the eighteenth MOS tube is connected with the gate of the nineteenth MOS tube and is connected with a third gate-on switch signal, the drain of the eighteenth MOS tube is connected with the drain of the nineteenth MOS tube and is connected with the third MOS sampling switch tube, the source of the eighteenth MOS tube is connected with the voltage buffer module, and the source of the nineteenth MOS tube is connected with the ground.

5. The circuit of claim 3, wherein, The first MOS sampling switch tube comprises a twelfth MOS tube and a thirteenth MOS tube, the second MOS sampling switch tube comprises a sixteenth MOS tube and a seventeenth MOS tube, and the third MOS sampling switch tube comprises a twentieth MOS tube and a twenty-first MOS tube, wherein: The gate of the twelfth MOS tube is connected with the gate of the thirteenth MOS tube and is connected with the first gate-on switch, the drain of the twelfth MOS tube is connected with the source of the thirteenth MOS tube and is connected with a first input voltage signal, the source of the twelfth MOS tube is connected with the gate voltage self-boosting circuit module, and the drain of the thirteenth MOS tube is connected with the second MOS sampling switch tube and the third MOS sampling switch tube respectively. The gate of the sixteenth MOS tube is connected with the gate of the seventeenth MOS tube and is connected with the second gate-on switch, the drain of the sixteenth MOS tube is connected with the source of the seventeenth MOS tube and is connected with a second input voltage signal, the source of the sixteenth MOS tube is connected with the gate voltage self-boosting circuit module, and the drain of the seventeenth MOS tube is connected with the first MOS sampling switch tube and the third MOS sampling switch tube respectively. The gate of the twentieth MOS tube is connected with the gate of the twenty-first MOS tube and is connected with the third gate-on switch, the drain of the twentieth MOS tube is connected with the source of the twenty-first MOS tube and is connected with a third input voltage signal, the source of the twentieth MOS tube is connected with the gate voltage self-boosting circuit module, and the drain of the twenty-first MOS tube is connected with the first MOS sampling switch tube and the second MOS sampling switch tube respectively.

6. The circuit of claim 3, wherein, Further comprising: The first gate-on switch is used for controlling the first MOS sampling switch tube module to be in a conductive state or a holding state according to the first gate-on switch signal; The second gate-on switch is used for controlling the second MOS sampling switch tube module to be in a conductive state or a holding state according to the second gate-on switch signal; The third gate-on switch is used for controlling the third MOS sampling switch tube module to be in a conductive state or a holding state according to the third gate-on switch signal; The first MOS sampling switch tube is used for sampling and holding a first input voltage signal; The second MOS sampling switch tube is used for sampling and holding a second input voltage signal; and The third MOS sampling switch tube is used for sampling and holding a third input voltage signal. The third MOS sampling switch tube is used for sampling and holding the third input voltage signal.

7. A method of controlling a gate voltage bootstrap switch circuit of a multiplexed analog-to-digital converter, characterized by, The method comprises the following steps: The voltage buffer module, the gating switch module and the MOS sampling switch tube module are controlled to be in a sampling stage or a holding stage according to the first control clock signal and the second control clock signal. The voltage output of the drive gate voltage self-boosting circuit module is obtained to obtain an output voltage signal. The MOS sampling switch tube module is controlled to be in a conduction state or a holding state according to the gating switch signal, and if the MOS sampling switch tube module is in the conduction state, the output voltage signal is transmitted to the MOS sampling switch tube module. The input voltage signal is sampled and held. In the sampling stage, the self-boosting capacitor in the gate voltage self-boosting circuit module is disconnected from the power supply and the ground respectively by the first control clock signal and the second control clock signal, and the voltage buffer module and the first gating switch, the second gating switch and the third gating switch are connected to the gate of the first MOS sampling switch tube, the gate of the second MOS sampling switch tube and the gate of the third MOS sampling switch tube respectively when the corresponding channels are selected, and the top plate voltage value of the self-boosting capacitor is the sum of the input signal of the gating switch module and the power supply voltage. In the holding stage, the two ends of the self-boosting capacitor in the gate voltage self-boosting circuit module are connected to the ground and the power supply respectively by the first control clock signal and the second control clock signal, and the voltage difference between the two ends of the self-boosting capacitor is charged to the power supply voltage value.

8. The method of claim 7, wherein, The second control clock signal is obtained by inverting the first control clock signal.

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