A method and system for detecting commercial encryption capability of FPGA chip

Abstract

The present invention relates to the field of chip data analysis technology, specifically to a commercial secret capability detection method and system for an FPGA chip, comprising the following steps: based on random data collected in real time during key generation, statistically processing the collected random data, calculating the entropy value of the information bit according to the probability distribution, and generating an entropy value distribution result. The present invention performs statistical processing and probability distribution analysis through real-time collected random voltage fluctuations, clock jitter, thermal noise and other data, and further dynamically adjusts the entropy value and the insertion frequency and position of the interference signal to achieve real-time security protection in a commercial secret environment. By detecting the entropy value fluctuation characteristics within a specified period of time, the insertion parameters of potential interference signals can be effectively identified. By optimizing the intensity and timing distribution of the interference signal, key signal characteristics such as power consumption and electromagnetic radiation are concealed, making it more difficult to obtain information during commercial secret operations through side channel analysis.

Description

Technical Field

[0001] The present invention relates to the technical field of chip data analysis, and in particular to a method and system for detecting the commercial encryption capability of an FPGA chip. Background Art

[0002] Chip data analysis mainly involves the analysis and evaluation of chip operation data, structural data, and various performance indicators. Through the mining and modeling of chip data, the operating status of the chip can be identified, its functional performance can be optimized, and its safety and reliability can be ensured. In the process of chip data analysis, data mining, statistical modeling, machine learning and other technical means are usually used to achieve real-time monitoring and evaluation of internal and external data of the chip, so as to timely detect anomalies and potential risks.

[0003] Among them, the commercial cryptographic capability detection method of FPGA chips is based on the commercial cryptographic application capability detection technology of FPGA (field programmable gate array) chips, which aims to evaluate and detect the security and performance of FPGA chips in cryptographic application scenarios. Through commercial cryptographic capability detection, it is possible to determine whether the FPGA chip meets specific security standards and its adaptability and performance under different commercial cryptographic algorithms.

[0004] In the commercial encryption capability detection of FPGA chips, the existing technology is difficult to detect and deal with potential security risks in the encryption process in a timely manner. For example, relying solely on fixed detection steps to determine the adaptability and performance of the chip under different commercial encryption algorithms is likely to miss security risks caused by environmental noise or load changes. In addition, the existing technology is difficult to identify potential security issues caused by time fluctuations at each stage in terms of execution response of different encryption stages, which easily increases the risk of information leakage in commercial encryption operations. In addition, when the chip faces sudden fluctuations in input characteristics, it is also prone to instability due to the influence of external signal interference. Summary of the invention

[0005] The purpose of the present invention is to solve the shortcomings of the prior art and to propose a method and system for detecting the commercial encryption capability of an FPGA chip.

[0006] In order to achieve the above object, the present invention adopts the following technical solution: a method for detecting the commercial encryption capability of an FPGA chip, comprising the following steps:

[0007] S1: Based on the random data collected in real time during the key generation process, statistical processing is performed on the collected random data, the entropy value of the information bit is calculated according to the probability distribution, and the entropy value distribution result is generated;

[0008] S2: Based on the entropy value distribution result, the entropy value fluctuation characteristics are analyzed, and during the encryption process, a random interference signal is inserted in a corresponding time period according to the probability parameter information, and the insertion frequency and position are adjusted according to the entropy value change to generate a dynamic entropy value and interference signal update result;

[0009] S3: Based on the dynamic entropy value and the interference signal update result, the strength and timing of the interference signal are adjusted to mask the key operation signal characteristics during the chip execution, and the interference signal insertion optimization result is generated;

[0010] S4: referring to the signal features in the interference signal insertion optimization result, collecting the response time data of the commercial encryption operation under normal working conditions, classifying and arranging the time data of the encryption algorithm, and comparing and analyzing it with the response time of the key time period to generate a response time difference evaluation result;

[0011] S5: Based on the response time difference evaluation result, gradually apply disturbances to the input data used in the encryption process, collect the output response data of the chip under the disturbance characteristics, analyze the impact of the variation of the input characteristics on the output response, and generate the input characteristic variation association result;

[0012] S6: Based on the input feature variation association results, identify the key risk features in the input features that cause the chip security to be reduced, adjust the parameters of the input disturbance and the insertion position and strength of the interference signal according to the key risk features, and generate an optimization result for the FPGA chip commercial security capability detection.

[0013] The present invention has improvements in that the entropy value distribution result includes the probability distribution of information bits, the overall information entropy level and the fluctuation characteristic parameters; the dynamic entropy value and interference signal update result include the insertion frequency parameter, the position selection rule and the update intensity of the interference signal within the time period; the interference signal insertion optimization result includes the power consumption shielding optimization parameter, the electromagnetic interference mask and the signal timing perturbation configuration; the response time difference evaluation result includes the range parameter of the task response time, the time comparison data of the key stage and the stage delay feature analysis; the input feature variation association result includes the amplitude change association parameter, the timing offset influence coefficient and the noise interference response information; the FPGA chip commercial confidentiality capability detection optimization result includes the risk feature identification parameter, the interference signal insertion position optimization and the power consumption and electromagnetic masking adjustment.

[0014] The present invention is improved in that, based on the random data collected in real time during the key generation process, the collected random data is statistically processed, and the entropy value of the information bit is calculated according to the probability distribution. The specific steps of generating the entropy value distribution result are as follows:

[0015] S101: based on the voltage fluctuation data, clock jitter data and thermal noise data collected during the key generation process, group the data according to the information bit, calculate the probability value of each group of data bit by bit, count the probability data of each information bit, and generate the information bit probability distribution result;

[0016] S102: Based on the information bit probability distribution result, according to the probability data distribution of each information bit, the probability density of the information bit is calculated to obtain an initial entropy value, and the probability data of the information bit is readjusted according to the weight by setting a weighting factor, and the entropy value data after the weight adjustment is merged to obtain an information bit entropy value set;

[0017] S103: Based on the information bit entropy value set, the information bit entropy value data is accumulated item by item, the overall information entropy value is calculated, the integrity of the overall entropy value data is confirmed by verification, and an entropy value distribution result is generated.

[0018] The present invention is improved in that, based on the entropy distribution result, the entropy fluctuation characteristics are analyzed, a random interference signal is inserted in a corresponding time period according to the probability parameter information during the encryption process, and the insertion frequency and position are adjusted according to the entropy change. The specific steps of generating dynamic entropy value and interference signal update results are as follows:

[0019] S201: Based on the entropy distribution result, the entropy data is transferred to the buffer periodically, the entropy data is updated in segments using a sliding time window, the entropy change trend in the current period is monitored, and a time window entropy value set is generated;

[0020] S202: Based on the time window entropy value set, compare the current entropy value data with the safety reference value, extract the multi-frequency segments of entropy value fluctuations, analyze the interference signal insertion frequency and position parameters of the multi-frequency segments, and obtain the interference signal insertion parameter information;

[0021] S203: Based on the interference signal insertion parameter information, adjust the frequency and position of the interference signal insertion periodically during the encryption process, monitor the entropy value change characteristics in real time and update the signal to generate a dynamic entropy value and an interference signal update result.

[0022] The present invention is improved in that, based on the dynamic entropy value and the interference signal update result, the strength and timing of the interference signal are adjusted to mask the key operation signal characteristics during chip execution, and the specific steps of generating the interference signal insertion optimization result are as follows:

[0023] S301: Based on the dynamic entropy value and the interference signal update result, extract the time period data of the entropy value fluctuation by frequency band classification, calculate the fluctuation amplitude, allocate the basic strength and initial timing of the interference signal, and obtain the initial configuration result of the interference signal;

[0024] S302: Based on the initial configuration result of the interference signal, combined with the time point of each fluctuation frequency band, adjust the interference signal strength one by one, change the interference timing according to the change of entropy value, generate corresponding timing signals according to the frequency band, and obtain the interference signal adjustment result;

[0025] S303: Based on the interference signal adjustment result, embed the interference signal with adjusted strength in the key operation time period, add interference shielding operations to power consumption fluctuation, electromagnetic radiation, and timing signal respectively, and generate interference signal insertion optimization results.

[0026] The present invention is improved in that the fluctuation amplitude is calculated by using the formula:

[0027] ,

[0028] Calculate the basic strength A of the interference signal;

[0029] in, It is the time period The entropy fluctuation range is It is the time period The fluctuation frequency, It is the time period duration, is the data noise impact coefficient, and n is the total number of time periods.

[0030] The present invention is improved in that, referring to the signal characteristics in the interference signal insertion optimization result, the response time data of the commercial encryption operation under normal working state is collected, the time data of the encryption algorithm is classified and sorted, and compared and analyzed with the response time of the key time period, and the specific steps of generating the response time difference evaluation result are as follows:

[0031] S401: Based on the interference signal insertion optimization result, the response time of the commercial secret operation under the normal working state is collected, the overall execution time of the task is recorded, and the normal response time data is generated;

[0032] S402: Based on the normal response time data, sort the response time by task type, distribute the execution time of the encryption task to the encryption startup, key generation, and data output stages, calculate the average response time range, and generate a staged response time classification result;

[0033] S403: Based on the staged response time classification result, cross-comparison is performed on the time difference data of key stages, the time difference range between stages is marked, the response time difference is segmented and sorted, and a response time difference evaluation result is generated.

[0034] The present invention has the following improvements: based on the response time difference evaluation result, the input data used in the encryption process is gradually disturbed, the output response data of the chip under the disturbance feature is collected, the influence of the variation of the input feature on the output response is analyzed, and the specific steps of generating the input feature variation association result are as follows:

[0035] S501: Based on the response time difference evaluation result, applying amplitude disturbance to the input data, gradually increasing the amplitude values ​​of the key information and the plaintext data, collecting the output response under the corresponding disturbance state, and generating the input data amplitude disturbance result;

[0036] S502: Based on the input data amplitude disturbance result, applying a timing offset to the input data, adjusting the input timing position one by one, recording the response time data of the chip in the offset state, and obtaining the input data timing offset analysis result;

[0037] S503: Based on the input data timing offset analysis result, randomly superimpose noise on the input data, embed the noise feature into the key information, plaintext data and operation parameters, collect the response data of the chip after the disturbance, and generate the input feature variation association result.

[0038] The present invention is improved in that, based on the input feature variation association result, the key risk features in the input features that lead to reduced chip security are identified, the parameters of the input disturbance and the insertion position and strength of the interference signal are adjusted according to the key risk features, and the specific steps of generating the optimization result of the commercial confidentiality capability detection of the FPGA chip are as follows:

[0039] S601: Based on the input feature variation association result, extract key risk features that lead to reduced chip security, analyze the features of data amplitude anomaly and time series instability item by item, classify and mark them, and generate a key risk feature set;

[0040] S602: Based on the key risk feature set, real-time monitoring of chip power consumption, electromagnetic radiation and timing signals, combining the dynamic entropy value and the interference signal update result, correlating the features of the monitoring signal with the dynamic entropy value and the interference signal update result, and obtaining the associated monitoring signal;

[0041] S603: Based on the associated monitoring signal and in combination with the response time difference evaluation result, the parameters of the input disturbance are adjusted, the insertion position and strength of the interference signal are reconfigured according to the risk characteristics, and the optimization result of the FPGA chip commercial confidentiality capability detection is generated.

[0042] A commercial encryption capability detection system for an FPGA chip, the system comprising:

[0043] The random data processing module counts each type of data bit by bit based on the voltage fluctuation, clock jitter and thermal noise data collected during the key generation process, calculates the probability distribution of the data, calculates the information entropy value according to the probability of each bit, summarizes the information bit entropy value into an overall distribution structure, and generates the entropy value distribution result;

[0044] The interference signal insertion module analyzes the entropy value fluctuation amplitude of each time period based on the entropy value distribution result, sets the interference signal insertion for the fluctuation period, determines the insertion frequency and position, marks the multi-frequency fluctuation section as the interference position and adjusts the signal insertion frequency, and generates dynamic entropy value and interference signal update results;

[0045] The interference signal optimization module analyzes the fluctuation influence of signal insertion based on the dynamic entropy value and the interference signal update result, shields the power consumption fluctuation, electromagnetic radiation and timing signal one by one, masks the operation characteristics by adjusting the signal strength, selects the timing allocation signal strength for the operation stage, and generates the interference signal insertion optimization result;

[0046] The response time analysis module collects the response time of the chip in normal working state based on the interference signal insertion optimization result, records the execution time one by one according to the encryption startup, key generation, and data output stages, classifies the data and calculates the average response range between stages, compares the response characteristics section by section, and generates a response time difference evaluation result;

[0047] Based on the response time difference evaluation results, the disturbance input adjustment module applies amplitude changes, timing offsets and random noise injection disturbances to the key information, plaintext data and operating parameters one by one, collects the response changes of the chip under the disturbance state, identifies key risk features that affect security, reconfigures the disturbance parameters and the insertion position and strength of the interference signal, and generates the optimization results of the FPGA chip commercial encryption capability detection.

[0048] Compared with the prior art, the advantages and positive effects of the present invention are:

[0049] In the present invention, statistical processing and probability distribution analysis are performed through real-time collection of random voltage fluctuations, clock jitter, thermal noise and other data, and further by dynamically adjusting the entropy value and the insertion frequency and position of the interference signal, real-time security protection in a commercial secret environment is achieved. By detecting the entropy value fluctuation characteristics within a specified period of time, the insertion parameters of potential interference signals can be effectively identified to ensure the best match between the signal and the scrambling in each encryption stage. By optimizing the intensity and timing distribution of the interference signal, masking key signal characteristics such as power consumption and electromagnetic radiation, making it more difficult to obtain information during commercial secret operations through side channel analysis, the anti-interference and stability of the chip are further improved. In the response time difference evaluation, by comparing the response time differences of different encryption stages, the task robustness under different behavioral disturbances is improved. In the data disturbance test process, the key risks in the input features are identified, and the random noise injection and entropy value update information are combined to flexibly regulate the interference signal and disturbance features, improve the stability of the chip under different input disturbances, and significantly reduce the safety hazards caused by abnormal signals or sudden changes in input. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a work flow chart of the present invention;

[0051] Figure 2 This is a detailed flow chart of step S1 of the present invention;

[0052] Figure 3 This is a detailed flow chart of step S2 of the present invention;

[0053] Figure 4 This is a detailed flow chart of step S3 of the present invention;

[0054] Figure 5 This is a detailed flow chart of step S4 of the present invention;

[0055] Figure 6 This is a detailed flow chart of step S5 of the present invention;

[0056] Figure 7 This is a detailed flow chart of step S6 of the present invention;

[0057] Figure 8 It is a system module diagram of the present invention. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0059] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating positions or positional relationships, are based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, in the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0060] See also Figure 1 The present invention provides a technical solution: a method for detecting the commercial encryption capability of an FPGA chip, comprising the following steps:

[0061] S1: Based on the random data collected in real time during the key generation process, the random data includes voltage fluctuation data, clock jitter data, and thermal noise data, the collected random data is statistically processed to calculate the probability distribution of each information bit, and the entropy value of the information bit is calculated according to the probability distribution to calculate the overall information entropy and generate the entropy value distribution result;

[0062] S2: Store the periodic entropy value data in a buffer, use a sliding time window to gradually update the entropy value, compare the entropy value with the security benchmark value, analyze the entropy value fluctuation characteristics based on the entropy value distribution result, determine the interference signal insertion probability parameter within the time period, insert a random interference signal within the corresponding time period according to the probability parameter information during the encryption process, adjust the insertion frequency and position according to the entropy value change, and generate dynamic entropy value and interference signal update results;

[0063] S3: Based on the dynamic entropy value and the interference signal update results, the current interference signal is optimized and configured according to the entropy value fluctuation within the time period, the strength and timing of the interference signal are adjusted, and the key operation signal characteristics during the chip execution are masked. The key operation signals include power consumption fluctuation signals, electromagnetic radiation signals and timing signals. Ensure that the interference signal and the operation characteristics are intertwined to maximize the shielding effect, and generate the interference signal insertion optimization result;

[0064] S4: referring to the signal features in the interference signal insertion optimization result, collecting the response time data of the commercial cryptographic operation under normal working conditions, measuring the overall execution time of the chip running the encryption task, calculating the response time range of the task, classifying and arranging the time data of the encryption algorithm, and comparing and analyzing it with the response time of the key time period, which includes the encryption startup phase, the encryption key generation phase, and the data output phase, to generate the response time difference evaluation result;

[0065] S5: Based on the response time difference evaluation results, gradually apply disturbances to the input data used in the encryption process. The input data includes key information, plaintext data, and operation parameters. Collect the output response data of the chip under the disturbance characteristics. The disturbance characteristics include data amplitude changes, timing offsets, and randomly injected noise. Analyze the impact of the variation of the input characteristics on the output response, and generate the input feature variation association results.

[0066] S6: Based on the input feature variation correlation results, identify the key risk features in the input features that lead to reduced chip security. The key risk features include data amplitude abnormality and timing instability. By real-time monitoring of the chip's power consumption signal, electromagnetic radiation signal, and timing signal, combined with the dynamic entropy value and interference signal update results and response time difference evaluation results, adjust the input disturbance parameters and the insertion position and strength of the interference signal, optimize the chip's security in commercial cryptographic operations, and generate FPGA chip commercial cryptographic capability detection optimization results.

[0067] The entropy value distribution results include the probability distribution of information bits, the overall information entropy level and the fluctuation characteristic parameters. The dynamic entropy value and interference signal update results include the insertion frequency parameters, the position selection rules and the update intensity of the interference signal within the time period. The interference signal insertion optimization results include the power consumption shielding optimization parameters, electromagnetic interference masking and signal timing perturbation configuration. The response time difference evaluation results include the range parameters of the task response time, the time comparison data of the key stages and the stage delay feature analysis. The input feature variation association results include the amplitude change association parameters, the timing offset influence coefficient and the noise interference response information. The FPGA chip commercial confidentiality capability detection optimization results include the risk feature identification parameters, the interference signal insertion position optimization and the power consumption and electromagnetic masking adjustment.

[0068] See also Figure 2 Based on the random data collected in real time during the key generation process, the collected random data is statistically processed, and the entropy value of the information bit is calculated according to the probability distribution. The specific steps for generating the entropy value distribution result are as follows:

[0069] S101: based on the voltage fluctuation data, clock jitter data and thermal noise data collected during the key generation process, group the data according to the information bit, calculate the probability value of each group of data bit by bit, count the probability data of each information bit, and generate the information bit probability distribution result;

[0070] By collecting data, the frequency of states 1 and 0 in each group of data is counted bit by bit, and the ratio of the probability of each bit being 1 is calculated, thereby generating the probability distribution result of the information bit. By grouping the data and counting the probability of each state, the probability data of each information bit is formed; the probability of the information bit is calculated according to the formula: ,in, represents the probability distribution of information bit i, It represents the state value of information bit i in data set j. The state value is obtained by FPGA chip signal capture software. N represents the number of samples. It is set by the size of the data set. The total number of samples is usually determined by data acquisition equipment. Assume that the collected data is 500 samples. The state value of each bit is Changing between 1 and 0, if the state value of a certain information bit i is 1 250 times, the probability distribution is: The results show that the information bit i has a high probability of occurrence and is evenly distributed during the key generation process, making it suitable as a reference for subsequent entropy value calculations.

[0071] S102: Based on the information bit probability distribution result, according to the probability data distribution of each information bit, the probability density of the information bit is calculated to obtain an initial entropy value, and the probability data of the information bit is readjusted according to the weight by setting a weighting factor, and the entropy value data after the weight adjustment is merged to obtain an information bit entropy value set;

[0072] By setting the weighting factor, the probability data of the information bit is redistributed according to the weight, the probability value of each information bit is weighted, and the adjusted entropy value data is merged item by item into the entropy value data set of the information bit; the information bit entropy value calculation formula is: , after weighting adjustment: ;in, represents the initial entropy value of information bit i, represents the probability of state k of information bit i, represents the logarithm with base 2, represents the information bit entropy value after weighted adjustment, w is the weight factor, which is set according to the chip security standard, usually through historical statistical data. The weight can be adjusted through empirical judgment to optimize the calculation result. Specifically, first collect historical data of multiple key generation processes, and count the entropy value distribution of each information bit. Assign lower weights to entropy values ​​that frequently fluctuate greatly, and assign higher weights to stable entropy values. In this way, the specific value of the weight factor is determined to optimize the overall evaluation of information entropy and make it more in line with the security requirements of actual commercial secret applications. If the probability of a certain information bit is and , the initial entropy value is calculated as follows: ; The weighting factor is set to w=0.8, and the weighted entropy value is: ; This weighted entropy value reflects the distribution adjustment of the information bits in the key.

[0073] S103: Based on the information bit entropy value set, the information bit entropy value data is accumulated item by item, the overall information entropy value is calculated, the integrity of the overall entropy value data is confirmed by verification, and the entropy value distribution result is generated;

[0074] The overall information entropy value calculation formula is: ,in, is the overall information entropy value, representing the sum of all information bit entropy values, m is the total number of information bits, which is determined by the actual FPGA chip design and key structure. For example, in common key structures, each key group may contain 64 or 128 bits, etc., which is set by the bit configuration in the key generation design; if the information bit entropy value set is set to contain the entropy values ​​of 5 information bits, the values ​​are 0.8, 0.9, 1, 0.7 and 1.1, the overall information entropy value is calculated by the formula: The overall information entropy value indicates the security of the accumulated entropy values ​​of each information bit, and can be used as a reference standard for commercial secret detection. The entropy value of each information bit is checked step by step through verification to verify whether the overall information entropy value is consistent with the expected result. If a deviation is found, the statistics are re-performed to ensure data integrity. After the verification is completed, the obtained overall information entropy value is organized into an entropy value distribution result;

[0075] See also Figure 3 ,Based on the entropy value distribution results, the entropy value fluctuation characteristics are analyzed.,During the encryption process, a random interference signal is inserted in the corresponding time period according to the probability parameter information, and the insertion frequency and position are adjusted according to the entropy value change.,The specific steps for generating dynamic entropy value and interference signal update results are as follows:

[0076] S201: Based on the entropy distribution result, the entropy data is transferred to the buffer periodically, the entropy data is updated in segments using a sliding time window, the entropy change trend in the current period is monitored, and a time window entropy value set is generated;

[0077] By setting a fixed length of the sliding time window to cover the data within the period, data acquisition and monitoring software such as LabVIEW is used to record the changes in entropy values ​​window by window. In each time window, the entropy value change amplitude and trend in each segment are monitored and recorded period by period. If the entropy value fluctuation amplitude in a window is large, the entropy value fluctuation characteristics of the window segment are marked. By monitoring the mean change trend in the window, the entropy value distribution is recorded, updated and analyzed window by window. At the same time, during the update process of the sliding window, the end data of the window is used as the starting position of the next window to ensure that the data in the new window is connected in chronological order, and the old data in the sliding window is removed to maintain the real-time update and efficient storage of the entropy value in the window. Finally, the time window entropy value set is generated by periodic updating and real-time monitoring of the entropy value fluctuation trend.

[0078] S202: Based on the time window entropy value set, compare the current entropy value data with the safety reference value, extract the multi-frequency segments of entropy value fluctuations, analyze the interference signal insertion frequency and position parameters of the multi-frequency segments, and obtain the interference signal insertion parameter information;

[0079] By using Matlab's signal analysis tool to compare and analyze the entropy data in the current cycle with the safety benchmark value, the amplitude and frequency distribution in each segment are gradually extracted, and the standard for defining the multi-frequency fluctuation segment is the segment where the amplitude fluctuation exceeds the preset safety benchmark threshold. In the specific operation, the frequency and amplitude changes of each entropy segment are detected by the amplitude discrimination function, and the segments with large amplitude fluctuations, that is, the segments where the amplitude exceeds the safety benchmark value, are extracted segment by segment, and the entropy amplitude and the corresponding time point in the segment are recorded. In order to further obtain the best position for interference signal insertion, the maximum fluctuation frequency in the multi-frequency segment is located, and the time point with the highest fluctuation frequency is marked as the interference signal insertion point, and the frequency and position parameters of the insertion point are obtained at the same time. After each detection, the frequency and position parameters are stored as an interference signal insertion parameter set, and the reasonable range and time point of the insertion frequency are determined by this set. The interference signal insertion parameter information finally obtained will provide an effective signal insertion position and frequency basis.

[0080] S203: Based on the interference signal insertion parameter information, the frequency and position of the interference signal insertion are adjusted periodically during the encryption process, the entropy value change characteristics are monitored in real time, and the signal is updated to generate a dynamic entropy value and an interference signal update result;

[0081] The frequency and position of the interference signal insertion are adjusted periodically during the encryption process of the FPGA chip. In the specific implementation process, the interference signal in the encryption cycle is dynamically configured using chip programming tools such as Vivado, and the insertion frequency and specific position of the interference signal in the new cycle are set according to the high-frequency entropy value fluctuation information in the previous cycle. In each encryption cycle, the insertion effect of the detection signal is used to monitor the real-time entropy value distribution using a signal monitoring tool, and the entropy value distribution result after insertion is compared with the safety benchmark value. If a deviation from the benchmark value is detected, the insertion frequency of the interference signal is further increased or the insertion position is adjusted. After each cycle is completed, the updated interference signal insertion scheme and entropy value change characteristics are recorded for use in the next cycle. Finally, the dynamic entropy value and interference signal update results are generated based on the real-time monitoring and adjustment of the signal insertion strategy.

[0082] See also Figure 4 ,Based on the dynamic entropy value and the interference signal update result, the strength and timing of the interference signal are adjusted to mask the key operation signal characteristics during the chip execution. The specific steps to generate the interference signal insertion optimization result are as follows:

[0083] S301: Based on the dynamic entropy value and the interference signal update result, extract the time period data of the entropy value fluctuation by frequency band classification, calculate the fluctuation amplitude, allocate the basic strength and initial timing of the interference signal, and obtain the initial configuration result of the interference signal;

[0084] For the fluctuation range calculation, the formula is used:

[0085] ,

[0086] Calculate the basic strength A of the interference signal;

[0087] Among them, A is used to set the initial interference effect of the interference signal. This parameter is the strength benchmark used in the interference signal configuration. It can be set by analyzing the real-time monitoring data of the FPGA chip and determining the appropriate interference effect by comparing with the actual data. It is the time period The entropy fluctuation range reflects the change of data entropy value in this period of time, which is obtained by comparing the benchmark fluctuation value obtained from historical samples. It is the time period The fluctuation frequency represents the frequency of entropy value change in this time period. The frequency component is extracted by performing fast Fourier transform (FFT) on the time series data. It can be obtained through existing tool software such as Matlab and Python. The sampling frequency of FFT is usually set, and the main frequency component is extracted for each time period. It is the time period The duration is used to measure the length of the time period. The start and end time of each time period is recorded by the timestamp of the data acquisition device to calculate the duration. The duration data can usually be directly exported from time monitoring tools such as LabVIEW. It is the data noise influence coefficient, which indicates the degree of interference of noise on the change of signal entropy value. The noise level data is collected and SNR is calculated through signal monitoring tools such as LabVIEW, and the SNR value is standardized and converted into the data noise influence coefficient. Obtained, usually a higher noise level will lead to greater interference, n is the total number of time periods, indicating the total number of time periods involved in the calculation, usually divided according to the sampling time length, the data acquisition device will record the information of each time period according to the set time interval.

[0088] If there are 3 time periods in a cycle, the entropy fluctuation range of the time period is , the frequency value is , the duration is , the noise influence coefficient is , substituting into the formula, the basic strength of the interference signal is calculated as:

[0089] ,

[0090] The results show that the basic strength of the interference signal is 18.15. The calculation result A is used as the basis for the basic strength of the interference signal to allocate the initial interference signal strength and timing. In the specific process, the basic strength of the interference signal is first set according to the value of A. This strength determines the strength of the interference signal in the initial stage to ensure that it effectively covers sensitive data. Next, the basic strength A is allocated according to time periods so that an appropriate amount of interference signal strength is allocated to each time period to meet the fluctuation characteristics of each time period. According to the duration of each time period and the fluctuation frequency The calculated initial timing is used to control the triggering and duration of the interference signal, execute the interference signal configuration in each time period, generate the preliminary interference signal distribution and activation frequency, ensure the coverage of key data segments in the entire encryption cycle, and form the initial configuration result of the interference signal.

[0091] S302: Based on the initial configuration result of the interference signal, combined with the time point of each fluctuation frequency band, adjust the interference signal strength one by one, change the interference timing according to the change of entropy value, generate corresponding timing signals according to the frequency band, and obtain the interference signal adjustment result;

[0092] First, extract the fluctuation data of each frequency band, set the initial configuration strength of the interference signal, apply the signal monitoring method to detect the entropy fluctuation, enhance the interference signal strength in the high-fluctuation frequency band, and gradually increase the initial configuration strength to adapt to the fluctuation range to ensure sufficient signal strength; for the low-fluctuation section, reduce the interference intensity or maintain the initial value, and gradually lower the interference signal through the signal amplifier to keep it consistent with actual needs. Establish a signal trigger time point for the entropy fluctuation recorded in each frequency band, generate the corresponding timing signal according to the frequency band, activate the signals of each time period in turn through signal triggering, and finally integrate the timing signal strength and trigger point information of each section to form the interference signal adjustment result.

[0093] S303: Based on the interference signal adjustment result, embed the interference signal with adjusted strength in the key operation time period, add interference shielding operations to power consumption fluctuation, electromagnetic radiation, and timing signal, and generate interference signal insertion optimization results;

[0094] First, add a frequency distribution interference signal that matches the power consumption fluctuation to the power consumption fluctuation frequency band, and shield the power consumption change through high-frequency embedding. For the electromagnetic radiation signal, frequency interference is performed according to the noise level and radiation frequency band. Through signal loading, the interference signal is inserted directionally to cover the electromagnetic fluctuation at the frequency jump point. Finally, gradually reduce the trigger interval of the interference signal in the timing signal, so that the signal is distributed at the key nodes to form uniform interference, complete the interference of power consumption, electromagnetic radiation, and timing signals, and generate the interference signal insertion optimization result.

[0095] See also Figure 5, refer to the signal characteristics in the interference signal insertion optimization result, collect the response time data of the commercial encryption operation under normal working conditions, classify and organize the time data of the encryption algorithm, and compare and analyze it with the response time of the key time period. The specific steps to generate the response time difference evaluation result are as follows:

[0096] S401: Based on the interference signal insertion optimization result, the response time of the commercial secret operation under the normal working state is collected, the overall execution time of the task is recorded, and the normal response time data is generated;

[0097] First, set the collection cycle under normal working conditions, and select multiple commercial secret task nodes in each cycle to record the response time. During the cycle, the system captures the start and completion time of each commercial secret task in turn, records the time when the task enters the execution queue and the time when the operation is completed through the timestamp, and calculates the overall execution time of the task. The system automatically subtracts the start and completion time to obtain the response time of each task, and associates it with the task ID. All response time data is sorted at the end of the cycle and written into the response time database, which contains record items such as the characteristic information, cycle number, and execution duration of each task. This process ensures the accuracy and traceability of the response time data, so that the data can be quickly retrieved and queried when the response time of the commercial secret operation is statistically analyzed later.

[0098] S402: Based on the normal response time data, the response time is sorted by task type, the execution time of the encryption task is allocated to the encryption startup, key generation, and data output stages, the average response time range is calculated, and a staged response time classification result is generated;

[0099] Arrange the response time according to the task type, according to the formula: , calculate the average response time of each stage, where It represents the average response time of each task type, which is the basis for the classification results of the phased response time. It is obtained by summing and averaging the segmented data of each task. To ensure the accuracy of the average value, LabVIEW can be used to record the actual response time of each stage and automatically accumulate and generate statistical data. It is the startup response time of the encryption task, indicating the response time used to start task y. It is obtained by subtracting the time record of the task start point from the start timestamp of the task entering the execution queue. The data can be directly exported from the automated data acquisition system. The system will automatically record the start time according to the task queue. It is the key generation response time, which records the time taken for key generation of task y. It is calculated by the difference between the start and completion timestamps of key generation. This parameter indicates the execution time of the key generation phase. The timestamp is automatically generated and exported. is the data output response time, which indicates the data output duration of task y. It is the time difference from data generation to data output completion. With the help of the output monitoring tool, the data output stage of each task is automatically recorded by the tool system according to the time record of the data output start and end points, forming a specific output time. m is the number of tasks, which represents the total number of encrypted tasks in this response time classification. This parameter records the number of the entire task set and is used for the average statistics of the stage response time. If the number of tasks is 3, the stage time of the task is as follows: (Second), (Second), (seconds), substitute into the formula:

[0100] ,

[0101] The results show that the average response time in each stage is 5.03 seconds, which serves as a reference value for subsequent allocation and scheduling.

[0102] S403: Based on the stage response time classification result, cross-comparison is performed on the time difference data of the key stages, the time difference range between the stages is marked, the response time difference is sorted into segments, and the response time difference evaluation result is generated;

[0103] By conducting a detailed analysis of the time difference data of key stages, the response time of each task's encryption startup, key generation, and data output stages is extracted in segments, and the time difference range of each stage is marked. During execution, the system extracts the response time of each stage from the task data set in turn, records the maximum response time and the minimum response time of the stage respectively, and calculates the time difference of each stage. During the recording process, tasks that exceed the preset time difference threshold are marked as abnormal and saved to a separate data area for subsequent processing. The system adds record tags to these abnormal tasks in the data marking area, and records their stage-by-stage time differences in detail. This process classifies and organizes the response times of different stages, and performs segmented analysis according to the time difference range to generate response time difference evaluation results, so that tasks with abnormal fluctuations can be monitored and managed more finely in the future.

[0104] See also Figure 6 ,Based on the response time difference evaluation results, the input data used in the encryption process is gradually perturbed, the output response data of the chip under the perturbation characteristics is collected, and the impact of the variation of the input characteristics on the output response is analyzed. The specific steps for generating the input feature variation association results are as follows:

[0105] S501: Based on the response time difference evaluation result, amplitude disturbance is applied to the input data, the amplitude values ​​of the key information and the plaintext data are gradually increased, the output response under the corresponding disturbance state is collected, and the input data amplitude disturbance result is generated;

[0106] The amplitude values ​​of the key information and plaintext data are gradually increased through the signal perturbation analysis method. Before the operation begins, a benchmark standard is set for the amplitude value of the original input data and used as the initial reference value. When implementing the amplitude perturbation, the amplitude of the input signal is gradually increased, and a fixed increment is set to stabilize each amplitude increase to avoid amplitude changes beyond the range. After each amplitude increase, the amplitude state of the input data is measured, the current amplitude value of the key and plaintext data is recorded, and the output response at the amplitude value is collected to ensure that a corresponding record is formed between the amplitude and the response. This process is repeated in sequence until the amplitude reaches the predetermined upper limit. The collected data is then sorted according to the perturbation level to generate the input data amplitude perturbation result to ensure that the output response relationship at different amplitudes is accurately recorded.

[0107] S502: Based on the input data amplitude disturbance result, applying a timing offset to the input data, adjusting the input timing position one by one, recording the response time data of the chip in the offset state, and obtaining the input data timing offset analysis result;

[0108] First, determine the initial timing point of the input data and use it as a reference for the offset. Then gradually adjust the position of the input data, offsetting a fixed time interval each time, and update the adjusted timing position to the current offset state. After each offset, measure the response time of the chip, and record the current offset and the chip response time under the offset state. The collected data is matched with the corresponding response time according to the increment of the timing offset, and a set of corresponding timing offset data is generated for each offset. Finally, all the data recorded by the offset is archived according to the offset and response time, and the input data timing offset analysis results are generated to ensure that the chip response data under different offset levels is complete and available.

[0109] S503: Based on the input data timing offset analysis result, randomly superimpose noise on the input data, embed the noise feature into the key information, plaintext data and operation parameters, collect the response data of the chip after the disturbance, and generate the input feature variation association result;

[0110] First, select an appropriate random noise generation method to ensure that the noise characteristics can cover the signal frequency range of the key, plaintext, and operating parameters. Next, gradually increase the noise intensity. After each increase in noise intensity, measure the current characteristics of the input data under superimposed noise, embed the noise into the key and plaintext data, and record the chip output response under this intensity to form a set of input-output correspondence. The collected data is classified and sorted according to the noise intensity level, and the noise characteristics and corresponding chip responses are recorded one by one to generate input feature variation association data, providing detailed input-output correspondence records for subsequent analysis of the impact of noise on chip characteristics.

[0111] See also Figure 7Based on the input feature variation correlation results, identify the key risk features in the input features that lead to reduced chip security, adjust the input perturbation parameters and the insertion position and strength of the interference signal according to the key risk features, and generate the FPGA chip commercial security capability detection optimization results. The specific steps are as follows:

[0112] S601: Based on the input feature variation correlation results, extract the key risk features that lead to reduced chip security, analyze the features of data amplitude anomaly and time series instability item by item, classify and mark them, and generate a key risk feature set;

[0113] By screening the feature data contained in the input feature variation association results, the amplitude of the signal and the corresponding timing are used as two key feature dimensions for successive comparison and analysis. The abnormal values ​​of the amplitude change are judged and the corresponding timing offset characteristics are marked to identify the abnormality of the data amplitude. Each feature data is based on the set amplitude threshold range, and the abnormal data with amplitude exceeding the threshold is screened, and its frequency and deviation amplitude are recorded. At the same time, the time point when the amplitude abnormality occurs is marked, and the amplitude abnormality information is classified. For the extraction of timing instability features, the timing fluctuations of the signal are gradually measured and segmented according to the deviation range. Data that exceeds the preset timing error range is recorded as timing instability. After sorting out the two types of abnormal data, amplitude and timing, all features are classified and marked according to feature type to generate a key risk feature set for further analysis of subsequent risk feature associations.

[0114] S602: Based on the key risk feature set, the chip power consumption, electromagnetic radiation and timing signal are monitored in real time, and the dynamic entropy value and the interference signal update result are combined to associate the features of the monitoring signal with the dynamic entropy value and the interference signal update result to obtain the associated monitoring signal;

[0115] By taking the power consumption signal, electromagnetic radiation signal and timing signal of the chip as the basic data input, the change trend and amplitude of each signal are recorded in real time. After each signal data acquisition, the entropy value of the current signal is calculated according to the dynamic entropy value update rule, and the change amplitude of the actual signal entropy value and the interference signal update result is compared to judge the correlation between the signal change and the interference effect, and screen out the signal characteristics of power consumption, electromagnetic radiation and timing signals that change significantly when the dynamic entropy value fluctuates. In this process, the characteristic data of power consumption signals, electromagnetic radiation and timing signals are gradually associated with the dynamic entropy value and the interference signal update results one by one during the signal monitoring process, and the associated monitoring signal acquisition is completed.

[0116] S603: Based on the associated monitoring signal and the response time difference evaluation result, the input disturbance parameters are adjusted, the insertion position and strength of the interference signal are reconfigured according to the risk characteristics, and the FPGA chip commercial security capability detection optimization result is generated;

[0117] First, determine the input disturbance parameters that need to be adjusted based on the associated monitoring signal and the feature type in the key risk feature set, configure different disturbance parameters for signals of different feature types, and select appropriate amplitude, frequency or timing disturbance values ​​to match the response characteristics of the chip to avoid mismatching the input disturbance with the chip's operating status. The configuration process gradually adjusts the insertion position and intensity according to the type of disturbance, and monitors the adjusted insertion position and intensity in real time. This process continuously collects the response time and difference data of the adjusted signal, and finally organizes and generates the optimized results of the FPGA chip commercial confidentiality capability detection to ensure that the optimized detection data has consistent interference intensity configuration and accurate input disturbance parameter settings.

[0118] See also Figure 8 , a commercial encryption capability detection system for an FPGA chip, the system comprising:

[0119] The random data processing module counts each type of data bit by bit based on the voltage fluctuation, clock jitter and thermal noise data collected during the key generation process, calculates the probability distribution of the data, calculates the information entropy value according to the probability of each bit, summarizes the information bit entropy value into an overall distribution structure, and generates the entropy value distribution result;

[0120] The interference signal insertion module analyzes the entropy fluctuation amplitude of each time period based on the entropy value distribution results, sets the interference signal insertion for the fluctuation period, determines the insertion frequency and position, marks the multi-frequency fluctuation section as the interference position and adjusts the signal insertion frequency, and generates dynamic entropy value and interference signal update results;

[0121] The interference signal optimization module analyzes the fluctuation impact of signal insertion based on the dynamic entropy value and the interference signal update results, shields the power consumption fluctuation, electromagnetic radiation and timing signals one by one, covers the operation characteristics by adjusting the signal strength, selects the timing allocation signal strength for the operation stage, and generates the interference signal insertion optimization results;

[0122] The response time analysis module collects the chip response time in normal working state based on the interference signal insertion optimization results, records the execution time of encryption startup, key generation, and data output stages, classifies the data and calculates the average response range between stages, compares the response characteristics section by section, and generates response time difference evaluation results;

[0123] Based on the response time difference evaluation results, the disturbance input adjustment module applies amplitude changes, timing offsets and random noise injection disturbances to the key information, plaintext data and operating parameters one by one, collects the response changes of the chip under the disturbance state, identifies key risk features that affect security, reconfigures the disturbance parameters and the insertion position and strength of the interference signal, and generates optimization results for the commercial encryption capability detection of the FPGA chip.

[0124] The above are only preferred embodiments of the present invention and are not intended to limit the present invention in other forms. Any technician familiar with the profession may use the technical contents disclosed above to change or modify them into equivalent embodiments with equivalent changes and apply them to other fields. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for detecting the commercial encryption capability of an FPGA chip, characterized in that: The following steps are involved: Based on the random data collected in real time during the key generation process, statistical processing is performed on the collected random data, the entropy value of the information bit is calculated according to the probability distribution, and the entropy value distribution result is generated; Based on the random data collected in real time during the key generation process, the collected random data is statistically processed, and the entropy value of the information bit is calculated according to the probability distribution. The specific steps for generating the entropy value distribution result are as follows: Based on the voltage fluctuation data, clock jitter data and thermal noise data collected during the key generation process, the data is grouped according to the information bit, the probability value of each group of data is calculated bit by bit, the probability data of each information bit is counted, and the probability distribution result of the information bit is generated; Based on the information bit probability distribution result, according to the probability data distribution of each information bit, the probability density of the information bit is calculated to obtain an initial entropy value, and the probability data of the information bit is readjusted according to the weight by setting a weighting factor, and the entropy value data after the weight adjustment is merged to obtain an information bit entropy value set; Based on the information bit entropy value set, the information bit entropy value data is accumulated item by item, the overall information entropy value is calculated, the integrity of the overall entropy value data is confirmed by verification, and the entropy value distribution result is generated; Based on the entropy value distribution result, the entropy value fluctuation characteristics are analyzed, and during the encryption process, a random interference signal is inserted in a corresponding time period according to the probability parameter information, and the insertion frequency and position are adjusted according to the entropy value change to generate a dynamic entropy value and interference signal update result; Based on the dynamic entropy value and the interference signal update result, the strength and timing of the interference signal are adjusted to mask the key operation signal characteristics during the chip execution, and the interference signal insertion optimization result is generated; Referring to the signal characteristics in the interference signal insertion optimization result, the response time data of the commercial encryption operation under normal working conditions is collected, the time data of the encryption algorithm is classified and sorted, and compared and analyzed with the response time of the key time period to generate a response time difference evaluation result; Based on the response time difference evaluation result, gradually apply disturbances to the input data used in the encryption process, collect the output response data of the chip under the disturbance characteristics, analyze the impact of the variation of the input characteristics on the output response, and generate the input characteristic variation association result; Based on the input feature variation association result, identify the key risk features in the input features that lead to reduced chip security, adjust the input disturbance parameters and the insertion position and strength of the interference signal according to the key risk features, and generate the FPGA chip commercial security capability detection optimization result; The entropy value distribution result includes the probability distribution of information bits, the overall information entropy level and the fluctuation characteristic parameters; the dynamic entropy value and interference signal update result include the insertion frequency parameters, the position selection rules and the update intensity of the interference signal within the time period; the interference signal insertion optimization result includes the power consumption shielding optimization parameters, electromagnetic interference masking and signal timing perturbation configuration; the response time difference evaluation result includes the range parameters of the task response time, the time comparison data of the key stage and the stage delay feature analysis; the input feature variation association result includes the amplitude change association parameter, the timing offset influence coefficient and the noise interference response information; the FPGA chip commercial confidentiality capability detection optimization result includes the risk feature identification parameter, the interference signal insertion position optimization and the power consumption and electromagnetic masking adjustment.

2. The method for detecting the commercial encryption capability of an FPGA chip according to claim 1, wherein: Based on the entropy distribution result, the entropy fluctuation characteristics are analyzed, and during the encryption process, a random interference signal is inserted in the corresponding time period according to the probability parameter information, and the insertion frequency and position are adjusted according to the entropy change. The specific steps for generating dynamic entropy and interference signal update results are as follows: Based on the entropy distribution result, the entropy data is transferred to the buffer periodically, the entropy data is updated in segments using a sliding time window, the entropy change trend in the current period is monitored, and a time window entropy value set is generated; Based on the time window entropy value set, compare the current entropy value data with the safety reference value, extract the multi-frequency segments of entropy value fluctuations, analyze the interference signal insertion frequency and position parameters of the multi-frequency segments, and obtain the interference signal insertion parameter information; Based on the interference signal insertion parameter information, the frequency and position of the interference signal insertion are adjusted periodically during the encryption process, the entropy value change characteristics are monitored in real time and the signal is updated to generate a dynamic entropy value and an interference signal update result.

3. The method for detecting the commercial encryption capability of an FPGA chip according to claim 1, wherein: Based on the dynamic entropy value and the interference signal update result, the intensity and timing of the interference signal are adjusted to mask the key operation signal characteristics during chip execution, and the specific steps of generating the interference signal insertion optimization result are as follows: Based on the dynamic entropy value and the interference signal update result, the time period data of the entropy value fluctuation is extracted by frequency band classification, the fluctuation amplitude is calculated, the basic strength and initial timing of the interference signal are allocated, and the initial configuration result of the interference signal is obtained; Based on the initial configuration result of the interference signal, combined with the time point of each fluctuation frequency band, the interference signal strength is adjusted one by one, the interference timing is changed according to the change of the entropy value, the corresponding timing signal is generated according to the frequency band, and the interference signal adjustment result is obtained; Based on the interference signal adjustment result, the interference signal with adjusted strength is embedded in the key operation time period, and interference shielding operations are added to power consumption fluctuation, electromagnetic radiation and timing signal respectively to generate interference signal insertion optimization results.

4. The method for detecting the commercial encryption capability of an FPGA chip according to claim 3, wherein: For the fluctuation range calculation, the formula is used: ， Calculate the basic strength A of the interference signal; in, It is the time period The entropy fluctuation range is It is the time period The fluctuation frequency, It is the time period duration, is the data noise impact coefficient, and n is the total number of time periods.

5. The method for detecting the commercial encryption capability of an FPGA chip according to claim 1, wherein: Referring to the signal features in the interference signal insertion optimization result, the response time data of the commercial encryption operation under normal working conditions is collected, the time data of the encryption algorithm is classified and sorted, and compared and analyzed with the response time of the key time period. The specific steps for generating the response time difference evaluation result are as follows: Based on the interference signal insertion optimization result, the response time of the commercial secret operation under normal working conditions is collected, the overall execution time of the task is recorded, and normal response time data is generated; Based on the normal response time data, the response time is sorted by task type, the execution time of the encryption task is allocated to the encryption startup, key generation, and data output stages, the average response time range is calculated, and a staged response time classification result is generated; Based on the staged response time classification results, the time difference data of key stages are cross-compared, the time difference ranges between stages are marked, the response time differences are segmented and sorted, and the response time difference evaluation results are generated.

6. The method for detecting the commercial encryption capability of an FPGA chip according to claim 1, wherein: Based on the response time difference evaluation result, the input data used in the encryption process is gradually disturbed, the output response data of the chip under the disturbance feature is collected, the influence of the variation of the input feature on the output response is analyzed, and the specific steps of generating the input feature variation association result are as follows: Based on the response time difference evaluation result, applying amplitude disturbance to the input data, gradually increasing the amplitude values ​​of the key information and the plaintext data, collecting the output response under the corresponding disturbance state, and generating the input data amplitude disturbance result; Based on the input data amplitude disturbance result, applying a timing offset to the input data, adjusting the input timing position one by one, recording the response time data of the chip in the offset state, and obtaining the input data timing offset analysis result; Based on the input data timing offset analysis result, noise is randomly superimposed on the input data, the noise characteristics are embedded in the key information, plaintext data and operation parameters, the response data of the chip after the disturbance is collected, and the input feature variation association result is generated.

7. The method for detecting the commercial encryption capability of an FPGA chip according to claim 1, wherein: Based on the input feature variation association result, the key risk features in the input features that lead to reduced chip security are identified, and the parameters of the input disturbance and the insertion position and strength of the interference signal are adjusted according to the key risk features. The specific steps for generating the optimization result of the commercial confidentiality capability detection of the FPGA chip are as follows: Based on the input feature variation association results, extract key risk features that lead to reduced chip security, analyze the features of data amplitude anomaly and time series instability item by item, classify and mark them, and generate a key risk feature set; Based on the key risk feature set, the chip power consumption, electromagnetic radiation and timing signal are monitored in real time, and the dynamic entropy value and the interference signal update result are combined to associate the characteristics of the monitoring signal with the dynamic entropy value and the interference signal update result to obtain the associated monitoring signal; Based on the associated monitoring signal and combined with the response time difference evaluation results, the parameters of the input disturbance are adjusted, the insertion position and strength of the interference signal are reconfigured according to the risk characteristics, and the FPGA chip commercial confidentiality capability detection optimization results are generated.

8. A commercial encryption capability detection system for an FPGA chip, characterized in that: According to the method for detecting the commercial encryption capability of an FPGA chip according to any one of claims 1 to 7, the system comprises: The random data processing module counts each type of data bit by bit based on the voltage fluctuation, clock jitter and thermal noise data collected during the key generation process, calculates the probability distribution of the data, calculates the information entropy value according to the probability of each bit, summarizes the information bit entropy value into an overall distribution structure, and generates the entropy value distribution result; The interference signal insertion module analyzes the entropy value fluctuation amplitude of each time period based on the entropy value distribution result, sets the interference signal insertion for the fluctuation period, determines the insertion frequency and position, marks the multi-frequency fluctuation section as the interference position and adjusts the signal insertion frequency, and generates dynamic entropy value and interference signal update results; The interference signal optimization module analyzes the fluctuation influence of signal insertion based on the dynamic entropy value and the interference signal update result, shields the power consumption fluctuation, electromagnetic radiation and timing signal one by one, masks the operation characteristics by adjusting the signal strength, selects the timing allocation signal strength for the operation stage, and generates the interference signal insertion optimization result; The response time analysis module collects the response time of the chip in normal working state based on the interference signal insertion optimization result, records the execution time one by one according to the encryption startup, key generation, and data output stages, classifies the data and calculates the average response range between stages, compares the response characteristics section by section, and generates a response time difference evaluation result; Based on the response time difference evaluation results, the disturbance input adjustment module applies amplitude changes, timing offsets and random noise injection disturbances to the key information, plaintext data and operating parameters one by one, collects the response changes of the chip under the disturbance state, identifies key risk features that affect security, reconfigures the disturbance parameters and the insertion position and strength of the interference signal, and generates the optimization results of the FPGA chip commercial encryption capability detection.

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