Array substrate, mother board, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a mother board, a display panel and a display device. The array substrate comprises a substrate base plate, a first electrode, a second electrode, a third electrode and a fourth electrode, a first conductive portion; a second conductive portion; a second insulating layer; a connection electrode; the connecting electrode is electrically connected with the first conductive part through the plurality of first via holes penetrating through the second insulating layer and the first insulating layer, and is electrically connected with the second conductive part through the plurality of second via holes penetrating through the second insulating layer and the second conductive part; the first conductive part is electrically connected with the second conductive part; wherein the plurality of first via holes comprise at least two columns extending along the first direction, the plurality of second via holes comprise at least one column extending along the first direction, and the at least one column of second via holes are located between the two adjacent columns of first via holes.

Description

Array substrate, motherboard, display panel and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a motherboard, a display panel, and a display device. Background Art

[0002] Liquid Crystal Displays (LCDs) are highly favored due to their low power consumption, high image quality, compact size, and light weight, making them the mainstream display technology. With competition in the panel industry becoming increasingly fierce and demanding for higher image quality, improving panel display quality and yield can effectively enhance product competitiveness.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a motherboard, a display panel, and a display device. The array substrate includes:

[0005] substrate;

[0006] A first conductive portion is located on a first conductive layer, and the first conductive layer is located on one side of the base substrate;

[0007] a first insulating layer, the first insulating layer being located on a side of the first conductive layer facing away from the substrate;

[0008] a second conductive portion, located in the second conductive layer, the second conductive layer is located on a side of the first insulating layer away from the first conductive layer, and the second conductive portion extends along a first direction;

[0009] a second insulating layer, the second insulating layer being located on a side of the second conductive layer facing away from the first insulating layer;

[0010] a connecting electrode, located on the third conductive layer, wherein the third conductive layer is located on a side of the second insulating layer away from the second conductive layer;

[0011] a plurality of first via holes and a plurality of second via holes, wherein the connecting electrode is electrically connected to the first conductive portion through the plurality of first via holes penetrating the second insulating layer and the first insulating layer, and is electrically connected to the second conductive portion through the plurality of second via holes penetrating the second insulating layer;

[0012] The plurality of first vias include at least two columns extending along the first direction, the plurality of second vias include at least one column extending along the first direction, and at least one column of the second vias is located between two adjacent columns of the first vias.

[0013] In a possible implementation manner, at least one column of the first via holes is further provided with the second via holes.

[0014] In a possible implementation manner, the plurality of first via holes and the plurality of second via holes include at least one group of first via holes arranged along the first direction;

[0015] In at least one of the first via hole groups, the plurality of first via holes and the plurality of second via holes are arranged in three rows and three columns, wherein the plurality of second via holes are distributed in the second row and the second column.

[0016] In a possible implementation manner, the plurality of first via holes and the plurality of second via holes include three groups of first via holes arranged along the first direction;

[0017] There is at least one second via group between each adjacent first via group. In the second via group, the plurality of first vias and the plurality of second vias are arranged in one row and three columns, wherein the second vias are distributed in the second column.

[0018] In a possible implementation, the second conductive portion includes a main portion extending along the first direction, and at least one branch portion extending from the first main portion to both sides perpendicular to the first direction;

[0019] The second via hole column located between two adjacent columns of the first via holes is located in the main portion, and the second via holes distributed in the column where the first via holes are located are located in the branch portion.

[0020] In a possible implementation, the plurality of first via holes include two columns extending along the first direction, the plurality of second via holes include one column extending along the first direction, and one column of the second via holes is located between two adjacent columns of the first via holes.

[0021] In a possible implementation, the array substrate includes a display area and a non-display area located outside the display area, and the non-display area is provided with a gate driving circuit;

[0022] The non-display area is provided with a first signal line extending along the first direction, and a second signal line extending perpendicular to the first direction;

[0023] The first signal line includes the first conductive portion, the second signal line includes the second conductive portion, and the first signal line transmits a signal to the gate driving circuit through the second signal line.

[0024] In a possible implementation, the array substrate further includes: a gate layer, a source / drain layer, a pixel electrode layer, and a common electrode layer;

[0025] The first conductive layer is provided in the same layer as the gate layer, the second conductive layer is provided in the same layer as the source and drain electrode layer, and the connecting electrode is provided in the same layer as one of the pixel electrode layer and the common electrode layer.

[0026] In a possible implementation manner, the non-display area further has a plurality of binding areas, and a non-binding area located between adjacent binding areas;

[0027] The binding area has a plurality of binding patterns;

[0028] The non-binding area has a plurality of floating binding patterns, and the film thickness of the floating binding patterns is the same as the film thickness of the binding patterns.

[0029] In a possible implementation manner, the film layer included in the floating binding pattern is the same as the film layer included in the binding pattern.

[0030] In a possible implementation manner, in the binding pattern and the floating binding pattern, only the area where the binding pattern is located is provided with a via.

[0031] The embodiment of the present disclosure further provides a motherboard, which includes the plurality of array substrates provided by the embodiment of the present disclosure, and further includes a test area located at the periphery of the array substrate, and a non-test area located between adjacent test areas;

[0032] The test area includes a surface film layer having a test pattern;

[0033] The non-test area has a floating test pattern, and the floating test pattern is made of the same material as the test pattern.

[0034] In a possible implementation manner, the floating test pattern has the same or similar shape as the test pattern.

[0035] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0036] An embodiment of the present disclosure further provides a display device, which includes the array substrate provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1 is a schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0038] FIG2 is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0039] FIG3 may be a schematic cross-sectional view of FIG1 or FIG2 taken along the dotted line EF;

[0040] FIG4 is a single-layer schematic diagram of the first conductive portion 2 in FIG1 ;

[0041] FIG5 is a schematic diagram of a single film layer of the second conductive portion 3 in FIG1 ;

[0042] Figure 6 is a schematic diagram of a single film layer connected to electrodes;

[0043] FIG7 is a single-layer schematic diagram of the first conductive portion 2 in FIG2 ;

[0044] FIG8 is a schematic diagram of a single film layer of the second conductive portion 3 in FIG2 ;

[0045] FIG9 is a schematic diagram of a single film layer connected to electrodes;

[0046] FIG10A is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0047] FIG10B is a fourth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0048] FIG10C is a schematic diagram showing the distribution of first signal lines and second signal lines provided by an embodiment of the present disclosure;

[0049] FIG10D may be an enlarged schematic diagram of the dotted line coil G in FIG10C ;

[0050] FIG11 is a schematic top view of an array substrate provided in accordance with an embodiment of the present disclosure;

[0051] FIG12 is an enlarged schematic diagram of the dotted coil in FIG11;

[0052] FIG13 is an enlarged schematic diagram of one of the binding patterns in FIG12;

[0053] FIG14 is a schematic diagram of a test area and a non-test area in the related art;

[0054] FIG15 is an enlarged schematic diagram of the dotted line frame W1 in FIG14;

[0055] FIG16 is an enlarged schematic diagram of the dotted line frame W2 in FIG14;

[0056] FIG17A is a schematic diagram of a test area and a non-test area according to an embodiment of the present disclosure;

[0057] FIG17B is a second schematic diagram of a test area and a non-test area according to an embodiment of the present disclosure;

[0058] FIG18 is an enlarged schematic diagram of FIG17A at the dotted line frame W1;

[0059] FIG19 is an enlarged schematic diagram of FIG17A at the dotted line frame W2;

[0060] FIG. 20 is an enlarged schematic diagram of the dotted line frame W3 in FIG. 17A . DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0063] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0064] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0065] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0066] An embodiment of the present disclosure provides an array substrate, as shown in FIG1 , FIG2 , and FIG3 , wherein FIG3 may be a cross-sectional schematic diagram of FIG1 or FIG2 at the dotted line EF, FIG4 is a single-layer schematic diagram of the first conductive portion 2 in FIG1 , FIG5 is a single-film schematic diagram of the second conductive portion 3 in FIG1 , FIG6 is a single-film schematic diagram of the connecting electrode, FIG7 is a single-layer schematic diagram of the first conductive portion 2 in FIG2 , FIG8 is a single-film schematic diagram of the second conductive portion 3 in FIG2 , and FIG9 is a single-film schematic diagram of the connecting electrode. The array substrate includes:

[0067] Base substrate 1;

[0068] The first conductive portion 2 is located on the first conductive layer 20 , and the first conductive layer 20 is located on one side of the base substrate 1 ;

[0069] A first insulating layer 51, the first insulating layer 51 is located on a side of the first conductive layer 20 facing away from the substrate 1;

[0070] The second conductive portion 3 is located in the second conductive layer 30. The second conductive layer 30 is located on the side of the first insulating layer 51 away from the first conductive layer 20. The second conductive portion 3 extends along the first direction X. Specifically, the width h1 of the second conductive portion 3 perpendicular to the first direction X may be smaller than the width h2 of the first conductive portion 2.

[0071] The second insulating layer 52 is located on a side of the second conductive layer 30 away from the first insulating layer 51 , and the second via K2 penetrates the second insulating layer 52 and the first insulating layer 51 ;

[0072] The connecting electrode 4 is located on the third conductive layer 40 . The third conductive layer 40 is located on a side of the second insulating layer 52 away from the second conductive layer 30 .

[0073] Multiple first vias K1 and multiple second vias K2, the connecting electrode 4 is electrically connected to the first conductive part 2 through the multiple first vias K1 that penetrate the second insulating layer 52 and the first insulating layer 51, and is connected to the second conductive part 3 through the multiple second vias K2 that penetrate the second insulating layer 52, so as to electrically connect the first conductive part 2 and the second conductive part 3.

[0074] The plurality of first via holes K1 include at least two columns extending along the first direction X, the plurality of second via holes K2 include at least one column extending along the first direction X, and at least one column of second via holes K2 is located between two adjacent columns of first via holes K1.

[0075] In the embodiment of the present disclosure, the plurality of first vias K1 include at least two columns extending along the first direction X, the plurality of second vias K2 include at least one column extending along the first direction X, and at least one column of second vias K2 is located between two adjacent columns of first vias K1. In the extension direction perpendicular to the second conductive portion 3 (that is, the direction in which the current is conducted), the first vias K1 and the second vias K2 are alternately arranged, which can increase the number of effective vias through which current passes, increase the current resistance value of each via (that is, it is not easy to burn when current passes through), and reduce the probability of the first via K1 and / or the second via K2 being burned.

[0076] In one possible embodiment, as shown in FIG1 , a second via K2 is further provided in at least one column of first vias K1. For example, a second via K2 is further provided in the leftmost column of first vias K1 in FIG1 . In the disclosed embodiment, a second via K2 is further provided in at least one column of first vias K1, that is, a second via K2 is further interspersed in the column of first vias K1. This can improve the effective path for current extraction, further increase the number of effective vias through which current passes, further increase the current resistance value of each via (that is, it is not easy to burn when current passes through), and further reduce the probability of the first via K1 and / or the second via K2 being burned.

[0077] In a possible embodiment, as shown in FIG1 , the plurality of first via holes K1 and the plurality of second via holes K2 include at least one first via hole group Z1 arranged along the first direction X;

[0078] In at least one first via group Z1, multiple first vias K1 and multiple second vias K2 are arranged in three rows and three columns, wherein multiple second vias K2 are distributed in the second row and second column. The first vias K1 in the first via group Z1 are distributed in the remaining rows and columns.

[0079] Specifically, as shown in FIG1 , the plurality of first via holes and the plurality of second via holes K2 include three groups of first via hole groups Z1 arranged along the first direction X1;

[0080] There is also at least one second via group Z2 between every two adjacent first via groups Z1. In the second via group Z2, multiple first vias K1 and multiple second vias K2 are arranged in a row of three columns, where the second vias K2 are distributed in the second column.

[0081] Specifically, as shown in FIG. 1, with the above arrangement of the first vias K1 and the second vias K2, the first vias K1 and the second vias K2 can be arranged in a "rich" shape. Each via is an effective via design, which can maximize the current-carrying capacity of each via.

[0082] In a possible implementation manner, as shown in FIG. 1, the second conductive part 3 includes a main part 31 extending along the first direction X, and at least one branch part 32 extending from the first main part 31 to both sides perpendicular to the first direction X; among them, the column of the second vias K2 located between two adjacent columns of the first vias K1 is located in the main part 31, that is, the orthographic projection of the second vias K2 located between two adjacent columns of the first vias K1 on the substrate 1 is located within the orthographic projection of the main part 31 on the substrate 1; the second vias K2 distributed in the column where the first vias K1 are located are located in the branch part 32, that is, the orthographic projection of the second vias K2 located in the column where the first vias K1 are located on the substrate 1 is located within the orthographic projection of the branch part 32 on the substrate 1. Specifically, for example, as shown in FIG. 1, the column of the second vias K2 located in the middle column is located in the main part 31, and the second vias K2 located in the side columns are located in the branch part 32.

[0083] In a possible implementation manner, as shown in FIG. 2, the multiple first vias K2 include two columns extending along the first direction, and the multiple second vias K2 include one column extending along the first direction X, and one column of the second vias K2 is located between two adjacent columns of the first vias K1. In the embodiments of the present disclosure, the multiple first vias K2 include two columns extending along the first direction, the multiple second vias K2 include one column extending along the first direction X, and one column of the second vias K2 is located between two adjacent columns of the first vias K1. Each via is an effective via, which can improve the current-carrying capacity of the vias in the array substrate while simplifying the pattern design of the second conductive part 3 and the arrangement of the second vias K2, and further simplify the manufacturing process of the array substrate.

[0084] In a possible implementation manner, as shown in FIG. 10A, the multiple first vias K1 and the multiple second vias K2 can also be distributed in two columns, one column is all first vias K1, and the other column is all second vias K2, that is, the first vias K1 and the second vias K2 are arranged side by side. Each via is an effective via, which can also effectively improve the current-carrying capacity of the vias.

[0085] In a possible embodiment, referring to FIG10B , the plurality of first vias K1 and the plurality of second vias K2 may be distributed in two columns, and the first via K1 column may be interspersed with second vias K2. For example, specifically, in the first via K1 column, a second via K2 may be provided every three first vias K1, and in the second via K2 column, all of them may be second vias K2. Thus, the plurality of first vias K1 and the plurality of second vias K2 may be arranged in a "mountain" shape. With this arrangement, each via is also an effective via, and the current carrying capacity of the via can be effectively improved.

[0086] Specifically, in a possible embodiment, in combination with what is shown in FIG10B , the first conductive portion 2 may further be provided with a plurality of second conductive layer vias 200 . Specifically, the orthographic projection of the first via K1 on the base substrate 1 and the orthographic projection of the second conductive layer via 200 on the base substrate 1 do not overlap with each other, and the orthographic projection of the second via K2 on the base substrate 1 and the orthographic projection of the second conductive layer via 200 on the base substrate 1 do not overlap with each other.

[0087] It can be understood that the above is only a schematic explanation of the example of the first conductive part 2 being further provided with multiple second conductive layer vias 200, taking Figure 10B as an example. In a specific implementation, in the array substrate shown in Figures 1, 2, and 10A, the second conductive part 2 may also be provided with multiple second conductive layer vias 200. Similarly, the orthographic projection of the first via K1 on the base substrate 1 and the orthographic projection of the second conductive layer via 200 on the base substrate 1 do not overlap with each other, and the orthographic projection of the second via K2 on the base substrate 1 and the orthographic projection of the second conductive layer via 200 on the base substrate 1 do not overlap with each other.

[0088] In a possible implementation, referring to FIG. 10C and FIG. 10D , FIG. 10D may be an enlarged schematic diagram of the dotted line coil G in FIG. 10C , and FIG. 1 or FIG. 2 may be an enlarged schematic diagram of the dotted line coil G2 in FIG. 10D . The array substrate includes a display area AA and a non-display area BB located outside the display area. The gate drive circuit GOA is provided in the non-display area BB.

[0089] The non-display area AA is provided with a first signal line L1 extending along a first direction X, and a second signal line L2 extending perpendicular to the first direction X;

[0090] The first signal line L1 includes a first conductive portion 2 , the second signal line L2 includes a second conductive portion 3 , and the first signal line L1 transmits a signal to the gate driving circuit GOA through the second signal line L2 .

[0091] Specifically, the first signal line L1 and / or the second signal line L2 can be signal lines electrically connected to the gate drive circuit GOA. For example, the first signal line L1 can be a clock signal line (CLK), and the second signal line L2 can be a clock signal lead CLK'(L2). For another example, the first signal line L1 can be a DC signal line (such as a high-level signal line VGH and / or a low-level signal line VGL), and the second signal line L2 can be a DC signal lead. For another example, the first signal line L1 can be a start signal line (STV), and the second signal line L2 can be an start signal lead.

[0092] In one possible embodiment, the array substrate further includes: a gate layer, a source / drain layer, a pixel electrode layer, and a common electrode layer; specifically, the first conductive layer 20 can be provided in the same layer as the gate layer, the second conductive layer 30 can be provided in the same layer as the source / drain layer, and the connecting electrode 4 can be provided in the same layer as one of the pixel electrode layer and the common electrode layer. In the embodiment of the present disclosure, the first conductive layer 20 can be provided in the same layer as the gate layer, the second conductive layer 30 can be provided in the same layer as the source / drain layer, and the connecting electrode 4 can be provided in the same layer as one of the pixel electrode layer and the common electrode layer. The first conductive layer 20 can be formed at the same time as the gate layer is formed, the second conductive layer 30 can be formed at the same time as the source / drain layer is formed, and the connecting electrode 4 can be formed at the same time as the pixel electrode or the common electrode is formed, thereby simplifying the manufacturing process of the array substrate.

[0093] In a possible implementation, referring to FIG. 11 and FIG. 12 , FIG. 12 is an enlarged schematic diagram of the dotted line circle in FIG. 11 , the non-display area BB further includes a plurality of binding areas P and a non-binding area Q located between adjacent binding areas P.

[0094] The binding area P has a plurality of binding patterns 6;

[0095] The non-binding region Q has a plurality of floating binding patterns 7 , and the film thickness of the floating binding patterns 7 is the same as the film thickness of the binding patterns 6 .

[0096] In the disclosed embodiment, the non-binding area Q has a plurality of floating binding patterns 7, and the film thickness of the floating binding pattern 7 is the same as the film thickness of the binding pattern 6. When the array substrate is subjected to rubbing orientation (Rubbing), the film thickness contacted by the Rubbing cloth near the binding area P is consistent, thereby reducing the risk of horizontal stripes Mura caused by Rubbing.

[0097] Specifically, the binding pattern 6 of the binding area P can be used to bind the signal line of the display area AA and the circuit board (such as a flexible circuit board FPC), thereby achieving electrical connection between the two.

[0098] Specifically, as shown in FIG13 , the binding pattern 6 may include a first binding electrode 61 and a second binding electrode 62 located on a side of the first binding electrode 61 facing away from the substrate 1 . Specifically, the first binding electrode 61 may be provided on the same layer as the gate layer, and the second binding electrode 62 may be provided on the same layer as the pixel electrode layer or the common electrode layer. Specifically, the first binding electrode 61 and the second binding electrode 62 may be strip-shaped.

[0099] Specifically, the film layer included in the floating binding pattern 7 is the same as the film layer included in the binding pattern 6. For example, the binding pattern 6 may include a first binding electrode 61 and a second binding electrode 62 located on the side of the first binding electrode 61 facing away from the base substrate 1. The floating binding pattern 7 may include a first floating binding electrode 71 and a second floating binding electrode 72 located on the side of the first floating binding electrode 71 facing away from the base substrate 1. The material and pattern of the first floating binding electrode 71 may be the same as the material and pattern of the first binding electrode 61, and the material and pattern of the second floating binding electrode 72 may be the same as the material and pattern of the second binding electrode 62.

[0100] Specifically, in the binding pattern 6 and the floating binding pattern 7, only the area where the binding pattern 6 is located is provided with a via K3. In the embodiment of the present disclosure, in the binding pattern 6 and the floating binding pattern 7, only the area where the binding pattern 6 is located is provided with a via K3. That is, the newly added floating binding pattern 7 is used to improve the horizontal mura defect during friction alignment, and does not perform a conductive function. Vias connecting different film layers do not need to be provided. On the one hand, this can simplify the manufacturing process of the array substrate. On the other hand, it can also avoid other unnecessary adverse effects on the performance of the array substrate when additional vias are provided around the periphery of the array substrate.

[0101] As shown in Figures 14, 15, and 16, Figure 15 is an enlarged schematic diagram of the dotted line frame W1 in Figure 14, and Figure 16 is an enlarged schematic diagram of the dotted line frame W2 in Figure 14. As shown in Figures 14-16, the periphery of the array substrate may include a test area S1 and a non-test area S2. The test area S1 has a test pattern 81, and the area near some of the test patterns 81 and the non-test area S2 is blank. In other words, in the related art, after the array substrate process is completed, a test (array test) is required to check for defects in the array section and determine whether signals can be input. In other words, electrical signals are applied through test patterns (AT Pads) to test whether various signal lines within the array substrate have defects such as short circuits or open circuits, thereby intercepting defects during the array process. The array test requires a special test pattern, which is not conducive to rubbing. Therefore, this design needs to be improved. In the Rubbing process, when the Rubbing cloth is rubbing and aligning with the array substrate, the contact surface has a second layer of indium tin oxide (for example, a pixel electrode layer or a common electrode layer) and a passivation layer (where there is no second layer of indium tin oxide). On the AT Pad side, because there are different Patterns, different Patterns may be composed of different film layers, for example, including an insulating layer + a gate layer, an insulating layer, an insulating layer + a source and drain layer, an insulating layer + a second layer of indium tin oxide, or an insulating layer + a source and drain layer + a gate layer, etc., so the film thickness cannot be the same at each position. Specifically, the film layer composition of the AT Pad can be a gate layer + a second layer of indium tin oxide, that is, a gate layer / insulating layer / a second layer of indium tin oxide, and the insulating layer between the second layer of indium tin oxide and the gate layer is removed, so that the second layer of indium tin oxide is directly overlapped with the gate layer.

[0102] Based on this consideration, as shown in FIG17B , a floating slit design, such as a dummy slit, is made on the surface without the indium tin oxide (ITO) layer between two adjacent test areas S1 (the area shown as the non-test area S2 in the middle of FIG17B ), and between the test area S1 and the edge of the motherboard 10 (the areas shown as the uppermost and lowermost non-test areas S2 in FIG17B ). The morphology is consistent with the film pattern of the top layer of the test pattern 81 of the test area S1. For example, if the top layer is an indium tin oxide layer, the pattern is consistent with the indium tin oxide layer. In this way, it can be ensured that the rubbing cloth contacts the indium tin oxide layer on this surface during operation, thereby reducing the risk of rubbing horizontal mura and improving the life of the rubbing cloth. Specifically, the film layer below the newly added indium tin oxide (ITO) layer in the non-test area S2 can be consistent with that of the prior art. Specifically, referring to Figures 17A, 18, 19, and 20, wherein Figure 18 is an enlarged schematic diagram of the dotted line frame W1 in Figure 17A, Figure 19 is an enlarged schematic diagram of the dotted line frame W2 in Figure 17A, and Figure 20 is an enlarged schematic diagram of the dotted line frame W3 in Figure 17A, the motherboard includes a plurality of array substrates according to the embodiment of the present disclosure, and further includes a test area S1 located at the periphery of the array substrate, and a non-test area S2 located between adjacent test areas S1;

[0103] The test area S1 includes a surface film layer having a test pattern 81;

[0104] Non-test area S2 has a floating test pattern 82 made of the same material as the test pattern. Specifically, floating test pattern 82 can be set in an area adjacent to test area S1 within non-test area S2. Specifically, floating test pattern 82 can also be set near test pattern 81 within test area S1.

[0105] Specifically, in this public embodiment, after the motherboard is cut, multiple array substrates of the disclosed embodiment can be formed. After the motherboard is cut, the test pattern of the test area S1 and the non-test pattern of the non-test area S2 can be removed.

[0106] In one possible embodiment, the floating test pattern has the same and / or similar shape as the test pattern. Specifically, the floating test pattern has a similar shape to the test pattern. For example, as shown in FIG18 , the test pattern 81 may be in the shape of a bow, and the floating test pattern 82 may be in the shape of a bar. This simplifies the manufacturing process of the floating test pattern 82.

[0107] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0108] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes the array substrate provided by the embodiment of the present disclosure.

[0109] In the embodiment of the present disclosure, the plurality of first vias K1 include at least two columns extending along the first direction X, the plurality of second vias K2 include at least one column extending along the first direction X, and at least one column of second vias K2 is located between two adjacent columns of first vias K1. In the extension direction perpendicular to the second conductive portion 3 (that is, the direction in which the current is conducted), the first vias K1 and the second vias K2 are alternately arranged, which can increase the number of effective vias through which current passes, increase the current resistance value of each via (that is, it is not easy to burn when current passes through), and reduce the probability of the first via K1 and / or the second via K2 being burned.

[0110] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0111] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, include: substrate substrate; A first conductive portion, located on a first conductive layer, wherein the first conductive layer is located on one side of the base substrate; A first insulating layer, wherein the first insulating layer is located on a side of the first conductive layer away from the substrate; A second conductive portion, located in a second conductive layer, the second conductive layer is located on a side of the first insulating layer away from the first conductive layer, and the second conductive portion extends along a first direction; a second insulating layer, the second insulating layer being located on a side of the second conductive layer away from the first insulating layer; a connecting electrode, located on a third conductive layer, wherein the third conductive layer is located on a side of the second insulating layer away from the second conductive layer; a plurality of first via holes and a plurality of second via holes, wherein the connection electrode is electrically connected to the first conductive part through the plurality of first via holes penetrating the second insulating layer and the first insulating layer, and is electrically connected to the second conductive part through the plurality of second via holes penetrating the second insulating layer; The plurality of first via holes include at least two columns extending along the first direction, the plurality of second via holes include at least one column extending along the first direction, and at least one column of the second via holes is located between two adjacent columns of the first via holes.

2. The array substrate according to claim 1, wherein, The second via holes are also arranged in at least one column of the first via holes.

3. The array substrate according to claim 2, wherein, The plurality of first via holes and the plurality of second via holes include at least one group of first via holes arranged along the first direction; In at least one of the first via hole groups, the plurality of first via holes and the plurality of second via holes are arranged in three rows and three columns, wherein the plurality of second via holes are distributed in the second row and the second column.

4. The array substrate according to claim 3, wherein, The plurality of first via holes and the plurality of second via holes include three groups of the first via holes arranged along the first direction; There is at least one second via group between each adjacent first via group, and in the second via group, the plurality of first vias and the plurality of second vias are arranged in one row and three columns, wherein the second vias are distributed in the second column.

5. The array substrate according to claim 4, wherein, The second conductive portion includes a main portion extending along the first direction, and at least one branch portion extending from the first main portion to both sides perpendicular to the first direction; The second via hole column located between two adjacent columns of the first via holes is located in the main portion, and the second via holes distributed in the column where the first via holes are located are located in the branch portion.

6. The array substrate according to claim 1, wherein, The plurality of first via holes include two columns extending along the first direction, the plurality of second via holes include one column extending along the first direction, and one column of the second via holes is located between two adjacent columns of the first via holes.

7. The array substrate according to any one of claims 1-6, wherein, The array substrate comprises a display area and a non-display area located outside the display area, wherein the non-display area is provided with a gate driving circuit; The non-display area is provided with a first signal line extending along the first direction, and a second signal line extending perpendicular to the first direction; The first signal line includes the first conductive portion, the second signal line includes the second conductive portion, and the first signal line transmits a signal to the gate driving circuit through the second signal line.

8. The array substrate according to claim 7, wherein The array substrate further includes: a gate layer, a source-drain layer, a pixel electrode layer, and a common electrode layer; The first conductive layer is disposed on the same layer as the gate layer, the second conductive layer is disposed on the same layer as the source-drain layer, and the connection electrode is disposed on the same layer as one of the pixel electrode layer and the common electrode layer.

9. The array substrate according to claim 6, wherein, The non-display area further has a plurality of bonding areas and non-bonding areas located between adjacent bonding areas; The bonding area has a plurality of bonding patterns; The non-bonding area has a plurality of floating bonding patterns, and the film thickness of the floating bonding patterns is the same as that of the bonding patterns.

10. The array substrate according to claim 9, wherein, The film layers included in the floating bonding patterns are the same as those included in the bonding patterns.

11. The array substrate according to claim 10, wherein, Among the bonding patterns and the floating bonding patterns, vias are provided only in the area where the bonding patterns are located.

12. A motherboard, wherein, Including a plurality of array substrates according to any one of claims 1-11, further including a test area located on the periphery of the array substrate and a non-test area located between adjacent test areas; The test area includes a surface film layer having test patterns; The non-test area has floating test patterns, and the floating test patterns are made of the same material as the test patterns.

13. The motherboard according to claim 12, wherein, The floating test patterns have the same or similar shapes as the test patterns.

14. A display panel, wherein, Including an array substrate according to any one of claims 1-11.

15. A display device, wherein, Including a display panel according to claim 14.

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