Imaging device

Abstract

The sensitivity of the second cell (100b) is lower than the sensitivity of the first cell (100a), the first cell (100a) includes a first charge storage unit (FD1) and a first wiring, the first charge storage unit (FD1) stores a first signal charge and is electrically connected to the first node (FDA), the first wiring is located in the upper wiring layer and is electrically connected to the first node (FDA), the second cell (100b) includes a second charge storage unit (FD2) stores a second signal charge and a second wiring, the second charge storage unit (FD2) stores a second signal charge and is electrically connected to the second node (FDA). The first wiring is located in the first wiring layer and electrically connected to the second node (FDB), the second wiring is located in the upper wiring layer and electrically connected to the second node (FDB), and in the upper wiring layer, the shortest distance between the first wiring and the plurality of wiring is greater than the shortest distance between the second wiring and the plurality of wiring.

Description

Technical Field

[0001] The present invention relates to a camera device. Background Art

[0002] Image pickup devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary MOS) image sensors are known, and various studies are being conducted on image pickup devices.

[0003] For example, an imaging device having a structure for realizing a wide dynamic range has been proposed. The imaging device of Patent Document 1 has a 1-pixel 2-unit structure. Specifically, in the imaging device of Patent Document 1, a large-area photodiode is arranged in a high-sensitivity unit, and a small-area photodiode is arranged in a low-sensitivity unit.

[0004] In addition, for example, a stacked imaging device is proposed in which a photoelectric conversion unit is arranged above a semiconductor substrate. In the stacked imaging device, the charge generated by the photoelectric conversion is accumulated in the charge accumulation unit. An electrical signal corresponding to the amount of charge accumulated in the charge accumulation unit is read out via a CCD circuit or a CMOS circuit provided on the semiconductor substrate. Patent document 2 discloses such a stacked imaging device.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent No. 4018820

[0008] Patent Document 2: Japanese Patent No. 6213743

[0009] Patent Document 3: Japanese Patent No. 6323813

[0010] Patent Document 4: Japanese Patent No. 6782431 Summary of the invention

[0011] The present disclosure provides a technology suitable for realizing an imaging device with high image quality.

[0012] A camera device according to a technical solution of the present disclosure comprises: a semiconductor substrate; and pixels, including a first unit, a second unit having a lower sensitivity than the first unit, and an upper wiring layer above the semiconductor substrate and including a plurality of wirings; the first unit includes: a first photoelectric conversion unit that converts light into a first signal charge; a first charge accumulation unit that is located in the semiconductor substrate, accumulates the first signal charge, and is electrically connected to a first node; and a first wiring that is located in the upper wiring layer and is electrically connected to the first node; the second unit includes: a second photoelectric conversion unit that converts light into a second signal charge; a second charge accumulation unit that is located in the semiconductor substrate, accumulates the second signal charge, and is electrically connected to a second node; and a second wiring that is located in the upper wiring layer and is electrically connected to the second node; the nodes electrically connected to each of the plurality of wirings are different from the first node and the second node; in the upper wiring layer, the shortest distance between the first wiring and the plurality of wirings is greater than the shortest distance between the second wiring and the plurality of wirings.

[0013] The technology related to the present disclosure is suitable for realizing a high-quality imaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is an exemplary configuration diagram of the imaging device according to the first embodiment.

[0015] Figure 2 This is an exemplary circuit diagram of a pixel according to the first embodiment.

[0016] Figure 3 This is a schematic structural diagram of a pixel in a cross section parallel to the thickness direction of a semiconductor substrate.

[0017] Figure 4 FIG. 1 is a top view showing a microlens group.

[0018] Figure 5 This is a top view of the pixel electrode, etc.

[0019] Figure 6 It is a schematic partial enlarged view of a capacitor element having a trench structure.

[0020] Figure 7 This is a circuit diagram of a pixel according to another example of the first embodiment.

[0021] Fig. 8A The overflow transistor is applied to Figure 2 Circuit diagram after circuit diagram.

[0022] Figure 8B The overflow transistor is applied to Figure 7 Circuit diagram after circuit diagram.

[0023] Fig. 9 This is an explanatory diagram of a circuit configuration using a photodiode.

[0024] Fig. 10A This is a schematic diagram of the structure of the gate wiring layer when viewed from above.

[0025] Fig. 10B This is a schematic diagram of the structure of the first wiring layer when viewed from above.

[0026] Fig. 10C This is a schematic diagram of the MIM hierarchy when viewed from above.

[0027] Fig. 10D It is a schematic structural diagram of the second wiring layer when viewed from above.

[0028] Fig.10E This is a schematic diagram of the structure of the third wiring layer when viewed from above.

[0029] Fig.10F This is a schematic diagram of the structure of the fourth wiring layer when viewed from above.

[0030] Figure 10G This is a schematic diagram of the structure of the fifth wiring layer when viewed from above.

[0031] Fig. 10H This is a schematic diagram of the structure of the sixth wiring layer when viewed from above.

[0032] Fig.10I This is a schematic diagram of the structure of the pixel electrode layer when viewed from above.

[0033] Fig.11A is with Figure 8B A schematic structural diagram of the gate wiring layer when viewed from above, corresponding to the structure of .

[0034] Fig. 11B is with Figure 8B A schematic structural diagram of the first wiring layer when viewed from above, corresponding to the structure of .

[0035] Fig. 11C is with Figure 8B A schematic structural diagram of the second wiring layer when viewed from above, corresponding to the structure of .

[0036] Fig.12 It is a schematic plan view for explaining the magnitude relationship of the area ratio. DETAILED DESCRIPTION

[0037] (Insights that form the basis of this disclosure)

[0038] The inventor of the present application has studied an imaging device with a 1-pixel 2-unit structure. The imaging device related to the study has a high-sensitivity unit and a high-saturation unit. The high-sensitivity unit has a higher sensitivity than the high-saturation unit. The high-saturation unit has a larger saturation charge than the high-sensitivity unit. Each of the high-sensitivity unit and the high-saturation unit includes a photoelectric conversion unit that converts light into signal charge, and a charge accumulation unit that accumulates the signal charge. In each of the high-sensitivity unit and the high-saturation unit, the charge accumulation unit is located in the semiconductor substrate.

[0039] In order to improve the image quality of the above-mentioned imaging device with a one-pixel two-cell structure, it is effective to reduce the noise of the high-sensitivity cell. In order to reduce the noise of the high-sensitivity cell, it is effective to increase the conversion gain of the high-sensitivity cell.

[0040] Here, the term charge accumulation node is used. A charge accumulation node is a node electrically connected to a charge accumulation portion. A charge accumulation node is also referred to as a floating diffusion node. In addition, the term capacitance of a charge accumulation node is used. The capacitance of a charge accumulation node is the entire capacitance electrically connected to the charge accumulation node. In addition, the term capacitance value of a charge accumulation node is used. The capacitance value of a charge accumulation node is the capacitance value of the capacitance of the charge accumulation node. The capacitance of a charge accumulation node may include parasitic capacitance between a charge accumulation portion and an electrical path connecting a photoelectric conversion portion and a charge accumulation portion and other structures. The capacitance value of a charge accumulation node may include the capacitance value of the charge accumulation portion and the capacitance value of the above-mentioned parasitic capacitance.

[0041] In order to improve the conversion gain of the high-sensitivity unit, it is effective to reduce the capacitance value of the charge accumulation node of the high-sensitivity unit. In order to reduce the capacitance value of the charge accumulation node of the high-sensitivity unit, it is effective to reduce the capacitance value of the above-mentioned parasitic capacitance in the high-sensitivity unit. Following this point, the present disclosure provides a technology suitable for realizing a high-quality camera device.

[0042] (Abstract of a technical solution of the present disclosure)

[0043] The camera device of the first technical solution of the present disclosure comprises: a semiconductor substrate; and pixels, including a first unit, a second unit with lower sensitivity than the above-mentioned first unit, and an upper wiring layer above the above-mentioned semiconductor substrate and including multiple wirings; the above-mentioned first unit includes: a first photoelectric conversion part, which converts light into a first signal charge; a first charge accumulation part, which is located in the above-mentioned semiconductor substrate, accumulates the above-mentioned first signal charge, and is electrically connected to the first node; and a first wiring, which is located in the above-mentioned upper wiring layer and is electrically connected to the above-mentioned first node; the above-mentioned second unit includes: a second photoelectric conversion part, which converts light into a second signal charge; a second charge accumulation part, which is located in the above-mentioned semiconductor substrate, accumulates the above-mentioned second signal charge, and is electrically connected to the second node; and a second wiring, which is located in the above-mentioned upper wiring layer and is electrically connected to the above-mentioned second node; the nodes electrically connected to each of the above-mentioned multiple wirings are different from the above-mentioned first node and the above-mentioned second node; in the above-mentioned upper wiring layer, the shortest distance between the above-mentioned first wiring and the above-mentioned multiple wirings is larger than the shortest distance between the above-mentioned second wiring and the above-mentioned multiple wirings.

[0044] The first technical solution is suitable for realizing a high-quality imaging device.

[0045] In the second technical solution of the present disclosure, for example, in the camera device related to the first technical solution, the above-mentioned pixel may also include a first capacitor wiring layer above the above-mentioned semiconductor substrate; the above-mentioned first capacitor wiring layer may also include: a first prescribed wiring, electrically connected to the above-mentioned first node; and a first specific wiring, electrically connected to a specific node different from the above-mentioned first node; the above-mentioned first unit may also include a specific capacitor element; the above-mentioned specific capacitor element may also include the above-mentioned first prescribed wiring and the above-mentioned first specific wiring.

[0046] The second technical solution is suitable for realizing a specific capacitance element with high precision and a small capacitance value.

[0047] In the third technical solution of the present disclosure, for example, in the camera device related to the second technical solution, the above-mentioned pixel may also include a second capacitor wiring layer above the above-mentioned semiconductor substrate and above or below the above-mentioned first capacitor wiring layer; the above-mentioned second capacitor wiring layer may also include: a second prescribed wiring, electrically connected to the above-mentioned first node; and a second specific wiring, electrically connected to the above-mentioned specific node; the above-mentioned specific capacitor element may also include the above-mentioned second prescribed wiring and the above-mentioned second specific wiring.

[0048] According to the third aspect, it is easy to increase the ratio of the capacitance value of the specific capacitance element to the capacitance value of the specific node, thereby improving the accuracy of the capacitance value of the specific node.

[0049] In the fourth technical solution of the present disclosure, for example, in the camera device related to the second technical solution or the third technical solution, there may be a straight line passing through the first part of the first specific wiring, the specified part of the first specified wiring, and the second part of the first specific wiring in sequence in a cross section passing through the first capacitor wiring layer and perpendicular to the thickness direction of the semiconductor substrate.

[0050] According to the fourth aspect, it is easy to increase the ratio of the capacitance value of the specific capacitance element to the capacitance value of the specific node, thereby improving the accuracy of the capacitance value of the specific node.

[0051] In the fifth technical solution of the present disclosure, for example, in a camera device related to any one of the second to fourth technical solutions, the first unit may also include a first amplifier transistor, which generates a first electric signal corresponding to the potential of the first charge accumulation unit; the first electric signal may also be negatively fed back to the first charge accumulation unit via the specific capacitor element.

[0052] According to the fifth aspect, the specific capacitance element can be used for negative feedback of the first electric signal.

[0053] In the sixth technical solution of the present disclosure, for example, the camera device related to any one of the second to fifth technical solutions may also have a power supply wiring electrically connected to a power supply node, which is different from the above-mentioned first node, the above-mentioned second node and the above-mentioned specific node; the above-mentioned first unit may also include a first amplifier transistor, which generates a first electrical signal corresponding to the potential of the above-mentioned first charge accumulation part, and is supplied with the power supply potential via the above-mentioned power supply wiring; in the above-mentioned first capacitor wiring layer, the above-mentioned first specific wiring may also be located between the above-mentioned power supply wiring and the above-mentioned first specified wiring.

[0054] According to the sixth aspect, the first specific wiring can function as a shield for suppressing coupling between the power supply wiring and the first predetermined wiring.

[0055] In the seventh technical solution of the present disclosure, for example, in the camera device related to the sixth technical solution, the first electric signal can also be negatively fed back to the first charge accumulation unit via the specific capacitor element; the potential of the negatively fed back first electric signal can also be applied to the power supply wiring.

[0056] According to the seventh aspect, even if a potential variation occurs in the power supply wiring due to negative feedback of the first electric signal, the influence on the capacitance of the first node can be suppressed by the shielding effect.

[0057] In the 8th technical solution of the present disclosure, for example, in the camera device related to any one of the 2nd to 7th technical solutions, the above-mentioned first unit may also include a first capacitor element; the above-mentioned first capacitor element may also have a first electrode electrically connected to the above-mentioned specific node and a second electrode electrically separated from the above-mentioned first electrode; the above-mentioned first electrode may also be located between the above-mentioned second electrode and the above-mentioned semiconductor substrate; the shortest distance between the above-mentioned first prescribed wiring in the above-mentioned first capacitor wiring layer and the above-mentioned first specific wiring may also be smaller than the shortest distance between the above-mentioned first electrode and the above-mentioned semiconductor substrate.

[0058] According to the eighth technical solution, it is easy to increase the ratio of the capacitance value of the specific capacitance element to the capacitance value of the specific node, thereby improving the accuracy of the capacitance value of the specific node.

[0059] In a ninth technical solution of the present disclosure, for example, in the imaging device according to any one of the second to eighth technical solutions, the first unit may include a MIM capacitor element or a MOS capacitor element electrically connected to the specific node.

[0060] The ninth technical solution is suitable for increasing the capacitance value of a specific node.

[0061] In the tenth technical solution of the present disclosure, for example, in the imaging device related to any one of the second to ninth technical solutions, the plurality of wirings may be wirings obtained by removing all wirings electrically connected to the specific node from all wirings of the upper wiring layer.

[0062] The structure of the tenth technical solution is an example of the structure of a camera device.

[0063] In the 11th technical solution of the present disclosure, for example, in the imaging device related to any one of the 1st to 9th technical solutions, the plurality of wirings may be all wirings in the upper wiring layer.

[0064] The structure of the 11th technical solution is an example of the structure of a camera device.

[0065] The camera device of the 12th technical solution of the present disclosure comprises: a semiconductor substrate; and pixels, including a first unit, a second unit with lower sensitivity than the above-mentioned first unit, and an upper wiring layer located above the above-mentioned semiconductor substrate and including a first signal wiring and a second signal wiring; the above-mentioned first unit includes: a first photoelectric conversion unit that converts light into a first signal charge; a first charge accumulation unit that is located in the above-mentioned semiconductor substrate and accumulates the above-mentioned first signal charge and is electrically connected to a first node; a first wiring that is located in the above-mentioned upper wiring layer and is electrically connected to the above-mentioned first node; and a first transistor that includes a first source or a first drain that serves as the above-mentioned first charge accumulation unit, and a first signal charge that is electrically connected to the first node via the above-mentioned first wiring. The first signal wiring is connected to the first gate and is supplied with the first control signal; the second unit includes: a second photoelectric conversion unit that converts light into a second signal charge; a second charge accumulation unit that is located in the semiconductor substrate, accumulates the second signal charge, and is electrically connected to the second node; a second wiring that is located in the upper wiring layer and is electrically connected to the second node; and a second transistor that includes a second source or a second drain that serves as the second charge accumulation unit, and a second gate that is supplied with the second control signal via the second signal wiring; in the upper wiring layer, the shortest distance between the first wiring and the first signal wiring is larger than the shortest distance between the second wiring and the second signal wiring.

[0066] The twelfth technical solution is suitable for realizing a high-definition camera device.

[0067] The camera device of the 13th technical solution of the present disclosure comprises: a semiconductor substrate; and pixels, including a first unit, a second unit having a lower sensitivity than the first unit, and an upper wiring layer located above the semiconductor substrate and including a plurality of wirings; the first unit includes: a first photoelectric conversion unit that converts light into a first signal charge; a first charge accumulation unit that is located in the semiconductor substrate and accumulates the first signal charge and is electrically connected to a first node; and a first wiring that is located in the upper wiring layer and is electrically connected to the first node ; The above-mentioned second unit includes: a second photoelectric conversion part, which converts light into a second signal charge; a second charge accumulation part, which is located in the above-mentioned semiconductor substrate, accumulates the above-mentioned second signal charge and is electrically connected to the second node; and a second wiring, which is located in the above-mentioned upper wiring layer and is electrically connected to the above-mentioned second node; the nodes electrically connected to each of the above-mentioned multiple wirings are different from the above-mentioned first node and the above-mentioned second node; in a cross-section passing through the above-mentioned upper wiring layer and perpendicular to the thickness direction of the above-mentioned semiconductor substrate, the area of ​​the above-mentioned first wiring is smaller than the area of ​​the above-mentioned second wiring.

[0068] The 13th technical solution is suitable for realizing a high-definition camera device.

[0069] The camera device of the 14th technical solution of the present disclosure comprises: a semiconductor substrate; and a plurality of pixels arranged at a predetermined pitch; the plurality of pixels include at least one pixel; the at least one pixel includes a first unit, a second unit having a lower sensitivity than the first unit, and an upper wiring layer located above the semiconductor substrate and including a plurality of wirings; the first unit includes: a first photoelectric conversion unit that converts light into a first signal charge; a first charge accumulation unit that is located in the semiconductor substrate, accumulates the first signal charge, and is electrically connected to a first node; and a first wiring that is located in the upper wiring layer and is electrically connected to the first node; the second unit includes: a second photoelectric conversion unit that converts light into a second signal charge; a second charge accumulation unit that is located in the semiconductor substrate, accumulates the second signal charge, and is electrically connected to a second node; and a second wiring that is located in the upper wiring layer and is electrically connected to the first node. In the upper wiring layer, it is electrically connected to the above-mentioned second node; the nodes electrically connected to each of the above-mentioned multiple wirings are different from the above-mentioned first node and the above-mentioned second node; in a cross-section passing through the above-mentioned upper wiring layer and perpendicular to the thickness direction of the above-mentioned semiconductor substrate, when the geometric center of the above-mentioned first wiring is defined as the first center point, the geometric center of the above-mentioned second wiring is defined as the second center point, the area surrounded by a circle with the above-mentioned first center point as the center and a radius of 1 / 8 of the above-mentioned spacing is defined as the first enclosed area, the area surrounded by a circle with the above-mentioned second center point as the center and a radius of 1 / 8 of the above-mentioned spacing is defined as the second enclosed area, the ratio of the areas occupied by the above-mentioned multiple wirings in the above-mentioned first enclosed area is defined as the first area ratio, and the ratio of the areas occupied by the above-mentioned multiple wirings in the above-mentioned second enclosed area is defined as the second area ratio, the above-mentioned first area ratio is smaller than the above-mentioned second area ratio.

[0070] The 14th technical solution is suitable for realizing a high-definition camera device.

[0071] The camera device of the 15th technical solution of the present disclosure comprises: a semiconductor substrate; and pixels, including a first unit and a second unit with lower sensitivity than the above-mentioned first unit; the above-mentioned first unit includes: a first photoelectric conversion part, which converts light into a first signal charge; a first charge accumulation part, which is located in the above-mentioned semiconductor substrate, accumulates the above-mentioned first signal charge, and is electrically connected to the first node; a first plug, which is electrically connected to the above-mentioned first node; and a first capacitor element, which has a first electrode and a second electrode; the above-mentioned second unit includes: a second photoelectric conversion part, which converts light into a second signal charge; a second charge accumulation part, which is located in the above-mentioned semiconductor substrate, accumulates the above-mentioned second signal charge, and is electrically connected to the second node; a second plug, which is electrically connected to the above-mentioned second node; and a second capacitor element, which has a third electrode and a fourth electrode; in a cross section passing through the above-mentioned first capacitor element and perpendicular to the thickness direction of the above-mentioned semiconductor substrate, the shortest distance between the above-mentioned first plug and the above-mentioned second electrode is larger than the shortest distance between the above-mentioned second plug and the above-mentioned fourth electrode.

[0072] The 15th technical solution is suitable for realizing a high-definition camera device.

[0073] In the 16th technical solution of the present disclosure, for example, in the camera device related to the 15th technical solution, the above-mentioned first unit may also include a first transistor; the above-mentioned second unit may also include a second transistor; one of the source and drain of the above-mentioned first transistor may also be the above-mentioned first charge accumulation part; one of the source and drain of the above-mentioned second transistor may also be the above-mentioned second charge accumulation part; the above-mentioned first transistor and the above-mentioned first electrode may also be electrically connected; the above-mentioned second transistor and the above-mentioned third electrode may also be electrically connected.

[0074] The structure of the 16th technical solution is an example of the structure of a camera device.

[0075] The camera device of the 17th technical solution of the present disclosure comprises a semiconductor substrate and a pixel, wherein the pixel comprises: an upper wiring layer, which is located above the semiconductor substrate and includes a first signal wiring; a first photoelectric conversion unit, which converts light into a first signal charge; a first charge accumulation unit, which is located in the semiconductor substrate, accumulates the first signal charge and is electrically connected to a first node; a first wiring, which is located in the upper wiring layer and is electrically connected to the first node; a first plug, which is electrically connected to the first node; a first capacitor, which has a first electrode and a second electrode; and a first transistor, which includes a first source or a first drain as the first charge accumulation unit and a first gate to which a first control signal is supplied via the first signal wiring; in a cross section passing through the first capacitor and perpendicular to the thickness direction of the semiconductor substrate, the first plug is located in a recess provided in the first capacitor and opening in a prescribed direction; in the upper wiring layer, the first signal wiring is located on the prescribed direction side of the first wiring.

[0076] The 17th technical solution is suitable for realizing a high-definition camera device.

[0077] In the 18th technical solution of the present disclosure, for example, the camera device related to the 17th technical solution may also have an intermediate wiring that electrically connects the above-mentioned first plug with the above-mentioned first wiring; when viewed from above, the above-mentioned intermediate wiring may also extend from a position within the above-mentioned recess to a position closer to the above-mentioned prescribed direction side than the above-mentioned recess.

[0078] According to the intermediate wiring of the eighteenth technical solution, the positional relationship among the recess, the first plug, the first wiring, and the first signal wiring of the seventeenth technical solution can be easily realized.

[0079] In the 19th technical solution of the present disclosure, for example, in the camera device related to the 17th technical solution or the 18th technical solution, the ratio of the shortest distance between the first plug and the second electrode in the cross section passing through the first capacitor element and perpendicular to the thickness direction of the semiconductor substrate to the shortest distance between the first wiring and the first signal wiring in the upper wiring layer can also be greater than 0.5 and less than 2.

[0080] The 19th technical solution is suitable for realizing a high-definition camera device.

[0081] In the 20th technical solution of the present disclosure, for example, in the camera device related to any one of the 17th to 19th technical solutions, the above-mentioned pixel may also include a first unit and a second unit having lower sensitivity than the above-mentioned first unit; the above-mentioned first unit may also include: the above-mentioned first photoelectric conversion part; the above-mentioned first charge accumulation part; the above-mentioned first wiring; the above-mentioned first plug; the above-mentioned first capacitor element; and the above-mentioned first transistor.

[0082] The 20th technical solution is suitable for realizing a high-definition camera device.

[0083] As long as there is no particular contradiction, the techniques of the first to twentieth technical solutions can be combined arbitrarily. For example, as long as there is no particular contradiction, at least one part or all of the second to eleventh technical solutions can be combined with the twelfth to twentieth technical solutions, respectively. In addition, for example, as long as there is no particular contradiction, the first technical solution, the twelfth to fifteenth technical solutions, and the seventeenth technical solution can also be combined.

[0084] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments described below all represent inclusive or specific examples. The numerical values, shapes, materials, constituent elements, configurations of constituent elements and connection forms, steps, the order of steps, etc. shown in the following embodiments are examples, and their main purpose is not to limit the present disclosure. The various technical solutions described in this specification can be combined with each other as long as there is no contradiction. In each figure, constituent elements having substantially the same function are represented by common reference numerals, and repeated descriptions are sometimes omitted or simplified.

[0085] Various elements shown in the drawings are schematically shown only for understanding of the present disclosure, and dimensional ratios, appearances, etc. may be different from actual objects.

[0086] In the embodiment, the terms "upper", "lower", "side", etc. are used only to specify the relative configuration between components, and are not intended to limit the posture of the camera device when in use or to limit the posture of the components of the camera device in the middle of manufacturing and the manufacturing device.

[0087] In this specification, there are cases where ordinal numbers such as 1st, 2nd, 3rd, etc. are used. When an ordinal number is given to a certain element, it is not necessary that there is a smaller element of the same kind. The number of the ordinal number can be changed as needed. The ordinal number is not given for the purpose of limiting the interpretation of the element with it. The same applies to the terms such as "determine" and "prescribe".

[0088] In the embodiments, “viewed from above” means viewing from the thickness direction of the semiconductor substrate.

[0089] In the embodiments, the polarity of the transistor and the conductivity type of the impurity region are merely examples, and the polarity of the transistor and the conductivity type of the impurity region may be reversed as long as there is no contradiction.

[0090] In the embodiments, an expression such as “element A is connected to element B” may be used. This expression includes a case where a part or all of element A is included in a part or all of element B. In addition, this expression includes not only a case where element A is directly connected to element B, but also a case where element A is indirectly connected to element B via other elements.

[0091] In the embodiments, the expression "element A is electrically connected to element B" may be used. This expression means that element A and element B are connected at the same potential. In addition, in the embodiments, "connected" and "electrically connected" may be interchanged unless there is any particular contradiction.

[0092] (First embodiment)

[0093] Figure 1FIG. 1 is an exemplary structural diagram of an imaging device 1 according to the first embodiment. The imaging device 1 includes a pixel array 10 and peripheral circuits. The pixel array 10 includes a plurality of pixels 100, which constitute an imaging area. In this example, the plurality of pixels 100 are disposed on a semiconductor substrate 2 (see FIG. 1 ). Figure 3 ) are arranged two-dimensionally on a grid. Specifically, the plurality of pixels 100 are arranged in a matrix of m rows and n columns. More specifically, the center of each pixel 100 is located at a lattice point of a square grid.

[0094] The configuration of the pixels 100 is not limited to the illustrated example. For example, the center of each pixel 100 may be located at a grid point of a triangular grid, a hexagonal grid, or the like. A plurality of pixels 100 may also be arranged in one dimension. That is, the configuration of the pixels 100 may be m rows and 1 column or 1 row and n columns. In this case, the imaging device 1 may be used as a line sensor. The number of pixels 100 in the imaging device 1 may also be 1.

[0095] exist Figure 1 In the illustrated structure, the peripheral circuit includes a row scanning circuit 310, a column circuit 312, a signal processing circuit 313, an output circuit 314, and a control circuit 311. The pixel array 10 and the peripheral circuit can be configured on the same semiconductor substrate 2. Alternatively, the pixel array 10 is configured on the semiconductor substrate 2, and the peripheral circuit is configured on another semiconductor substrate. Alternatively, the pixel array 10 is configured on the semiconductor substrate 2, a part of the peripheral circuit is configured on the semiconductor substrate 2, and another part of the peripheral circuit is configured on another semiconductor substrate.

[0096] The row scanning circuit 310 is connected to the first reset control line RSTiA, the second reset control line RSTiB, and the feedback control line FBi. The first reset control line RSTiA, the second reset control line RSTiB, and the feedback control line FBi are provided corresponding to each row of the pixel array 10. That is, one or more pixels 100 belonging to the i-th row among the plurality of pixels 100 are connected to the first reset control line RSTiA, the second reset control line RSTiB, and the feedback control line FBi. Here, i is 0 to n-1, and n is an integer greater than 1.

[0097] The row scanning circuit 310 is connected to Figure 1 The first address control line SELiA and the second address control line SELiB not shown in the figure are connected (refer to Fig.10E). The first address control line SELiA and the second address control line SELiB are also provided corresponding to each row of the pixel array 10, similarly to the first reset control line RSTiA, the second reset control line RSTiB and the feedback control line FBi, and are connected to one or more pixels 100 belonging to the i-th row. The row scanning circuit 310 applies a predetermined potential to the first address control line SELiA and the second address control line SELiB, thereby selecting the pixel 100 in a row unit, and performs the readout of the electrical signal and the reset operation described later. The row scanning circuit 310 is also called a vertical scanning circuit.

[0098] The column circuit 312 is connected to the first vertical signal line SIGjA and the second vertical signal line SIGjB provided corresponding to each column of the pixel array 10. Here, j is 0 to m-1, and m is an integer greater than 1. One or more pixels 100 belonging to the j-th column among the plurality of pixels 100 are connected to the first vertical signal line SIGjA and the second vertical signal line SIGjB, and the electrical signal output from the pixel 100 selected in row units by the row scanning circuit 310 is read out to the column circuit 312 via the first vertical signal line SIGjA and the second vertical signal line SIGjB. The column circuit 312 performs noise suppression signal processing, analog-to-digital conversion (AD conversion), etc. on the electrical signal read out from the pixel 100. The noise suppression signal processing is, for example, correlated double sampling.

[0099] The signal processing circuit 313 performs various processing on the image signal obtained from the pixel 100. In this specification, the "image signal" refers to the electrical signal used for image formation among the electrical signals read out via the first vertical signal line SIGjA and the second vertical signal line SIGjB. The pixel 100 includes a first unit 100a with high sensitivity and a second unit 100b with low sensitivity and high saturation (see Figure 2 ). The high-sensitivity image signal is read out from the first unit 100a and the low-sensitivity image signal is read out from the second unit 100b. The signal processing circuit 313 forms a wide dynamic range image based on these high-sensitivity image signals and low-sensitivity image signals. The output of the signal processing circuit 313 is read out to the outside of the imaging device 1 via the output circuit 314.

[0100] The control circuit 311 receives command data, clocks, etc. The command data, clocks, etc. are provided, for example, from the outside of the imaging device 1. The control circuit 311 controls the entire imaging device 1 based on the received command data, clocks, etc. The control circuit 311 typically has a timing generator, and supplies drive signals to the row scanning circuit 310, the column circuit 312, etc.

[0101] Figure 21 is an exemplary circuit diagram of a pixel 100 according to the first embodiment. One pixel 100 includes a first unit 100a and a second unit 100b. The first unit 100a is more sensitive than the second unit 100b. The second unit 100b is more saturated than the first unit 100a. That is, the saturation charge amount of the second unit 100b is greater than the saturation charge amount of the first unit 100a. The first unit 100a may also be referred to as a high-sensitivity unit or a first imaging unit. The second unit 100b may also be referred to as a high-saturation unit or a second imaging unit.

[0102] The first unit 100a is responsible for capturing images of areas with relatively low illumination. The first unit 100a functions as a low noise unit. On the other hand, the second unit 100b is responsible for capturing images of areas with relatively high illumination. The second unit 100b functions as a dynamic range extension unit that extends the dynamic range toward the high illumination side. By using the first unit 100a and the second unit 100b, it becomes easy to capture images of scenes with a wide dynamic range.

[0103] The first unit 100a has a first microlens 113a (see Figure 3 ), a first photoelectric conversion unit 120 and a first signal detection circuit 200. Light is incident on the first photoelectric conversion unit 120 via the first microlens 113a. The first photoelectric conversion unit 120 converts the light into a first signal charge. The first signal detection circuit 200 is electrically connected to the first photoelectric conversion unit 120. The first signal detection circuit 200 reads out a first electrical signal based on the first signal charge generated by the first photoelectric conversion unit 120. In the present embodiment, the first signal detection circuit 200 is a MOS (Metal Oxide Semiconductor) circuit. The first signal detection circuit 200 may also be a TFT (Thin Film Transistor) circuit.

[0104] In this embodiment, the imaging device 1 is a stacked type. The first unit 100a is a stacked type. The first photoelectric conversion part 120 is provided on the semiconductor substrate 2. The first photoelectric conversion part 120 has a first pixel electrode 102, a first counter electrode 111a, and a first photoelectric conversion film 110a. The first photoelectric conversion film 110a is arranged between the first pixel electrode 102 and the first counter electrode 111a.

[0105] Typically, the first pixel electrode 102 is provided for each pixel 100. The first pixel electrodes 102 and the first pixel electrodes 102 adjacent to each other are electrically separated. The first pixel electrode 102 is electrically connected to the first node FDA. The first node FDA may also be referred to as the first charge accumulation node, the first floating diffusion node, etc. Hereinafter, the capacitance of the capacitor electrically connected to the first node FDA is sometimes referred to as the capacitance of the first node FDA as a whole. The capacitance value of the capacitor of the first node FDA is sometimes referred to as the capacitance value of the first node FDA.

[0106] The first counter electrode 111a is disposed on the light receiving surface side of the first photoelectric conversion film 110a. The first counter electrode 111a is transparent and has conductivity. When the imaging device 1 is in operation, a predetermined potential VpA is applied to the first counter electrode 111a.

[0107] By applying a potential VpA to the first counter electrode 111a, one of the holes and the electrons in the hole-electron pair generated by the first counter electrode 111a through photoelectric conversion can be collected by the first pixel electrode 102. In the case of using holes as the first signal charge, for example, a potential of about 10V is applied to the first counter electrode 111a as the potential VpA. By making the potential of the first counter electrode 111a higher than the potential of the first pixel electrode 102, the holes can be accumulated in the capacitance of the first node FDA. The following describes an example of using holes as the first signal charge. Of course, electrons can also be used as the first signal charge.

[0108] The first signal detection circuit 200 includes a first amplifier transistor 205 , a first selection transistor 206 , a first reset transistor 202 , and a first feedback circuit FC1 .

[0109] In the present embodiment, the transistor is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), specifically an N-channel MOSFET. The transistor is disposed on a semiconductor substrate 2. The semiconductor substrate 2 is not limited to a substrate whose entirety is a semiconductor. The semiconductor substrate 2 may also have an insulating layer and a semiconductor layer. A transistor may be disposed on the semiconductor layer. A photosensitive region may be disposed on the semiconductor layer side. The transistor may also be a TFT (Thin Film Transistor). These points are the same not only in the first unit 100a, but also in the second unit 100b.

[0110] The control terminal of the first amplifier transistor 205 is electrically connected to the first node FDA. In this embodiment, the control terminal of the first amplifier transistor 205 is a gate.

[0111] The gate of the first amplifier transistor 205 is electrically connected to the first photoelectric conversion section 120, specifically, to the first pixel electrode 102. A potential corresponding to the amount of first signal charges generated by the first photoelectric conversion section 120 is applied to the gate. The first amplifier transistor 205 generates a first electrical signal corresponding to the applied potential.

[0112] One of the source and drain of the first amplifier transistor 205 is electrically connected to one of the source and drain of the first selection transistor 206. The other of the source and drain of the first amplifier transistor 205 is electrically connected to a power supply node VR to which a power supply potential VDD is applied. The other of the source and drain of the first selection transistor 206 is electrically connected to a first vertical signal line 208a. The first selection transistor 206 selectively outputs the first electrical signal generated by the first amplifier transistor 205 to the first vertical signal line 208a. The first vertical signal line 208a is electrically connected to the first vertical signal line 208a. Figure 1 It corresponds to the first vertical signal line SIGjA shown.

[0113] One of the source and drain of the first reset transistor 202 is electrically connected to the first node FDA. The first reset transistor 202 resets (initializes) the potential of the capacitor of the first node FDA. In this embodiment, one of the source and drain of the first reset transistor 202 is the first charge storage unit FD1.

[0114] The first feedback circuit FC1 includes a band control transistor 207 , a first inverting amplifier 300 a , a first capacitor 203 , and a specific capacitor 204 .

[0115] The first reference potential VREFA is applied to the first input terminal of the first inverting amplifier 300a. The first vertical signal line 208a is electrically connected to the second input terminal of the first inverting amplifier 300a. The output terminal of the first inverting amplifier 300a is connected to one of the source and drain of the band control transistor 207 via the first feedback line 209a provided corresponding to each column. The other of the source and drain of the band control transistor 207 is electrically connected to the specific node RD. The other of the source and drain of the first reset transistor 202, the first capacitor 203, and the specific capacitor 204 are electrically connected to the specific node RD.

[0116] The first capacitor 203 includes an electrode 203 a and an electrode 203 b. The electrode 203 a is electrically connected to the specific node RD. A potential is applied to the electrode 203 b from the first capacitor control line TPA. The capacitance value of the first capacitor 203 is larger than the capacitance value of the specific capacitor 204 .

[0117] The specific capacitor 204 includes a specific electrode 204a and a specific electrode 204b. The specific electrode 204a is electrically connected to the first node FDA, and the specific electrode 204b is electrically connected to the specific node RD.

[0118] The band control transistor 207 performs band control of the first feedback circuit FC1. The first feedback circuit FC1 includes a first feedback path FP1. The first feedback path FP1 includes a first inverting amplifier 300a, a band control transistor 207, and a specific capacitor element 204 in sequence. The first feedback path FP1 negatively feeds back the kTC noise generated when the first reset transistor 202 is turned off to the capacitor of the first node FDA. The first inverting amplifier 300a can increase the gain of the first feedback path FP1 and improve the noise suppression effect.

[0119] The first feedback line 209a is provided corresponding to each column. The first feedback line 209a connects the plurality of first cells 100a belonging to the column. Thus, column feedback is realized for the plurality of first cells 100a belonging to the column.

[0120] The second unit 100b has a second microlens 113b (see Figure 3 ), a second photoelectric conversion unit 130 and a second signal detection circuit 210. Light is incident on the second photoelectric conversion unit 130 via the second microlens 113b. The second photoelectric conversion unit 130 converts the light into a second signal charge. The second signal detection circuit 210 is electrically connected to the second photoelectric conversion unit 130. The second signal detection circuit 210 reads out a second electrical signal based on the second signal charge generated by the second photoelectric conversion unit 130. In the present embodiment, the second signal detection circuit 210 is a MOS circuit. The second signal detection circuit 210 may also be a TFT circuit.

[0121] In this embodiment, the second unit 100b is a stacked type. The second photoelectric conversion part 130 is provided on the semiconductor substrate 2. The second photoelectric conversion part 130 includes a second pixel electrode 103, a second counter electrode 111b, and a second photoelectric conversion film 110b. The second photoelectric conversion film 110b is arranged between the second pixel electrode 103 and the second counter electrode 111b.

[0122] Typically, the second pixel electrode 103 is provided for each pixel 100. The second pixel electrodes 103 and the second pixel electrodes 103 adjacent to each other are electrically separated. The second pixel electrode 103 is electrically connected to the second node FDB. The second node FDB may also be referred to as a second charge accumulation node, a second floating diffusion node, etc. In the following, the capacitor electrically connected to the second node FDB is sometimes referred to as the capacitance of the second node FDB as a whole. The capacitance value of the capacitance of the second node FDB is sometimes referred to as the capacitance value of the second node FDB. The capacitance value of the second node FDB is larger than the capacitance value of the first node FDA.

[0123] The second counter electrode 111b is disposed on the light receiving surface side of the second photoelectric conversion film 110b. The second counter electrode 111b is transparent and has conductivity. When the imaging device 1 is in operation, a predetermined potential VpB is applied to the second counter electrode 111b.

[0124] By applying a potential VpB to the second counter electrode 111b, one of the holes and the electrons in the hole-electron pair generated by the second counter electrode 111b through photoelectric conversion can be collected by the second pixel electrode 103. In the case of using holes as the second signal charge, for example, a potential of about 10V is applied to the second counter electrode 111b as the potential VpB. By making the potential of the second counter electrode 111b higher than the potential of the second pixel electrode 103, the holes can be accumulated in the capacitance of the second node FDB. The following describes an example of using holes as the second signal charge. Of course, electrons can also be used as the second signal charge.

[0125] The second signal detection circuit 210 includes a second amplifying transistor 215 , a second selecting transistor 216 , a second capacitor 213 , and a second feedback circuit FC2 .

[0126] The control terminal of the second amplifier transistor 215 is electrically connected to the second node FDB. In the present embodiment, the control terminal of the second amplifier transistor 215 is a gate.

[0127] The gate of the second amplifier transistor 215 is electrically connected to the second photoelectric conversion section 130, specifically, to the second pixel electrode 103. A potential corresponding to the amount of second signal charges generated by the second photoelectric conversion section 130 is applied to the gate. The second amplifier transistor 215 generates a second electrical signal corresponding to the applied potential.

[0128] One of the source and drain of the second amplifier transistor 215 is electrically connected to one of the source and drain of the second selection transistor 216. The other of the source and drain of the second amplifier transistor 215 is electrically connected to the power supply node VR to which the power supply potential VDD is applied. The other of the source and drain of the second selection transistor 216 is electrically connected to the second vertical signal line 208b. The second selection transistor 216 selectively outputs the second electrical signal generated by the second amplifier transistor 215 to the second vertical signal line 208b. The second vertical signal line 208b is connected to the second vertical signal line 208b. Figure 1 It corresponds to the second vertical signal line SIGjB shown.

[0129] One of the source and drain of the second reset transistor 217 is electrically connected to the second node FDB. The second reset transistor 217 resets (initializes) the potential of the capacitor of the second node FDB. In this embodiment, one of the source and drain of the second reset transistor 217 is the second charge storage unit FD2.

[0130] The second capacitor 213 is electrically connected to the second node FDB. The second capacitor 213 improves the high saturation characteristics of the second unit 100b and expands the dynamic range of the imaging device 1.

[0131] The second feedback circuit FC2 includes a second reset transistor 217 and a second inverting amplifier 300 b .

[0132] The second reference potential VREFB is applied to the first input terminal of the second inverting amplifier 300b. The second vertical signal line 208b is electrically connected to the second input terminal of the second inverting amplifier 300b. The other of the source and drain of the second reset transistor 217 is electrically connected to the output terminal of the second inverting amplifier 300b via the second feedback line 209b provided corresponding to each column.

[0133] The second capacitor 213 includes an electrode 213a and an electrode 213b. The electrode 213a is electrically connected to the second node FDB. A potential is applied to the electrode 213b from the second capacitor control line TPB.

[0134] The second feedback circuit FC2 includes a second feedback path FP2. The second feedback path FP2 includes a second inverting amplifier 300b and a second reset transistor 217. The second feedback path FP2 negatively feeds back the kTC noise generated when the second reset transistor 217 is turned off to the capacitor of the second node FDB. The second inverting amplifier 300b can increase the gain of the second feedback path FP2 and improve the noise suppression effect.

[0135] The second feedback line 209b is provided corresponding to each column. The second feedback line 209b connects the plurality of second cells 100b belonging to the column. Thus, column feedback is realized for the plurality of second cells 100b belonging to the column.

[0136] The first unit 100a and the second unit 100b may have at least one structure selected from the following structures. These structures can make the sensitivity of the first unit 100a higher than the sensitivity of the second unit 100b:

[0137] When viewed from above, the light-collecting area of ​​the first microlens 113 a is larger than the light-collecting area of ​​the second microlens 113 b ;

[0138] In a plan view, the area of ​​the first pixel electrode 102 is larger than the area of ​​the second pixel electrode 103 in a plan view.

[0139] As described above, the first unit 100a and the second unit 100b have the following characteristics:

[0140] The first unit 100a is more sensitive than the second unit 100b;

[0141] The first unit 100a is low noise compared to the second unit 100b;

[0142] The second unit 100b is highly saturated compared to the first unit 100a;

[0143] The capacitance value of the second node FDB is larger than the capacitance value of the first node FDA.

[0144] The statement "the first unit 100a is more sensitive than the second unit 100b" is explained. In the present embodiment, this statement means that when a certain amount of white light is incident on the imaging device 1, the amount of the first signal charge generated is greater than the amount of the second signal charge generated. The sensitivity depends on the area of ​​the microlens and the pixel electrode.

[0145] The statement "the first unit 100a has lower noise than the second unit 100b" is explained. In the present embodiment, the statement means that, when a certain amount of white light is incident on the imaging device 1, the absolute value of the noise of the first electrical signal derived from the light incident on the first unit 100a is greater than the absolute value of the noise of the second electrical signal derived from the light incident on the second unit 100b.

[0146] The expression "the second unit 100b is highly saturated compared to the first unit 100a" is explained. In the present embodiment, this expression means that, when the amount of white light incident on the imaging device 1 gradually increases, the second timing (timing) appears later than the first timing. The second timing is the timing when the level of the second electrical signal derived from the light incident on the second unit 100b reaches the top. The first timing is the timing when the level of the first electrical signal derived from the light incident on the first unit 100a reaches the top.

[0147] The first unit 100a is responsible for capturing images of dark scenes. Therefore, the necessity for the first unit 100a to have high saturation characteristics is relatively low. On the other hand, the necessity for the first unit 100a to have low noise characteristics is relatively high.

[0148] In contrast, the second unit 100b is responsible for the imaging of brighter scenes. Therefore, the necessity for the second unit 100b to have high saturation characteristics is relatively high. On the other hand, the necessity for the second unit 100b to have low noise characteristics is relatively low. This is because, in the imaging of brighter scenes, the amount of light is large, and the influence of dark current shot noise on image quality is reduced.

[0149] The first cell 100a includes the first feedback circuit FC1, thereby suppressing noise generated when the first reset transistor 202 is turned off. The second cell 100b includes the second feedback circuit FC2, thereby suppressing noise generated when the second reset transistor 217 is turned off.

[0150] Figure 3 1 is a schematic structural diagram of a pixel 100 in a cross section parallel to the thickness direction of a semiconductor substrate 2. A plurality of insulating layers 3 are provided above the semiconductor substrate 2. The pixel 100 is formed using the semiconductor substrate 2 and the plurality of insulating layers 3.

[0151] The pixel 100 has a microlens group 113 connected in one piece. Figure 3 In the example of FIG. 1 , in one pixel 100 , the microlens group 113 includes a first microlens 113 a and a second microlens 113 b . Figure 4 FIG. 1 is a top view showing the microlens group 113. Figure 4 In FIG. 1 , reference numerals MLa and MLb respectively indicate a first microlens 113a and a second microlens 113b belonging to the same pixel 100. In addition, a microlens group refers to two or more microlenses.

[0152] The microlens group 113 may be provided across all pixels 100. A plurality of pixel blocks having microlens groups 113 provided across a plurality of pixels 100 may also be provided. The microlens group 113 may also be provided independently for each pixel 100. In addition, in one pixel 100, the first microlens 113a and the second microlens 113b may be separated from each other.

[0153] The pixel 100 has a photoelectric conversion film 110 connected integrally. Figure 3 In the example of FIG. 1 , in one pixel 100 , the photoelectric conversion film 110 includes a first photoelectric conversion film 110 a and a second photoelectric conversion film 110 b . The photoelectric conversion film 110 may have a uniform film thickness in the pixel array 10 .

[0154] The photoelectric conversion film 110 may be provided across all pixels 100. A plurality of pixel blocks having the photoelectric conversion film 110 provided across a plurality of pixels 100 may be provided. The photoelectric conversion film 110 may be provided independently for each pixel 100. Furthermore, in one pixel 100, the first photoelectric conversion film 110a and the second photoelectric conversion film 110b may be separated from each other.

[0155] The pixel 100 has an opposing electrode 111 connected integrally. Figure 3 In the example of FIG. 1 , in one pixel 100, the counter electrode 111 includes a first counter electrode 111a and a second counter electrode 111b. When the imaging device 1 is in operation, a predetermined potential Vp is applied to the counter electrode 111. Therefore, the potential VpA applied to the first counter electrode 111a and the potential VpB applied to the second counter electrode 111b are both the potential Vp and are the same.

[0156] The opposing electrode 111 may be provided across all pixels 100. In this case, a common potential can be supplied to the opposing electrodes 111 of all pixels 100. A plurality of pixel blocks having opposing electrodes 111 provided across a plurality of pixels 100 may be provided. A different potential may be supplied to the opposing electrode 111 of each pixel block. In this case, the sensitivity of the pixel 100 may be changed for each pixel block. The opposing electrode 111 may be provided independently for each pixel 100. A different potential may be supplied to the opposing electrode 111 of each pixel 100. In this case, the sensitivity may be changed for each pixel 100. In addition, in one pixel 100, the first opposing electrode 111a and the second opposing electrode 111b may be separated from each other.

[0157] The pixel 100 has an auxiliary electrode 104 . Figure 5 FIG. 1 is a top view of the first pixel electrode 102, the second pixel electrode 103, and the auxiliary electrode 104. Figure 5In FIG. 1 , reference numerals ELa and ELb respectively indicate the first pixel electrode 102 and the second pixel electrode 103 belonging to the same pixel 100. Hereinafter, the term pixel electrode level ES is used. The pixel electrode level ES of this embodiment includes the first pixel electrode 102, the second pixel electrode 103 and the auxiliary electrode 104. Figure 3 In FIG. 8 , a pixel electrode level ES is shown.

[0158] like Figure 5 As shown, when viewed from above, the auxiliary electrode 104 is arranged between the first pixel electrode 102 and the second pixel electrode 103. When viewed from above, the auxiliary electrode 104 is arranged between the first pixel electrode 102 and the first pixel electrode 102 adjacent to each other. When viewed from above, the auxiliary electrode 104 is arranged between the second pixel electrode 103 and the second pixel electrode 103 adjacent to each other. Specifically, when viewed from above, the auxiliary electrode 104 surrounds the first pixel electrode 102. When viewed from above, the auxiliary electrode 104 surrounds the second pixel electrode 103. The first pixel electrode 102, the second pixel electrode 103 and the auxiliary electrode 104 are electrically separated from each other. The auxiliary electrode 104 is also called a shielding electrode.

[0159] In the present embodiment, the first capacitor element 203 is a MIM (Metal Insulator Metal) capacitor element. According to the MIM capacitor element, the first capacitor element 203 with a higher capacitance density can be realized. In addition, "M" of MIM refers to at least one of metal and metal compound. "I" of MIM is an insulator, such as an oxide. That is, MIM is a concept including MOM (Metal Oxide Metal). That is, for the first capacitor element 203 as a MIM capacitor element, a dielectric as an insulator which can also be an oxide is sandwiched between an electrode 203a and an electrode 203b including at least one of a metal and a metal compound. The dielectric of the first capacitor element 203 includes, for example, a high-k material. As a High-k material, a metal oxide is given as an example. As a metal oxide, hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ) etc. In this embodiment, the first capacitor 203 has a trench structure. Figure 6 It is a schematic partial enlarged view of the first capacitor element 203 having a groove structure. The groove structure refers to a structure including a bent portion. The use of high-k materials and groove structures is advantageous from the perspective of ensuring the capacitance value of the first capacitor element 203. In this embodiment, the description of the first capacitor element 203 is also applicable to the second capacitor element 213. Specifically, the description of the structure, material, etc. of the first capacitor element 203 can also be applied to the structure, material, etc. of the second capacitor element 213. Figure 6 In FIG. 1 , the reference numerals in parentheses represent the second capacitor element 213 and the elements included in the second capacitor element 213 according to the present embodiment.

[0160] exist Figure 6 In the embodiment, the first capacitor 203 includes an electrode 203a and an electrode 203b. The electrode 203a is located between the electrode 203b and the semiconductor substrate 2. The second capacitor 213 includes an electrode 213a and an electrode 213b. The electrode 213a is located between the electrode 213b and the semiconductor substrate 2.

[0161] Hereinafter, the term MIM level MS may be used. The MIM level MS of this embodiment includes a first capacitor 203 as a MIM capacitor and a second capacitor 213 as a MIM capacitor. Figure 3 The MIM level MS is represented in .

[0162] like Figure 3 As shown, the pixel 100 has a buffer layer 4, a sealing layer 5, a color filter 112, and a planarization layer 6. In the thickness direction of the semiconductor substrate 2, a photoelectric conversion film 110 is provided above the first pixel electrode 102, the second pixel electrode 103, and the auxiliary electrode 104. The photoelectric conversion film 110, the counter electrode 111, the buffer layer 4, the sealing layer 5, the color filter 112, and the planarization layer 6 are provided in order from bottom to top. The color filter 112 has a transmission wavelength range corresponding to each pixel 100. Above the planarization layer 6, a first microlens 113a and a second microlens 113b are provided.

[0163] The first signal detection circuit 200 and the second signal detection circuit 210 are respectively provided in a manner straddling the interface between the semiconductor substrate 2 and the insulating layer 3. The first signal detection circuit 200 detects the potential of the capacitor of the first node FDA. The first signal detection circuit 200 can also be said to detect the potential of the first charge accumulation unit FD1. The second signal detection circuit 210 detects the potential of the capacitor of the second node FDB. The second signal detection circuit 210 can also be said to detect the potential of the second charge accumulation unit FD2.

[0164] In the plurality of insulating layers 3, a plurality of plugs 105, a plurality of plugs 106, a pixel electrode level ES, a MIM level MS, and a plurality of wiring layers WL are provided. Typically, each wiring layer WL includes a plurality of wirings. The first pixel electrode 102 is electrically connected to the first signal detection circuit 200 via the plurality of plugs 105 and the plurality of wiring layers WL. The second pixel electrode 103 is electrically connected to the second signal detection circuit 210 via the plurality of plugs 106 and the plurality of wiring layers WL. The plugs 105 and 106 may also be referred to as contacts.

[0165] Specifically, the plurality of insulating layers 3 include an insulating layer 3a, an insulating layer 3b, an insulating layer 3c, an insulating layer 3d, an insulating layer 3e, and an insulating layer 3f. At least one plug 105 and at least one plug 106 are provided in each of the insulating layers 3a, 3b, 3c, 3d, 3e, and 3f. At least one wiring layer WL is provided in each of the insulating layers 3a, 3b, 3c, 3d, and 3e.

[0166] More specifically, the plurality of plugs 105 include a plurality of via plugs 105v and a contact plug 105c. The plurality of plugs 106 include a plurality of via plugs 106v and a contact plug 106c. The plurality of wiring layers WL include a gate wiring layer WLG, a first wiring layer WL1, a second wiring layer WL2, a third wiring layer WL3, a fourth wiring layer WL4, a fifth wiring layer WL5, and a sixth wiring layer WL6.

[0167] The plurality of insulating layers 3 are respectively configured as follows:

[0168] In the insulating layer 3a, a gate wiring layer WLG, a contact plug 105c, a contact plug 106c, a first wiring layer WL1, a via plug 105v, a via plug 106v, a second wiring layer WL2 and a MIM level MS are provided;

[0169] In the insulating layer 3b, a via plug 105v, a via plug 106v and a third wiring layer WL3 are provided;

[0170] In the insulating layer 3c, a via plug 105v, a via plug 106v and a fourth wiring layer WL4 are provided;

[0171] In the insulating layer 3d, a via plug 105v, a via plug 106v and a fifth wiring layer WL5 are provided;

[0172] In the insulating layer 3e, a via plug 105v, a via plug 106v and a sixth wiring layer WL6 are provided;

[0173] In the insulating layer 3f, a dielectric plug 105v, a dielectric plug 106v and a pixel electrode layer ES are provided.

[0174] A first transmission path 125 is formed which includes a contact plug 105c, a first wiring layer WL1, an interlayer plug 105v of an insulating layer 3a, a second wiring layer WL2, an interlayer plug 105v of an insulating layer 3b, a third wiring layer WL3, an interlayer plug 105v of an insulating layer 3c, a fourth wiring layer WL4, an interlayer plug 105v of an insulating layer 3d, a fifth wiring layer WL5, an interlayer plug 105v of an insulating layer 3e, a sixth wiring layer WL6, and an interlayer plug 105v of an insulating layer 3f in this order. The first pixel electrode 102 is electrically connected to the first charge storage unit FD1 via the first transmission path 125. A part of the charge generated by the photoelectric conversion film 110 is captured by the first pixel electrode 102 as the first signal charge. The first signal charge is transmitted from the first pixel electrode 102 to the first charge storage unit FD1 via the first transmission path 125.

[0175] A second transmission path 135 is formed which includes, in order, a contact plug 106c, a first wiring layer WL1, an interlayer plug 106v of an insulating layer 3a, a second wiring layer WL2, an interlayer plug 106v of an insulating layer 3b, a third wiring layer WL3, an interlayer plug 106v of an insulating layer 3c, a fourth wiring layer WL4, an interlayer plug 106v of an insulating layer 3d, a fifth wiring layer WL5, an interlayer plug 106v of an insulating layer 3e, a sixth wiring layer WL6, and an interlayer plug 106v of an insulating layer 3f. The second pixel electrode 103 is electrically connected to the second charge storage unit FD2 via the second transmission path 135. A part of the charge generated by the photoelectric conversion film 110 is captured by the second pixel electrode 103 as a second signal charge. The second signal charge is transmitted from the second pixel electrode 103 to the second charge storage unit FD2 via the second transmission path 135.

[0176] A portion of the charges generated by the photoelectric conversion film 110 is captured by the auxiliary electrode 104. As a result, it is difficult for the charges that should be captured by a certain first pixel electrode 102 to be captured by the adjacent first pixel electrode 102. It is difficult for the charges that should be captured by a certain second pixel electrode 103 to be captured by the adjacent second pixel electrode 103. In addition, it is difficult for the charges that should be captured by a certain first pixel electrode 102 to be captured by the adjacent second pixel electrode 103, or for the charges that should be captured by a certain second pixel electrode 103 to be captured by the adjacent first pixel electrode 102. As a result, noise such as color mixing between adjacent pixels can be suppressed. Specifically, the auxiliary electrode 104 is connected to, for example, a voltage supply circuit or ground potential that is omitted from the figure, and is maintained at a specified potential. In the case of using holes as signal charges, by making the potential of the auxiliary electrode 104 lower than the potential of the opposing electrode 111, the signal charges can be pulled closer to the auxiliary electrode 104. The potential of the auxiliary electrode 104 is a fixed potential in the present embodiment, but may be a variable potential.

[0177] exist Figure 3 In the example of , the 4th wiring layer WL4 and the 5th wiring layer WL5 are used to form a specific capacitor element 204. Specifically, the specific capacitor element 204 includes a specified electrode 204a, a specific electrode 204b, and a dielectric located between the specified electrode 204a and the specific electrode 204b. The specified electrode 204a includes a plurality of wirings electrically connected to the first node FDA. Specifically, the specified electrode 204a can be a plurality of wirings included in the first transmission path 125. The specific electrode 204b includes a plurality of wirings electrically connected to the specific node RD. The dielectric includes a portion of a plurality of insulating layers 3.

[0178] exist Figure 3 In the embodiment, one of the source and drain of the first reset transistor 202 is a diffusion layer constituting the first charge accumulation unit FD1, and the other is a diffusion layer DL1. The diffusion layer DL1 is electrically connected to the electrode 203a of the first capacitor 203 via the first wiring layer WL1. The diffusion layer DL1 and the electrode 203a are electrically connected to the specific node RD. In addition, one of the source and drain of the second reset transistor 217 is a diffusion layer constituting the second charge accumulation unit FD2, and the other is a diffusion layer DL2.

[0179] A part of the insulating layer 3f is inserted between the adjacent first pixel electrode 102, second pixel electrode 103, and auxiliary electrode 104. The first pixel electrode 102, second pixel electrode 103, and auxiliary electrode 104 each have a uniform film thickness and a planarized upper surface.

[0180] The photoelectric conversion film 110 is composed of a photoelectric conversion material that generates electric charge according to the intensity of the received light. The photoelectric conversion material may include at least one of an organic material and an inorganic material. The organic material may be an organic semiconductor material. The organic semiconductor material may include at least one of a p-type organic semiconductor and an n-type organic semiconductor. The inorganic material is, for example, amorphous silicon. The photoelectric conversion film 110 may also be a mixed film of organic donor molecules and acceptor molecules, a mixed film of semiconductor-type carbon nanotubes and acceptor molecules, or a film containing quantum dots. The photoelectric conversion film 110 may also be a metal oxide film. The metal oxide film is, for example, a copper oxide (CuO) film. These descriptions of the material of the photoelectric conversion film 110 can also be applied to the first photoelectric conversion film 110a and the second photoelectric conversion film 110b.

[0181] The counter electrode 111 may include a transparent conductive material. The transparent conductive material is, for example, a transparent oxide conductive material. The transparent oxide conductive material is, for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The above description of the material of the counter electrode 111 can also be applied to the first counter electrode 111a and the second counter electrode 111b.

[0182] The first pixel electrode 102 may include at least one of a metal material and a metal compound material. The metal material is, for example, copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), etc. The metal compound material is, for example, a compound of the metal materials listed above. The metal compound material may be a metal nitride. The metal nitride is, for example, titanium nitride (TiN). These descriptions of the material of the first pixel electrode 102 can also be applied to the second pixel electrode 103 and the auxiliary electrode 104.

[0183] The via plug 105v may include a conductive material. The conductive material is, for example, copper (Cu), tungsten (W), etc. The via plug 105v may be formed by embedding the conductive material into the insulating layer 3. These descriptions about the material of the via plug 105v can also be applied to the via plug 106v. The descriptions can also be applied to the via plugs vp1a, vp1b, vp1c, vp1d, vp1e, vp1f, vp1g, vp1h, vp1i, vp1j, vp1k, vp1m, vp1n, vp1p, vp1q, vp1r, vp2a, vp2b, vp2c, vp2d, vp2e, vp2f, vp2 g, vp2h, vp2i, vp2j, vp2k, vp2m, vp2n, vp2s, vp2t, vp3a, vp3b, vp3d, vp3e, vp3h, vp3j, vp3s, vp3t, vp4a, vp4b, vp4d, vp4e, vp5a, vp5d, vp6a and vp6d and other via plugs.

[0184] The wiring included in the wiring layer WL may include a conductive material. The conductive material is, for example, copper (Cu), tungsten (W), etc. In this context, the wiring included in the wiring layer WL may be the first wiring, the second wiring, the first signal wiring, the second signal wiring, at least one of a plurality of wirings, etc., which will be described later.

[0185] The contact plug 105c may be polysilicon doped with impurities. The impurities are phosphorus, boron, etc. The contact plug 105c may be formed by embedding such a material into the insulating layer 3. These descriptions about the material of the contact plug 105c can also be applied to the contact plug 106c. The description can also be applied to other contact plugs such as the contact plugs cpa1, cpa2, cpa3, cpb, cpc, cpd1, cpd2, cpe1, cpe2, cpe3, cpe4, cpf, cpg, cph, cpi, cpj, cpk, cpp, cpq, and cpr described later.

[0186] The first charge storage portion FD1 may include an impurity of the same conductivity type as the impurity included in the contact plug 105c. The second charge storage portion FD2 may include an impurity of the same conductivity type as the impurity included in the contact plug 106c.

[0187] The semiconductor substrate 2 includes, for example, silicon (Si). The plurality of insulating layers 3 include, for example, silicon dioxide (SiO 2 ). The insulating layer 3a, the insulating layer 3b, the insulating layer 3c, the insulating layer 3d, the insulating layer 3e, and the insulating layer 3f include, for example, silicon dioxide.

[0188] In addition, the number of insulating layers 3 can be set arbitrarily and is not limited to Figure 3 The same is true for the number of wiring layers WL.

[0189] The first unit 100a may also have Figure 2 The second unit 100b may also have a structure different from the structure of Figure 2 The structure is different from the structure.

[0190] Figure 7 This is a circuit diagram of another example of the pixel 100 according to the first embodiment.

[0191] exist Figure 7 In the structure of FIG. 1 , the power supply wiring 209u is shared by both the first unit 100a and the second unit 100b.

[0192] exist Figure 7 In the structure of , the power supply wiring 209u is electrically connected to the power supply node VR. The power supply node VR is electrically connected to one of the source and drain of the band control transistor 207, the other of the source and drain of the second reset transistor 217, the other of the source and drain of the first amplifier transistor 205, and the other of the source and drain of the second amplifier transistor 215.

[0193] During the signal readout period, the power supply potential VDD is applied to the other of the source and drain of the first amplifier transistor 205 via the power supply wiring 209u. In this potential application state, as schematically indicated by the dotted arrow ARs1, the first electrical signal output from the terminal on the first selection transistor 206 side of the source and drain of the first amplifier transistor 205 sequentially flows through the first selection transistor 206 and the first vertical signal line 208a. In this way, the first electrical signal based on the first signal charge generated by the first photoelectric conversion unit 120 is read out.

[0194] During the signal readout period, the power supply potential VDD is applied to the other of the source and drain of the second amplifier transistor 215 via the power supply wiring 209u. In this potential application state, as schematically indicated by the dotted arrow ARs2, the second electrical signal output from the terminal on the second selection transistor 216 side of the source and drain of the second amplifier transistor 215 sequentially flows through the second selection transistor 216 and the second vertical signal line 208b. In this way, the second electrical signal based on the second signal charge generated by the second photoelectric conversion unit 130 is read out.

[0195] During the feedback period, as schematically indicated by a dotted arrow ARf1, the first electrical signal output from the terminal on the opposite side of the first selection transistor 206 of the source and the drain of the first amplifier transistor 205 is negatively fed back to the capacitance of the first node FDA via the band control transistor 207 and the specific capacitor 204. Thus, the kTC noise generated when the first reset transistor 202 is turned off is negatively fed back to the capacitance of the first node FDA.

[0196] During the feedback period, as schematically indicated by a dotted arrow ARf2, the second electrical signal output from the terminal on the opposite side of the second selection transistor 216 among the source and the drain of the second amplifier transistor 215 is negatively fed back to the capacitance of the second node FDB via the second reset transistor 217. Thus, the kTC noise generated when the second reset transistor 217 is turned off is negatively fed back to the capacitance of the second node FDB.

[0197] In addition, Figure 7In the circuit, the structure used to realize the signal readout period and the feedback period is not particularly limited. For example, by switching the control potential applied to the pixel 100, the signal readout period and the feedback period can be realized. Specifically, by switching the control potential applied to the pixel 100, it is possible to switch, with respect to the first unit 100a, whether to read the signal as shown by the dotted arrow ARs1 or to perform negative feedback of the signal as shown by the dotted arrow ARf1. In addition, by switching the control potential applied to the pixel 100, it is possible to switch, with respect to the second unit 100b, whether to read the signal as shown by the dotted arrow ARs2 or to perform negative feedback of the signal as shown by the dotted arrow ARf2. Regarding the switching of the control potential applied to the pixel 100, please refer to, for example, Patent Document 3 and Patent Document 4.

[0198] There are two types of power wiring 209u. The first type of power wiring 209u is referred to as power wiring 209x, and the second type of power wiring 209u is referred to as power wiring 209y. The power wiring 209x is electrically connected to the first unit 100a and the second unit 100b of the pixel 100 on one side of the odd-numbered row and the even-numbered row. The power wiring 209y is electrically connected to the first unit 100a and the second unit 100b of the pixel 100 on the other side of the odd-numbered row and the even-numbered row. Both the power wiring 209x and the power wiring 209y are wirings to which the power supply potential VDD can be applied, but are electrically separated from each other.

[0199] exist Figure 7 In the structure of , there are two types of the first vertical signal line 208a. The first type of the first vertical signal line 208a is expressed as a first vertical signal line 208ax, and the second type of the first vertical signal line 208a is expressed as a first vertical signal line 208ay. ​​The first vertical signal line 208ax is electrically connected to the first unit 100a of the pixel 100 on one side of the odd row and the even row. The first vertical signal line 208ay is electrically connected to the first unit 100a of the pixel 100 on the other side of the odd row and the even row. The first vertical signal line 208ax and the first vertical signal line 208ay are both wirings through which the first electrical signal can flow, but are electrically separated from each other.

[0200] exist Figure 7In the structure of FIG. 1 , there are two types of second vertical signal lines 208b. The first type of second vertical signal line 208b is expressed as a second vertical signal line 208bx, and the second type of second vertical signal line 208b is expressed as a second vertical signal line 208by. The second vertical signal line 208bx is electrically connected to the second unit 100b of the pixel 100 on one side of the odd row and the even row. The second vertical signal line 208by is electrically connected to the second unit 100b of the pixel 100 on the other side of the odd row and the even row. The second vertical signal line 208bx and the second vertical signal line 208by are both wirings through which the second electrical signal can flow, but are electrically separated from each other.

[0201] exist Figure 7 In the structure of FIG. 1 , with respect to the first unit 100a of the pixel 100 on one side of the odd-numbered row and the even-numbered row, the power supply potential VDD is supplied to the first amplifier transistor 205 via the power supply wiring 209x, and the first electrical signal from the first amplifier transistor 205 is output to the first vertical signal line 208ax. With respect to the first unit 100a of the pixel 100 on the other side of the odd-numbered row and the even-numbered row, the power supply potential VDD is supplied to the first amplifier transistor 205 via the power supply wiring 209y, and the first electrical signal from the first amplifier transistor 205 is output to the first vertical signal line 208ay. ​​With respect to the second unit 100b of the pixel 100 on one side of the odd-numbered row and the even-numbered row, the power supply potential VDD is supplied to the second amplifier transistor 215 via the power supply wiring 209x, and the second electrical signal from the second amplifier transistor 215 is output to the second vertical signal line 208bx. Regarding the second unit 100b of the other pixel 100 of the odd row and the even row, the power supply potential VDD is supplied to the second amplifier transistor 215 via the power supply wiring 209y, and the second electric signal from the second amplifier transistor 215 is output to the second vertical signal line 208by.

[0202] You can also Figure 2 or Figure 7 The pixel 100 is changed to,

[0203] The first unit 100a includes a first overflow transistor 231; and

[0204] The second unit 100 b includes a second overflow transistor 232 .

[0205] Fig. 8A Yes Figure 2 The circuit diagram of the circuit after applying the overflow transistor. Figure 8B Yes Figure 7 The circuit diagram of the circuit after applying the overflow transistor.

[0206] exist Fig. 8A and Figure 8BIn the first cell 100 a , the gate of the first overflow transistor 231 and one of the source and drain of the first overflow transistor 231 are electrically connected to the first node FDA. The other of the source and drain of the first overflow transistor 231 is electrically connected to the first discharge line 235 .

[0207] When the potential of the first node FDA reaches the first threshold potential, the first overflow transistor 231 is turned on. By being turned on, the excess charge accumulated in the capacitance of the first node FDA is discharged to the first discharge line 235 via the first overflow transistor 231. This can prevent the first unit 100a from being burned out or other failures.

[0208] exist Fig. 8A and Figure 8B In the second cell 100 b , the gate of the second overflow transistor 232 and one of the source and drain of the second overflow transistor 232 are electrically connected to the second node FDB. The other of the source and drain of the second overflow transistor 232 is electrically connected to the second discharge line 236 .

[0209] When the potential of the second node FDB reaches the second threshold potential, the second overflow transistor 232 is turned on. By being turned on, the excess charge accumulated in the capacitor of the second node FDB is discharged to the second discharge line 236 via the second overflow transistor 232. This prevents the second cell 100b from being burned out.

[0210] The first overflow transistor 231 and the first reset transistor 202 may share the first charge accumulation portion FD1. The second overflow transistor 232 and the second reset transistor 217 may share the second charge accumulation portion FD2. Alternatively, the first unit 100a may include the first overflow transistor 231, and the second unit 100b may not include the second overflow transistor 232. Alternatively, the first unit 100a may not include the first overflow transistor 231, and the second unit 100b may include the second overflow transistor 232.

[0211] You can Figure 2 , Figure 7 , Fig. 8A or Figure 8B The pixel 100 is changed to,

[0212] The first unit 100a includes a first photoelectric conversion part 241 instead of the first photoelectric conversion part 120;

[0213] The first unit 100a includes a first transfer transistor 245 sandwiched between the first photoelectric conversion section 241 and the first charge storage section FD1;

[0214] The second unit 100b includes a second photoelectric conversion part 242 instead of the second photoelectric conversion part 130;

[0215] The second unit 100b includes a second transfer transistor 246 sandwiched between the second photoelectric conversion section 242 and the second charge storage section FD2. Here, the first photoelectric conversion section 241 and the second photoelectric conversion section 242 are photodiodes, respectively. The first photoelectric conversion section 241 and the second photoelectric conversion section 242 are provided on the semiconductor substrate 2. Fig. 9 1 is an explanatory diagram of a circuit structure using a photoelectric conversion unit as a photodiode. Fig. 9 In Figure 2 The circuit structure of the circuit structure is obtained by applying this change.

[0216] exist Fig. 9 In the first unit 100a, the first photoelectric conversion unit 241 and the first charge accumulation unit FD1 are connected via the first transfer transistor 245. When the first transfer transistor 245 is turned on, the first signal charge is transferred from the first photoelectric conversion unit 241 to the first charge accumulation unit FD1. In the second unit 100b, the second photoelectric conversion unit 242 and the second charge accumulation unit FD2 are connected via the second transfer transistor 246. When the second transfer transistor 246 is turned on, the second signal charge is transferred from the second photoelectric conversion unit 242 to the second charge accumulation unit FD2.

[0217] The first transfer transistor 245 and the first reset transistor 202 may share the first charge storage unit FD1. The second transfer transistor 246 and the second reset transistor 217 may share the second charge storage unit FD2.

[0218] Refer to the following content FIG. 10A to FIG. 10I , describing the structure of each layer of the imaging device 1.

[0219] · Fig. 10A is a schematic structural diagram of the gate wiring layer WLG when viewed from above;

[0220] · Fig. 10B is a schematic structural diagram of the first wiring layer WL1 when viewed from above;

[0221] · Fig. 10C This is a schematic diagram of the structure of the MIM-level MS when viewed from above;

[0222] · Fig. 10D is a schematic structural diagram of the second wiring layer WL2 when viewed from above;

[0223] · Fig.10E is a schematic structural diagram of the third wiring layer WL3 when viewed from above;

[0224] · Fig.10F is a schematic structural diagram of the fourth wiring layer WL4 when viewed from above;

[0225] · Figure 10G is a schematic structural diagram of the fifth wiring layer WL5 when viewed from above;

[0226] · Fig. 10H is a schematic structural diagram of the sixth wiring layer WL6 when viewed from above;

[0227] · Fig.10I 1 is a schematic diagram of the structure of the pixel electrode layer ES when viewed from above. FIG. 10A to FIG. 10I The structure corresponds to Figure 7 However, as long as there is no particular contradiction, FIG. 10A to FIG. 10I part or all of the structure of Figure 2 The structure can also be combined with Fig. 8A The structure can also be combined with Figure 8B The structure can also be combined with Fig. 9 The structure is combined.

[0228] Regarding the gate wiring layer WLG Fig. 10A middle,

[0229] The gate 202g is the gate of the first reset transistor 202;

[0230] The gate 217g is the gate of the second reset transistor 217;

[0231] The gate 205g is the gate of the first amplifying transistor 205;

[0232] The gate 215g is the gate of the second amplifying transistor 215;

[0233] The gate 206g is the gate of the first selection transistor 206;

[0234] The gate 216g is the gate of the second selection transistor 216;

[0235] The gate 207 g is the gate of the band control transistor 207 .

[0236] In the present embodiment, the gate 202g, the gate 217g, the gate 205g, the gate 215g, the gate 206g, and the gate 216g are N-type polysilicon.

[0237] The control signal supplied to the gate can be described as follows:

[0238] The first reset control signal is supplied from the row scanning circuit 310 to the gate 202g via the first reset control line RSTiA, thereby controlling the on / off state of the first reset transistor 202:

[0239] The second reset control signal is supplied from the row scanning circuit 310 to the gate 217g via the second reset control line RSTiB, thereby controlling the on / off state of the second reset transistor 217:

[0240] The first selection control signal is supplied from the row scanning circuit 310 to the gate 206g via the first address control line SELiA, thereby controlling the on / off state of the first selection transistor 206:

[0241] The second selection control signal is supplied from the row scanning circuit 310 to the gate 216g via the second address control line SELiB, thereby controlling the on / off state of the second selection transistor 216:

[0242] The on / off state of the band control transistor 207 is controlled by supplying a band control signal to the gate 207 g from the row scanning circuit 310 via the feedback control line FBi.

[0243] These control signals are potential signals.

[0244] in addition, Fig. 9 In the example,

[0245] The first transfer control signal is supplied from the row scanning circuit 310 to the gate of the first transfer transistor 245 via the first transfer control line TRiA, thereby controlling the on / off state of the first transfer transistor 245:

[0246] The second transfer transistor 246 is controlled to be turned on / off by supplying a second transfer control signal from the row scanning circuit 310 to the gate of the second transfer transistor 246 via the second transfer control line TRiB.

[0247] These control signals are potential signals.

[0248] exist Fig. 10A In FIG. 1 , a plurality of diffusion layers located in the semiconductor substrate 2 are also depicted. Fig. 10A middle,

[0249] The first charge storage unit FD1 is a diffusion layer serving as one of the source and drain of the first reset transistor 202;

[0250] The diffusion layer DL1 is a diffusion layer that serves as the other of the source and the drain of the first reset transistor 202 and one of the source and the drain of the band control transistor 207;

[0251] The second charge storage unit FD2 is a diffusion layer serving as one of the source and drain of the second reset transistor 217;

[0252] The diffusion layer DL2 is a diffusion layer serving as the other of the source and the drain of the second reset transistor 217;

[0253] The diffusion layer DL3 is a diffusion layer serving as the other of the source and the drain of the band control transistor 207;

[0254] The diffusion layer DL4 is a diffusion layer that also serves as one of the source and drain of the first amplification transistor 205 and one of the source and drain of the first selection transistor 206;

[0255] The diffusion layer DL5 is a diffusion layer serving as the other of the source and the drain of the first selection transistor 206;

[0256] The diffusion layer DL6 is a diffusion layer that also serves as one of the source and drain of the second amplification transistor 215 and one of the source and drain of the second selection transistor 216;

[0257] The diffusion layer DL7 is a diffusion layer serving as the other of the source and the drain of the second selection transistor 216;

[0258] The diffusion layer DL8 is a diffusion layer that also serves as the other of the source and the drain of the first amplifier transistor 205 and the other of the source and the drain of the second amplifier transistor 215 .

[0259] like Fig. 10B As shown, the first wiring layer WL1 includes a wiring W1a, a wiring W1b, a wiring W1c, a wiring W1d, a wiring W1e, a wiring W1f, a wiring W1g, a wiring W1h, a wiring W1i, a wiring W1j, and a wiring W1k.

[0260] exist Fig. 10A Also depicted are contact plugs (hereinafter sometimes simply referred to as plugs) cpa1, cpa2, cpb, cpc, cpd1, cpd2, cpe1, cpe2, cpe3, cpe4, cpf, cpg, cph, cpi, cpj, and cpk.

[0261] According to the gate wiring layer WLG Fig. 10A And about the first wiring layer WL1 Fig. 10B Understandably,

[0262] The plug cpa1 electrically connects the first charge storage unit FD1 and the wiring W1a;

[0263] Plug cpa2 electrically connects gate 205g and wiring W1a;

[0264] The plug cpb electrically connects the diffusion layer DL1 and the wiring W1b;

[0265] The plug cpc electrically connects the gate 202g and the wiring W1c;

[0266] The plug cpd1 electrically connects the second charge storage unit FD2 and the wiring W1d;

[0267] Plug cpd2 electrically connects gate 215g and wiring W1d;

[0268] Plug cpe1 electrically connects the diffusion layer DL2 and the wiring W1e;

[0269] Plug cpe2 electrically connects the diffusion layer DL3 and the wiring W1e;

[0270] Plugs cpe3 and cpe4 are electrically connected to the diffusion layer DL8 and the wiring W1e;

[0271] The plug cpf electrically connects the gate 217g and the wiring W1f;

[0272] The plug cpg electrically connects the gate 207g and the wiring W1g;

[0273] The plug cph electrically connects the diffusion layer DL5 and the wiring W1h;

[0274] Plug cpi electrically connects gate 206g and wiring W1i;

[0275] The plug cpj electrically connects the diffusion layer DL7 and the wiring W1j;

[0276] The plug cpk electrically connects the gate 216g and the wiring W1k.

[0277] The contact plug cpa1 is the contact plug 105c. The contact plug cpd1 is the contact plug 106c.

[0278] As described above, the first capacitor 203 includes the electrode 203a closer to the semiconductor substrate 2 and the electrode 203b farther from the semiconductor substrate 2. The second capacitor 213 includes the electrode 213a closer to the semiconductor substrate 2 and the electrode 213b farther from the semiconductor substrate 2. Fig. 10C In the embodiment, the electrodes 203b and 213b are shaded. As described above, in the present embodiment, the first capacitor element 203 and the second capacitor element 213 have a groove structure. The electrode 203a has a plurality of protrusions 203p that are derived from the groove structure and protrude toward the semiconductor substrate 2. The electrode 213a has a plurality of protrusions 213p that are derived from the groove structure and protrude toward the semiconductor substrate 2. Fig. 10C In FIG. 1 , the protrusion 203p and the protrusion 213p are indicated by dotted lines.

[0279] exist Fig. 10B, via plugs (hereinafter sometimes simply referred to as plugs) vp1m, vp1n, vp1a, vp1b, vp1c, vp1d, vp1e, vp1f, vp1g, vp1h, vp1i, vp1j, and vp1k are also depicted.

[0280] According to the first wiring layer WL1 Fig. 10B And about MIM level MS Fig. 10C Understandably,

[0281] The plug vp1m electrically connects the wiring W1b and the protrusion 203p;

[0282] The plug vp1n electrically connects the wiring W1d and the protruding portion 213p.

[0283] In addition, Fig. 10C In FIG. 1 , the positions of the plug vp1m and the plug vp1n are shown by the dotted line. The electrode 203a is electrically connected to the specific node RD through the plug vp1m. The electrode 213a is electrically connected to the second node FDB through the plug vp1n.

[0284] like Fig. 10D As shown, the second wiring layer WL2 includes wiring W2a, wiring W2b, wiring W2c, wiring W2d, wiring W2e, wiring W2f, wiring W2g, wiring W2h, wiring W2i, wiring W2j, wiring W2k, wiring W2s, and wiring W2t.

[0285] According to the first wiring layer WL1 Fig. 10B And about the second wiring layer WL2 Fig. 10D Understandably,

[0286] Plug vp1a electrically connects the wiring W1a and the wiring W2a;

[0287] Plug vp1b electrically connects the wiring W1b and the wiring W2b;

[0288] Plug vp1c electrically connects the wiring W1c and the wiring W2c;

[0289] Plug vp1d electrically connects the wiring W1d and the wiring W2d;

[0290] Plug vp1e electrically connects wiring W1e and wiring W2e;

[0291] Plug vp1f electrically connects the wiring W1f and the wiring W2f;

[0292] Plug vp1g electrically connects the wiring W1g and the wiring W2g;

[0293] Plug vp1h electrically connects the wiring W1h and the wiring W2h;

[0294] Plug vp1i electrically connects wiring W1i and wiring W2i;

[0295] Plug vp1j electrically connects wiring W1j and wiring W2j;

[0296] The plug vp1k electrically connects the wiring W1k and the wiring W2k.

[0297] The via plug vp1a is the via plug 105v, and the via plug vp1d is the via plug 106v.

[0298] exist Fig. 10D Also depicted are interlayer plugs (hereinafter sometimes simply referred to as plugs) vp2m, vp2n, vp2a, vp2b, vp2c, vp2d, vp2e, vp2f, vp2g, vp2h, vp2i, vp2j, vp2k, vp2s, and vp2t.

[0299] According to the second wiring layer WL2 Fig. 10D And about MIM level MS Fig. 10C Understandably,

[0300] The plug vp2m is electrically connected to the wiring W2m and the electrode 203b;

[0301] The plug vp2n is electrically connected to the wiring W2n and the electrode 213b.

[0302] like Fig.10E As shown, the third wiring layer WL3 includes wiring W3a, wiring W3b, wiring W3c, wiring W3d, wiring W3e, wiring W3h, wiring W3i, wiring W3j, wiring W3s, wiring W3t, a first reset control line RSTiA, a second reset control line RSTiB, a feedback control line FBi, a first address control line SELiA, and a second address control line SELiB. In addition, as described above, the first reset control line RSTiA is provided corresponding to each row of the pixel array 10. Fig.10E In FIG. 1 , two rows of first reset control lines RSTiA are shown.

[0303] According to the second wiring layer WL2 Fig. 10D And about the third wiring layer WL3 Fig.10E Understandably,

[0304] Plug vp2a electrically connects the wiring W2a and the wiring W3a;

[0305] Plug vp2b electrically connects the wiring W2b and the wiring W3b;

[0306] Plug vp2c electrically connects the wiring W2c and the wiring W3c;

[0307] Plug vp2d electrically connects the wiring W2d and the wiring W3d;

[0308] Plug vp2e electrically connects the wiring W2e and the wiring W3e;

[0309] Plug vp2f electrically connects the wiring W2f and the second reset control line RSTiB;

[0310] Plug vp2g electrically connects wiring W2g and feedback control line FBi;

[0311] Plug vp2h electrically connects the wiring W2h and the wiring W3h;

[0312] Plug vp2i electrically connects wiring W2i and wiring W3i;

[0313] Plug vp2j electrically connects wiring W2j and wiring W3j;

[0314] Plug vp2k electrically connects the wiring W2k and the second address control line SELiB;

[0315] Plug vp2s electrically connects the wiring W2s and the wiring W3s;

[0316] The plug vp2t electrically connects the wiring W2t and the wiring W3t.

[0317] The via plug vp2a is the via plug 105v. The via plug vp2d is the via plug 106v. The wiring W3c is electrically connected to the first reset control line RSTiA. The wiring W3i is electrically connected to the first address control line SELiA.

[0318] exist Fig.10E , via plugs (hereinafter sometimes simply referred to as plugs) vp3a, vp3b, vp3d, vp3e, vp3h, vp3j, vp3s, and vp3t are also depicted.

[0319] like Fig.10F As shown, the fourth wiring layer WL4 includes wiring W4a, wiring W4b, wiring W4d, wiring W4e, the first vertical signal line 208ax, the first vertical signal line 208ay, the second vertical signal line 208bx, the second vertical signal line 208by, the first capacitor control line TPA and the second capacitor control line TPB.

[0320] According to the third wiring layer WL3 Fig.10E And about the 4th wiring layer WL4 Fig.10F Understandably,

[0321] Plug vp3a electrically connects the wiring W3a and the wiring W4a;

[0322] Plug vp3b electrically connects the wiring W3b and the wiring W4b;

[0323] Plug vp3d electrically connects the wiring W3d and the wiring W4d;

[0324] Plug vp3e electrically connects wiring W3e and wiring W4e;

[0325] The plug vp3h electrically connects the wiring W3h and the first vertical signal line 208ax;

[0326] The plug vp3j electrically connects the wiring W3j and the second vertical signal line 208bx;

[0327] The plug vp3s electrically connects the wiring W3s and the first capacitance control line TPA;

[0328] The plug vp3t electrically connects the wiring W3t and the second capacitance control line TPB.

[0329] The via plug vp3a is the via plug 105v, and the via plug vp3d is the via plug 106v.

[0330] The position of the via plug vp3h is different between the pixels 100 in the odd-numbered rows and the pixels 100 in the even-numbered rows. Specifically, Fig.10E The position of the via plug vp3h in the pixel 100 of one of the odd-numbered rows and the even-numbered rows is a position at which the wiring W3h is electrically connected to the first vertical signal line 208ax. The via plug vp3h is connected to the pixel 100 of the other of the odd-numbered rows and the even-numbered rows. Fig.10E As indicated by the dotted line, the wiring W3h is located on the right side in the figure, thereby electrically connecting the wiring W3h to the first vertical signal line 208ay.

[0331] The position of the via plug vp3j is different between the pixels 100 in the odd-numbered rows and the pixels 100 in the even-numbered rows. Specifically, Fig.10E The position of the via plug vp3j in the pixel 100 of one of the odd-numbered rows and the even-numbered rows is a position at which the wiring W3j is electrically connected to the second vertical signal line 208bx. The via plug vp3j is connected to the pixel 100 of the other of the odd-numbered rows and the even-numbered rows. Fig.10E As indicated by the dotted line, the wiring W3j is located on the right side of the figure, thereby electrically connecting the wiring W3j to the second vertical signal line 208by.

[0332] exist Fig.10F , via plugs (hereinafter sometimes simply referred to as plugs) vp4a, vp4b, vp4d, and vp4e are also depicted.

[0333] like Figure 10G As shown, the fifth wiring layer WL5 includes a wiring W5a, a wiring W5b, a wiring W5d, a wiring W5e, a power supply wiring 209x, and a power supply wiring 209y.

[0334] According to the fourth wiring layer WL4 Fig.10F And about the 5th wiring layer WL5 Figure 10G Understandably,

[0335] Plug vp4a electrically connects the wiring W4a and the wiring W5a;

[0336] Plug vp4b electrically connects the wiring W4b and the wiring W5b;

[0337] Plug vp4d electrically connects the wiring W4d and the wiring W5d;

[0338] Plug vp4e electrically connects the wiring W4e and the wiring W5e.

[0339] The via plug vp4a is the via plug 105v. The via plug vp4d is the via plug 106v. The wiring W5e is electrically connected to the power supply wiring 209x.

[0340] The position of the wiring W5e is different between the pixels 100 in the odd-numbered rows and the pixels 100 in the even-numbered rows. Specifically, Figure 10G The position of the wiring W5e in the pixel 100 of one of the odd-numbered and even-numbered rows is the position at which the plug vp4e is electrically connected to the power supply wiring 209x. The wiring W5e is connected to the pixel 100 of the other of the odd-numbered and even-numbered rows. Figure 10G As shown by the dotted line, the plug vp4e is located on the right side of the figure and is electrically connected to the power supply wiring 209y.

[0341] according to Fig.10F and Figure 10G It can be understood that the specific capacitor element 204 is formed in a manner that straddles the third wiring layer WL3 and the fourth wiring layer WL4. Specifically, the specified electrode 204a includes the wiring W4a and the wiring W5a. The specific electrode 204b includes the wiring W4b and the wiring W5b. The dielectric of the specific capacitor element 204 is located between the specified electrode 204a and the specific electrode 204b. The dielectric includes the portion of the plurality of insulating layers 3 located in the third wiring layer WL3 and the fourth wiring layer WL4.

[0342] exist Figure 10G In the figure, via plugs (hereinafter sometimes simply referred to as plugs) vp5a and vp5d are also depicted.

[0343] like Fig. 10H As shown, the sixth wiring layer WL6 includes a wiring W6a and a wiring W6d.

[0344] According to the fifth wiring layer WL5 Figure 10G And about the 6th wiring layer WL6 Fig. 10H Understandably,

[0345] Plug vp5a electrically connects the wiring W5a and the wiring W6a;

[0346] The plug vp5d electrically connects the wiring W5d and the wiring W6d.

[0347] The via plug vp5a is the via plug 105v, and the via plug vp5d is the via plug 106v.

[0348] exist Fig. 10H In the figure, interlayer plugs (hereinafter sometimes simply referred to as plugs) vp6a and vp6d are also depicted. Fig.10I As shown, the pixel electrode level ES includes a first pixel electrode 102 , a second pixel electrode 103 and an auxiliary electrode 104 .

[0349] According to the sixth wiring layer WL6 Fig. 10H and Fig.10I Understandably,

[0350] The plug vp6a electrically connects the wiring W6a and the first pixel electrode 102;

[0351] The plug vp6d electrically connects the wiring W6d and the second pixel electrode 103 .

[0352] The via plug vp6a is the via plug 105v, and the via plug vp6d is the via plug 106v.

[0353] Reference FIG. 11A to FIG. 11C The following content explains Figure 8B The structure of each level corresponds to the structure of the structure.

[0354] · Fig.11A is with Figure 8B A schematic structural diagram of the gate wiring layer WLG in a top view corresponding to the structure of

[0355] · Fig. 11B is with Figure 8B A schematic structural diagram of the first wiring layer WL1 in a top view corresponding to the structure of FIG.

[0356] · Fig. 11C is with Figure 8B Schematic diagram of the structure of the second wiring layer WL2 as viewed from above, corresponding to the structure of .

[0357] Regarding the gate wiring layer WLG Fig.11A middle,

[0358] The gate 231g is the gate of the first overflow transistor 231;

[0359] The gate 232 g is the gate of the second overflow transistor 232 .

[0360] In this embodiment, the gate 231g and the gate 232g may be P-type polysilicon.

[0361] exist Fig.11A middle,

[0362] The first charge storage unit FD1 is a diffusion layer that serves as one of the source and drain of the first reset transistor 202 and one of the source and drain of the first overflow transistor 231 ;

[0363] The second charge storage unit FD2 is a diffusion layer that serves as one of the source and drain of the second reset transistor 217 and one of the source and drain of the second overflow transistor 232;

[0364] The diffusion layer DL9 is a diffusion layer serving as the other of the source and the drain of the first overflow transistor 231 ;

[0365] The diffusion layer DL10 is a diffusion layer serving as the other of the source and the drain of the second overflow transistor 232 .

[0366] exist Fig.11A In the figure, contact plugs (hereinafter sometimes simply referred to as plugs) cpa3, cpp, cpq and cpr are also depicted.

[0367] For example, regarding the first wiring layer WL1 Fig. 11B As shown in FIG. 1 , the first wiring layer WL1 includes wirings W1p and W1r. Fig. 11B , via plugs (hereinafter sometimes simply referred to as plugs) vp1p, vp1q, and vp1r are also depicted.

[0368] For example, regarding the second wiring layer WL2 Fig. 11C As shown, the second wiring layer WL2 includes a wiring W2p, a wiring W2q, and a wiring W2r.

[0369] According to the gate wiring layer WLG Fig.11A , Regarding the first wiring layer WL1 Fig. 11B And about the second wiring layer WL2 Fig. 11C Understandably,

[0370] Plug cpa3 electrically connects gate 231g and wiring W2a;

[0371] The plug cpp electrically connects the diffusion layer DL9 and the wiring W1p;

[0372] The plug vp1p electrically connects the wiring W1p and the wiring W2p;

[0373] The plug cpq electrically connects the gate 232g and the wiring W2q;

[0374] Plug vp1q electrically connects wiring W1d and wiring W2q;

[0375] The plug cpr electrically connects the diffusion layer DL10 and the wiring W1r;

[0376] The plug vp1r electrically connects the wiring W1r and the wiring W2r.

[0377] The wiring W2p may be a wiring that electrically connects the other of the source and drain of the first overflow transistor 231 to the first discharge line 235, or may be the first discharge line 235 itself. The wiring W2r may be a wiring that electrically connects the other of the source and drain of the second overflow transistor 232 to the second discharge line 236, or may be the second discharge line 236 itself.

[0378] Omitted for Figure 8B The MIM layer MS, the third wiring layer WL3, the fourth wiring layer WL4, the fifth wiring layer WL5, the sixth wiring layer WL6 and the pixel electrode layer ES corresponding to the structure are viewed from above. Figure 8B In the case of a structure, it is also possible to Figure 7 Corresponding FIG. 10A to FIG. 10I These levels are constructed with reference to the structure of . Appropriate changes such as adjustment of the size of the first capacitor element 203 and the second capacitor element 213 in the MIM level MS can be made.

[0379] Hereinafter, the non-limiting structure of the imaging device 1 will be further described.

[0380] The imaging device 1 includes a semiconductor substrate 2 and a pixel 100. The pixel 100 includes a first unit 100a, a second unit 100b, and an upper wiring layer. The sensitivity of the second unit 100b is lower than that of the first unit 100a. The upper wiring layer is located above the semiconductor substrate 2. The upper wiring layer includes a plurality of wirings. The first unit 100a includes a first photoelectric conversion unit 120, a first charge accumulation unit FD1, and a first wiring. The first photoelectric conversion unit 120 converts light into a first signal charge. The first charge accumulation unit FD1 is located in the semiconductor substrate 2. The first charge accumulation unit FD1 accumulates the first signal charge. The first charge accumulation unit FD1 is electrically connected to the first node FDA. The first wiring is located in the upper wiring layer. The first wiring is electrically connected to the first node FDA. The second unit 100b includes a second photoelectric conversion unit 130, a second charge accumulation unit FD2, and a second wiring. The second photoelectric conversion unit 130 converts light into a second signal charge. The second charge accumulation section FD2 is located in the semiconductor substrate 2. The second charge accumulation section FD2 accumulates the second signal charge. The second charge accumulation section FD2 is electrically connected to the second node FDB. The second wiring is located in the upper wiring layer. The second wiring is electrically connected to the second node FDB. The nodes electrically connected to the above-mentioned plurality of wirings are different from the first node FDA and the second node FDB.

[0381] In the upper wiring layer, the shortest distance between the first wiring and the plurality of wirings is the first distance L1. In the upper wiring layer, the shortest distance between the second wiring and the plurality of wirings is the second distance L2. The first distance L1 is larger than the second distance L2. According to this structure, it is easy to make the first distance L1 larger, and it is easy to suppress the coupling between the plurality of wirings and the first wiring. Therefore, the capacitance value of the first node FDA is difficult to include the capacitance value of the parasitic capacitance caused by the coupling. This is advantageous from the viewpoint of improving the conversion gain and reducing the noise in the first unit 100a. Obtaining such an advantageous effect in the first unit 100a having a relatively high sensitivity is suitable for realizing a high-quality camera device 1. Furthermore, in this structure, the second distance L2 is relatively small. Therefore, according to this structure, a high-quality camera device 1 can be realized while suppressing the size of the pixel 100.

[0382] Specifically, the first charge storage unit FD1 is a diffusion layer. The second charge storage unit FD2 is a diffusion layer. The first node FDA and the second node FDB are different nodes.

[0383] Specifically, the first distance L1 and the second distance L2 are distances in a cross section perpendicular to the thickness direction of the semiconductor substrate 2. This also applies to the third distance L3, the fifth distance L5, the sixth distance L6, the seventh distance L7, and the eighth distance L8 described later.

[0384] In one example, the upper wiring layer is Fig. 10BThe first wiring layer WL1 is shown. The first wiring is the wiring W1a. The first distance L1 is the shortest distance LA between the wiring W1a and the wiring W1c. The second wiring is the wiring W1d. The second distance L2 is the shortest distance LB between the wiring W1d and the wiring W1e.

[0385] In another example, the upper wiring layer is Fig.10E The third wiring layer WL3 is shown. The first wiring is the wiring W3a. The first distance L1 is the shortest distance LC between the wiring W3a and the first reset control line RSTiA. The second wiring is the wiring W3d. The second distance L2 is the shortest distance LD between the wiring W3d and the first address control line SELiA.

[0386] However, other examples may also be used. For example, the upper wiring layer may also be Fig. 10A The gate wiring layer WLG shown may also be Fig. 10D The second wiring layer WL2 shown in FIG. Fig.10F The fourth wiring layer WL4 shown can also be Figure 10G The fifth wiring layer WL5 shown can also be Fig. 10HThe sixth wiring layer WL6 is shown. The first wiring may be the gate 205g, the wiring W2a, the wiring W4a, the wiring W5a, or the wiring W6a. The second wiring may be the gate 215g, the wiring W2d, the wiring W4d, the wiring W5d, or the wiring W6d. The above-mentioned multiple wirings may include a wiring W1c, a wiring W1e, a wiring W1f, a wiring W1g, a wiring W1h, a wiring W1i, a wiring W1j, a wiring W1k, a wiring W1p, a wiring W1r, a wiring W2c, a wiring W2e, a wiring W2f, a wiring W2g, a wiring W2h, a wiring W2i, a wiring W2j, a wiring W2k, a wiring W2p, a wiring W2q, a wiring W2r, a wiring W2s, a wiring W2t, a wiring W3c, a wiring W3e, a wiring W3h, a wiring W3i, a wiring W3j, a wiring W3s, a wiring W3t, a first reset control line RSTiA, a second reset control line RS TiB, feedback control line FBi, first address control line SELiA, second address control line SELiB, wiring W4e, first vertical signal line 208ax, first vertical signal line 208ay, second vertical signal line 208bx, second vertical signal line 208by, first vertical signal line 208a, second vertical signal line 208b, first capacitor control line TPA, second capacitor control line TPB, wiring W5e, power supply wiring 209u, power supply wiring 209x, power supply wiring 209y, first feedback line 209a, second feedback line 209b, first discharge line 235, second discharge line 236, first transfer control line TRiA and second transfer control line TRiB.

[0387] In the description of the structure described later, there may be cases where specific examples of an upper wiring layer, a first wiring, a second wiring, a plurality of wirings, etc. are given, but similarly to the description of the above structure, these specific examples are not particularly limited.

[0388] The expression “the sensitivity of the second unit 100b is lower than the sensitivity of the first unit 100a” may be changed to “the area of ​​the second pixel electrode 103 of the second unit 100b when viewed from above is smaller than the area of ​​the first pixel electrode 102 of the first unit 100a when viewed from above”. The expression may also be changed to “the light-collecting area of ​​the second microlens 113b of the second unit 100b when viewed from above is smaller than the light-collecting area of ​​the first microlens 113a of the first unit 100a when viewed from above”.

[0389] The ratio L1 / L2 of the first distance L1 to the second distance L2 is, for example, 1.5 to 10. The ratio L1 / L2 may be 2 to 5.

[0390] The first distance L1 is, for example, not less than 100 nm and not more than 1000 nm. The first distance L1 may be, for example, not less than 200 nm and not more than 500 nm. The second distance L2 is, for example, not less than 50 nm and not more than 1000 nm. The second distance L2 may be, for example, not less than 100 nm and not more than 500 nm.

[0391] Pixel 100 includes the first capacitor wiring layer. The first capacitor wiring layer is located above the semiconductor substrate 2. The first capacitor wiring layer includes the first prescribed wiring and the first specific wiring. The first prescribed wiring is electrically connected to the first node FDA. The first specific wiring is electrically connected to the specific node RD. The first node FDA and the specific node RD are mutually different nodes. The first unit 100a includes a specific capacitor element 204. The specific capacitor element 204 includes a prescribed electrode 204a and a specific electrode 204b. The prescribed electrode 204a is electrically connected to the first node FDA. The specific electrode 204b is electrically connected to the specific node RD. The prescribed electrode 204a includes the first prescribed wiring. The specific electrode 204b includes the first specific wiring. In this structure, the electrode pair of the prescribed electrode 204a and the specific electrode 204b includes the wiring pair of the first prescribed wiring and the first specific wiring. Therefore, it is suitable to utilize the characteristics of the wiring pair structure to realize the specific capacitor element 204 with high precision and small capacitance value. The specific capacitor element 204 that realizes high precision can contribute to improving the precision of the capacitance value of the specific node RD. In addition, in this context, "high precision" means that the specific capacitor element 204 has a structure suitable for reducing the manufacturing deviation of the camera device 1 and the deviation of the capacitance value caused by the driving condition of the camera device 1. The capacitance value of the specific node RD is the capacitance value of the entire capacitor electrically connected to the specific node RD.

[0392] Pixel 100 includes the second capacitor wiring layer. The second capacitor wiring layer is located above the semiconductor substrate 2. The second capacitor wiring layer is located above or below the first capacitor wiring layer. The second capacitor wiring layer includes the second specified wiring and the second specific wiring. The second specified wiring is electrically connected to the first node FDA. The second specific wiring is electrically connected to the specific node RD. The specified electrode 204a includes the second specified wiring. The specific electrode 204b includes the second specific wiring. According to this structure, it is easy to improve the ratio of the capacitance value of the specific capacitor element 204 relative to the capacitance value of the specific node RD, and it is easy to improve the precision of the capacitance value of the specific node RD. Specifically, if the ratio of the component brought by the parasitic capacitance in the capacitance value of the specific node RD is higher, it is difficult to obtain the precision of the capacitance value of the specific node RD. However, according to this structure, it is easy to ensure the area of ​​the specified electrode 204a and the specific electrode 204b, and ensure the capacitance value of the specific capacitor element 204. Therefore, it is easy to improve the ratio of the capacitance value of the specific capacitor element 204 relative to the capacitance value of the specific node RD, and the precision of the capacitance value of the specific node RD is improved.

[0393] Regarding the first capacitor wiring layer and the second capacitor wiring layer, the specific capacitor element 204 includes a dielectric located between the predetermined electrode 204 a and the specific electrode 204 b. The dielectric may include at least a part of one insulating layer 3.

[0394] Regarding the first capacitor wiring layer and the second capacitor wiring layer, the first capacitor wiring layer may be the same as or different from the upper wiring layer. The first prescribed wiring may be the same as or different from the first wiring. The second capacitor wiring layer may be the same as or different from the upper wiring layer. The second prescribed wiring may be the same as or different from the first wiring.

[0395] Regarding the first capacitor wiring layer and the second capacitor wiring layer, in one example, the first capacitor wiring layer is Figure 10G The fifth wiring layer WL5 is shown. The first predetermined wiring is the wiring W5a. The first specific wiring is the wiring W5b. The second capacitor wiring layer is Fig.10F The fourth wiring layer WL4 is shown. The second predetermined wiring is the wiring W4a. The second specific wiring is the wiring W4b.

[0396] Regarding the first capacitor wiring layer and the second capacitor wiring layer, in another example, the first capacitor wiring layer is Fig.10F The fourth wiring layer WL4 shown in FIG. 1 is the wiring W4a. The first specific wiring is the wiring W4b. The second capacitor wiring layer is Figure 10G The fifth wiring layer WL5 is shown. The second predetermined wiring is the wiring W5a. The second specific wiring is the wiring W5b.

[0397] In the first capacitor wiring layer, the shortest distance between the first predetermined wiring and the first specific wiring is the third distance L3. The third distance L3 is smaller than the first distance L1. In one example, the third distance L3 is Figure 10G The shortest distance LE between the wiring W5a and the wiring W5b in the fifth wiring layer WL5 is shown in FIG. 3. The third distance L3 may be smaller than the second distance L2.

[0398] The ratio L3 / L1 of the third distance L3 to the first distance L1 is, for example, 0.1 to 0.67. The ratio L3 / L1 may be 0.2 to 0.5. The ratio L3 / L2 of the third distance L3 to the second distance L2 is, for example, 0.1 to 0.67. The ratio L3 / L2 may be 0.2 to 0.5.

[0399] The third distance L3 is, for example, not less than 100 nm and not more than 1000 nm. The third distance L3 may be not less than 200 nm and not more than 500 nm.

[0400] like Figure 10G As shown, in one example, in a cross section passing through the first capacitor wiring layer and perpendicular to the thickness direction of the semiconductor substrate 2, there is a straight line SL passing through the first part po1 of the first specific wiring, the specified part pp of the first specified wiring and the second part Po2 of the first specific wiring in sequence. According to this structure, it is easy to improve the ratio of the capacitance value of the specific capacitor element 204 relative to the capacitance value of the specific node RD, and it is easy to improve the precision of the capacitance value of the specific node RD. Specifically, if the ratio of the component brought by the parasitic capacitance in the capacitance value of the specific node RD is higher, it is difficult to obtain the precision of the capacitance value of the specific node RD. However, according to this structure, it is easy to ensure the capacitance value of the specific capacitor element 204. Therefore, it is easy to improve the ratio of the capacitance value of the specific capacitor element 204 relative to the capacitance value of the specific node RD, and the precision of the capacitance value of the specific node RD is improved.

[0401] Specifically, in the cross section passing through the first capacitor wiring layer and perpendicular to the thickness direction of the semiconductor substrate 2, no matter where the specified portion pp is set on the first specified wiring, there is a straight line SL passing through the first portion po1, the specified portion pp, and the second portion Po2 in sequence. According to this structure, it is easy to increase the ratio of the capacitance value of the specific capacitor element 204 to the capacitance value of the specific node RD, and it is easy to improve the accuracy of the capacitance value of the specific node RD.

[0402] The first unit 100a includes a first amplifier transistor 205 that generates a first electrical signal corresponding to the potential of the first charge storage unit FD1. The first electrical signal is negatively fed back to the first charge storage unit FD1 via the specific capacitor 204. According to this structure, the specific capacitor 204 can be used for negative feedback of the first electrical signal.

[0403] The imaging device 1 includes a power supply wiring 209u electrically connected to a power supply node VR, and the power supply node VR is different from the first node FDA, the second node FDB, and the specific node RD. The first unit 100a includes a first amplifier transistor 205. The first amplifier transistor 205 generates a first electrical signal corresponding to the potential of the first charge accumulation unit FD1. The power supply potential VDD is supplied to the first amplifier transistor 205 via the power supply wiring 209u. Figure 10G In the example of , in the first capacitor wiring layer, the first specific wiring is located between the power wiring 209u and the first predetermined wiring. According to this structure, the first specific wiring can function as a shield to suppress coupling between the power wiring 209u and the first predetermined wiring.

[0404] The statement "In the first capacitor wiring layer, the first specific wiring is located between the power wiring 209u and the first prescribed wiring" in the above structure is explained. Specifically, the statement means that in a cross section passing through the first capacitor wiring layer and perpendicular to the thickness direction of the semiconductor substrate 2, there is a straight line passing through the power wiring 209u, the first specific wiring, and the first prescribed wiring in sequence.

[0405] The first electrical signal is negatively fed back to the first charge accumulation unit FD1 via the specific capacitor element 204. The potential of the negatively fed back first electrical signal is applied to the power supply wiring 209u. According to this structure, even if the potential changes in the power supply wiring 209u due to the negative feedback of the first electrical signal, the influence on the capacitance of the first node FDA can be suppressed by the above-mentioned shielding effect. This is suitable for reducing the noise in the first unit 100a and realizing the high-quality imaging device 1.

[0406] As described above, in the first capacitor wiring layer, the shortest distance between the first prescribed wiring and the first specific wiring is the third distance L3. The first unit 100a includes the first capacitor element 203. The first capacitor element 203 has an electrode 203a and an electrode 203b. Electrode 203a is electrically connected to a specific node RD. Electrode 203b is electrically separated from electrode 203a. Electrode 203a is located between electrode 203b and semiconductor substrate 2. The shortest distance between electrode 203a and semiconductor substrate 2 is the fourth distance L4. The third distance L3 is smaller than the fourth distance L4. According to this structure, it is easy to improve the ratio of the capacitance value of the specific capacitor element 204 relative to the capacitance value of the specific node RD, so that the accuracy of the capacitance value of the specific node RD is improved. Specifically, in the first unit 100a related to this structure, there may be a parasitic capacitance between electrode 203a and semiconductor substrate 2. However, according to this structure, it is easy to improve the ratio of the capacitance value of the specific capacitor element 204 relative to the capacitance value of the parasitic capacitance. Therefore, it is easy to increase the ratio of the capacitance value of the specific capacitor 204 to the capacitance value of the specific node RD, thereby improving the accuracy of the capacitance value of the specific node RD.

[0407] The ratio L3 / L4 of the third distance L3 to the fourth distance L4 is, for example, 0.1 to 0.67. The ratio L3 / L4 may be 0.2 to 0.5.

[0408] The fourth distance L4 is, for example, not less than 100 nm and not more than 1000 nm. The fourth distance L4 may be not less than 200 nm and not more than 500 nm.

[0409] In one example, the third distance L3 is Figure 10G The shortest distance LE between the wiring W5a and the wiring W5b in the fifth wiring layer WL5 is shown in FIG. Figure 3 The shortest distance LF between the protruding portion 203 p and the semiconductor substrate 2 is shown. Specifically, the fourth distance L4 is a distance in a direction parallel to the thickness direction of the semiconductor substrate 2 .

[0410] The first unit 100a includes a first capacitor element 203 electrically connected to a specific node RD. The first capacitor element 203 is a MIM capacitor element. This structure is suitable for realizing a first capacitor element 203 with a large capacitance value. The first capacitor element 203 may also be a MOS (Metal Oxide Semiconductor) capacitor element. In this way, a first capacitor element 203 with a large capacitance value can also be realized.

[0411] The second unit 100b includes a second capacitor 213 electrically connected to the second node FDB. The second capacitor 213 is a MIM capacitor. This structure is suitable for realizing a second capacitor 213 with a large capacitance value. The second capacitor 213 may also be a MOS capacitor. In this way, a second capacitor 213 with a large capacitance value can also be realized.

[0412] The capacitance value of the specific capacitance element 204 is smaller than the capacitance value of the first capacitance element 203. The ratio of the capacitance value of the specific capacitance element 204 to the capacitance value of the first capacitance element 203 is, for example, 5% to 20%. The ratio may be 5% to 15%.

[0413] The capacitance value of the specific capacitance element 204 is smaller than the capacitance value of the second capacitance element 213. The ratio of the capacitance value of the specific capacitance element 204 to the capacitance value of the second capacitance element 213 is, for example, 5% to 20%. The ratio may be 5% to 15%.

[0414] In one example, the specific capacitor element 204 is formed across multiple wiring layers. The multiple wiring layers include, for example, the 4th wiring layer WL4 and the 5th wiring layer WL5. In addition, the specific capacitor element 204 is formed across multiple insulating layers 3. The multiple insulating layers 3 include, for example, insulating layers 3c and 3d. In contrast, the first capacitor element 203 and the second capacitor element 213 are contained in one insulating layer 3. One insulating layer 3 is, for example, insulating layer 3a. Here, "across the first element and the second element" refers to including at least a portion of the first element and at least a portion of the second element.

[0415] In one example, the plurality of wirings are wirings obtained by removing all wirings electrically connected to the specific node RD from all wirings in the upper wiring layer. In another example, the plurality of wirings are all wirings in the upper wiring layer. In this context, the number of “all wirings electrically connected to the specific node RD” may be one or more.

[0416] In a cross section passing through the upper wiring layer and perpendicular to the thickness direction of the semiconductor substrate 2, the area S1 of the first wiring is smaller than the area S2 of the second wiring. According to this structure, it is easy to reduce the area S1 of the first wiring and to suppress the coupling of multiple wirings with the first wiring. Therefore, the capacitance value of the first node FDA is difficult to include the capacitance value of the parasitic capacitance caused by the coupling. This is advantageous from the perspective of increasing the conversion gain and reducing noise in the first unit 100a. Obtaining such an advantageous effect in the first unit 100a with relatively high sensitivity is suitable for realizing a high-quality camera device 1.

[0417] The ratio S1 / S2 of the area S1 to the area S2 is, for example, 10% to 90%. The ratio S1 / S2 may be 30% to 50%.

[0418] Fig.12 It is a schematic plan view for explaining the magnitude relationship of the area ratio. Fig.12 The area ratio considerations shown can be applied to FIG. 10A to FIG. 10H and FIG. 11A to FIG. 11C The schematic structure diagram of each wiring layer when viewed from above is shown.

[0419] In the imaging device 1, a plurality of pixels 100 are arranged at a predetermined pitch L0. Fig.12 Schematically shown in FIG. 2 , in a cross section passing through the upper wiring layer and perpendicular to the thickness direction of the semiconductor substrate 2, the geometric center of the first wiring Wx1 is defined as the first center point G1. In this cross section, the geometric center of the second wiring Wx2 is defined as the second center point G2. In this cross section, the area surrounded by a circle with a radius of 1 / 8 of the pitch L0 and the first center point G1 as the center is defined as the first enclosing area En1. In this cross section, the area surrounded by a circle with a radius of 1 / 8 of the pitch L0 and the second center point G2 as the center is defined as the second enclosing area En2. In this cross section, the ratio of the areas occupied by the plurality of wirings Wz in the first enclosing area En1 is defined as the first area ratio R1. In this cross section, the ratio of the areas occupied by the plurality of wirings Wz in the second enclosing area En2 is defined as the second area ratio R2. At this time, the first area ratio R1 is smaller than the second area ratio R2. According to this structure, it is easy to reduce the first area ratio R1 and to suppress the coupling of the plurality of wirings Wz with the first wiring. Therefore, the capacitance value of the first node FDA is unlikely to include the capacitance value of the parasitic capacitance caused by the coupling. This is advantageous from the perspective of increasing the conversion gain and reducing noise in the first unit 100a. Obtaining such an advantageous effect in the first unit 100a having a relatively high sensitivity is suitable for realizing a high-quality imaging device 1.

[0420] In more detail, the first area ratio R1 is the ratio of the area of ​​the portion of the plurality of wirings Wz located in the first enclosing area En1 to the area of ​​the first enclosing area En1. The second area ratio R2 is the ratio of the area of ​​the portion of the plurality of wirings Wz located in the second enclosing area En2 to the area of ​​the second enclosing area En2.

[0421] One side reference Figure 4 and Figure 5 The pitch L0 will be described below. The pitch L0 is based on any one of the following definitions 1 to 12.

[0422] Definition 1: The pitch L0 is the pitch Pm1x at which the first microlenses 113 a are arranged in the row direction.

[0423] Definition 2: The pitch L0 is the pitch Pm1y at which the first microlenses 113 a are arranged in the column direction.

[0424] Definition 3: The spacing L0 is the average of the spacing Pm1x and the spacing Pm1y.

[0425] Definition 4: The pitch L0 is the pitch Pm2x at which the second microlenses 113 b are arranged in the row direction.

[0426] Definition 5: The pitch L0 is the pitch Pm2y at which the second microlenses 113 b are arranged in the column direction.

[0427] Definition 6: The spacing L0 is the sum of the spacing Pm2x and the spacing Pm2y.

[0428] Definition 7: The pitch L0 is the pitch Pe1x at which the first pixel electrodes 102 are arranged in the row direction.

[0429] Definition 8: The pitch L0 is the pitch Pe1y at which the first pixel electrodes 102 are arranged in the column direction.

[0430] Definition 9: The spacing L0 is the sum of the spacing Pe1x and the spacing Pe1y.

[0431] Definition 10: The pitch L0 is the pitch Pe2x at which the second pixel electrodes 103 are arranged in the row direction.

[0432] Definition 11: The pitch L0 is the pitch Pe2y at which the second pixel electrodes 103 are arranged in the column direction.

[0433] Definition 12: The spacing L0 is the sum of the spacing Pe2x and the spacing Pe2y.

[0434] In the present embodiment, when it can be said that “the first area ratio R1 is smaller than the second area ratio R2” based on any one of Definitions 1 to 12, it is handled as “the first area ratio R1 is smaller than the second area ratio R2”.

[0435] The ratio R1 / R2 of the first area ratio R1 to the second area ratio R2 is, for example, 10% to 90%. The ratio R1 / R2 may be 30% to 50%.

[0436] The first area ratio R1 is, for example, 10% to 70%. The first area ratio R1 may be 20% to 50%. The second area ratio R2 is, for example, 10% to 70%. The second area ratio R2 may be 20% to 50%.

[0437] The upper wiring layer includes a first signal wiring and a second signal wiring. The first unit 100a includes a first transistor. The first transistor includes a first source, a first drain, and a first gate. The first source or the first drain is a first charge accumulation unit FD1. A first control signal is supplied to the first gate via the first signal wiring. The second unit 100b includes a second transistor. The second transistor includes a second source, a second drain, and a second gate. The second source or the second drain is a second charge accumulation unit FD2. A second control signal is supplied to the second gate via the second signal wiring.

[0438] In the upper wiring layer, the shortest distance between the first wiring and the first signal wiring is the fifth distance L5. In the upper wiring layer, the shortest distance between the second wiring and the second signal wiring is the sixth distance L6. The fifth distance L5 is larger than the sixth distance L6. According to this structure, it is easy to increase the fifth distance L5 and suppress the coupling between the first signal wiring and the first wiring. Therefore, the capacitance value of the first node FDA is difficult to include the capacitance value of the parasitic capacitance caused by the coupling. This is advantageous from the perspective of improving the conversion gain and reducing noise in the first unit 100a. Obtaining such an advantageous effect in the first unit 100a with relatively high sensitivity is suitable for realizing a high-quality camera device 1. Furthermore, in this structure, the sixth distance L6 is relatively small. Therefore, according to this structure, a high-quality camera device 1 can be realized while suppressing the size of the pixel 100.

[0439] In one example, the first transistor is the first reset transistor 202. The first control signal is the first reset control signal. The second transistor is the second reset transistor 217. The second control signal is the second reset control signal. The upper wiring layer is Fig. 10B The first wiring layer WL1 is shown. The first wiring is the wiring W1a. The first signal wiring is the wiring W1c. The fifth distance L5 is the shortest distance LA between the wiring W1a and the wiring W1c. The second wiring is the wiring W1d. The second signal wiring is the wiring W1f. The sixth distance L6 is the shortest distance LG between the wiring W1d and the wiring W1f.

[0440] However, other examples may also be used. For example, the first transistor may also be the first transfer transistor 245. The first control signal may also be the first transfer control signal. The second transistor may also be the second transfer transistor 246. The second control signal may also be the second transfer control signal. The first signal wiring may also be other wiring electrically connected to the gate of the first transistor. The upper wiring layer may also be a wiring layer including the other wiring. The second signal wiring may also be other wiring electrically connected to the gate of the second transistor. The upper wiring layer may also be a wiring layer including the other wiring.

[0441] The ratio L5 / L6 of the fifth distance L5 to the sixth distance L6 is, for example, 1.5 to 10. The ratio L5 / L6 may be 2 to 5.

[0442] The fifth distance L5 is, for example, not less than 100 nm and not more than 1000 nm. The fifth distance L5 may be, for example, not less than 200 nm and not more than 500 nm. The sixth distance L6 is, for example, not less than 50 nm and not more than 1000 nm. The sixth distance L6 may be, for example, not less than 100 nm and not more than 500 nm.

[0443] The first unit 100a includes a first plug and a first capacitor element 203. The first plug is electrically connected to the first node FDA. The first capacitor element 203 has an electrode 203a and an electrode 203b. The second unit 100b includes a second plug and a second capacitor element 213. The second plug is electrically connected to the second node FDB. The second capacitor element 213 has an electrode 213a and an electrode 213b. In a cross section passing through the first capacitor element 203 and perpendicular to the thickness direction of the semiconductor substrate 2, the shortest distance between the first plug and the electrode 203b is the seventh distance L7. In this cross section, the shortest distance between the second plug and the electrode 213b is the eighth distance L8. The seventh distance L7 is larger than the eighth distance L8. According to this structure, it is easy to increase the seventh distance L7 and to suppress the coupling between the electrode 203b and the first plug. Therefore, it is difficult for the capacitance value of the first node FDA to include the capacitance value of the parasitic capacitance caused by the coupling. This is advantageous from the viewpoint of increasing the conversion gain and reducing the noise in the first unit 100a. Obtaining such an advantageous effect in the first unit 100a having a relatively high sensitivity is suitable for realizing a high-quality imaging device 1. Furthermore, in this structure, the eighth distance L8 is relatively small. Therefore, according to this structure, it is possible to realize a high-quality imaging device 1 while suppressing the size of the pixel 100.

[0444] In one example, the first plug is Fig. 10C The plug vp1a is shown. The second plug is the plug vp1d. The seventh distance L7 is the shortest distance LH between the plug vp1a and the electrode 203b. The eighth distance L8 is the shortest distance LI between the plug vp1d and the electrode 213b.

[0445] The ratio L7 / L8 of the seventh distance L7 to the eighth distance L8 is, for example, 1.5 to 10. The ratio L7 / L8 may be 2 to 5.

[0446] The seventh distance L7 is, for example, not less than 100 nm and not more than 1000 nm. The seventh distance L7 may be, for example, not less than 200 nm and not more than 500 nm. The eighth distance L8 is, for example, not less than 50 nm and not more than 1000 nm. The eighth distance L8 may be, for example, not less than 100 nm and not more than 500 nm.

[0447] The first unit 100a includes a first transistor. The second unit 100b includes a second transistor. One of the source and drain of the first transistor is a first charge accumulation unit FD1. One of the source and drain of the second transistor is a second charge accumulation unit FD2. The first transistor is electrically connected to the electrode 203a. The second transistor is electrically connected to the electrode 213a. In one example, Figure 2 As shown in FIG. 1 and FIG. 2 , the first transistor is the first reset transistor 202 and the second transistor is the second reset transistor 217 .

[0448] like Fig. 10C As shown, in a cross section passing through the first capacitor element 203 and perpendicular to the thickness direction of the semiconductor substrate 2, a recess 203x opening toward a prescribed direction Dx is provided in the first capacitor element 203. In this cross section, the first plug is located in the recess 203x. In the upper wiring layer, the first signal wiring is located on the prescribed direction Dx side of the first wiring. According to this structure, it is easier to ensure both the fifth distance L5 and the seventh distance L7, compared with a case where the recess 203x is not provided and the first plug is arranged in the recess 203x. This is advantageous from the viewpoint of increasing the conversion gain and reducing the noise in the first unit 100a. Obtaining such an advantageous effect in the first unit 100a having a relatively high sensitivity is suitable for realizing a high-quality imaging device 1. In one example, the upper wiring layer is Fig.10E The third wiring layer WL3 shown in FIG. 1 is the wiring W3a. The first signal wiring is the first reset control line RSTiA. The fifth distance L5 is the shortest distance LC between the wiring W3a and the first reset control line RSTiA. The seventh distance L7 is Fig. 10C The shortest distance LH between the plug vp1a and the electrode 203b is shown.

[0449] The ratio L7 / L5 of the seventh distance L7 to the fifth distance L5 is, for example, 0.5 or more and 2 or less. If the fifth distance L5 and the seventh distance L7 are set to values ​​close to each other, it is less likely that the fifth distance L5 becomes extremely small or the seventh distance L7 becomes extremely small. This is suitable for realizing a high-quality imaging device 1. The ratio L7 / L5 may also be 0.8 or more and 1.25 or less.

[0450] The fifth distance L5 may be greater than the seventh distance L7. The fifth distance L5 may be smaller than the seventh distance L7. The fifth distance L5 and the seventh distance L7 may be the same.

[0451] The camera device 1 includes an intermediate wiring. The intermediate wiring electrically connects the first plug and the first wiring. When viewed from above, the intermediate wiring extends from a position within the recess 203x to a position closer to the predetermined direction Dx than the recess 203x. The intermediate wiring facilitates the above-mentioned positional relationship among the recess 203x, the first plug, the first wiring, and the first signal wiring. In one example, the intermediate wiring is Fig.10E The wiring W3c shown in FIG. 1 shows a wiring W3c. In this example, in the upper wiring layer, the first signal wiring and the intermediate wiring are electrically connected.

[0452] The above description is based on the implementation of the camera device of the present disclosure in order to achieve low noise and wide dynamic range, but the present disclosure is not limited to these implementations and variations. As long as it does not deviate from the main purpose of the present disclosure, the implementations and variations are subjected to various modifications that can be thought of by those skilled in the art, or other forms constructed by combining some of the constituent elements in the implementations and variations are also included in the scope of the present disclosure.

[0453] Industrial Applicability

[0454] The imaging device of the present disclosure is useful for, for example, an image sensor, a digital camera, etc. The imaging device of the present disclosure can be used for a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, and the like.

[0455] Description of symbols

[0456] 1 Camera device

[0457] 2 Semiconductor substrate

[0458] 3, 3a, 3b, 3c, 3d, 3e, 3f insulation layer

[0459] 4 Buffer layer

[0460] 5 Sealing layer

[0461] 6 Planarization layer

[0462] 10-Pixel Array

[0463] 100 pixels

[0464] 100a Unit 1

[0465] 100b Unit 2

[0466] 102 1st pixel electrode

[0467] 103 2nd pixel electrode

[0468] 104 auxiliary electrode

[0469] 105, 105c, 105v, 106, 106c, 106v, cpa1, cpa2, cpa3, cpb, cpc, cpd1, cpd2, cpe1, cpe2, cpe3, cpe4, cpf, cp g, cph, cpi, cpj, cpk, cpp, cpq, cpr, vp1a, vp1b, vp1c, vp1d, vp1e, vp1f, vp1g, vp1h, vp1i, vp1j, vp1k, vp1 m, vp1n, vp1p, vp1q, vp1r, vp2a, vp2b, vp2c, vp2d, vp2e, vp2f, vp2g, vp2h, vp2i, vp2j, vp2k, vp2m, vp2n, v p2s, vp2t, vp3a, vp3b, vp3d, vp3e, vp3h, vp3j, vp3s, vp3t, vp4a, vp4b, vp4d, vp4e, vp5a, vp5d, vp6a, vp6d plug

[0470] 110 Photoelectric conversion film

[0471] 110a First photoelectric conversion film

[0472] 110b Second photoelectric conversion film

[0473] 111 Counter electrode

[0474] 111a First counter electrode

[0475] 111b Second counter electrode

[0476] 112 Color Filters

[0477] 113 Microlens Group

[0478] 113a First microlens

[0479] 113b Second microlens

[0480] 120, 241 First photoelectric conversion unit

[0481] 125 1st transmission path

[0482] 130, 242 Second photoelectric conversion unit

[0483] 135 Second transmission path

[0484] 200 1st signal detection circuit

[0485] 202 1st reset transistor

[0486] 202g, 205g, 206g, 207g, 215g, 216g, 217g, 231g, 232g grid

[0487] 203 First capacitor element

[0488] 204 Specific capacitor elements

[0489] 204a Specified electrodes

[0490] 204b Specific Electrode

[0491] 213 Second capacitor element

[0492] 203a, 203b, 213a, 213b electrodes

[0493] 203p, 213p protrusion

[0494] 203x recess

[0495] 205 1st amplifier transistor

[0496] 206 1st selection transistor

[0497] 207 Band Control Transistor

[0498] 208a, 208ax, 208ay, SIGjA 1st vertical signal line

[0499] 208b, 208bx, 208by, SIGjB 2nd vertical signal line

[0500] 209a 1st feedback line

[0501] 209b 2nd feedback line

[0502] 209u, 209x, 209y Power Supply Wiring

[0503] 210 Second signal detection circuit

[0504] 215 Second amplifier transistor

[0505] 216 2nd selection transistor

[0506] 217 2nd reset transistor

[0507] 231 1st overflow transistor

[0508] 232 2nd overflow transistor

[0509] 235 1st row line

[0510] 236 The 2nd row is discharged

[0511] 245 1st transfer transistor

[0512] 246 Second transfer transistor

[0513] 300a 1st inverting amplifier

[0514] 300b 2nd Inverting Amplifier

[0515] 310 Line scanning circuit

[0516] 311 Control Circuit

[0517] 312 Column Circuit

[0518] 313 Signal Processing Circuit

[0519] 314 Output Circuit

[0520] FBi Feedback Control Line

[0521] RSTiA 1st reset control line

[0522] RSTiB 2nd reset control line

[0523] SELiA 1st address control line

[0524] SELiB 2nd address control line

[0525] TRiA 1st transfer control line

[0526] TRiB 2nd transfer control line

[0527] TPA 1st capacitor control line

[0528] TPB 2nd capacitor control line

[0529] FD1 1st charge storage unit

[0530] FD2 Second charge storage unit

[0531] DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8 diffusion layer

[0532] FDA Node 1

[0533] FDB Node 2

[0534] RD Specific Node

[0535] VR Power Node

[0536] W1a, W1b, W1c, W1d, W1e, W1f, W1g, W1h, W1i, W1j, W1k, W1p, W1r, W2a, W2b, W2c, W2d, W2e, W2f, W2g, W2h, W2i, W2j, W2k, W2p , W2q, W2r, W2s, W2t, W3a, W3b, W3c, W3d, W3e, W3h, W3i, W3j, W3s, W3t, W4a, W4b, W4d, W4e, W5a, W5b, W5d, W5e, W6a, W6d, Wz wiring

[0537] Wx1 1st wiring

[0538] Wx2 2nd wiring

[0539] WL Routing Layer

[0540] WLG Gate wiring layer

[0541] WL1 1st wiring layer

[0542] MS MIM Level

[0543] WL2 2nd wiring layer

[0544] WL3 3rd wiring layer

[0545] WL4 4th wiring layer

[0546] WL5 5th wiring layer

[0547] WL6 6th wiring layer

[0548] ES pixel electrode level

[0549] En1 1st enclosed area

[0550] En2 Second encircled area

[0551] G1 1st center point

[0552] G2 2nd center point

[0553] FC1 1st feedback circuit

[0554] FC2 Second feedback circuit

[0555] FP1 1st feedback path

[0556] FP2 Second feedback path

[0557] SL Straight Line

[0558] po1 Part 1

[0559] po2 part 2

[0560] pp prescribed part

[0561] Dx specifies the direction

Claims

1. A camera device comprising: Semiconductor substrates; as well as The pixel includes a first unit, a second unit having a lower sensitivity than the first unit, and an upper wiring layer located above the semiconductor substrate and including a plurality of wirings. The above Unit 1 includes: a first photoelectric conversion unit that converts light into a first signal charge; a first charge accumulation unit, located in the semiconductor substrate, accumulating the first signal charge, and electrically connected to the first node; and a first wiring, located in the upper wiring layer and electrically connected to the first node; The above Unit 2 includes: a second photoelectric conversion unit that converts light into a second signal charge; a second charge accumulation unit, located in the semiconductor substrate, accumulating the second signal charge, and electrically connected to the second node; and a second wiring, located in the upper wiring layer and electrically connected to the second node; The nodes electrically connected to each of the plurality of wirings are different from the first node and the second node. In the upper wiring layer, the shortest distance between the first wiring and the plurality of wirings is greater than the shortest distance between the second wiring and the plurality of wirings.

2. The imaging device according to claim 1, The pixel includes a first capacitor wiring layer located above the semiconductor substrate. The first capacitor wiring layer includes: a first prescribed wiring electrically connected to the first node; as well as The first specific wiring is electrically connected to a specific node different from the first node. The first unit includes a specific capacitor element, The specific capacitor element includes the first predetermined wiring and the first specific wiring.

3. The imaging device according to claim 2, The pixel includes a second capacitor wiring layer, the second capacitor wiring layer being located above the semiconductor substrate and above or below the first capacitor wiring layer. The second capacitor wiring layer includes: a second predetermined wiring electrically connected to the first node; as well as a second specific wiring electrically connected to the specific node; The specific capacitor element includes the second predetermined wiring and the second specific wiring.

4. The imaging device according to claim 2, In a cross section passing through the first capacitor wiring layer and perpendicular to the thickness direction of the semiconductor substrate, there is a straight line passing through the first part of the first specific wiring, the specified part of the first specified wiring, and the second part of the first specific wiring in sequence.

5. The imaging device according to claim 2, The first unit includes a first amplifier transistor that generates a first electrical signal corresponding to the potential of the first charge storage unit. The first electric signal is negatively fed back to the first charge storage unit via the specific capacitive element.

6. The imaging device according to claim 2, The imaging device includes a power supply wiring electrically connected to a power supply node, and the power supply node is different from the first node, the second node, and the specific node. The first unit includes a first amplifier transistor that generates a first electric signal corresponding to the potential of the first charge storage unit, and the first amplifier transistor is supplied with a power supply potential via the power supply wiring. In the first capacitor wiring layer, the first specific wiring is located between the power supply wiring and the first prescribed wiring.

7. The imaging device according to claim 6, The first electrical signal is negatively fed back to the first charge storage unit via the specific capacitor element. The potential of the negatively fed-back first electric signal is applied to the power supply wiring.

8. The imaging device according to claim 2, The first unit includes a first capacitor element, The first capacitor element includes a first electrode electrically connected to the specific node and a second electrode electrically separated from the first electrode. The first electrode is located between the second electrode and the semiconductor substrate. The shortest distance between the first predetermined wiring and the first specific wiring in the first capacitor wiring layer is shorter than the shortest distance between the first electrode and the semiconductor substrate.

9. The imaging device according to claim 2, The first unit includes a MIM capacitor or a MOS capacitor electrically connected to the specific node.

10. The imaging device according to claim 2, The plurality of wirings are obtained by removing all wirings electrically connected to the specific node from all wirings in the upper wiring layer.

11. The imaging device according to claim 1, The plurality of wirings are all wirings in the upper wiring layer.

12. A camera device comprising: semiconductor substrate; and A pixel including a first unit, a second unit having a lower sensitivity than the first unit, and an upper wiring layer located above the semiconductor substrate and including a first signal wiring and a second signal wiring. The above Unit 1 includes: a first photoelectric conversion unit that converts light into a first signal charge; A first charge accumulation unit is located in the semiconductor substrate, accumulates the first signal charge, and is electrically connected to the first node; a first wiring, located in the upper wiring layer and electrically connected to the first node; as well as a first transistor including a first source or a first drain serving as the first charge storage unit and a first gate to which a first control signal is supplied via the first signal wiring. The above Unit 2 includes: a second photoelectric conversion unit that converts light into a second signal charge; A second charge accumulation unit is located in the semiconductor substrate, accumulates the second signal charge, and is electrically connected to the second node; a second wiring located in the upper wiring layer and electrically connected to the second node; and a second transistor including a second source or a second drain serving as the second charge storage unit and a second gate to which a second control signal is supplied via the second signal wiring. In the upper wiring layer, the shortest distance between the first wiring and the first signal wiring is greater than the shortest distance between the second wiring and the second signal wiring.

13. A camera device comprising: Semiconductor substrates; as well as The pixel includes a first unit, a second unit having a lower sensitivity than the first unit, and an upper wiring layer located above the semiconductor substrate and including a plurality of wirings. The above Unit 1 includes: a first photoelectric conversion unit that converts light into a first signal charge; a first charge accumulation unit, located in the semiconductor substrate, accumulating the first signal charge, and electrically connected to the first node; and a first wiring, located in the upper wiring layer and electrically connected to the first node; The above Unit 2 includes: a second photoelectric conversion unit that converts light into a second signal charge; a second charge accumulation unit, located in the semiconductor substrate, accumulating the second signal charge, and electrically connected to the second node; and a second wiring, located in the upper wiring layer and electrically connected to the second node; The nodes electrically connected to each of the plurality of wirings are different from the first node and the second node. In a cross section passing through the upper wiring layer and perpendicular to the thickness direction of the semiconductor substrate, an area of ​​the first wiring is smaller than an area of ​​the second wiring.

14. A camera device comprising: semiconductor substrate; and Multiple pixels are arranged at a predetermined pitch. The plurality of pixels include at least one pixel, The at least one pixel includes a first unit, a second unit having a lower sensitivity than the first unit, and an upper wiring layer located above the semiconductor substrate and including a plurality of wirings. The above Unit 1 includes: a first photoelectric conversion unit that converts light into a first signal charge; A first charge accumulation unit is located in the semiconductor substrate, accumulates the first signal charge, and is electrically connected to the first node; as well as a first wiring, located in the upper wiring layer and electrically connected to the first node; The above Unit 2 includes: a second photoelectric conversion unit that converts light into a second signal charge; a second charge accumulation unit, located in the semiconductor substrate, accumulating the second signal charge, and electrically connected to the second node; and a second wiring, located in the upper wiring layer and electrically connected to the second node; The nodes electrically connected to each of the plurality of wirings are different from the first node and the second node. In a cross section passing through the upper wiring layer and perpendicular to the thickness direction of the semiconductor substrate, When the geometric center of the first wiring is defined as the first center point, The geometric center of the second wiring is defined as the second center point. The area enclosed by a circle with the first center point as the center and a radius of 1 / 8 of the above pitch is defined as the first enclosed area. The area enclosed by a circle with the second center point as the center and a radius of 1 / 8 of the pitch is defined as the second enclosed area. The ratio of the areas occupied by the plurality of wirings in the first enclosing region is defined as a first area ratio. When the ratio of the areas occupied by the plurality of wirings in the second enclosing region is defined as a second area ratio, The first area ratio is smaller than the second area ratio.

15. A camera device comprising: Semiconductor substrates; as well as A pixel including a first unit and a second unit having a lower sensitivity than the first unit. The above Unit 1 includes: a first photoelectric conversion unit that converts light into a first signal charge; A first charge accumulation unit is located in the semiconductor substrate, accumulates the first signal charge, and is electrically connected to the first node; a first plug electrically connected to the first node; and The first capacitor element has a first electrode and a second electrode. The above Unit 2 includes: a second photoelectric conversion unit that converts light into a second signal charge; A second charge accumulation unit is located in the semiconductor substrate, accumulates the second signal charge, and is electrically connected to the second node; a second plug electrically connected to the second node; and The second capacitor element has a third electrode and a fourth electrode. In a cross section passing through the first capacitor element and perpendicular to the thickness direction of the semiconductor substrate, a shortest distance between the first plug and the second electrode is greater than a shortest distance between the second plug and the fourth electrode.

16. The camera device according to claim 15, The first unit includes a first transistor, The second unit includes a second transistor, One of the source and the drain of the first transistor is the first charge storage unit. One of the source and the drain of the second transistor is the second charge storage unit. The first transistor is electrically connected to the first electrode. The second transistor is electrically connected to the third electrode.

17. An imaging device comprising a semiconductor substrate and pixels, The above pixels include: An upper wiring layer, located above the semiconductor substrate, including a first signal wiring; a first photoelectric conversion unit that converts light into a first signal charge; A first charge accumulation unit is located in the semiconductor substrate, accumulates the first signal charge, and is electrically connected to the first node; a first wiring, located in the upper wiring layer and electrically connected to the first node; a first plug electrically connected to the first node; A first capacitor element having a first electrode and a second electrode; as well as a first transistor including a first source or a first drain serving as the first charge storage unit and a first gate to which a first control signal is supplied via the first signal wiring. In a cross section passing through the first capacitor element and perpendicular to the thickness direction of the semiconductor substrate, the first plug is located in a recess provided in the first capacitor element and opening in a predetermined direction. In the upper wiring layer, the first signal wiring is located on the predetermined direction side relative to the first wiring.

18. The imaging device according to claim 17, comprising an intermediate wiring electrically connecting the first plug and the first wiring, The intermediate wiring extends from a position within the recessed portion toward a position on the predetermined direction side relative to the recessed portion in a plan view.

19. The imaging device according to claim 17, A ratio of the shortest distance between the first plug and the second electrode in the cross section passing through the first capacitor element and perpendicular to the thickness direction of the semiconductor substrate to the shortest distance between the first wiring and the first signal wiring in the upper wiring layer is greater than 0.5 and less than 2.

20. The imaging device according to claim 17, The pixel includes a first unit and a second unit having a lower sensitivity than the first unit. The above Unit 1 includes: The first photoelectric conversion unit; The first charge storage unit; The first wiring mentioned above; The first plug mentioned above; The first capacitor element; as well as The first transistor mentioned above.

Images