Single photon avalanche diode macro pixel

Abstract

A macro pixel is disclosed. The macro pixel includes a plurality of pixels, each pixel including a single photon avalanche diode (SPAD). The macro pixel also includes a memory configured to store: a plurality of counts, each count associated with a pixel of the plurality of pixels; and a plurality of saturation bits, each saturation bit associated with a count of the plurality of counts. The macro pixel also includes a saturation detection circuit configured to gate recharging of each SPAD based on a state of a respective saturation bit.

Description

Technical Field

[0001] The present disclosure is in the field of SPAD-based pixels, and in particular relates to a macropixel comprising a plurality of SPAD-based pixels for an image sensor. Background Art

[0002] Single photon avalanche detector (SPAD) based sensors can be commonly implemented in various applications including, for example, LiDAR, time-of-flight (ToF), and 3D imaging applications.

[0003] The characteristics and operation of a SPAD may be affected by the underlying semiconductor technology used to implement the SPAD, as well as the associated circuitry used to control and sense the SPAD operation and record SPAD events (e.g., photon strikes). For example, the dynamic range, spatial resolution, signal-to-noise ratio, and / or bit count of a SPAD-based device may depend, at least in part, on the underlying semiconductor technology node on which the SPAD is fabricated and / or the associated measurement and storage circuitry.

[0004] In some examples, the circuitry required to read and / or store the state of a SPAD can substantially impact the size, cost, power consumption, and overall performance of a SPAD-based device.

[0005] The use of SPAD-based pixels in applications such as image sensing has been limited to some extent by this characteristic of SPAD-based pixels and their operation.

[0006] For example, implementing a cost-effective image sensor using SPAD-based pixels (wherein the SPAD-based image sensor has performance comparable to known megapixel CMOS image sensors) will require implementing SPAD-based pixels that exhibit a high photon count dynamic range but occupy a small enough space to ensure sufficiently low power consumption and commercial viability, where the commercial viability may be largely related to the number of megapixels in a standard optical lens format suitable for low z-height embedded cameras for mobile battery-powered applications.

[0007] The semiconductor technology nodes (e.g., sub-30 nm nodes) that may be required to implement circuits that meet such stringent size, power, and performance requirements may be very expensive. As a result, designs implemented for SPAD-based image sensors may require suboptimal compromises in spatial resolution, temporal resolution, bit count, power requirements, and / or signal-to-noise ratio.

[0008] In particular, the implementation of a counter for counting SPAD events may substantially impact the size, power, and performance of a SPAD-based photon counting image sensor.

[0009] Known counter solutions may include digital bit counters or analog bit counters.

[0010] Digital bit counters typically use N flip-flops for an N-bit counter, and despite process scaling to advanced CMOS manufacturing nodes (e.g., sub-30 nm nodes), such counters may still occupy a significant area due to their large transistor count, thereby limiting the pitch and, therefore, the resolution of any image array implemented using such a digital bit counter.

[0011] An alternative approach is to use analog counters, which can be beneficial in reducing pixel pitch and power. However, such analog counters can be prone to current leakage, mismatch errors, manufacturing process variations, and are not easily portable between different CMOS technology nodes.

[0012] It is therefore desirable to provide a highly integrated SPAD-based sensor suitable for implementation in megapixel image sensing applications. Furthermore, it is desirable that such a SPAD-based sensor be suitable for fabrication in cost-effective semiconductor process nodes while still providing sufficient dynamic range, spatial resolution, and signal-to-noise ratio to compete with known CMOS megapixel imagers. It is desirable to implement such a SPAD-based sensor using primarily digital circuits to avoid the disadvantages of the analog solutions described above. Furthermore, it is highly desirable that such a SPAD-based sensor meet stringent low power consumption requirements.

[0013] Therefore, an object of at least one embodiment of at least one aspect of the present disclosure is to eliminate or at least alleviate at least one of the above-mentioned disadvantages of the prior art. Summary of the invention

[0014] The present disclosure is in the field of SPAD-based pixels, and in particular relates to a macropixel comprising a plurality of SPAD-based pixels for an image sensor.

[0015] According to a first aspect of the present disclosure, there is provided a macropixel comprising a plurality of pixels, each pixel comprising a single photon avalanche diode (SPAD). The macropixel further comprises a memory configured to store: a plurality of counts, each count being associated with a pixel in the plurality of pixels; and a plurality of saturation bits, each saturation bit being associated with a count in the plurality of counts. The macropixel further comprises a saturation detection circuit configured to enable recharging of each SPAD based on a state of a corresponding saturation bit.

[0016] The term "macropixel" will be understood to refer to an optical device that includes multiple pixels (eg, two or more pixels).

[0017] The term "pixel" will be understood to refer to a SPAD-based pixel, such as a SPAD and circuitry associated with the SPAD. As described in more detail below, for example, such associated circuitry may include circuitry for sampling and holding voltage levels, circuitry for resetting the SPAD, circuitry for quenching the SPAD, etc.

[0018] The term "single photon avalanche diode" will be understood to refer only to the physical SPAD device itself, and not to include additional circuitry that can together form a SPAD-based pixel as described above.

[0019] The term "count" will be understood to refer to a value, such as a value that can be used with associated counter circuitry to implement a counter. The count can be a value that is incremented, decremented, or otherwise advanced to the next known state by the associated circuitry. In further examples, and as described in more detail below, the count can be a value that is sequentially incremented, decremented, or adjusted to one of a defined number of known states.

[0020] In a non-limiting example, the count may correspond to a word stored in memory.

[0021] Advantageously, the use of memory (e.g., SRAM or DRAM memory cells) can reduce the overall footprint and power consumption of the macropixel compared to a hardware counter (e.g., a flip-flop based binary counter that can be implemented in a prior art pixel). That is, the total transistor count of the memory-based macropixel can be substantially less than the transistor count associated with the hardware counter-based macropixel, thereby helping to reduce power consumption and size. In yet another example, other RAM types can be implemented, such as phase change RAM (PCRAM), synchronous dynamic RAM (SDRAM), spin transfer torque magnetic RAM (STT-MRAM), etc.

[0022] Advantageously, as described in more detail below, by gating the recharging of each SPAD based on the state of the corresponding saturation bit, the power consumption of the macropixel can be substantially reduced.

[0023] Advantageously, the memory and saturation detection circuitry is fully digital and suitable for implementation in compact macropixels where the digital circuitry can be optimally stacked beneath the SPAD of the pixel.

[0024] Advantageously, the all-digital solution described in more detail below enables macropixels that do not require analog-to-digital circuitry as may be achieved in prior art pixels.

[0025] Advantageously, the disclosed macropixels can achieve optical sensing with high dynamic range using low-power digital pixels of compact size that are suitable for implementation in low-cost semiconductor manufacturing technology nodes. That is, the disclosed macropixels avoid the need to move to increasingly advanced semiconductor manufacturing technology nodes to achieve pixels that meet stringent low power consumption and performance requirements, thereby minimizing cost and design cycle time.

[0026] The saturation detection circuit may be configured to gate recharging of each SPAD when the corresponding saturation bit indicates that the associated count has been saturated.

[0027] The saturation detection circuit may be configured to gate recharging of each SPAD when the corresponding saturation bit indicates that the associated count has reached a threshold.

[0028] Advantageously, power consumption may be reduced by gating recharging of each SPAD after the count associated with the SPAD has saturated or reached a threshold.

[0029] In an embodiment, saturation of the count may correspond to the value of the count reaching a maximum value.

[0030] In an embodiment, saturation of the count may correspond to the value of the count rolling over or returning to an initial value.

[0031] In an embodiment, saturation of the count may correspond to the value of the count sequentially passing through all possible states.

[0032] In an embodiment, the threshold may be user programmable.

[0033] When recharging of one or more SPADs in one or more of the plurality of pixels is enabled, the associated one or more counts may be used to indicate a time since a corresponding saturation bit indicated that the count has saturated and / or reached a threshold.

[0034] That is, in an embodiment, the number of refresh cycles (e.g., cycles during which the SPAD would be recharged if it were not already saturated) can be counted. Advantageously, as described in more detail below, such extended counting of refresh cycles can be used to effectively extend the dynamic range of the pixel even after enabling of the recharging of the SPAD.

[0035] When recharging of one or more SPADs in one or more pixels in the plurality of pixels is not enabled, the associated one or more counts may be used to indicate a number of photons detected.

[0036] Advantageously, each count may correspond to a photon count for an associated pixel.It will be appreciated that the "number of detected photons" may correspond to the number of SPAD events (eg the number of avalanche current triggering events) rather than the exact number of photons incident on the SPAD.

[0037] Access to the memory for each pixel may be provided on a time multiplexed basis.

[0038] When recharging of the SPADs is not gated, each SPAD may be recharged on a time multiplexed basis.

[0039] Advantageously, power consumption can be significantly reduced by implementing time multiplexing. In addition, the amount of logic (eg, transistor count) can be minimized, as described in more detail below with reference to the accompanying drawings.

[0040] In an embodiment, a high gain mode of each SPAD (eg, a mode in which the SPAD is recharged to a Geiger mode suitable for detecting photon impacts) is used, at a relatively low duty cycle, for the shortest time duration required to achieve the necessary signal-to-noise ratio.

[0041] The time multiplexing basis may be a cyclic basis.

[0042] That is, in use, each SPAD may be recharged and / or each count stored in memory may be accessed an average of substantially equal times.

[0043] Enabling recharging of each SPAD may include configuring at least one transistor in the corresponding pixel to maintain the SPAD in a sub-Geiger mode.

[0044] Sub-Geiger mode will be understood to be the mode in which the corresponding SPAD is biased below its reverse bias breakdown voltage.

[0045] Advantageously, keeping the SPAD at a voltage insufficient to achieve Geiger mode breakdown (e.g., below its reverse bias breakdown voltage) can reduce the power consumption of the SPAD and can extend the lifetime of the SPAD. For example, compared to a pinned photodiode, the power consumption of a SPAD can be relatively high because the avalanche multiplication process following a photon strike can consume a relatively large amount of charge. By keeping the SPAD below the reverse bias breakdown voltage, the avalanche multiplication process can be avoided.

[0046] Each pixel may include at least one transistor that may be configured to maintain the corresponding SPAD in a high impedance state when the SPAD is biased in Geiger mode.

[0047] In an embodiment, each SPAD may be periodically reset, wherein after resetting, the SPAD may remain in Geiger mode while being in a high impedance state, thereby advantageously reducing overall power consumption.

[0048] The macropixel may be configured such that when a photon triggers the SPAD, the SPAD discharges its internal capacitance, thereby bringing the SPAD's excess bias voltage below the breakdown voltage.

[0049] Advantageously, when an avalanche event triggering photon strikes (e.g., a photon is absorbed to generate an electron-hole pair that triggers the avalanche event), the corresponding SPAD can discharge its own capacitance, thereby reducing the excessive bias to below the breakdown level (e.g., entering sub-Geiger mode), effectively achieving self-quenching.

[0050] Each pixel may include a recharge transistor that may be configured to recharge the corresponding SPAD to Geiger mode.

[0051] Each pixel may include a sample and hold circuit for sampling and holding a voltage corresponding to the state of the corresponding SPAD.

[0052] Advantageously, in an embodiment, the above-described pixel (which may implement both a transistor that may be configured to maintain a corresponding SPAD in a high impedance state when the corresponding SPAD is biased in Geiger mode, and a sample and hold circuit for sampling and holding a voltage corresponding to the state of the corresponding SPAD) may effectively implement a dynamic D-type sampler in a compact area.

[0053] The macropixel may include a shared memory increment or decrement circuit. The macropixel may include a time-multiplexed memory increment or decrement circuit. The macropixel may include a shared and time-multiplexed memory increment or decrement circuit configured to increment or decrement each of a plurality of counts, respectively.

[0054] That is, as described in more detail below, the shared increment or decrement circuitry can be configured to selectively increment or decrement or otherwise advance each stored count in a time multiplexed manner. Advantageously, the active area of ​​each SPAD of circuitry associated with incrementing / decrementing / advancing the count and any associated saturation detection can be substantially minimized by the degree of sharing between the counts (e.g., by the amount of counts of the shared memory increment or decrement circuitry).

[0055] In addition, time multiplexing of shared circuits can also help reduce power consumption. That is, shared circuits can be associated with each of the multiple counts on a time multiplexed basis, for example, each count has a dedicated time slot, thereby avoiding duplication of the circuits.

[0056] In an example embodiment, such time multiplexing may be based on round-robin. However, the present disclosure is not limited to such an embodiment, and other scheduling methods may be implemented.

[0057] Each count may correspond to a value of a binary counter.

[0058] That is, in an example, as described in more detail below with reference to the disclosed embodiments, a shared increment or decrement circuit can be configured to selectively increment or decrement each stored count using binary arithmetic.

[0059] In an example embodiment, such a shared increment or decrement circuit may be implemented as a chain of full adder circuits.

[0060] Each count may correspond to a value representing the state of a linear feedback shift register (LFSR).

[0061] That is, in an example, as described in more detail below with reference to the disclosed embodiments, a shared increment or decrement circuit may be configured to selectively advance each stored count to the next state of the LFSR.

[0062] In an embodiment, even when considering any LFSR to binary decoding circuit implementation, each LFSR may require XOR feedback and shift operations, which can reduce the overall transistor count compared to a binary counter implementation.

[0063] Advantageously, a LFSR may be substantially smaller and may consume less power and / or circuit area than a binary counter.

[0064] Furthermore, LFSRs can reduce the need for higher levels of time-multiplexed shared access memory, which can increase the availability of memory to each SPAD, thereby beneficially increasing the dynamic range of the macropixel.

[0065] Although examples of binary counters and LFSRs are described herein, it will be appreciated that the present disclosure is not limited to such particular embodiments and that embodiments of alternative or additional circuits capable of incrementing and / or decrementing a count and / or advancing a code or state may be implemented.

[0066] The macropixel may include processing circuitry configured to read out each count and each associated saturation bit at the end of a frame time.

[0067] In an embodiment, the readout may be achieved by a "rolling shutter" technique (eg, reading out the memory row by row).

[0068] The processing circuitry may be configured to read out each count by clocking the corresponding pixel for at least a number of cycles corresponding to a number of memory cells associated with the pixel while maintaining the corresponding pixel in a reset state.

[0069] Advantageously, this may allow each count and saturation bit in the memory (eg, each row in the memory) to be read out while also resetting the memory.

[0070] The processing circuitry may additionally be configured to read out a saturation bit associated with each count.

[0071] Advantageously, the processing circuitry may use the saturation bit to implement an extended counting dynamic range extension scheme.

[0072] That is, in an example embodiment based on a LFSR implementation, a saturation detection circuit may detect a count of the all-zero state of the LFSR code associated with a pixel, indicating that the LFSR code has counted all possible states and will "wrap around", e.g., saturate.

[0073] Similarly, in an example embodiment based on binary counting, a saturation detection circuit may detect a count of the all-ones state of the binary code associated with a pixel, indicating that the binary count has counted all possible states and will "wrap around", eg, saturate.

[0074] When this occurs, a saturation bit may be set for the corresponding pixel, indicating that the corresponding SPAD has reached saturation of its LFSR or binary counter.

[0075] As described above, the saturation bit can be used to control the recharging of the corresponding SPAD. In this way, the corresponding SPAD will not be reset to a low level again, and can therefore maintain a high level state, such as a triggered state.

[0076] This in turn may cause the stored count (eg, a binary count or LFSR code) to be further incremented or decremented on each refresh cycle.

[0077] However, processing circuitry may use the saturation bit to determine that counts stored since the saturation bit was set represent the "time since saturation." In this way, the dynamic range of the pixel may also be increased without a significant decrease in the signal-to-noise ratio.

[0078] That is, when a saturation bit associated with a respective count is set and when recharging of the associated SPAD is enabled, the processing circuitry may be configured to use the respective count as an indication of a cyclic refresh period since the saturation bit was set.

[0079] The memory may include an array of static random access memory (SRAM) cells.

[0080] Advantageously, an SRAM-based implementation may represent a tradeoff between relatively higher density memory and low power consumption (eg, no refresh cycles that may be associated with DRAM) compared to flip-flop or logic-based counter implementations.

[0081] The memory may include an array of dynamic random access memory (DRAM) cells.

[0082] Advantageously, DRAM can represent extremely high density memory, eg, with as few as three transistors per memory cell, thereby enabling highly compact and integrated macro-pixels.

[0083] The macropixel may include a refresh circuit for refreshing the DRAM cell.

[0084] Advantageously, the DRAM can be refreshed without affecting the stored counts.

[0085] If the corresponding SPAD has not been triggered, the refresh circuit may be configured to increment the count by zero.

[0086] The refresh circuitry may be configured to add a predetermined number of additional refresh cycles to the count for subsequent subtraction by the processing circuitry.

[0087] Advantageously, the DRAM may be refreshed by affecting the stored count in a known manner.

[0088] The macropixel may be formed as a monolithic device.

[0089] In an example, the macropixel may be formed in a CMOS process.

[0090] The memory may be formed in a region of the substrate. The plurality of pixels may be formed directly above the memory. The plurality of SPADs may be formed directly above the memory.

[0091] Advantageously, the macropixels described above (and in particular, the memory and / or circuitry of the macropixels described above) may be sufficiently compact that an array of SPADs or an array of SPAD-based pixels may be formed directly over the memory and / or circuitry.

[0092] According to a second aspect of the present disclosure, there is provided an image sensor comprising the macro pixel array according to the first aspect.

[0093] Advantageously, implementing an image sensor using SPADs rather than pinned photodiodes (as may typically be used in CMOS image sensors) may allow the sensor to exhibit extremely high dynamic range and sensitivity.

[0094] In embodiments, a macropixel array may be used to implement a "megapixel array," eg, an array including hundreds of thousands or millions of pixels.

[0095] According to a third aspect of the present disclosure, there is provided a proximity sensor or a time-of-flight sensor, comprising at least one macropixel according to the first aspect.

[0096] Advantageously, the above-described time multiplexed operation mode (eg, where each SPAD may be reset in a cyclical manner) may enable the implementation of distance measurements.

[0097] For example, in an embodiment where the macropixel includes N SPADs and assuming that each SPAD remains in a reset state for one-Nth period, it can be assumed that a laser pulse return falling within the reset window of the i-th SPAD will have no signal within a distance between i / N and i+1 / N of the distance range. Therefore, the processing circuit can perform an indirect time-of-flight type of distance calculation.

[0098] The above description is intended to be exemplary and not restrictive. The present disclosure includes one or more corresponding aspects, embodiments or features, either alone or in various combinations, whether or not specifically described (including claimed) in that combination or alone. It should be understood that the features defined above according to any aspect of the present disclosure or the features related to any specific embodiment of the present disclosure below can be used alone or in combination with any other defined features in any other aspect or embodiment, or form another aspect or embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0099] These and other aspects of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0100] Figure 1 depicts a block diagram of a macropixel according to an embodiment of the present disclosure;

[0101] Figure 2 depicts a block diagram of a macropixel according to another embodiment of the present disclosure;

[0102] Figure 3 A circuit diagram of a macro pixel implemented using LFSR and DRAM according to another embodiment of the present disclosure is shown;

[0103] Figure 4 A circuit diagram of a macro pixel implemented using a binary increment circuit and a DRAM according to another embodiment of the present disclosure is shown;

[0104] Figure 5 A circuit diagram of a macro pixel implemented using LFSR and SRAM according to another embodiment of the present disclosure is shown;

[0105] Figure 6A circuit diagram of a macro pixel implemented using a binary increment circuit and an SRAM according to another embodiment of the present disclosure is shown;

[0106] Figure 7 depicts a pixel and associated timing diagram for a macropixel according to an embodiment of the present disclosure;

[0107] Figure 8 Describes the Figure 7 A timing diagram of a macro pixel of multiple pixels;

[0108] Figure 9a A sensor including a plurality of macro pixels according to an embodiment of the present disclosure is shown; and

[0109] Figure 9b Depicted Figure 9a A cross-sectional view of the sensor. DETAILED DESCRIPTION

[0110] Figure 1 A block diagram of a macropixel 100 is depicted in accordance with an embodiment of the present disclosure.

[0111] The example macropixel 100 includes a plurality of pixels, namely a first pixel 105a, a second pixel 105b, and a third pixel 105c. For purposes of example, only three pixels 105a, 105b, 105c are depicted, but it will be understood that in embodiments of the present disclosure, as few as two or more than three pixels may be implemented in a macropixel.

[0112] As reference below Figures 2 to 7 As described in more detail in the example of FIG. 1 , each pixel 105a, 105b, 105c includes a SPAD and associated circuitry. For example, as shown below with reference to Figure 3 As described for pixel 305, such associated circuits may include circuits for sampling and holding voltage levels, circuits for resetting the SPAD, circuits for quenching the SPAD, and the like.

[0113] The macro pixel 100 also includes a memory 110. Figures 1 to 6 In the example macropixel described, the memory 100 is an SRAM or a DRAM. It will be understood that this memory implementation is provided for exemplary purposes only, and in other examples, the memory 100 may be implemented as another memory type, such as a phase change RAM (PCRAM), a synchronous dynamic RAM (SDRAM), a spin transfer torque RAM (STTRAM), etc.

[0114] The memory 110 is configured to store a plurality of counts, such as may be used with associated counter circuits to implement the values ​​of the counters. Such counts may be stored as words in the memory 110. In an example, the memory 110 is configured to store: a first count 115a associated with a first pixel 105a; a second count 115b associated with a second pixel 115b; and a third count 115c associated with a third pixel 105c.

[0115] In some embodiments, as shown below Figure 4 and Figure 6 As described in more detail by way of example, each count 115a, 115b, 115b may correspond to the value of a binary counter.

[0116] In some embodiments, as shown below Figure 2 , Figure 3 and Figure 5 As described in more detail by way of example, each count 115a, 115b, 115b may correspond to a value or code representing a state of a linear feedback shift register (LFSR).

[0117] The memory 110 is also configured to store a plurality of saturation bits. In an example, the memory 110 is configured to store: a first saturation bit 120a associated with the first count 115a; a second saturation bit 120b associated with the second count 115b; and a third saturation bit 120c associated with the third count 115c.

[0118] The macropixel 100 also includes a saturation detection circuit 125 configured to enable recharging of each SPAD in each pixel 105a, 105b, 105c based on the state of the corresponding saturation bit 120a, 120b, 120c. That is, the saturation detection circuit 125 provides a signal 125a, 125b, 125c to each pixel 105a, 105b, 105c based on the state of the corresponding saturation bit 120a, 120b, 120c to control the operation of each pixel 105a, 105b, 105c.

[0119] Macropixel 100 also includes processing circuitry 130. Figure 1 In the example, processing circuitry 130 is illustrated as a feature of macropixel 100, but in other examples, macropixel 100 may be directly coupled to processing circuitry 130 that is not a feature of macropixel 100. For example, two or more macropixels 100 may be coupled to a common processing circuitry 130.

[0120] In an example, the processing circuit 130 may be configured to read out each count 115a, 115b, 115b and each associated saturation bit 120a, 120b, 120c at the end of a frame time.

[0121] In an example, the processing circuit can be configured to read out each count 115a, 115b, 115b by clocking the corresponding pixel 105a, 105b, 105c for at least a number of cycles corresponding to a number of memory cells associated with the pixel 105a, 105b, 105c while keeping the corresponding pixel 105a, 105b, 105c in a reset state.

[0122] In an example, the processing circuit 130 may additionally be configured to read out a saturation bit 120a, 120b, 120c associated with each count 115a, 115b, 115b.

[0123] As described in more detail below, the macropixel 100 may be configured such that access to the memory 100 by each pixel 105a, 105b, 105c may be provided on a time multiplexed basis (eg, a round-robin basis).

[0124] refer to Figures 2 to 7 The operation of the macropixel 100 is described in more detail in accordance with the corresponding specific embodiments of FIG.

[0125] Figure 2 A block diagram of a macropixel 200 according to another embodiment of the present disclosure is shown.

[0126] The macropixel 200 includes a plurality of pixels 205 , which are labeled “N High-Z SPAD Front Ends”.

[0127] The term "SPAD front end" will be understood to refer to a SPAD-based pixel, such as a SPAD, and circuitry associated with the SPAD. As described in more detail below, for example, such associated circuitry may include circuitry for sampling and holding voltage levels, circuitry for resetting the SPAD, circuitry for quenching the SPAD, etc. Figure 3 Describes the high-impedance (“High-Z”) state of each pixel.

[0128] The example macropixel 200 includes a DRAM memory 210. The memory 210 is configured to store N counts, such as may be used with associated counter circuits 235 to implement counter values, each count having M bits. Thus, the memory 210 is depicted as an "N×M bit memory."

[0129] The memory 210 is also configured to store N saturation bits 220 , wherein a saturation bit 220 is associated with each count.

[0130] Each count stored in memory 210 corresponds to a value representing the state of a linear feedback shift register (LFSR). Example counter circuit 235 includes LFSR logic, such as logic that provides XOR feedback and shift operations, where counter circuit 235 is provided to update the count.

[0131] As described above, an implementation of a LFSR is provided for example purposes only, and alternative or additional circuits may be implemented. That is, the photon count incrementing circuit may be implemented as a binary counter, a LFSR, or another circuit configured to increment, decrement, or otherwise advance or sequence through defined states.

[0132] The macropixel 100 also includes a saturation detection circuit 225 configured to detect whether any of the N counts has been saturated and set a corresponding saturation bit 220 , and further enable recharging of each corresponding SPAD of each pixel in the N pixels 205 based on the state of the corresponding saturation bit 220 .

[0133] That is, the saturation detection circuit 225 provides a signal ( ) to each of the N pixels 205 based on the state of the corresponding saturation bit 220. Figure 2 ), to control the operation of each of the N pixels 205.

[0134] Figure 2 Also described in the N read-write-precharge control circuit 250, for controlling the access of the N pixels 205 to the N×M memory 210, as shown in reference Figure 3 Describe in more detail.

[0135] N read-write-precharge control circuits 250 provide precharge, read and write signals to the memory 210 to implement updates to the counts stored in the memory 210 based on the signals "Photon<n-1:0>" received from the corresponding N pixels 205. A signal "Rst<n-1:0>" for holding the SPAD in each of the N pixels 205 in a reset state is also depicted, as described below with reference to Figures 3 to 6 The more detailed embodiments are described in detail.

[0136] Now turn to Figure 3 , which depicts a circuit diagram of a macro pixel 300 implemented using LFSR and DRAM. The circuit diagram of the macro pixel 300 generally corresponds to Figure 2 An example macro pixel 200 is shown.

[0137] The macro pixel 300 includes N pixels, but for illustration purposes, only a single pixel 305 is shown. The pixel 305 corresponds to Figure 2 One of the “N High-Z SPAD front ends” of the macropixel 200.

[0138] The example macropixel 300 includes a DRAM memory 310. The memory 310 is configured to store N counts, such as may be used with an associated counter circuit 335 to implement a counter value, each count having M bits. Thus, the memory 310 includes an N×M arrangement of memory cells for storing N counts, each count having M bits.

[0139] exist Figure 3 In the example of , each memory cell is implemented as a three-transistor (3T) cell. It will be appreciated that in other embodiments, each DRAM cell may be implemented as any of a two-transistor configuration, a three-transistor configuration, or a four-transistor configuration, for example. Furthermore, in embodiments, these cells may be implemented as NMOS gain cells or PMOS gain cells. Furthermore, other dense memory types may be implemented, such as 1T1C trench DRAM memory cells.

[0140] exist Figure 3 In an example N×M arrangement of memory cells, each memory cell includes a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are connected in series to a bit line bi<1:k-1>, and the third transistor is connected between an input line bi<0:k-2> and a gate of the first transistor (which actually acts as a storage node).

[0141] The read signal Rd<0:n-1> provides a control signal to the gate of each second transistor, and the write signal Wr<0:n-1> provides a control signal to the gate of each third transistor.

[0142] When data is to be read from a cell having a count of bits 0 to n, a read signal Rd<0:n-1> may be asserted, and data may be read through corresponding bit lines bi<1:k-1>.

[0143] When the count is incremented (eg, written), the write signal Wr<0:n-11> can be asserted, and the data from the input line bi<0:k-2> can be written to the corresponding memory cell. Each count can be maintained by a cyclic refresh operation of the DRAM memory cell until a new count is written.

[0144] Each count stored in memory 310 corresponds to a value representing the state of a linear feedback shift register (LFSR). Counter circuit 335 includes XOR feedback logic for implementing the LFSR to sequentially update the counts stored in memory 310. Figure 3 As shown, each of the bit lines "bi" is provided as a feedback signal to a XOR gate to increment the LFSR.

[0145] The memory 310 also includes a memory cell configured to store N saturation bits 320 , wherein a saturation bit 320 is associated with each count.

[0146] The first and second transistors of each saturation bit are connected in series to the saturation signal "sat", and the third transistor of each saturation bit is connected between the input line "nextSatb" and the gate of the corresponding first transistor of each saturation bit (which actually acts as a storage node).

[0147] The read signal Rd<0:n−1> provides a control signal to the gate of each second transistor of the saturation bit 320 , and the write signal Wr<0:n−1> provides a control signal to the gate of each third transistor of the saturation bit 320 .

[0148] The “nextSatb” signal is generated by a saturation detection circuit 325 which is configured to detect whether any of the N counts has been saturated and set the corresponding saturation bit 320 , and further enable recharging of each corresponding SPAD of each pixel in the N pixels 305 based on the state of the corresponding saturation bit 320 .

[0149] Figure 3 4 also depicts a memory access control circuit 340 according to some embodiments of the present disclosure, for generating a read signal Rd<0:n-1> and a write signal Wr<0:n-1> to perform count increment / decrement and refresh operations.

[0150] The example pixel 305 includes a SPAD 350. As is known in the art, the operation of the SPAD 350 is based on the pn junction of the SPAD 350 being biased outside of its breakdown region, which is referred to as operation in the "Geiger" region. The high reverse bias voltage produces an electric field of sufficient magnitude that a single charge carrier introduced into the depletion layer of the SPAD 350 may cause the development of a self-sustaining avalanche current due to impact ionization caused by one or more incident photons. In use, the avalanche can be "quenched" by a quenching circuit to allow the SPAD 350 to be reset, thereby enabling further detection of photons.

[0151] In example pixel 305 , the cathode of SPAD 350 is coupled to a high voltage supply line (denoted as VHV). The anode of the SPAD is coupled to a recharge transistor 355 , which can be configured by a signal Vcas coupled to the gate of the recharge transistor 355 to recharge the SPAD 350 .

[0152] The example pixel 305 also includes a transfer gate 360. The transfer gate 360 ​​includes a pair of transistors that can be configured by a sampling signal "Smp" to couple the voltage VSPAD generated by the SPAD 350 at the recharge transistor 355 to a capacitor 365. The transfer gate 360 ​​and the capacitor 365 effectively act as a sample and hold circuit. The pixel 305 also includes a sample and hold reset transistor 370 for resetting the voltage at the capacitor 365.

[0153] The recharge transistor 355 is gated by a quenching transistor 375 and a gate transistor 380 arranged in series. The gate of the quenching transistor 375 is controlled by the aforementioned "NextSatb" signal. The gate of the gate transistor 380 is controlled by the "Wrint" signal generated by the aforementioned memory access control circuit 340.

[0154] A clamping diode 385 is provided to limit the excessive bias voltage generated across the SPAD 350 to prevent damage to the SPAD 350 during use.

[0155] In use, pixel 305 can operate in a mode referred to as "high impedance quenching", wherein, after SPAD 350 is triggered (e.g., after a photon strike event occurs), pixel 305 is configured to hold the SPAD voltage on its own parasitic capacitance until transfer gate 360 ​​is configured to enable the voltage to be transferred to capacitor 365. That is, quench transistor 375 and gate transistor 380 can be configured to effectively cut off the quenching path to ground. In this way, pixel 305 can be configured such that: after SPAD 350 is triggered high, SPAD 350 maintains its state until a subsequent reset (e.g., high impedance quenching).

[0156] That is, pixel 350 is configured as a "high Z SPAD quench and sample-and-hold pixel," effectively implementing a dynamic D-type sampler in a compact area.

[0157] For purposes of example, several alternative embodiments of macropixels are also disclosed.

[0158] Figure 4 FIG. 4 is a circuit diagram of a macro pixel implemented using a binary increment circuit and a DRAM according to another embodiment of the present disclosure.

[0159] The characteristics of macro pixel 400 generally correspond to Figure 3 The features of the macro pixel 300 are not described in detail for the sake of brevity.

[0160] and Figure 3Compared to the macropixel 300 of FIG. 4 , the counter circuit 435 of the macropixel 400 includes binary increment or decrement logic instead of logic for implementing an LFSR. Thus, each count stored in the memory can be incremented or decremented by the counter circuit 435. That is, each of the bit lines "bi" is provided as a feedback signal to the binary increment or decrement logic to increment or decrement each count stored in the memory.

[0161] In addition, Figure 3 The saturation detection circuit 425 is also different compared to the macropixel 300 of FIG. That is, in the macropixel 400, the "nextSatb" signal is generated by the saturation detection circuit 425, which is configured to: detect whether any of the N counts has been saturated and set the corresponding saturation bit 420, and further enable the recharging of each corresponding SPAD of each pixel in the N pixels 405 based on the state of the corresponding saturation bit 420. The detection of saturation is based on the detection of the most significant bit (MSB) carry bit being set, which indicates that the corresponding count has reached a maximum value (or, if decrementing, a minimum value).

[0162] For example Figure 3 The selection of the LFSR implementation shown or the binary increment / decrement implementation as shown in macrocell 400 may be based on a number of factors.

[0163] As mentioned above, the LFSR requires the implementation of XOR feedback logic, which in the example can be implemented with about 16 transistors (16T) as well as logic for shift operations. This can reduce the total transistor count of the macro pixel relative to the binary increment / decrement implementation. However, the LFSR may require the implementation of LFSR to binary decoding circuitry. This LFSR to binary decoding circuitry can be implemented outside the pixel area of ​​the macro cell.

[0164] Similarly, a binary increment / decrement may be implemented with a chain of full adder circuits. This may exhibit a relatively large area overhead compared to an LFSR implementation. An example implementation of a binary increment / decrement circuit may have approximately 44 transistors per count (i.e., N×44T), and may exhibit a carry chain to account for delays.

[0165] The area per SPAD of the circuitry associated with up / down counting and providing saturation detection can be arbitrarily reduced by the degree of sharing between counts (e.g., by the size of N). However, a larger N may also result in more time multiplexing and therefore a lower maximum SPAD count rate and dynamic range.

[0166] Therefore, a design trade-off between binary and LFSR implementation can be made based on specific application requirements and a specific CMOS technology node.

[0167] Figure 5 and Figure 6 Generally correspond to Figure 3 and Figure 4 , where the memory is implemented as SRAM instead of DRAM.

[0168] Figure 5 A circuit diagram of a macropixel 500 implemented using LFSR and SRAM according to another embodiment of the present disclosure is shown. Each SRAM cell is implemented as a 6-transistor (6T) SRAM cell. Figure 6 A circuit diagram of a macropixel 600 implemented using a binary increment / decrement circuit and SRAM according to another embodiment of the present disclosure is depicted. Each SRAM cell is implemented as 6TSRAM cells.

[0169] The choice between SRAM and DRAM implementations can depend, for example, on the particular CMOS technology node in which the device is fabricated and the power requirements of the particular application. In either case, the implementation of the counter circuit and the count stored in SRAM or DRAM memory can be substantially more area efficient than an implementation of a logic counter (e.g., a D-type flip-flop based counter).

[0170] For example: the area of ​​a 1-bit high-density SRAM implemented in CMOS can be about 1 / 20 of that of a single counter D-type flip-flop; the area of ​​a 1-bit 3T gain unit DRAM implemented in CMOS can be about 1 / 40 of that of a single counter D-type flip-flop; and the area of ​​a 1-bit 1T1C trench DRAM implemented in CMOS can be about 1 / 100 of that of a single counter D-type flip-flop.

[0171] A more detailed comparison of a logic counter based solution (rather than the disclosed use of a memory cell to store a count) and associated increment / decrement circuits is shown below.

[0172] A logic counter using standard logic might require 20T per bit. The readout circuitry might require an additional 4T per bit. Therefore, for an N-bit counter with an additional saturation bit, the area per pixel is:

[0173] The area of ​​each pixel = (20+4)(N+1)T+AFE

[0174] Here, “AFE” is the area of ​​the pixel’s analog front end (e.g., SPAD device).

[0175] In contrast, for the disclosed shared memory based macropixel implementation (where the memory is configured to store M counts, each count having N bits and an associated saturation bit), the area of ​​each pixel can be expressed as:

[0176] Area per pixel = (((N+1)×memory bit size×M)+((N+1)×memory increment logic)+M×(address logic) (LFSR, state detection and readout tri-state)) / M

[0177] Assuming that the LFSR, state detection, and readout tri-states include 12T+12T+4T=28T, and assuming that the address logic (eg, memory access control circuit 340) is 2NAND+2NOR=16T per pixel, the area of ​​each pixel can be expressed as:

[0178] Area of ​​each pixel = (N+1)T / 20+16T+(16N+1)T / M+28T / M (for SRAM)+AFE

[0179] Applying this to each of the memory types mentioned above (e.g., high-density SRAM, 3T gain cell DRAM, and 1T1C DRAM), the area per pixel can be expressed as:

[0180] The area of ​​each pixel is (N+1)T / 20+16T+(9N+1)T / M+28T / M (for high-density SRAM)+AFE;

[0181] Area per pixel = (N+1)T / 40+16T+(9N+1)T / M+28T / M (for 3T gain cell DRAM)+AFE; and

[0182] The area of ​​each pixel is (N+1)T / 100+16T+(9N+1)T / M+28T / M (for 1T1C DRAM)+AFE.

[0183] As an example configuration of a macropixel, each count may include 12 bits (N=12), and there may be 16-way sharing of the memory, e.g., 16 counts stored in the macrocell (M=16). Based on this example configuration, and excluding the AFE for each pixel, the total area contribution for each pixel would be: 312T (for the logic counter); 31.4T (for Figure 5 SRAM-based implementation); 24.8T (for Figure 3 3T gain cell DRAM-based embodiments); and 23.9T (for 1T1C DRAM-based embodiments).

[0184] Thus, it can be seen that the disclosed embodiments employing a pixel shared memory array may require approximately one-tenth the area per pixel compared to a logic counter based solution, and thus may access an area achieving approximately ten times the resolution due to the increased pixel density.

[0185] The operation of the macro-pixels 300, 400, 500, 600 is as follows.

[0186] The disclosed macropixels 300, 400, 500, 600 are intended to achieve SPAD photon counting using digital circuitry in an extremely compact (eg, small die size) form factor with low power consumption. Figure 9b As described in more detail, the disclosed macropixels 300 , 400 , 500 , 600 may utilize wafer-level 3D integration of back-illuminated SPADs disposed above digital circuitry.

[0187] The power consumption of image sensors based on SPAD arrays can be higher than that of pinned photodiode CMOS image sensors because each SPAD can consume a relatively large charge for each detected photon that triggers an avalanche event. This charge can flow through a relatively high bias voltage, thereby increasing the power proportionally.

[0188] The power consumption of the SPAD can be managed by keeping the SPAD below its reverse bias breakdown voltage. Thus, in embodiments of the present disclosure, a high gain mode (e.g., operation in the Geiger region) can be used at a relatively low duty cycle, where the duty cycle is selected so as to provide the shortest duration high gain mode to achieve a desired signal-to-noise ratio (SNR).

[0189] In the example macropixels 300 , 400 , 500 , 600 , a target SNR (related to the number of photons, and thus the counting bit depth) may be selected by design, wherein when the target count is reached, detection of photons may be suppressed.

[0190] This can be achieved using high impedance quenching and clocked recharging. The SPAD in each pixel can be repeatedly reset on a clock pulse so that the SPAD can be kept above the breakdown level, such as in Geiger mode, in a high impedance state. When a photon triggers an avalanche effect in the SPAD, the SPAD discharges its own capacitance, thereby reducing the excess bias to below the breakdown level, such as entering sub-Geiger mode, thereby achieving self-quenching.

[0191] The proposed pixel structure (eg, pixel 305 ) achieves single photon counting with relatively high compactness and relatively low power consumption simultaneously.

[0192] The disclosed embodiments rely on the principles of time multiplexed sharing of counts (eg, counts 115a, 115b, 115c) stored in memory cells and time multiplexed SPAD clock controlled recharging.

[0193] That is, greater pixel compactness can be achieved compared to prior art SPAD-based sensors by using three mutually complementary elements. The first element is a dense memory for storing the photon counting states of multiple pixels, e.g. Figure 3 and Figure 4 Embodiments of the DRAM, Figure 5 and Figure 6 SRAM, or advanced memory (e.g., STT-MRAM, PCRAM), etc. of the embodiments.

[0194] The second element is the time-multiplexed sharing of memory access and increment logic between multiple SPADs.

[0195] The third element is incrementing logic implemented with very low logic overhead, such as the LFSR described above.

[0196] In the disclosed embodiments, time multiplexed incrementing of access to the shared memory can be conveniently combined with time multiplexed clocked recharging of the SPADs. This provides a technical advantage in reducing the peak power draw from the high voltage supply of each SPAD compared to synchronous global recharging of the SPAD matrix.

[0197] Turn again Figure 3 In the example embodiment of FIG. 5 , N SPADs 305 are configured to share access to an N×M bit memory 310 on a round-robin time multiplexing basis.

[0198] As described above, each SPAD 305 has a separate recharge transistor 355 and a sample and hold circuit provided by a transmission gate 360 ​​and a capacitor 365 .

[0199] In operation, the sample and hold circuit samples and holds the state of each SPAD 305 (e.g., signal “Photon <n-1:0>”, where the sampling and holding circuit is controlled by a cyclic control signal “Smp<n-1:0>”.

[0200] After each SPAD state is sampled, the corresponding SPAD is immediately recharged.

[0201] The recharge signal is gated by a saturation bit 320 "sat<N-1:0>" stored in memory for each detector (which indicates whether the stored SPAD count has reached saturation). That is, the saturation detection circuit is configured to gate the recharging of each SPAD 305 based on the state of the corresponding saturation bit 320.

[0202] The memory access control circuit 340 (which controls read, write and precharge operations for accessing the memory 310) uses the sampled state indicated by the signal "Photon<N-1:0>" to select a single row i of the memory 310 to increment or decrement corresponding to the SPAD 305 selected in the cycle.

[0203] Each "Photon" signal can be used to gate the global ExtRdb and ExtWrb clocks to generate memory row specific Rd and Wr signals, which read and write the increment / decrement state of the i-th SPAD photon count, respectively. The increment block (e.g., counter circuit 335) obtains the read state of the photon count b of SPAD i and increments the count to rewrite it to the i-th row of memory.

[0204] As described above, in some embodiments, counter circuit 335 may implement a LFSR, and in some embodiments, counter circuit 435 may include binary increment (or decrement) logic.

[0205] As described above, some features of each macropixel 300, 400, 500, 600 are replicated for each pixel, and some features of each macropixel 300, 400, 500, 600 can be shared by each pixel. For example, each pixel has an associated m bits of memory for storing an associated count. Using a dense memory cell structure (e.g., 3T DRAM memory cells) can mitigate the area impact of such non-shared features.

[0206] Similarly, each pixel 305 has its own recharge and sampling circuit. As described above, each pixel 305 can be implemented with as few as six transistors (i.e., recharge transistor 355, two transistors used to form transfer gate 360, sample and hold reset transistor 370 controlled by Rdb, quench transistor 375, and gating transistor 380).

[0207] Other features replicated for each pixel 305 include memory access control circuitry 340. To mitigate the area impact of memory access control circuitry 340, Figures 3 to 7 Area efficient circuits are depicted in the embodiments of FIG. 3. For example, for DRAM-based macrocells 300, 400, the memory access control circuit 340 includes pairs of NOR gates and NAND gates, which may include as few as 16 transistors. For the disclosed SRAM-based macrocells 500, 600, the memory access control circuit includes only a single NAND and a pair of NORs for each SPAD.

[0208] In an example embodiment, saturation detection may be implemented by detecting the final state of the m-bit count.

[0209] In macro-pixels 300, 400 using LFSR codes, an m-input NOR may be used to test for re-encountering the initial state of the m-bit count.

[0210] In macropixels 500, 600 using binary counting, it may be sufficient to test the most significant bit (MSB) carry bit from the counter circuit. This bit can be stored in an additional memory bit as a saturation bit for each SPAD and read out as an indication of the saturation state.

[0211] Therefore, each SPAD has a memory bit that indicates whether the photon count has reached saturation. If this bit is set, the SPAD is inhibited from resetting and will remain in sub-Geiger mode, consuming very little power. This is achieved by the series connection of the Wrint signal indicating the currently addressed SPAD and the nextsatb signal generated by detecting saturation of the i-th SPAD photon count. Advantageously, the series connection achieves conditional open-drain high-Z recharging of the SPAD without the need for additional logic.

[0212] That is, SPADs whose counts have been saturated are therefore maintained in a high cutoff state where they are biased below the breakdown voltage, thereby saving power for pixels with high detectivity.

[0213] The power consumption of pixels can be measured by ExtRdb and ExtWrb as well as Smp <n-1:0>These can be set to a minimum frequency related to DRAM leakage or a maximum frequency related to the DRAM update time 1 / (N×(TRd+TWr)).

[0214] If the saturation bit sat is set, the state of the SPAD will subsequently always be sampled high, indicating that the SPAD has triggered. This will cause the SPAD count to increment in each subsequent cycle period until the end of the frame - at which point the saturation bits of all SPADs are reset. In this way, the counter state now indicates the number of cyclic refresh cycles from the saturation time of a single SPAD to the end of the frame. From this information (i.e., the saturation bit of SPAD i and the counter value of SPAD i), a higher dynamic range photon count can be constructed without affecting the signal-to-noise ratio. In an embodiment, the saturation bit set to 1 can indicate that the count should be interpreted as the number of recharge cycles until the end of the frame, rather than the number of photon impact events.

[0215] That is, when recharging of one or more SPADs in one or more pixels of the plurality of pixels is enabled, the associated one or more counts may be used to indicate the time since the corresponding saturation bit indicated that the count was saturated.

[0216] If the saturation bit of SPAD i is not set, the counter value of SPAD i represents the number of detected photons. A SPAD with a high count rate will reach saturation faster and be inhibited earlier, saving most of the power.

[0217] At the end of a frame, all bits in memory 310 can be read out by addressing each memory row in turn. Figure 3 and Figure 4 In an LFSR implementation of , this can be achieved by simply clocking each pixel 305 (Rst = 1m times for each corresponding row of memory cells) and reading a bit from Dout on the output column line shared by all pixels 305 on the column. This will advantageously have the effect of resetting the corresponding row of memory cells simultaneously. The saturation bit Dsat associated with each count will also be read out.

[0218] In a binary implementation, it may be necessary to add a tri-state gate for each .Readout may be achieved by a rolling shutter (eg, row-by-row readout of the memory).

[0219] The macropixel may include processing circuitry configured to read out each count and each associated saturation bit at the end of a frame time (e.g., circuitry for sequentially addressing each memory row), and to read out each count by clocking the corresponding pixel for at least a number of cycles corresponding to a number of memory cells associated with the pixel while maintaining the corresponding pixel in a reset state.

[0220] DRAM based macropixels 300, 400 require a refresh operation. In an embodiment this can be accomplished by additional logic to cause an increment of 0 if the SPAD 305 is not triggered, or by adding / subtracting a predetermined number of additional periodic refresh cycles (which increments / decrements the memory by a fixed offset to the output code), which can be accounted for later after readout.

[0221] Figure 7 Depicted is a pixel 705 for a macropixel and an associated timing diagram in accordance with an embodiment of the present disclosure.

[0222] In example pixel 705 , the cathode of SPAD 750 is coupled to a high voltage supply line (denoted as VHV). The anode of the SPAD is coupled to a recharge transistor 755 , which can be configured by a signal Vcas coupled to the gate of the recharge transistor 755 to recharge the SPAD 750 .

[0223] The example pixel 705 also includes a transfer gate 760. The transfer gate 760 includes a pair of transistors that can be configured by a sampling signal "Smp" to couple the voltage VSPAD generated by the SPAD 750 at the recharge transistor 755 to a capacitor 765. The transfer gate 760 and the capacitor 765 effectively act as a sample and hold circuit. The pixel 705 also includes a sample and hold reset transistor 770 for resetting the voltage at the capacitor 765.

[0224] Pixel 705 generally corresponds to Figure 3 The pixel 305 does not include a separate quenching transistor 375 and a selection transistor 380. For the purpose of simplifying the illustration, only a single quenching transistor 775 is depicted. The quenching transistor 775 is controlled by a signal "SPADRst", where SPADRst="WrInt&NextSatb.

[0225] The recharge transistor 755 is controlled by the quenching transistor 775 .

[0226] A clamping diode 785 is provided to limit the excessive bias voltage generated across the SPAD 750 to prevent damage to the SPAD 750 during use.

[0227] In use, pixel 705 can operate in a mode referred to as "high impedance quenching", wherein, after SPAD 750 is triggered (e.g., after a photon strike event occurs), pixel 705 is configured to hold the SPAD voltage VSPAD on its own parasitic capacitance (which is represented as capacitor Cp) until transfer gate 760 is configured to enable this voltage (i.e., charge) to be transferred to capacitor 765. That is, quenching transistor 775 can be configured to effectively cut off the quenching path to ground. In this way, pixel 705 can be configured such that: after SPAD 750 is triggered high, SPAD 750 maintains its state until a subsequent reset (e.g., high impedance quenching). That is, pixel 750 is configured as a "high Z SPAD quench and sample and hold pixel", effectively implementing a dynamic D-type sampler in a compact area.

[0228] That is, a macro-pixel using the disclosed pixel 705 may be configured such that when a photon triggers the SPAD, the SPAD discharges its internal capacitance, thereby bringing the excess bias voltage of the SPAD below the breakdown voltage.

[0229] The operation of the pixel 750 is described in the accompanying timing diagram. It can be seen that the signal SPADRst is periodically negated at a relatively low duty cycle, and the sample and hold transmission gate 760 is periodically clocked at the same rate, so that the state of the SPAD (e.g., voltage VSPAD) can be periodically sampled, and when not sampled, the pixel is held in a high-Z quenched state.

[0230] In use, signal Photon (which as described above can be used to gate the global RdInt and WrInt clocks to generate memory row specific Rd and Wr signals, which read and write the incrementing state of the i-th SPAD photon count, respectively) remains low during the low state of Smp.

[0231] It is worth noting that the capacitance of capacitor Cp is substantially larger than that of capacitor 765, so that charge sharing on the rising edge of Smp maintains the reset SPAD state.

[0232] It can be seen that when the signal SPADRst is high, the SPAD 750 is quenched, for example, the voltage VSPAD, which may be high due to a photon strike event, is reset to a low voltage.

[0233] It can be seen that if VSPAD is high when signal Smp is high, then signal Photon is asserted, indicating a photon impact event.

[0234] Figure 8 Depicts a timing diagram for an example of a macropixel comprising four pixels, each pixel being clocked according to Figure 7 The description of the pixels to be operated on.

[0235] Of note, the cyclic time multiplexing of the pixels is clearly depicted, where the SPADRst and smp signals of each pixel are asserted in sequence, enabling cyclic sampling of VSPAD<0>, VSPAD<1>, VSPAD<2>, and VSPAD<3> in sequence.

[0236] Furthermore, the disclosed macropixel configuration is capable of generating time-resolved information.

[0237] For example, it can be assumed that each SPAD in macro-pixel reset is held for 1 / N of the cycle time for N-way SPAD sharing. This means that a laser pulse return (from VSEL etc.) that falls in the i-th SPAD reset window will not generate a signal within the distance between i / N and i+1 / N of the distance range. This can therefore enable indirect time-of-flight (iToF) style distance calculations.

[0238] This can allow full resolution intensity pattern imaging or macro-pixel based range imaging that can account for distance. In some examples, full resolution intensity pattern imaging and macro-pixel based range imaging that can account for distance can be achieved because the background light will not be affected by the time-dependent light that is only reset.

[0239] In an example embodiment, a 4x4 macropixel (e.g., 16 pixels) would allow for an effective 16-bin histogram. The distance can be explained by the pixel with the lowest signal (e.g., lowest count) which does not integrate the return pulse compared to other pixels which integrate the return pulse 15 / 16 of the time.

[0240] Figure 9a Depicted is a plan view of an example of a sensor 900 including a plurality of macropixels 905 - 1 through 905 - 9 according to an embodiment of the present disclosure. Figure 9b A cross-sectional view of sensor 900 along line AA is depicted.

[0241] The sensor 900 may be configured as an image sensor, but as described above, such a sensor may be capable of determining time-resolved information and thus may additionally or alternatively be configured to operate as a time-of-flight sensor.

[0242] In an example embodiment, the sensor 900 includes only 9 macropixels 905-1 to 905-9. Each macropixel may be a macropixel 300, 400, 500, 600 as described above.

[0243] Macropixels 905-1 to 905-9 are formed on a substrate 910. In an example, macropixels 905-1 to 905-9 are arranged as a regular array of macropixels. Each macropixel 905-1 to 905-9 includes a plurality of pixels. As just one example, each macropixel may include an array of 4×4 pixels.

[0244] In other embodiments, a macropixel array may be used to implement a "megapixel array," eg, an array including hundreds of thousands or millions of pixels (including substantially multiple macropixels).

[0245] Also shown is processing circuitry 915 , which may be configured to read out the memory array of each macropixel 905 - 1 to 905 - 9 of sensor 900 .

[0246] The macro pixel 900 is formed as a monolithic device manufactured on a single substrate, for example, rather than being formed by coupling a plurality of discrete devices.

[0247] Due to the compactness of macrocells 905-1 to 905-9 (i.e., because the macrocells correspond to new macrocells 300, 400, 500, 600), the power consumption of the SPAD of each macrocell can be reduced relative to SPAD arrays of the prior art because the pitch of the SPAD can be reduced and therefore the capacitance can also be reduced.

[0248] In addition, if Figure 9b When viewed from a cross section, it can be seen that the circuitry of each macropixel 905-1, 905-2, 905-3 (e.g., at least the memory array 920-1, 920-2, 920-3) is formed in the substrate 910, and the pixels 925-1, 925-2, 925-3 (or at least the SPADs of these pixels) associated with each macropixel 905-1, 905-2, 905-3 are formed above the corresponding memory array 920-1, 920-2, 920-3. The memory array 920-1, 920-2, 920-3 is formed in an area of ​​the substrate 910, and the plurality of pixels 925-1, 925-2, 925-3 is formed directly above the memory array 920-1, 920-2, 920-3.

[0249] That is, due to the extremely compact size of the circuitry in each macropixel 905-1, 905-2, 905-3, the disclosed macropixels 905-1, 905-2, 905-3 can utilize wafer-level 3D integration of back-illuminated SPADs disposed above digital circuitry, such as Figure 9b Depicted.

[0250] Although the present disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and the claims are not limited to these embodiments. In view of this disclosure, those skilled in the art will be able to make modifications and substitutions, which are considered to fall within the scope of the appended claims. Each feature disclosed or shown in this specification, whether alone or in any suitable combination with any other feature disclosed or shown herein, can be included in any embodiment.

[0251] Reference numerals

[0252] 100 macro pixels

[0253] 105a First Pixel

[0254] 105b second pixel

[0255] 105c Third Pixel

[0256] 110 Memory

[0257] 115a First Count

[0258] 115b Second Count

[0259] 115c Third Count

[0260] 120a first saturation position

[0261] 120b second saturation bit

[0262] 120c third saturation position

[0263] 125 Saturation Detection Circuit

[0264] 125a signal

[0265] 125b signal

[0266] 125c signal

[0267] 130 processing circuit

[0268] 200 macro pixels

[0269] 205N pixels

[0270] 210 Memory

[0271] 235 counter circuit

[0272] 220N saturation bits

[0273] 225 Saturation Detection Circuit

[0274] 250 read and write precharge control circuit

[0275] 300 macro pixels

[0276] 305 pixels

[0277] 310 Memory

[0278] 335 counter circuit

[0279] 320 saturation bits

[0280] 325 Saturation Detection Circuit

[0281] 340 memory access control circuit

[0282] 350SPAD

[0283] 355 Recharge Transistor

[0284] 360 Transmission Gate

[0285] 365 Capacitor

[0286] 370 Sample and hold reset transistor

[0287] 375 Quenching transistor

[0288] 380 gate transistor

[0289] 385 clamping diode

[0290] 400 macro pixels

[0291] 425 Saturation Detection Circuit

[0292] 435 Counter Circuit

[0293] 500 macro pixels

[0294] 600 macro pixels

[0295] 705 pixels

[0296] 750SPAD

[0297] 755 Recharge Transistor

[0298] 760 transmission gate

[0299] 765 capacitor

[0300] 770 Sample and Hold Reset Transistor

[0301] 775 Quenching Transistor

[0302] 785 clamping diode

[0303] 900 Sensors

[0304] 905-1 Macro Pixel

[0305] 905-2 Macro Pixel

[0306] 905-3 Macro Pixel

[0307] 905-4 Macro Pixel

[0308] 905-5 Macro Pixel

[0309] 905-6 Macro Pixel

[0310] 905-7 Macro Pixel

[0311] 905-8 Macro Pixel

[0312] 905-9 Macro Pixel

[0313] 910 substrate

[0314] 915 processing circuit

[0315] 920-1 Memory Array

[0316] 920-2 Memory Array

[0317] 920-3 Memory Array

[0318] 925-1 pixels

[0319] 925-2 pixels

[0320] 925-3 pixels.

Claims

1. A macro pixel, comprising: - a plurality of pixels, each pixel comprising a single photon avalanche diode (SPAD); - a memory configured to store: a plurality of counts, each count associated with a pixel in the plurality of pixels; and a plurality of saturation bits, each saturation bit being associated with a count in the plurality of counts; and - A saturation detection circuit configured to enable recharging of each SPAD based on the state of a corresponding saturation bit.

2. The macropixel according to claim 1, wherein: The saturation detection circuit is configured to enable recharging of each SPAD when the corresponding saturation bit indicates that the associated count has been saturated.

3. The macro pixel according to claim 1 or 2, wherein: When recharging of one or more SPADs in one or more pixels of the plurality of pixels is enabled, the associated one or more counts are used to indicate a time since the corresponding saturation bit indicated that the count was saturated.

4. The macro pixel according to claim 3, wherein: When recharging of one or more SPADs in one or more pixels of the plurality of pixels is not enabled, the associated one or more counts are used to indicate a number of detected photons.

5. A macropixel according to any preceding claim, wherein: Access to the memory is provided to each pixel on a time multiplexed basis.

6. A macropixel according to any preceding claim, wherein: When recharging of that SPAD is not enabled, each SPAD is recharged on a time multiplexed basis.

7. The macropixel according to claim 5 and 6, wherein: The time multiplexing basis is a round-robin basis.

8. A macropixel according to any preceding claim, wherein: Enabling recharging of each SPAD includes configuring at least one transistor in the corresponding pixel to maintain the SPAD in a sub-Geiger mode.

9. A macropixel according to any preceding claim, wherein: Each pixel includes at least one transistor that can be configured to maintain the corresponding SPAD in a high impedance state when the SPAD is biased in Geiger mode.

10. A macropixel as claimed in any preceding claim, configured such that when a photon triggers a SPAD, the SPAD discharges its internal capacitance such that the excess bias voltage of the SPAD is below the breakdown voltage.

11. A macropixel according to any preceding claim, wherein: Each pixel consists of: - a recharge transistor configurable to recharge the corresponding SPAD to Geiger mode; and - A sample and hold circuit for sampling and holding a voltage corresponding to the state of the corresponding SPAD.

12. A macropixel as claimed in any preceding claim, comprising shared and time multiplexed memory increment or decrement circuitry configured to increment or decrement each of the plurality of counts.

13. A macropixel according to any preceding claim, wherein: Each count corresponds to the value of a binary counter.

14. The macropixel according to any one of claims 1 to 12, wherein: Each count corresponds to a value representing the state of the linear feedback shift register LFSR.

15. A macropixel as claimed in any preceding claim, comprising processing circuitry configured to read out each count and each associated saturation bit at the end of a frame time.

16. The macropixel according to claim 15, wherein: The processing circuit is configured to read out each count by clocking the corresponding pixel for at least a number of cycles corresponding to a number of memory cells associated with the pixel while maintaining the corresponding pixel in a reset state.

17. The macropixel according to claim 16, wherein: The processing circuit is additionally configured to read out a saturation bit associated with each count.

18. The macropixel according to claim 15 or 16, wherein: When a saturation bit associated with a respective count is set and when recharging of the associated SPAD is enabled, the processing circuit is configured to use the respective count as an indication of a cyclic refresh period since the saturation bit was set.

19. A macropixel according to any preceding claim, wherein: The memory includes a static random access memory (SRAM) cell array.

20. The macropixel according to any one of claims 1 to 18, wherein: The memory comprises an array of dynamic random access memory DRAM cells.

21. The macropixel of claim 20, comprising a refresh circuit for refreshing the DRAM cell, wherein: The refresh circuit is configured as follows: - if the corresponding SPAD has not been triggered, incrementing the count by zero; or - adding a predetermined number of additional refresh cycles to the count for subsequent subtraction by the processing circuitry.

22. A macropixel as claimed in any preceding claim formed as a monolithic device.

23. A macropixel according to any preceding claim, wherein: - the memory is formed in the area of ​​the substrate; and - The plurality of pixels are formed directly above the memory.

24. An image sensor comprising an array of macropixels according to any one of claims 1 to 23.

25. A proximity sensor or a time-of-flight sensor comprising at least one macropixel according to any one of claims 1 to 23.

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