Fast radar tracking signal detection and data communication device based on FPGA

Abstract

The invention discloses a fast radar tracking signal detection and data communication device based on an FPGA (Field Programmable Gate Array), which optimizes the flow of an FPGA correlation calculation algorithm and aims to solve the problems of low efficiency and high delay of a traditional correlation detection method.According to the fast radar tracking signal detection and data communication device based on the FPGA, a sending end and a receiving end based on the FPGA are used, a modular pipeline structure is adopted, signal LFM-MSK signal modulation is carried out at the sending end, and the LFM-MSK signal modulation is carried out at the receiving end; a receiving end synchronizes and demodulates an LFM-MSK signal, a parallel computing algorithm structure is adopted in a radar tracking signal detection part, the computing speed is increased by several times compared with a traditional correlation detection method, and the time required for signal synchronization is greatly shortened while the computing precision is not affected. The method can be widely applied to the technical field of radar communication, and provides efficient performance support for a radar communication system.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a fast radar tracking signal detection and data communication device based on FPGA. Background Art

[0002] In radar applications, real-time and accurate detection and acquisition of the arrival time of the received signal is a key issue. Only when the radar correctly detects the arrival time of the received signal can it receive the received signal completely without missing any useful information. For various radar systems, especially high-precision and high-real-time application scenarios such as military radar, air traffic control radar, and weather radar, efficient radar signal detection algorithms are particularly important.

[0003] Existing radar signal detection methods mainly include frequency domain detection methods and time domain detection methods. The frequency domain detection method involves Fourier transform and inverse Fourier transform, which has large computational complexity, significant time delay, and consumes a lot of hardware resources, which is not conducive to the implementation of hardware FPGA, and is therefore not suitable for real-time signal detection.

[0004] In contrast, the time domain detection method uses the frequency characteristics of the radar signal itself to generate a reference signal that is the same as the radar signal locally. The energy of the pulse signal is accumulated continuously through the correlation accumulation of the two signals in the time domain, and finally a peak value appears, thereby determining the arrival and end time of the signal. This method has lower computational complexity and less hardware resource consumption, and is more suitable for radar systems with high real-time requirements.

[0005] As an important technology in time domain detection, correlation detection method detects the target signal by calculating the correlation between the received signal and the known reference signal. Its basic principle is to use the similarity between the known reference signal and the received signal to determine the arrival time of the received signal by calculating their correlation function. The specific steps are as follows:

[0006] Filter and denoise the received signal to reduce the impact of noise and interference;

[0007] The received signal is correlated with a known reference signal to obtain a correlation function, which reflects the similarity of the signals under different time delays;

[0008] Find the peak in the correlation function. The position and height of the peak reflect the arrival time and strength of the signal respectively.

[0009] According to the analysis result of the correlation function, it is judged whether there is a target signal. If there is a significant peak in the correlation function, it indicates that there is a received signal similar to the reference signal at this delay, which may correspond to the target echo signal.

[0010] Although the correlation detection method has obvious advantages over the frequency domain detection method in the hardware field and has been widely used in practical applications, the existing correlation detection method still has low computational efficiency and high time delay. In order to solve the above problems and improve the real-time and accuracy of radar signal detection, a fast synchronization detection algorithm is proposed. This algorithm optimizes the correlation calculation and signal processing process to achieve more efficient signal detection and synchronization, which can significantly improve the real-time and accuracy of radar signal detection and provide guarantee for the efficient operation of the radar system. Summary of the invention

[0011] The object of the present invention is to provide a fast radar tracking signal detection and data communication device based on FPGA.

[0012] The technical solution for achieving the purpose of the present invention is: a communication system based on FPGA linear frequency modulation rapid synchronization method, including an FPGA-based LFM-MSK signal generating end for simulating radar signal output, and an FPGA-based LFM-MSK signal receiving end for verifying the synchronous demodulation effect of the radar signal;

[0013] The FPGA-based LFM-MSK signal generating end includes a symbol generation module, an LFM-MSK signal modulation module and a radio frequency module; the symbol generation module is used to perform binary coding modulation on the information source, and the coding modulation includes differential coding and serial-to-parallel conversion; the LFM-MSK signal modulation module is used to process the signal output by the symbol modulation module into a digital signal with minimum frequency shift, continuous phase, linear carrier frequency change and information carrying; the radio frequency module includes a filter module, a DAC module and an antenna module, which is responsible for converting the digital signal into a radio form;

[0014] The FPGA-based LFM-MSK signal receiving end includes a wireless signal receiving end including a radio frequency receiving module, a radar signal detection module based on FPGA, a coherent demodulation module, and a differential decoding module; the radio frequency receiving module is used to convert the radio signal into a digital signal; the FPGA-based radar signal detection module obtains the carrier synchronization information; the coherent demodulation module is responsible for performing the de-carrier synchronization and MSK demodulation process, and adopts the coherent square ring demodulation method to demodulate the digital signal containing the carrier into a binary signal with a bit width of one; the binary signal is decoded by the differential decoding module to obtain the final source code information.

[0015] Compared with the prior art, the present invention has the following significant advantages:

[0016] (1) In the radar signal detection part, a parallel computing algorithm structure is adopted, which increases the calculation speed several times compared with the traditional correlation detection method. While not affecting the calculation accuracy, it greatly reduces the time required for signal synchronization;

[0017] (2) Parallel parameters are adjustable. The number of parallel structures can be increased to improve the running speed or reduced to reduce power consumption according to actual needs. The degree of freedom is extremely high and the internal resources of FPGA can be fully utilized.

[0018] (3) The present invention can be widely applied to the field of radar communication technology and provide efficient performance support for radar communication systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is the overall structure diagram of the communication system.

[0020] Figure 2 This is the conversion relationship diagram between the source signal and the orthogonal signal.

[0021] Figure 3 Generate a schematic for the LFM-MSK signal.

[0022] Figure 4 This is the FPGA implementation result diagram of the digital information modulation process.

[0023] Figure 5 This is the final signal diagram of the I and Q paths.

[0024] Figure 6 This is the structure diagram of the radar signal detection module.

[0025] Figure 7 Simulation test results for the radar signal detection module. DETAILED DESCRIPTION

[0026] At present, although the correlation detection method has been used in actual radar systems and has obvious advantages over the frequency domain detection method in the hardware field, the existing correlation detection method still has low computational efficiency and high time delay. In order to solve the above problems and improve the real-time and accuracy of radar signal detection, a fast synchronization detection algorithm is proposed. This algorithm optimizes the correlation calculation and signal processing flow by leveraging the parallel processing characteristics of FPGA, optimizes linear calculations into "surface" calculations, and realizes signal detection and synchronization more efficiently. It can significantly improve the real-time and accuracy of radar signal detection, aiming to solve the problems of inefficiency and serious delay of traditional correlation detection methods and provide guarantee for the efficient operation of radar systems.

[0027] The present invention optimizes the FPGA-related calculation algorithm process and designs a fast radar signal detection and data communication device based on FPGA, aiming to solve the problems of low efficiency and serious delay of traditional correlation detection methods.

[0028] The communication device is as follows Figure 1As shown, it includes a linear frequency modulation (LFM)-minimum shift keying (MSK) signal generating end based on FPGA, which is used to simulate radar signal output, and a LFM-MSK signal receiving end based on FPGA, which is used to verify the synchronous demodulation effect of the radar signal.

[0029] The FPGA-based LFM-MSK signal generating end comprises an FPGA-based symbol generating module, an LFM-MSK signal modulating module and a radio frequency transmitting module.

[0030] Through the FPGA symbol generation module, the data to be transmitted is differentially encoded in binary according to specific rules, and serial-to-parallel conversion is performed;

[0031] The purpose of the differential encoding is to solve the phase ambiguity problem generated when the signal receiving end performs carrier recovery on the modulated signal.

[0032] Furthermore, the differential coding expression is:

[0033]

[0034] Among them, a k is the kth bit of the data source code, b k for a k The data is differentially encoded.

[0035] The serial-to-parallel conversion is to use a serial-to-parallel converter to divide the output signal after differential encoding into two paths, I and Q, and interleave them with a code element width T. b , Figure 2 Examples are given to illustrate differential encoding and serial-to-parallel conversion rules.

[0036] The LFM-MSK signal modulation module processes the signal output by the symbol modulation module into a digital signal with minimum frequency shift, continuous phase, linear carrier frequency change and information carrying. Figure 3 The schematic diagram of the LFM-MSK signal generation process is shown.

[0037] The LFM-MSK signal modulation module first performs weighted processing on the two paths of data after differential encoding using the weighting function generated by DDS;

[0038] The weighting functions are respectively expressed as:

[0039] Where t is time, T b is the symbol period;

[0040] There is only half a period of carrier signal in each symbol period. When the transmitted data is 0, the phase of the signal is deflected by 180 degrees, and when it is 1, the phase of the signal remains unchanged. This change of carrier phase carries the digital signal. Figure 4 The FPGA implementation results of the digital information modulation process are given, where msk_i is the result after the I branch is modulated, and msk_q is the result after the Q branch is modulated.

[0041] The two weighted signals are respectively subjected to linear frequency modulation orthogonal carrier signals cos(ω c t+πμt 2 ) and sin(ω c t+πμt 2 ) are modulated and superimposed.

[0042] Among them, ω c is the initial carrier frequency, μ is the linear frequency modulation coefficient, which is expressed as the frequency change rate of the linear frequency modulation signal.

[0043] The modulated signal is the LFM-MSK signal carrying the symbol information, and its expression S LFM-MSK for:

[0044]

[0045] Among them, I k , Q k ∈{±1} and carries code element information.

[0046] The final signal multiplied by the carrier signal is Figure 5 As shown, msk_lfm_i is the final signal of I branch modulation, and msk_lfm_q is the final signal of Q branch modulation.

[0047] The filter module, DAC module and antenna module of the radio frequency transmission module belong to the hardware circuit part, which is responsible for converting the digital signal into radio form.

[0048] The FPGA-based LFM-MSK signal receiving end includes a radio frequency receiving module, a radar signal detection module based on FPGA, a coherent demodulation module, and a differential decoding module;

[0049] The antenna module, ADC module and filter module of the radio frequency receiving module belong to the hardware circuit part and are responsible for converting the radio signal into a digital signal.

[0050] The antenna module can receive radio signals in space and send them to the ADC module in the form of analog signals;

[0051] The analog signal is converted into a digital signal through the ADC module, the digital signal is extracted and filtered by the filter module, and sent to the FPGA for signal processing.

[0052] The FPGA-based radar signal detection module adopts a correlation detection method. The basic principle of the correlation detection method is to detect the target signal by using the similarity between a known reference signal and a received signal. The algorithm is based on the calculation of a correlation function between signals, and the correlation function reflects the similarity of the signals under different time delays.

[0053] For a radar system, the correlation function between the local reference signal s(t) and the received signal r(t) is defined as:

[0054]

[0055] Since the signal received by the FPGA is a clock-based, discrete, finite-length digital signal, in the digital circuit system, the continuous signals s(t) and r(t) are replaced by discrete signals x(n) and y(n) of length N, respectively, and the above formula becomes

[0056]

[0057] The radar signal detection module is based on the above algorithm and has a structure as follows: Figure 6 As shown, the calculation inside the FPGA uses the following steps:

[0058] Before the program is run, use MATLAB to generate a linear frequency modulation reference signal y(n) with the same carrier frequency and linear frequency modulation coefficient as the transmitter, and store it in the ROM inside the FPGA;

[0059] When the program starts running, the system is initialized by waiting for the startup delay (START_WAIT) to ensure that all components are ready to run. After the initialization phase is over, the input signal (din) is continuously sampled and stored in the FPGA internal RAM. After ensuring that a complete pulse is stored, the signal input lock flag (din_lock) is pulled high, and the input signal is no longer saved during the operation cycle to prevent new data from entering the processing pipeline. This ensures that the data being processed is consistent and will not be changed during the calculation process;

[0060] After the signal input lock flag (din_lock) register becomes high and the input signal is no longer updated, the reference signal is read from the ROM and the received signal information is read from the RAM, and stored in the input signal memory buffer array (rec_dat) and the reference signal memory buffer array (ref_dat), respectively. The depth of the array register is equal to the depth of the reference signal. Then the correlation value of the stored input signal and reference signal is calculated; the input signal and reference signal data used for each set of correlation calculations are pre-loaded into another array register, respectively, and the depth of the array register is equal to the number of reference signals;

[0061] When performing relevant calculations, the two array registers that read the input signal (rac_dat) and the reference signal (ref_dat) are first divided into several groups at equal intervals. Data in different groups are calculated in parallel. In the same group, the data at the same address of the input signal (rac_dat) and the reference signal (ref_dat) are multiplied, and the multiplication result is added to the multiplication result of the next cycle. Each clock cycle is calculated in turn until the data in each group and each group are multiplied and added, and the result is assigned to the result array register (sum_phase);

[0062] After the multiplication and addition calculations are completed, the result part of each stage, that is, the sum of each bit of the result array register (sum_phase), is further accumulated, and the final result is a set of related calculation results of the input data and the reference signal;

[0063] When a set of correlation calculation processes is completed, the read address of the input signal register (RAM) is increased by one bit, the read new data is placed in the input signal array register, and then the correlation value of the new set of data is calculated until the entire reference data set is processed;

[0064] At the same time as the previous set of steps, when a set of correlation calculation processes is completed, the correlation value will be output to the peak detection module. The peak detection module is responsible for judging the input correlation value and retaining the maximum value. When the correlation calculations of all input signals are completed, the address information of the peak value is output to obtain the accurate signal arrival time and end time;

[0065] The system also includes a module internal reset mechanism (rst_internal) to ensure that all components except the peak detection result are restored to their initial state at the end of the calculation. Once all the stored external pulse signals have been processed, this reset is triggered to ensure that the system can perform radar signal detection on the next set of pulses without the need for an external reset signal;

[0066] Through the radar signal detection module, the carrier synchronization information can be accurately obtained. The simulation test results are as follows: Figure 7As shown in the figure, the carrier frequency at the signal generation end begins to be linearly modulated at the 8000th position. In the figure, the sum_final signal obtains the maximum value of the correlation calculation at the 8000th position, and the calculation result is significantly higher than other positions, which also proves that this algorithm has strong anti-interference characteristics. The subsequent de-carrier synchronization process, that is, the coherent demodulation process, is carried out based on this calculation result.

[0067] The coherent demodulation module performs carrier synchronization and MSK demodulation on the LFM-MSK digital signal received by the ADC based on the obtained carrier synchronization information. The coherent square loop demodulation method is designed to demodulate the digital signal containing the carrier into a binary signal with a bit width of one.

[0068] After the demodulated signal is decoded by the differential decoding module, the source code information can be obtained. The expression of differential decoding is: Among them, a k is the kth bit after differential encoding decoding, b k is the differentially encoded data obtained after demodulation.

Claims

1. A fast radar tracking signal detection and data communication device based on FPGA, characterized in that: It includes an FPGA-based LFM-MSK signal generator for simulating radar signal output, and an FPGA-based LFM-MSK signal receiver for verifying the synchronous demodulation effect of radar signals; The FPGA-based LFM-MSK signal generating end includes a symbol generation module, an LFM-MSK signal modulation module and a radio frequency transmission module; the symbol generation module is used to perform binary coding modulation on the information source, and the coding modulation includes differential coding and serial-to-parallel conversion; the LFM-MSK signal modulation module is used to process the signal output by the symbol modulation module into a digital signal with minimum frequency shift, continuous phase, linear carrier frequency change and information carrying; the radio frequency transmission module includes a filter module, a DAC module, and an antenna module, which is responsible for converting the digital signal into a radio form; The FPGA-based LFM-MSK signal receiving end includes a wireless signal receiving end including a radio frequency receiving module, a radar signal detection module based on FPGA, a coherent demodulation module, and a differential decoding module; the radio frequency receiving module is used to convert the radio signal into a digital signal; the FPGA-based radar signal detection module obtains carrier synchronization information; the coherent demodulation module is responsible for de-carrier synchronization and MSK demodulation processes, and adopts a coherent square ring demodulation method to demodulate the digital signal containing the carrier into a binary signal with a bit width of one; The binary signal is decoded by the differential decoding module to obtain the final source code information.

2. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1, characterized in that: The code element generation module inside the FPGA differentially encodes the data to be transmitted in binary according to specific rules and performs serial-to-parallel conversion. The differential encoding expression is: where a k is the kth bit of the data source code, b k is the data after differential encoding; The serial-to-parallel conversion is to divide the output signal after differential encoding into two paths by a serial-to-parallel converter, and interleave them with a code element width T. b .

3. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1, characterized in that: The LFM-MSK signal modulation module firstly performs weighted processing on the two paths of data after differential encoding using weighting functions respectively; the weighting functions are respectively expressed as: Where t is time, T b is the symbol period; The two weighted signals are respectively orthogonally modulated and superimposed using linear frequency modulated orthogonal carrier signals; the linear frequency modulated orthogonal carrier signals are respectively expressed as: cos(ω c t+πμt 2 ), sin(ω c t+πμt 2 ), where ω c is the initial carrier frequency, μ is the linear frequency modulation coefficient, which is expressed as the frequency change rate of the linear frequency modulation signal; The modulated signal is the LFM-MSK signal carrying the code element information, and its expression S LFM-MSK for: Among them, I k , Q k ∈{±1} and carries code element information.

4. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1, characterized in that: The radio frequency receiving module includes an antenna module, an ADC module, and a filter module, and is responsible for converting radio signals into digital signals; The antenna module receives the radio signal in space and sends it to the ADC module in the form of an analog signal. The ADC module converts the analog signal into a digital signal, which is extracted and filtered by the filter module and sent to the FPGA for signal processing.

5. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1, characterized in that: The radar signal detection module adopts the correlation detection method, and the calculation inside the FPGA includes the following steps: Before the program is run, a linear frequency modulation reference signal y(n) having the same carrier frequency and linear frequency modulation coefficient as the transmitting end is generated and stored in the FPGA; When the program starts running, the system initializes by waiting for the startup delay to ensure that all components are ready to run; after the initialization phase is over, the input signal is continuously sampled and stored in the memory buffer; after ensuring that a complete pulse is stored, the signal input lock flag is pulled high, and the input signal is no longer saved during the operation cycle; Calculate the correlation value of the stored input signal and the reference signal; each group of input signal and reference signal data used in the correlation calculation is pre-loaded into another array register respectively, the depth of the array register is equal to the number of reference signals, when performing the correlation calculation, the two array registers that read the input signal and the reference signal are first divided into several groups at equal intervals, and the data of different groups are calculated in parallel. In the same group, the data of the same address of the input signal and the reference signal are multiplied, and the multiplication result is added to the multiplication result of the next cycle. The calculation is performed in turn in each clock cycle until the data in each group and each group are multiplied and added, and the result is assigned to the result array register; After the multiplication and addition calculations are completed, the result part of each stage, that is, the sum of each bit of the result array register, is further accumulated, and the final result obtained is a set of related calculation results of the input data and the reference signal; When a set of correlation calculation processes is completed, the read address of the input signal register is increased by one bit, the read new data is placed in the input signal array register, and then the correlation value of the new set of data is calculated until the entire reference data set is processed; At the same time as the previous set of steps, when a set of correlation calculation processes is completed, the correlation value will be output to the peak detection module. The peak detection module is responsible for judging the input correlation value and retaining the maximum value. When the correlation calculations of all input signals are completed, the address information of the peak value is output to obtain the accurate signal arrival time and end time; The system also includes an internal reset mechanism to ensure that all components except the peak detection results are restored to their initial state at the end of the calculation; once all stored external pulse signals have been processed, this reset is triggered to ensure that the system can perform radar signal detection on the next set of pulses without the need for an external reset signal.

6. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1, characterized in that: The coherent demodulation module performs carrier synchronization and MSK demodulation on the LFM-MSK digital signal received by the ADC based on the obtained carrier synchronization information. The coherent square loop demodulation method is designed to demodulate the digital signal containing the carrier into a binary signal with a bit width of one.

7. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1 or 6, characterized in that: The demodulated signal is decoded by the differential decoding module to obtain the source code information; the expression of differential decoding is: Among them, a k is the kth bit after differential encoding decoding, b k is the differentially encoded data obtained after LFM-MSK demodulation.

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