Clock taming and maintenance method, system, device and medium

Abstract

The present invention relates to a clock taming and maintenance method, system, device and medium. The method comprises: obtaining a clock signal waveform of a clock generator; taking the transition edge of the pulse signal waveform as a reference, respectively measuring the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform; calculating the output frequency of the clock generator by the time difference of the transition edges; and adjusting the frequency of the clock generator by calculating the difference between the output frequency and the expected frequency, thereby outputting a tamed clock signal. The present invention does not require the introduction of an additional reference signal, can quickly obtain the time difference of the clock signal, and reduces the taming time of the clock generator, thereby being able to tame the frequency more quickly and improve the stability and accuracy of the clock output.

Description

Technical Field

[0001] The present invention relates to the field of precise time service technology, and in particular to a clock taming and maintaining method, system, device and medium. Background Art

[0002] With the rapid development of communications, navigation, and other applications requiring high-precision clock synchronization, systems are placing increasingly stringent demands on the accuracy, stability, and continuity of clock signals. Traditional clock training technologies rely on external reference clock signals, such as satellite timing signals or network-synchronized clocks, to ensure system clock synchronization by comparing and adjusting them with the local clock. This technology relies on the stability and accuracy of the external reference signal. Any instability in the external reference signal directly affects the accuracy of the local clock, and thus the normal operation of the system.

[0003] However, in practical applications, the quality of external reference clock signals often fails to meet the system's high requirements. For example, in satellite timing systems, the stability and continuity of the external reference signal are particularly important. However, ground-based equipment often experiences signal intermittence due to limitations in the satellite's reception angle. Furthermore, atmospheric interference can cause the received satellite reference clock signal to fall below the required accuracy and stability. These factors collectively impact the performance of satellite-based timing systems, preventing them from reliably providing high-precision clock signals.

[0004] Similarly, for clock systems that rely on network synchronization, load variations in the routing network can cause problems with the accuracy and stability of the clock synchronization signal. In this case, the uncertainty of network load increases the difficulty of clock synchronization, thereby affecting the overall performance of the system. Summary of the Invention

[0005] Based on this, it is necessary to provide a clock taming and maintenance method, system, device and medium that can ensure the stability of the system's input clock without relying on an external reference signal to address the above technical problems.

[0006] A clock taming and maintaining method, the method comprising:

[0007] Obtaining a clock signal waveform of a clock generator;

[0008] Taking the transition edge of the pulse signal waveform as a reference, respectively measuring the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform;

[0009] The output frequency of the clock generator is calculated by the time difference of the jump edge;

[0010] The difference between the output frequency and the expected frequency is calculated, the frequency of the clock generator is adjusted according to the difference, and a tamed clock signal is output.

[0011] A clock taming and maintaining system, comprising:

[0012] The clock generator is used to generate a clock signal;

[0013] The measuring device is connected to the clock generator and is used to measure the waveform of the clock signal;

[0014] The processing chip is connected to the measuring device and is used to obtain a clock signal waveform and provide a pulse signal waveform; and calculate the clock signal waveform based on the pulse signal waveform to obtain an output frequency;

[0015] The digital-to-analog converter is connected to the processing chip and the clock generator respectively, and is used to obtain the output frequency, adjust the output frequency based on the difference between the output frequency and the expected frequency, and obtain a tamed clock signal; and convert the tamed clock signal into an analog signal, which is then sent to the clock generator for output.

[0016] A computer device comprises a memory and a processor, wherein the memory stores a computer program and the processor implements the steps of the clock taming and maintaining method when executing the computer program.

[0017] A computer-readable storage medium stores a computer program thereon, wherein the computer program implements the steps of the clock taming and maintaining method when executed by a processor.

[0018] Compared with the prior art, the clock taming and maintenance method, system, device and medium provided by the present invention have the following effects:

[0019] 1. In terms of method, there is no need to introduce an additional reference signal. Instead, the time difference of the clock signal waveform is calculated directly using the pulse signal that the chip can provide as a reference. Then, the output frequency is calculated based on the time difference. The frequency of the clock generator is adjusted according to the difference between the output frequency and the expected frequency. This can quickly obtain the time difference of the clock signal, reduce the clock generator taming time, and thus tame the frequency more quickly, thereby improving the stability and accuracy of the clock output.

[0020] 2. It can effectively reduce risks such as external electromagnetic interference and enhance the system's anti-interference ability.

[0021] 3. It avoids the problem of accuracy loss during the propagation of the reference signal and the signal synchronization problem when introducing an external reference signal, making the clock adjustment process more direct and efficient.

[0022] 4. Since no external reference signal is required, the clock taming process can better adapt to changes in chip working conditions and ensure reliable operation in different environments.

[0023] 5. In terms of the system, it eliminates the need for additional reference signal sources such as external crystal oscillators and GPS signals, simplifies system design, reduces hardware costs, and reduces the complexity of external reference sources in connection, configuration, and debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0025] Figure 1 1 is a flow chart of a clock taming and maintaining method according to an embodiment;

[0026] Figure 2 A schematic diagram of a waveform reference during time difference calculation in one embodiment;

[0027] Figure 3 A block diagram of a clock taming and maintaining system in one embodiment;

[0028] Figure 4 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment.

[0029] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0032] In addition, the terms "first," "second," and so on, used in this disclosure are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referenced. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this disclosure, "plurality" means at least two, such as two or three, unless otherwise specifically defined.

[0033] Unless otherwise specified or limited, the terms "connect," "fix," etc. should be understood broadly. For example, "fix" can mean a fixed connection, a detachable connection, or an integral connection; it can mean a mechanical connection, an electrical connection, a physical connection, or a wireless communication connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean internal communication between two elements or an interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0034] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0035] The following describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0036] Example 1

[0037] This embodiment discloses a clock taming and maintenance method, which does not require the introduction of an additional reference signal. Instead, it directly uses the pulse signal that the chip can provide as a reference to calculate the time difference of the clock signal waveform, and then calculates the output frequency based on the time difference. The frequency of the clock generator is adjusted according to the difference between the output frequency and the expected frequency. The time difference of the clock signal can be quickly obtained, and the output convergence time can be improved, so that the frequency adjustment can be performed more quickly and the stability of the clock can be improved. At the same time, it can effectively reduce risks such as external electromagnetic interference and enhance the anti-interference ability of the system. It avoids the time delay problem in the propagation process of the reference signal to obtain a more accurate clock adjustment; and the signal synchronization problem when introducing an external reference signal, making the clock adjustment process more direct and efficient. In addition, since the chip's own pulse signal is used, the clock taming process can better adapt to changes in the chip's working conditions and ensure reliable operation in different environments.

[0038] refer to Figure 1 , the clock taming and maintaining method provided includes the following steps:

[0039] Step 201: Acquire a clock signal waveform of a clock generator.

[0040] It is understood that when clock training is performed, the resulting signal waveform is usually required to have clear rising and falling edges to ensure accurate time measurement. Therefore, if the clock signal waveform is a non-square wave signal, it is generally necessary to convert it to a square wave.

[0041] In step 202 , the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform is measured respectively, with the transition edge of the pulse signal waveform as a reference.

[0042] As you can understand, pulse signals are generally periodic, with the length of each cycle determined by the chip's clock frequency. Their waveforms feature distinct rising and falling edges. Using a pulse signal waveform as a reference provides clear rising and falling edges, facilitating accurate calculation of clock signal time differences. Furthermore, pulse signals typically have strict level and timing characteristics, providing a more consistent reference for clocks during training, helping to maintain data transmission accuracy. Furthermore, pulse signals can be measured periodically at a high rate, enabling rapid adjustment of clock signals, making them suitable for systems requiring fast response times. Error detection and correction during the training process can be more timely, reducing the accumulation of errors caused by clock drift.

[0043] Step 203: Calculate the output frequency of the clock generator based on the time difference of the transition edges.

[0044] Step 204 , calculating the difference between the output frequency and the expected frequency, adjusting the frequency of the clock generator according to the difference, and outputting a tamed clock signal.

[0045] In the specific implementation process of step 202, taking the transition edge of the pulse signal waveform as a reference, respectively calculating the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edges of the pulse signal waveform, including:

[0046] In a measurement cycle, the time difference between a plurality of consecutive transition edges in the clock signal waveform and the initial transition edge is calculated with the initial transition edge of the pulse signal waveform as a reference.

[0047] It is worth noting that the transition edge type of the pulse signal waveform and the clock signal waveform must be the same.

[0048] Specifically, within a measurement period, the time differences between a plurality of consecutive rising edges of the clock signal waveform and the initial rising edge are calculated with reference to the initial rising edge of the pulse signal waveform. Alternatively, within a measurement period, the time differences between a plurality of consecutive falling edges of the clock signal waveform and the initial falling edge are calculated with reference to the initial falling edge of the pulse signal waveform.

[0049] like Figure 2 The figure shows an example of calculating time differences using rising edges. The START signal is a pulse signal waveform, primarily used to control the measurement behavior of the measuring device; the STOP signal is a clock signal waveform. During the measurement cycle, the clock signal waveform has three rising edges. Using the first rising edge of the START signal as the initial transition edge and the leftmost edge of the initial transition edge as a reference, the time differences between the three consecutive transition edges in the clock signal waveform and the initial transition edge are calculated as follows: 、 and .

[0050] In the specific implementation process of step 203, the output frequency of the clock generator is calculated by the time difference, and the calculation expression is:

[0051] ;

[0052] Where, Indicates the output frequency; Indicates the time difference between the nth clock signal transition edge starting from the clock signal waveform relative to the pulse signal waveform transition edge; Indicates the time difference from the (n-1)th clock signal transition edge relative to the pulse signal waveform transition edge.

[0053] It can be understood that by calculating the output frequency of the clock generator by the time difference between two adjacent transition edges and averaging multiple consecutive output frequencies, the output error can be reduced and the accuracy can be improved.

[0054] In one embodiment, the output frequency of the clock generator is filtered.

[0055] Understandably, the clock generator's output frequency is affected by factors such as ambient temperature (for oven-controlled crystal oscillators, this factor has minimal impact), material aging, input voltage ripple, and measurement errors of the measuring device. Therefore, filtering is necessary to reduce frequency jitter caused by other factors, which can lead to frequency regulation and unstable system output. Software filtering algorithms such as Kalman filtering or very low-frequency digital filters can be applied to mitigate the impact of system noise.

[0056] It's worth noting that the clock taming and maintenance method provided by the present invention is targeted at multi-device systems involving inter-device clock synchronization or phase synchronization. For such systems, the clock taming system still requires an external reference signal for phase synchronization. However, since clock frequency taming doesn't rely on an external reference signal, once taming accuracy is achieved and phase synchronization is performed based on the external reference signal, even if the external reference signal is lost, the clock system output is not affected. This is because a stable clock taming system has a long-term stable output phase, and discontinuities in the phase reference signal do not affect the system output.

[0057] Although this embodiment Figure 1 The steps in the diagram are shown in the order indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0058] Example 2

[0059] Based on the clock taming and maintaining method in Example 1, this embodiment discloses a clock taming and maintaining system, such as Figure 3 As shown, the clock taming and holding system includes: a clock generator, a measurement device, a processing chip and a digital-to-analog converter. Among them:

[0060] The clock generator is used to generate the clock signal.

[0061] The measuring device is connected to the clock generator and is used for measuring the waveform of the clock signal.

[0062] The processing chip is connected to the measuring device and is used to obtain a clock signal waveform and provide a pulse signal waveform; and calculate the clock signal waveform based on the pulse signal waveform to obtain an output frequency.

[0063] The digital-to-analog converter is connected to the processing chip and the clock generator respectively, and is used to obtain the output frequency, adjust the output frequency based on the difference between the output frequency and the expected frequency, and obtain a tamed clock signal; and convert the tamed clock signal into an analog signal, which is then sent to the clock generator for output.

[0064] from Figure 3It can be seen that the clock generator, measuring device, processing chip, and digital-to-analog converter form an inner-loop data processing process. Through such a design, the system does not rely on the validity of the external reference signal. When the system is in working state, the clock generator can be tamed and calibrated by using the pulse signal as a reference, thereby improving the long-term stability of the clock generator.

[0065] Preferably, the measuring device may employ a time-to-digital converter.

[0066] The clock taming and holding system proposed in the present invention does not rely on an external reference signal, reduces the complexity and computational complexity of the clock holding system, and avoids the situation where the system output clock signal does not meet expectations due to production and material issues.

[0067] In this embodiment, the specific operating processes and operating principles of the clock generator, measurement device, processing chip, and digital-to-analog converter are the same as those in the method of Example 1, and therefore will not be described in detail in this embodiment. Each unit module can be implemented in whole or in part through software, hardware, or a combination thereof. Each unit module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above unit modules.

[0068] Example 3

[0069] like Figure 4 The terminal device disclosed in this embodiment includes a transmitter, a receiver, a memory, and a processor. The transmitter is used to send instructions and data, the receiver is used to receive instructions and data, the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions stored in the memory to implement the method in the above-mentioned embodiment 1.

[0070] It should be noted that the above memory can be independent or integrated with the processor. When the memory is independently provided, the terminal device further includes a bus for connecting the memory and the processor.

[0071] Example 4

[0072] This embodiment discloses a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the method in the above-mentioned embodiment 1 is implemented.

[0073] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0074] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above-described embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A clock taming and maintaining method, characterized in that: The method comprises: Obtaining a clock signal waveform of a clock generator; Taking the transition edge of the pulse signal waveform as a reference, respectively measuring the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform; The output frequency of the clock generator is calculated by the time difference of the jump edge; The difference between the output frequency and the expected frequency is calculated, the frequency of the clock generator is adjusted according to the difference, and a tamed clock signal is output.

2. The clock taming and maintaining method according to claim 1, characterized in that: It also includes that if the clock signal waveform is not a square wave, it needs to be converted into a square wave.

3. The clock taming and maintaining method according to claim 1 or 2, characterized in that: Taking the transition edge of the pulse signal waveform as a reference, respectively calculating the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform, including: In a measurement period, the time differences between a plurality of consecutive transition edges in the clock signal waveform and the initial transition edge are calculated with reference to the initial transition edge of the pulse signal waveform.

4. The clock taming and maintaining method according to claim 3, characterized in that: In a measurement period, taking an initial transition edge of a pulse signal waveform as a reference, respectively calculating time differences between a plurality of consecutive transition edges in the clock signal waveform and the initial transition edge, including: During a measurement period, the time differences between a plurality of consecutive rising edges in the clock signal waveform and the initial rising edge are calculated with reference to the initial rising edge of the pulse signal waveform.

5. The clock taming and maintaining method according to claim 3, characterized in that: In a measurement period, taking an initial transition edge of a pulse signal waveform as a reference, respectively calculating time differences between a plurality of consecutive transition edges in the clock signal waveform and the initial transition edge, including: During a measurement period, the time differences between a plurality of consecutive falling edges in the clock signal waveform and the initial falling edge are calculated with reference to the initial falling edge of the pulse signal waveform.

6. The clock taming and maintaining method according to claim 4 or 5, characterized in that: The output frequency of the clock generator is calculated by the time difference, and the calculation expression is: ； Where, Indicates the output frequency; Indicates the time difference between the nth clock signal transition edge starting from the clock signal waveform relative to the pulse signal waveform transition edge; Indicates the time difference from the (n-1)th clock signal transition edge relative to the pulse signal waveform transition edge.

7. The clock taming and maintaining method according to claim 6, characterized in that: Also includes: Filter the output frequency of the clock generator.

8. A clock taming and maintaining system, characterized in that, The system comprises: The clock generator is used to generate a clock signal; The measuring device is connected to the clock generator and is used to measure the waveform of the clock signal; The processing chip is connected to the measuring device and is used to obtain a clock signal waveform and provide a pulse signal waveform; and calculate the clock signal waveform based on the pulse signal waveform to obtain an output frequency; The digital-to-analog converter is connected to the processing chip and the clock generator respectively, and is used to obtain the output frequency, adjust the output frequency based on the difference between the output frequency and the expected frequency, and obtain a tamed clock signal; and convert the tamed clock signal into an analog signal, which is then sent to the clock generator for output.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the clock taming and maintaining method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the clock taming and maintaining method according to any one of claims 1 to 7 are implemented.

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