A fast-response low-dropout linear regulator with three feedback loops

Abstract

The present invention discloses a three-feedback loop fast response low voltage difference linear regulator, including providing a reference voltage V REF The first part of the circuit receives the reference voltage V REF and feedback voltage V FB Compare and judge to realize voltage error comparison and feedback regulation control, and output voltage V ERR and bias current I PB1 The second part of the circuit receives the voltage V ERR , determine the main pole positions of the second and third loops, and improve the third part of the loop phase margin circuit; receive the bias current I PB1 , output bias voltage V B1 and V B2 The fourth circuit; the fifth circuit isolating the second circuit and the sixth circuit; outputting a small fluctuation and stable voltage V OUT and feedback voltage V FB The sixth part of the circuit; voltage V OUT As the output voltage of the low-voltage difference linear regulator; the present invention has high integration, fast transient response, high stability and simple structure.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic design, and in particular to a three-feedback loop fast-response low-voltage-dropout linear regulator. Background Art

[0002] With the continuous development of modern electronic devices, the requirements for power management of modern electronic devices are constantly increasing. Low voltage dropout linear regulators can operate at a lower input-output voltage difference, reduce circuit power consumption, improve conversion efficiency, low noise, and maintain a high output voltage stability, which makes them widely used.

[0003] As integrated circuit technology advances into the deep submicron and nanometer eras, circuit frequencies continue to increase, posing increasingly stringent challenges to the transient response and stability of traditional low-dropout (LDO) linear regulators (LDOs). Due to their limited bandwidth, LDOs experience slow transient response and poor output voltage stability when subjected to large load current jumps. This can easily lead to malfunctions in subsequent circuits and compromise overall circuit performance. Therefore, developing LDOs with fast transient response, high stability, and a simple structure is a trendy and practical necessity. Summary of the Invention

[0004] Technical purpose: In response to the problems in the prior art, the present invention discloses a three-feedback loop fast response low voltage dropout linear regulator with high integration, fast transient response, high stability and simple structure.

[0005] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0006] A three-feedback-loop fast-response low-dropout linear regulator, comprising:

[0007] The first circuit includes a bandgap reference, which is used to provide a reference voltage V REF ;

[0008] The second circuit includes an error amplifier for receiving the reference voltage V output by the first circuit. REF And the feedback voltage V output by the sixth circuit FB Perform comparison and judgment to realize voltage error comparison and feedback regulation control, and output voltage V ERR and bias current I PB1 ;

[0009] The third circuit is used for phase compensation low-pass filtering, and its input receives the voltage V output by the second circuit. ERR , used to determine the main pole positions of the second and third loops and improve the loop phase margin;

[0010] The fourth circuit is used to provide a bias voltage and receive the bias current I output by the second circuit. PB1 , and output bias voltage V B1 and V B2 ;

[0011] The fifth circuit includes a voltage buffer for isolating the second circuit and the sixth circuit. The fifth circuit receives the voltage V output by the second circuit. ERR , the bias voltage V output by the fourth circuit B1 and V B2 , and output voltage V PG ;

[0012] The sixth circuit is used to receive the voltage V output by the fifth circuit PG , and outputs a small fluctuation stable voltage V OUT and feedback voltage V FB , voltage V OUT As the output voltage of the low-dropout linear regulator;

[0013] The fifth and sixth circuits contain a first loop, which is used as a fast feedback loop for regulating the output voltage of the low-dropout linear regulator and improving the transient response speed.

[0014] The fifth circuit, the sixth circuit, the second circuit, the third circuit, and the fourth circuit contain a second loop and a third loop. The second loop is used as a medium-speed negative feedback loop for regulating and controlling the output voltage of the low-voltage difference linear regulator, and the third loop is used as a low-speed negative feedback loop for regulating and controlling the output voltage of the low-voltage difference linear regulator.

[0015] Beneficial effect: In the low voltage difference linear regulator of the present invention, the output voltage V OUT It can regulate and control, improve the load capacity of the circuit system and the stability of the output voltage, eliminate the use of compensation capacitors, effectively save the total circuit area, and has high integration, fast transient response, high stability, and simple circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a circuit structure of a three-feedback-loop fast-response low-dropout linear regulator provided in an embodiment of the present application;

[0017] Figure 2 for Figure 1 Schematic diagram of the structure of the second part of the circuit. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0020] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0021] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0022] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0023] The present invention provides a three-feedback-loop fast-response low-dropout linear regulator based on a CMOS process platform. Applicable applications include integrated circuit chips, radio frequency chips, and other electronic circuits and systems. Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. Example

[0024] As attached Figure 1 As shown, a three-feedback loop fast response low voltage dropout linear regulator of this embodiment includes:

[0025] The first circuit 100 includes a bandgap reference for providing a reference voltage V REF ;

[0026] The second circuit 200 includes an error amplifier for receiving the reference voltage V output by the first circuit 100. REF and the feedback voltage V output by the sixth circuit 600 FB Perform comparison and judgment to realize voltage error comparison and feedback regulation control, and output voltage V ERR and bias current I PB1 ;

[0027] The third circuit 300 is used for phase compensation low-pass filtering, and its input terminal receives the voltage V output by the second circuit 200. ERR , used to determine the main pole positions of the second loop L2 and the third loop L3, and improve the loop phase margin;

[0028] The fourth circuit 400 is used to provide a bias voltage. The fourth circuit 400 is used to receive the bias current I output by the second circuit 200. PB1 , and output bias voltage V B1 and V B2 ;

[0029] The fifth circuit 500 includes a voltage buffer for isolating the second circuit 200 from the sixth circuit 600. The fifth circuit 500 receives the voltage V output by the second circuit 200. ERR , the bias voltage V output by the fourth circuit 400 B1 and V B2 , and output voltage V PG ;

[0030] The sixth circuit 600 is used to receive the voltage V output by the fifth circuit 500. PG , and outputs a small fluctuation stable voltage V OUT and feedback voltage V FB , voltage V OUT As the output voltage of the low dropout linear regulator.

[0031] The fifth circuit 500 and the sixth circuit 600 contain a first loop L1, which is used as a fast feedback loop for regulating the output voltage of the low-dropout linear regulator and improving the transient response speed;

[0032] The fifth circuit 500, the sixth circuit 600, the second circuit 200, the third circuit 300, and the fourth circuit 400 include a second loop L2 and a third loop L3. The second loop L2 is used as a medium-speed negative feedback loop for regulating and controlling the output voltage of the low-dropout linear regulator, and the third loop L3 is used as a low-speed negative feedback loop for regulating and controlling the output voltage of the low-dropout linear regulator.

[0033] like Figure 2 As shown, the second circuit 200 in this embodiment serves as an error amplifier circuit and includes an error amplifier. The error amplifier in the second circuit 200 uses a folded cascode amplifier structure. The circuit structure of the error amplifier includes: a seventh N-type transistor NM7, an eighth N-type transistor NM8, a ninth N-type transistor NM9, a tenth N-type transistor NM10, an eleventh N-type transistor NM11, a twelfth N-type transistor NM12, a thirteenth N-type transistor NM13, a fourteenth N-type transistor NM14, a fifteenth N-type transistor NM15, a sixteenth N-type transistor NM16, a fourth P-type transistor PM4, a fifth P-type transistor PM5, a sixth P-type transistor PM6, a seventh P-type transistor PM7, an eighth P-type transistor PM8, a ninth P-type transistor PM9, a tenth P-type transistor PM10, and an eleventh P-type transistor PM11.

[0034] The seventh N-type transistor NM7, the eighth N-type transistor NM8, the ninth N-type transistor NM9, the tenth N-type transistor NM10, the eleventh N-type transistor NM11, and the twelfth N-type transistor NM12 form a current mirror bias structure with the sixth P-type transistor PM6, the seventh P-type transistor PM7, and the eighth P-type transistor PM8; the thirteenth N-type transistor NM13, the fourteenth N-type transistor NM14, the fifteenth N-type transistor NM15, and the sixteenth N-type transistor NM16 form a folded cascode amplifier structure with the fourth P-type transistor PM4, the fifth P-type transistor PM5, the ninth P-type transistor PM9, the tenth P-type transistor PM10, and the eleventh P-type transistor PM11;

[0035] The gate of the seventh N-type transistor NM7 and the drain of the seventh N-type transistor NM7 output a bias current I NB1, the gate of the seventh N-type transistor NM7 is connected to the gate of the eighth N-type transistor NM8, the source of the seventh N-type transistor NM7 is connected to the drain of the ninth N-type transistor NM9, the source of the eighth N-type transistor NM8 is connected to the drain of the tenth N-type transistor NM10, the gate of the ninth N-type transistor NM9 is connected to the drain of the ninth N-type transistor NM9, the source of the ninth N-type transistor NM9 and the source of the tenth N-type transistor NM10 are grounded, and the gate of the ninth N-type transistor NM9 is connected to the gate of the tenth N-type transistor NM10;

[0036] a gate of the ninth N-type transistor NM9 connected to the gate of the thirteenth N-type transistor NM13 and the gate of the fourteenth N-type transistor NM14, a gate of the twelfth N-type transistor NM12 connected to the drain of the twelfth N-type transistor NM12, a gate of the twelfth N-type transistor NM12 connected to the gate of the eleventh N-type transistor NM11, a source of the twelfth N-type transistor NM12 connected to the drain of the eleventh N-type transistor NM11, a source of the eleventh N-type transistor NM11, a source of the thirteenth N-type transistor NM13, and a source of the fourteenth N-type transistor NM14 connected to ground;

[0037] The gate of the twelfth N-type transistor NM12 is connected to the gate of the fifteenth N-type transistor NM15 and the gate of the sixteenth N-type transistor NM16, the source of the fifteenth N-type transistor NM15 is connected to the drain of the thirteenth N-type transistor NM13, and the source of the sixteenth N-type transistor NM16 is connected to the drain of the fourteenth N-type transistor NM14;

[0038] The gate of the fourth P-type transistor PM4 is connected to the reference voltage V REF The gate of the fifth P-type transistor PM5 is connected to the feedback voltage V output by the sixth circuit 600. FB , the drain of the fourth P-type transistor PM4 is connected to the drain of the thirteenth N-type transistor NM13, and the drain of the fifth P-type transistor PM5 is connected to the drain of the fourteenth N-type transistor NM14;

[0039] The gate of the seventh P-type transistor PM7 is connected to the drain of the seventh P-type transistor PM7, the gate of the eighth P-type transistor PM8 is connected to the drain of the eighth P-type transistor PM8, the gate of the seventh P-type transistor PM7 is connected to the gate of the eighth P-type transistor PM8, the drain of the seventh P-type transistor PM7 is connected to the gate of the sixth P-type transistor PM6, and the drain of the sixth P-type transistor PM6 outputs a bias current I PB1, the gate of the eighth P-type transistor PM8 is connected to the gate of the ninth P-type transistor PM9, the drain of the seventh P-type transistor PM7 is connected to the drain of the eighth N-type transistor NM8, the drain of the eighth P-type transistor PM8 is connected to the drain of the twelfth N-type transistor NM12, and the drain of the ninth P-type transistor PM9 is connected to the source of the fourth P-type transistor PM4 and the source of the fifth P-type transistor PM5;

[0040] The gate of the tenth P-type transistor PM10 is connected to the drain of the tenth P-type transistor PM10, the gate of the eleventh P-type transistor PM11 is connected to the drain of the eleventh P-type transistor PM11, the gate of the eleventh P-type transistor PM11 is connected to the gate of the tenth P-type transistor PM10, the drain of the tenth P-type transistor PM10 is connected to the drain of the fifteenth N-type transistor NM15, the drain of the eleventh P-type transistor PM11 is connected to the drain of the sixteenth N-type transistor NM16, and the drain of the sixteenth N-type transistor NM16 outputs V ERR ;

[0041] The source of the sixth P-type transistor PM6 , the source of the seventh P-type transistor PM7 , the source of the eighth P-type transistor PM8 , the source of the ninth P-type transistor PM9 , the source of the tenth P-type transistor PM10 , and the source of the eleventh P-type transistor PM11 are connected to the power supply.

[0042] The third circuit 300 in this embodiment includes a capacitor C1. The capacitor C1 serves as a phase compensation low-pass filter capacitor. The upper plate of the capacitor C1 is connected to the voltage V output by the second circuit 200. ERR The third circuit 300 is connected to the circuit board, with the lower plate of capacitor C1 grounded. The third circuit 300 can be used to determine the location of the dominant poles in the second loop L2 and the third loop L3, improving the loop phase margin. The second circuit 200 has a high output impedance. The product of capacitor C1, used for phase-compensating low-pass filtering in the third circuit 300, and the output impedance of the second circuit 200 is significantly greater than the RC constant at the node between the fifth circuit 500 and the sixth circuit 600. Therefore, the location of the dominant poles in the second loop L2 and the third loop L3 is determined by capacitor C1 in the third circuit 300. Phase compensation provided by capacitor C1 shifts the dominant poles toward lower frequencies in the frequency domain, increasing the loop phase margin and improving loop stability.

[0043] The fourth circuit 400 in this embodiment is a current mirror bias structure, and includes: a first N-type transistor NM1, a second N-type transistor NM2, a third N-type transistor NM3, a fourth N-type transistor NM4, and a first P-type transistor PM1;

[0044] The drain of the first N-type transistor NM1 is connected to the bias current I output by the second circuit 200. PB1The gate of the first N-type transistor NM1 is connected to the drain of the first N-type transistor NM1, and the source of the first N-type transistor NM1 outputs a bias voltage V B1 The source of the first N-type transistor NM1 is connected to the drain of the third N-type transistor NM3, the drain of the third N-type transistor NM3 is connected to the gate of the third N-type transistor NM3, the gate of the third N-type transistor NM3 is connected to the gate of the fourth N-type transistor NM4, and the source of the fourth N-type transistor NM4 and the source of the third N-type transistor NM3 are grounded; the drain of the fourth N-type transistor NM4 is connected to the source of the second N-type transistor NM2, the gate of the first N-type transistor NM1 is connected to the gate of the second N-type transistor NM2, the drain of the second N-type transistor NM2 is connected to the drain of the first P-type transistor PM1, the drain of the first P-type transistor PM1 is connected to the gate of the first P-type transistor PM1, and the gate of the first P-type transistor PM1 outputs the bias voltage V B2 ; The source of the first P-type transistor PM1 is connected to the power supply;

[0045] The fifth circuit 500 of this embodiment includes a voltage buffer. The voltage buffer uses a source follower structure to isolate the output terminal V ERR The high impedance and the third P-type transistor PM3 of the sixth circuit 600 isolate the front and rear stage circuits to eliminate mutual influence, and the output voltage V PG , the fifth circuit 500 includes: a fifth N-type transistor NM5, a sixth N-type transistor NM6 and a second P-type transistor PM2;

[0046] The gate of the fifth N-type transistor NM5 is connected to the bias voltage VB1 output by the fourth partial circuit 400; the source of the fifth N-type transistor NM5 is grounded, the drain of the fifth N-type transistor NM5 is connected to the source of the sixth N-type transistor NM6, and the gate of the sixth N-type transistor NM6 is connected to the voltage VERR output by the second partial circuit 200; the drain of the sixth N-type transistor NM6 is connected to the drain of the second P-type transistor PM2, the gate of the second P-type transistor PM2 is connected to the bias voltage VB2 output by the fourth partial circuit 400, and the source of the second P-type transistor PM2 is connected to the power supply; the drain of the second P-type transistor PM2 outputs the voltage VPG.

[0047] In this embodiment, the fifth part of the circuit 500 and the sixth part of the circuit 600 constitute a super source follower structure, that is, the fifth N-type transistor NM5, the sixth N-type transistor NM6, the second P-type transistor PM2, and the third P-type transistor PM3 constitute a super source follower structure, which reduces the output impedance of the circuit and optimizes the load and driving capabilities of the circuit.

[0048] The sixth circuit 600 in this embodiment is the final output stage of the low voltage drop linear regulator, which is used to output a small fluctuation and stable voltage V OUT and feedback voltage V FB The sixth circuit 600 includes a third P-type transistor PM3, a resistor R1, and a resistor R2;

[0049] The gate of the third P-type transistor PM3 is connected to the voltage V output by the fifth circuit 500. PG The source of the third P-type transistor PM3 is connected to the power supply, the drain of the third P-type transistor PM3 is connected to the source of the sixth N-type transistor NM6 in the fifth circuit 500, and the drain of the third P-type transistor PM3 outputs a voltage V OUT The drain of the third P-type transistor PM3 is connected to the positive electrode of the resistor R1, and the negative electrode of the resistor R1 outputs the feedback voltage V FB , the negative electrode of the resistor R1 is connected to the positive electrode of the resistor R2, and the negative electrode of the resistor R2 is grounded.

[0050] The first loop L1 includes the sixth N-type transistor NM6 in the fifth circuit 500 and the third P-type transistor PM3 in the sixth circuit 600, and is used as a fast feedback loop to regulate and control the output voltage of the low-dropout linear regulator and improve the transient response speed, thereby optimizing the output voltage V OUT The transient response speed, specifically, the first loop L1 regulates the output voltage V OUT And improve the transient response speed of the regulator, the first loop L1 can optimize the output voltage V OUT transient response speed.

[0051] The second loop L2 includes the sixth N-type transistor NM6 in the fifth circuit 500, the resistors R1 and R2 in the sixth circuit 600, the second circuit 200, the third circuit 300, and the fourth circuit 400; it is used as a medium-speed negative feedback loop to regulate the output voltage of the low-dropout linear regulator, and can provide a feedback voltage to adjust the output voltage V OUT stability, optimizing the bandwidth and stability of the regulator.

[0052] The third loop L3 includes the sixth circuit 600, the sixth N-type transistor NM6 in the fifth circuit 500, the second circuit 200, the third circuit 300, the fourth circuit 400, the third P-type transistor PM3, the sixth N-type transistor NM6, the resistors R1 and R2, the error amplifier of the second circuit 200, the phase compensation low-pass filter capacitor of the third circuit 300, and the current mirror bias structure of the fourth circuit 400 as the core, and is used as a low-speed negative feedback loop for regulating and controlling the output voltage of the low-dropout linear regulator, which can provide a low-speed negative feedback path so that VFB With V REF Equal, V ERR Regulate the gate voltage of the sixth N-type transistor NM6, and regulate the gate voltage of the third P-type transistor PM3 through voltage transmission, thereby regulating V OUT , so that V OUT The DC voltage value is at a stable threshold with little fluctuation, which ultimately ensures that V OUT And the stability of the DC operating point of the entire circuit, improving the circuit's sensitivity to external changes.

[0053] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

[0054] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A three-feedback-loop fast-response low-dropout linear regulator, characterized in that: include: The first circuit (100) includes a bandgap reference for providing a reference voltage V REF ; The second circuit (200) includes an error amplifier for receiving the reference voltage V output by the first circuit (100). REF and the feedback voltage V output by the sixth circuit (600) FB Perform comparison and judgment to realize voltage error comparison and feedback regulation control, and output voltage V ERR and bias current I PB1 ; The third circuit (300) is used for phase compensation low-pass filtering, and its input terminal receives the voltage V output by the second circuit (200). ERR , used to determine the main pole positions of the second loop (L2) and the third loop (L3) to improve the loop phase margin; The fourth circuit (400) is used to provide a bias voltage. The fourth circuit (400) is used to receive the bias current I output by the second circuit (200). PB1 , and output bias voltage V B1 and V B2 ; The fifth circuit (500) includes a voltage buffer for isolating the second circuit (200) and the sixth circuit (600). The fifth circuit (500) receives the voltage V output by the second circuit (200). ERR , the bias voltage V output by the fourth circuit (400) B1 and V B2 , and output voltage V PG ; The sixth circuit (600) is used to receive the voltage V output by the fifth circuit (500) PG , and outputs a small fluctuation stable voltage V OUT and feedback voltage V FB , voltage V OUT As the output voltage of the low-dropout linear regulator; The fifth circuit (500) and the sixth circuit (600) contain a first loop (L1), which is used as a fast feedback loop for regulating and controlling the output voltage of the low-dropout linear regulator and improving the transient response speed; The fifth circuit (500), the sixth circuit (600), the second circuit (200), the third circuit (300), and the fourth circuit (400) contain a second loop (L2) and a third loop (L3); the second loop (L2) is used as a medium-speed negative feedback loop for regulating and controlling the output voltage of the low-voltage difference linear regulator; and the third loop (L3) is used as a low-speed negative feedback loop for regulating and controlling the output voltage of the low-voltage difference linear regulator. The second circuit (200) structure comprises: The seventh N-type transistor NM7, the eighth N-type transistor NM8, the ninth N-type transistor NM9, the tenth N-type transistor NM10, the eleventh N-type transistor NM11, and the twelfth N-type transistor NM12 form a current mirror bias structure with the sixth P-type transistor PM6, the seventh P-type transistor PM7, and the eighth P-type transistor PM8; the thirteenth N-type transistor NM13, the fourteenth N-type transistor NM14, the fifteenth N-type transistor NM15, and the sixteenth N-type transistor NM16 form a folded cascode amplifier structure with the fourth P-type transistor PM4, the fifth P-type transistor PM5, the ninth P-type transistor PM9, the tenth P-type transistor PM10, and the eleventh P-type transistor PM11; The gate of the seventh N-type transistor NM7 and the drain of the seventh N-type transistor NM7 output a bias current I NB1 , the gate of the seventh N-type transistor NM7 is connected to the gate of the eighth N-type transistor NM8, the source of the seventh N-type transistor NM7 is connected to the drain of the ninth N-type transistor NM9, the source of the eighth N-type transistor NM8 is connected to the drain of the tenth N-type transistor NM10, the gate of the ninth N-type transistor NM9 is connected to the drain of the ninth N-type transistor NM9, the source of the ninth N-type transistor NM9 and the source of the tenth N-type transistor NM10 are grounded, and the gate of the ninth N-type transistor NM9 is connected to the gate of the tenth N-type transistor NM10; a gate of the ninth N-type transistor NM9 connected to the gate of the thirteenth N-type transistor NM13 and the gate of the fourteenth N-type transistor NM14, a gate of the twelfth N-type transistor NM12 connected to the drain of the twelfth N-type transistor NM12, a gate of the twelfth N-type transistor NM12 connected to the gate of the eleventh N-type transistor NM11, and a source of the twelfth N-type transistor NM12 connected to the drain of the eleventh N-type transistor NM11; The gate of the twelfth N-type transistor NM12 is connected to the gate of the fifteenth N-type transistor NM15 and the gate of the sixteenth N-type transistor NM16, the source of the fifteenth N-type transistor NM15 is connected to the drain of the thirteenth N-type transistor NM13, and the source of the sixteenth N-type transistor NM16 is connected to the drain of the fourteenth N-type transistor NM14; The gate of the fourth P-type transistor PM4 is connected to the reference voltage V output by the first circuit (100). REF The gate of the fifth P-type transistor PM5 is connected to the feedback voltage V output by the sixth circuit (600). FB , the drain of the fourth P-type transistor PM4 is connected to the drain of the thirteenth N-type transistor NM13, and the drain of the fifth P-type transistor PM5 is connected to the drain of the fourteenth N-type transistor NM14; The gate of the seventh P-type transistor PM7 is connected to the drain of the seventh P-type transistor PM7, the gate of the eighth P-type transistor PM8 is connected to the drain of the eighth P-type transistor PM8, the gate of the seventh P-type transistor PM7 is connected to the gate of the eighth P-type transistor PM8, the drain of the seventh P-type transistor PM7 is connected to the gate of the sixth P-type transistor PM6, and the drain of the sixth P-type transistor PM6 outputs a bias current I PB1 , the gate of the eighth P-type transistor PM8 is connected to the gate of the ninth P-type transistor PM9, the drain of the seventh P-type transistor PM7 is connected to the drain of the eighth N-type transistor NM8, the drain of the eighth P-type transistor PM8 is connected to the drain of the twelfth N-type transistor NM12, and the drain of the ninth P-type transistor PM9 is connected to the source of the fourth P-type transistor PM4 and the source of the fifth P-type transistor PM5; The gate of the tenth P-type transistor PM10 is connected to the drain of the tenth P-type transistor PM10, the gate of the eleventh P-type transistor PM11 is connected to the drain of the eleventh P-type transistor PM11, the gate of the eleventh P-type transistor PM11 is connected to the gate of the tenth P-type transistor PM10, the drain of the tenth P-type transistor PM10 is connected to the drain of the fifteenth N-type transistor NM15, the drain of the eleventh P-type transistor PM11 is connected to the drain of the sixteenth N-type transistor NM16, and the drain of the sixteenth N-type transistor NM16 outputs V ERR .

2. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The third circuit (300) includes a capacitor C1, the upper plate of the capacitor C1 and the voltage V output by the second circuit (200) ERR The third circuit (300) can be used to determine the main pole positions of the second loop (L2) and the third loop (L3), thereby improving the loop phase margin.

3. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The fourth circuit (400) is a current mirror bias structure, and the fourth circuit (400) comprises: a first N-type transistor NM1, a second N-type transistor NM2, a third N-type transistor NM3, a fourth N-type transistor NM4, and a first P-type transistor PM1; The drain of the first N-type transistor NM1 is connected to the bias current I output by the second circuit (200). PB1 The gate of the first N-type transistor NM1 is connected to the drain of the first N-type transistor NM1, and the source of the first N-type transistor NM1 outputs a bias voltage V B1 The source of the first N-type transistor NM1 is connected to the drain of the third N-type transistor NM3, the drain of the third N-type transistor NM3 is connected to the gate of the third N-type transistor NM3, the gate of the third N-type transistor NM3 is connected to the gate of the fourth N-type transistor NM4, and the source of the fourth N-type transistor NM4 and the source of the third N-type transistor NM3 are grounded; the drain of the fourth N-type transistor NM4 is connected to the source of the second N-type transistor NM2, the gate of the first N-type transistor NM1 is connected to the gate of the second N-type transistor NM2, the drain of the second N-type transistor NM2 is connected to the drain of the first P-type transistor PM1, the drain of the first P-type transistor PM1 is connected to the gate of the first P-type transistor PM1, and the gate of the first P-type transistor PM1 outputs the bias voltage V B2 ; The source of the first P-type transistor PM1 is connected to the power supply.

4. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The fifth circuit (500) includes a voltage buffer, which uses a source follower structure. The fifth circuit (500) includes: a fifth N-type transistor NM5, a sixth N-type transistor NM6, and a second P-type transistor PM2; The gate of the fifth N-type transistor NM5 is connected to the bias voltage V output by the fourth circuit (400). B1 The source of the fifth N-type transistor NM5 is grounded, the drain of the fifth N-type transistor NM5 is connected to the source of the sixth N-type transistor NM6, and the gate of the sixth N-type transistor NM6 is connected to the voltage V output by the second part of the circuit (200) ERR The drain of the sixth N-type transistor NM6 is connected to the drain of the second P-type transistor PM2, and the gate of the second P-type transistor PM2 is connected to the bias voltage V output by the fourth circuit (400) B2 , the source of the second P-type transistor PM2 is connected to the power supply; the drain of the second P-type transistor PM2 outputs a voltage V PG .

5. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The sixth circuit (600) is the final output stage of the low voltage difference linear regulator, and the sixth circuit (600) comprises a third P-type transistor PM3, a resistor R1, and a resistor R2; The gate of the third P-type transistor PM3 is connected to the voltage V output by the fifth circuit (500). PG The source of the third P-type transistor PM3 is connected to the power supply, the drain of the third P-type transistor PM3 is connected to the source of the sixth N-type transistor NM6 in the fifth circuit (500), and the drain of the third P-type transistor PM3 outputs a voltage V OUT The drain of the third P-type transistor PM3 is connected to the positive electrode of the resistor R1, and the negative electrode of the resistor R1 outputs the feedback voltage V FB , the negative electrode of the resistor R1 is connected to the positive electrode of the resistor R2, and the negative electrode of the resistor R2 is grounded.

6. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The first loop (L1) includes a sixth N-type transistor NM6 in the fifth circuit (500) and a third P-type transistor PM3 in the sixth circuit (600), which optimizes the output voltage V OUT transient response speed.

7. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The second loop (L2) comprises a sixth N-type transistor NM6 in the fifth partial circuit (500), resistors R1 and R2 in the sixth partial circuit (600), the second partial circuit (200), the third partial circuit (300), and the fourth partial circuit (400); and is used to provide a feedback voltage to adjust the output voltage V OUT stability, optimizing the bandwidth and stability of the regulator.

8. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The third loop (L3) includes a third P-type transistor PM3, a resistor R1 and a resistor R2 in the sixth partial circuit (600), a sixth N-type transistor NM6 in the fifth partial circuit (500), a second partial circuit (200), a third partial circuit (300), and a fourth partial circuit (400), and adjusts the output voltage V by feedback voltage. OUT Guaranteed output voltage V OUT And the stability of the DC operating point of the entire circuit.

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