Bias circuits, chips and electronic devices

Abstract

The disclosed embodiment discloses a bias circuit, a chip and an electronic device, wherein the bias circuit includes: a bias generating module, a first input terminal of the bias generating module is used to input a start signal; a first output terminal of the bias generating module is used to output a first bias voltage; a negative feedback module, a second input terminal of the negative feedback module is connected to the first output terminal of the bias generating module, and a second output terminal of the negative feedback module is connected to the bias generating module; the bias generating module is used to generate a first bias voltage under the action of the start signal, and output the first bias voltage from the first output terminal; the negative feedback module is used to feed back a regulating voltage to the bias generating module under the action of the first bias voltage, so as to adjust the first bias voltage generated by the bias generating module to a second bias voltage. The disclosed embodiment can effectively reduce the fluctuation range of the bias voltage and improve the stability of the overall circuit.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a bias circuit, a chip, and an electronic device. Background Art

[0002] In analog circuits such as analog to digital converter (ADC), operational amplifier (OA), and low dropout regulator (LDO), one or more current biases are usually required, and bias voltage or bias current is provided to these analog circuits through bias circuits. The bias voltage generated by the current bias circuit in the related art has a large fluctuation range, which can easily cause abnormal functions of other modules of the analog circuit, thereby affecting the stability of the overall circuit. Summary of the invention

[0003] Embodiments of the present disclosure provide a bias circuit, a chip, and an electronic device.

[0004] According to one aspect of an embodiment of the present disclosure, a bias circuit is provided, comprising: a bias generating module, wherein a first input terminal of the bias generating module is used to input a start signal; a first output terminal of the bias generating module is used to output a first bias voltage; a negative feedback module, wherein a second input terminal of the negative feedback module is connected to the first output terminal of the bias generating module, and a second output terminal of the negative feedback module is connected to the bias generating module; the bias generating module is used to generate the first bias voltage under the action of the start signal, and output the first bias voltage from the first output terminal; and the negative feedback module is used to feed back an adjustment voltage to the bias generating module under the action of the first bias voltage, so as to adjust the first bias voltage generated by the bias generating module to a second bias voltage.

[0005] In some embodiments, the negative feedback module includes: a first transistor component, a first end of the first transistor component is connected to the second input end, a second end of the first transistor component is connected to the power supply voltage, and a third end of the first transistor component is connected to the second output end; a second transistor component, a first end of the second transistor component is connected to the second input end, a second end of the second transistor component is respectively connected to the third end of the first transistor component and the second output end, and the third end of the second transistor component is grounded; the first transistor component and the second transistor component are used to: when the first bias voltage is higher than a first voltage threshold, make the second output end output a first adjustment voltage to adjust the first bias voltage to the second bias voltage less than the first bias voltage; and, when the first bias voltage is lower than a second voltage threshold, make the second output end output a second adjustment voltage to adjust the first bias voltage to the second bias voltage greater than the first bias voltage.

[0006] In some embodiments, the first transistor component includes: a first PMOS transistor, a first end of the first PMOS transistor serving as a first enable end, and a second end of the first PMOS transistor serving as a second end of the first transistor component connected to a power supply voltage; a second PMOS transistor, a first end of the second PMOS transistor serving as a first end of the first transistor component, and a second end of the second PMOS transistor connected to a third end of the first PMOS transistor; and a third end of the second PMOS transistor serving as a third end of the first transistor component.

[0007] In some embodiments, the second transistor component includes: a first NMOS transistor, a first end of the first NMOS transistor serves as a first end of the second transistor component, and a second end of the first NMOS transistor serves as a second end of the second transistor component; a second NMOS transistor, a first end of the second NMOS transistor serves as a second enable end, a second end of the second NMOS transistor is connected to a third end of the first NMOS transistor, and a third end of the second NMOS transistor is grounded as a third end of the second transistor component; the first enable end and the second enable end are connected to opposite enable signals; when the first enable end and the second enable end are both in an enabled state, the negative feedback module is in a working state; when the first enable end and the second enable end are both in a disabled state, the negative feedback module is in a closed state.

[0008] In some embodiments, the bias generating module includes: a start-up control component, wherein the first end of the start-up control component serves as the first input end of the bias generating module, and the second end of the start-up control component is connected to the power supply voltage; a transistor current mirror component, which is respectively connected to the third end of the start-up control component and the second output end of the negative feedback module; an auxiliary transistor component, which is respectively connected to the transistor current mirror component and the power supply voltage; a cascade transistor component, which is respectively connected to the auxiliary transistor component and the first output end; a resistor, wherein the first end of the resistor is respectively connected to the cascade transistor component and the first output end, and the second end of the resistor is grounded; the start-up control component starts the bias generating module under the action of the start-up signal, provides current to the transistor current mirror component, the cascade transistor component and the resistor, generates the first bias voltage at the first end of the resistor, and outputs the first bias voltage through the first output end; the transistor current mirror component is used to adjust the current of the transistor current mirror component, the cascade transistor component and the resistor under the action of the adjustment voltage of the negative feedback module, so as to adjust the first bias voltage at the first end of the resistor to the second bias voltage.

[0009] In some embodiments, the bias generating module further includes: a capacitor, a first end of the capacitor is connected to the first end of the resistor, and a second end of the capacitor is grounded.

[0010] In some embodiments, the transistor current mirror component includes: a third NMOS transistor, the first end of the third NMOS transistor is respectively connected to the second end of the third NMOS transistor and the second output end of the negative feedback module; the second end of the third NMOS transistor is connected to the third end of the start control component; the third end of the third NMOS transistor is grounded; a fourth NMOS transistor, the first end of the fourth NMOS transistor is connected to the first end of the third NMOS transistor, the second end of the fourth NMOS transistor is connected to the auxiliary transistor component, and the third end of the fourth NMOS transistor is grounded; a fifth NMOS transistor, the first end of the fifth NMOS transistor is connected to the first end of the third NMOS transistor, the second end of the fifth NMOS transistor is connected to the auxiliary transistor component, and the third end of the fifth NMOS transistor is grounded.

[0011] In some embodiments, the auxiliary transistor component includes: a third PMOS transistor, a first end of the third PMOS transistor is connected to the cascade transistor component, a second end of the third PMOS transistor is connected to the power supply voltage, and a third end of the third PMOS transistor is respectively connected to the first end of the third PMOS transistor and the second end of the fourth NMOS transistor; a fourth PMOS transistor, a first end of the fourth PMOS transistor is connected to the cascade transistor component, a second end of the fourth PMOS transistor is connected to the power supply voltage, and a third end of the fourth PMOS transistor is respectively connected to the first end of the fourth PMOS transistor and the second end of the fifth NMOS transistor.

[0012] In some embodiments, the cascade transistor component includes: a fifth PMOS transistor, a first end of the fifth PMOS transistor is connected to the first end of the third PMOS transistor, and a second end of the fifth PMOS transistor is connected to a power supply voltage; a sixth PMOS transistor, a first end of the sixth PMOS transistor is connected to the first end of the fourth PMOS transistor, a second end of the sixth PMOS transistor is connected to the third end of the fifth PMOS transistor, and the third end of the sixth PMOS transistor is respectively connected to the first output end and the first end of the resistor.

[0013] In some embodiments, the bias circuit further includes: a bias adjustment module, including at least one parallel switch branch, each of the switch branches including at least one switch component; a first end of each of the switch branches is connected to an adjustment control signal, a second end of each of the switch branches is connected to a power supply voltage, and a third end of each of the switch branches is connected to the bias generation module; each of the switch branches is used to inject a current into the bias generation module when the adjustment control signal is valid, so as to increase the first bias voltage generated by the bias generation module.

[0014] In some embodiments, the bias generating module includes a startup control component, a transistor current mirror component, an auxiliary transistor component, a cascade transistor component and a resistor; the third end of each of the switch branches is respectively connected to the third end of the startup control component and the transistor current mirror component; each of the switch branches is used to inject a current into the transistor current mirror component when the adjustment control signal is valid, so as to increase the gate voltage of the transistor in the transistor current mirror component, so that the current flowing through the resistor increases, and the first bias voltage is adjusted to a third bias voltage greater than the first bias voltage.

[0015] In some embodiments, each of the switch branches includes: at least two switch components connected in series; the first end of each switch component is connected to the first end of the switch branch; each switch component is turned on when the adjustment control signal is valid to generate current in the switch branch; each switch component is turned off when the adjustment control signal is invalid to disconnect the current generated by the switch branch.

[0016] According to another aspect of the embodiments of the present disclosure, a chip is provided, comprising: the bias circuit provided by any one of the above embodiments.

[0017] According to another aspect of the embodiments of the present disclosure, there is provided an electronic device, including: the chip provided by any one of the above embodiments.

[0018] The bias circuit, chip and electronic device provided by the above-mentioned embodiments of the present disclosure generate a first bias voltage through a bias generating module. When the first bias voltage is too high or too low, a regulating voltage can be generated through a negative feedback module to adjust the first bias voltage generated by the bias generating module to a second bias voltage, thereby limiting the fluctuation of the bias voltage output by the bias generating module to a smaller range, effectively reducing the fluctuation range of the bias voltage and improving the stability of the overall circuit.

[0019] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps;

[0021] Figure 1 It is a current bias circuit;

[0022] Figure 2 is a schematic structural diagram of a bias circuit provided by an exemplary embodiment of the present disclosure;

[0023] Figure 3 is a structural schematic diagram of a bias circuit provided by another exemplary embodiment of the present disclosure;

[0024] Figure 4 is a structural schematic diagram of a negative feedback module provided by an exemplary embodiment of the present disclosure;

[0025] Figure 5 is a structural schematic diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure;

[0026] Figure 6 is a structural schematic diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure;

[0027] Figure 7 is a structural schematic diagram of a bias generating module provided by an exemplary embodiment of the present disclosure;

[0028] Figure 8 is a structural schematic diagram of a bias generating module provided by another exemplary embodiment of the present disclosure;

[0029] Fig. 9 is a structural schematic diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure;

[0030] Fig.10 is a structural schematic diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure;

[0031] Fig.11 is a structural schematic diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure;

[0032] Fig.12 is a structural schematic diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure;

[0033] Fig.13 is a structural schematic diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure;

[0034] Fig.14 is a structural diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0036] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0037] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0038] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0039] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0040] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0041] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0042] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0043] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0044] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0045] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0046] SUMMARY OF THE DISCLOSURE

[0047] In the related art, the current bias circuit is often composed of a startup circuit and a bias circuit. Figure 1 is a current bias circuit, see Figure 1 , the current bias circuit includes transistors T1, T2, T3, T4, T5, T6 and T7, and resistor R1. Transistors T5, T6 and T7 form a startup module, transistors T1, T2, T3, T4 and resistor R1 form a bias module, and output a bias voltage Vref. Iref1 and Iref2 are the currents of the two branches in the bias circuit, VDD represents the power supply voltage, the sources of T1 and T5 are grounded, and one end of resistor R1 is grounded. This current bias circuit is sensitive to process angle and temperature. Under different process angles, the output bias voltage Vref has a large fluctuation range. Vref with a large fluctuation range is used as a reference voltage for other modules of the analog circuit, which is easy to cause abnormal functions of other modules, thereby affecting the stability of the overall circuit.

[0048] Exemplary Structure

[0049] Figure 2 1 is a schematic diagram of a bias circuit provided by an exemplary embodiment of the present disclosure. The components included in the bias circuit can be integrated into a chip or set into discrete components, and data communication links are established between these discrete components. Figure 2 As shown, the bias circuit 20 may include: a bias generating module 21 and a negative feedback module 22 .

[0050] The first input terminal r1 of the bias generating module 21 is used to input a start signal (which can be expressed as start); the first output terminal d1 of the bias generating module 21 is used to output a first bias voltage Vref1.

[0051] The second input terminal r2 of the negative feedback module 22 is connected to the first output terminal d1 of the bias generation module 21, and the second output terminal d2 of the negative feedback module 22 is connected to the bias generation module 21. Specifically, the second output terminal d2 can be connected to the third input terminal of the bias generation module 21.

[0052] The bias generating module 21 is used for generating a first bias voltage Vref1 under the action of a start signal, and outputting the first bias voltage Vref1 from a first output terminal d1 .

[0053] The negative feedback module 22 is used for feeding back the adjustment voltage Vr to the bias generation module 21 under the action of the first bias voltage Vref1 , so as to adjust the first bias voltage Vref1 generated by the bias generation module 21 to the second bias voltage Vref2 .

[0054] In some optional embodiments, the bias generation module 21 can be implemented based on a group of transistors and at least one resistor. The group of transistors can include at least one of NMOS (N-Metal-Oxide-Semiconductor) transistors (which can be referred to as NMOS transistors) and PMOS (P-Metal-Oxide-Semiconductor) transistors (which can be referred to as PMOS transistors). The group of transistors and the resistors are connected in a certain manner to form a bias generation module 21 capable of generating a bias voltage.

[0055] In some optional embodiments, when the first bias voltage Vref1 is too high (for example, Vref1 is greater than the first voltage threshold), the adjusted second bias voltage Vref2 is less than Vref1. When the first bias voltage Vref1 is too low (for example, Vref1 is less than the second voltage threshold), the adjusted second bias voltage Vref2 is greater than Vref1.

[0056] In some optional embodiments, the negative feedback module 22 may be implemented based on a group of transistors, which may include at least two transistors.

[0057] In an optional example, the group of transistors of the negative feedback module 22 may include a PMOS transistor and an NMOS transistor, the PMOS transistor and the NMOS transistor are co-gate (i.e., the gates of the two transistors are connected), and the common gate terminal serves as the second input terminal r2 of the negative feedback module, and the common gate terminal is connected to the first output terminal of the bias generation module 21, so that the bias voltage (e.g., the above-mentioned first bias voltage) generated by the bias generation module 21 acts on the negative feedback module 22. The PMOS transistor and the NMOS transistor have a common drain (i.e., the drain of the PMOS transistor is connected to the drain of the NMOS transistor), and the common drain terminal serves as the second output terminal d2 of the negative feedback module 21. In the case where the bias voltage is too high, the NMOS transistor pulls down the voltage of the second output terminal d2, and feeds back a lower adjustment voltage Vr to the bias generation module 21. Under the action of the adjustment voltage Vr, the bias generation module 21 adjusts the bias voltage outputted from the first output terminal d1 from the first bias voltage Vref1 to a lower second bias voltage Vref2. On the contrary, when the bias voltage is too low, the PMOS transistor pulls up the voltage of the second output terminal d2 and feeds back a higher adjustment voltage Vr to the bias generating module 21. Under the action of the adjustment voltage Vr, the bias generating module 21 adjusts the bias voltage outputted from the first output terminal d1 from the first bias voltage Vref1 to the higher second bias voltage Vref2, thereby limiting the bias voltage outputted by the bias generating module 21 to a smaller fluctuation range.

[0058] In another optional example, the group of transistors of the negative feedback module 22 may include at least two PMOS transistors and at least two NMOS transistors, wherein one PMOS transistor and one NMOS transistor may be used as switches of the negative feedback module 22 to control the start and shut down of the negative feedback module 22. In the process of generating the regulated voltage, the specific working principle of the multiple PMOS transistors and the multiple NMOS transistors is similar to that of one PMOS transistor and one NMOS transistor in the above example, the PMOS transistor is used to pull up the voltage of the second output terminal d2 when the bias voltage is too low to generate a higher regulated voltage, and the NMOS transistor is used to pull down the voltage of the second output terminal d2 when the bias voltage is too high to generate a lower regulated voltage. The specific number of PMOS transistors and the number of NMOS transistors can be set according to actual needs.

[0059] In some optional embodiments, the bias generation module 21 can be implemented based on a current mirror component, at least one transistor and a resistor, at least one transistor is connected in series with the resistor, and the connection end of the transistor and the resistor serves as the first output end d1 of the bias generation circuit 21 to output a bias voltage. The current of the resistor is associated with the current of the current mirror component, and the gate voltage of the current mirror component is adjusted by the adjustment voltage generated by the negative feedback module 22, thereby adjusting the current of the current mirror component, and then adjusting the current of the resistor to achieve adjustment of the bias voltage.

[0060] In some optional embodiments, the bias generating module 21 may include a current mirror component, a cascade transistor component, and at least one resistor connected in series with the cascade transistor component. The second output terminal d2 of the negative feedback module 22 may be connected to the current mirror component, and the gate voltage of the transistor in the current mirror component may be adjusted to adjust the current of the current mirror component through the adjustment voltage fed back by the negative feedback module 22, thereby adjusting the current of the cascade transistor component and the resistor. When the resistor is fixed, the bias voltage is the voltage between the resistor and the cascade transistor component, which changes with the current of the resistor, thereby achieving the adjustment of the bias voltage. The cascade transistor component may increase the output impedance of the branch in which it is located, weaken the influence of the drain-source voltage on the current of a single transistor, thereby making the branch current more stable, that is, making the current of the resistor more stable.

[0061] In some optional embodiments, the bias generation module 21 may include a start-up control transistor (or start-up control component), a current mirror component, a cascade transistor component, and a capacitor for starting the bias circuit generation module 21. The gate of the start-up control transistor is connected to a start-up signal, and the start-up and shutdown of the bias generation module 21 are controlled by the start-up signal.

[0062] It can be understood that the first bias voltage Vref1 and the second bias voltage Vref2 are only used to represent two relatively different bias voltages generated during the operation of the bias circuit, and are not limited to specific fixed voltage values. The first bias voltage can change with time or different working states of the bias circuit. For example, at one moment, the value of the first bias voltage is V1, and at another moment, the value of the first bias voltage is V2. Similarly, the second bias voltage is a bias voltage adjusted according to the first bias voltage and the overall working conditions of the bias circuit, and can be different voltage values ​​at different moments.

[0063] In the bias circuit provided by the embodiment of the present disclosure, when the bias generating module generates the first bias voltage, the negative feedback module can generate an adjustment voltage under the action of the first bias voltage and provide it to the bias generating module, so that the bias generating module can adjust the excessively high first bias voltage to a lower second bias voltage, and adjust the excessively low first bias voltage to a higher second bias voltage under the action of the adjustment voltage, thereby limiting the bias voltage output by the bias generating module to a smaller fluctuation range, effectively reducing the fluctuation range of the bias voltage, and avoiding the situation where the generated bias voltage fluctuates too much due to the influence of process angle, temperature, etc., thereby helping to improve the stability of the overall circuit.

[0064] Figure 3 is a schematic structural diagram of a bias circuit provided by another exemplary embodiment of the present disclosure.

[0065] In some optional embodiments, in the above Figure 2 Based on the embodiment shown, Figure 3 As shown, the negative feedback module 22 may include: a first transistor component 221 and a second transistor component 222 .

[0066] The first end d11 of the first transistor component 221 is connected to the second input end r2 of the negative feedback module 22 , the second end d12 of the first transistor component 221 is connected to the power supply voltage VDD, and the third end d13 of the first transistor component 221 is connected to the second output end d2 of the negative feedback module 22 .

[0067] The first end d21 of the second transistor component 222 is connected to the second input terminal r2 , the second end d22 of the second transistor component 222 is respectively connected to the third end d13 of the first transistor component 221 and the second output terminal d2 , and the third end d23 of the second transistor component 222 is grounded (GND).

[0068] The first transistor component 221 and the second transistor component 222 are used to: when the first bias voltage Vref1 is higher than the first voltage threshold, enable the second output terminal d2 to output the first adjustment voltage Vr1 to adjust the first bias voltage Vref1 to a second bias voltage Vref2 that is lower than the first bias voltage Vref1; and when the first bias voltage Vref1 is lower than the second voltage threshold, enable the second output terminal d2 to output the second adjustment voltage Vr2 to adjust the first bias voltage Vref1 to a second bias voltage Vref2 that is higher than the first bias voltage Vref1.

[0069] In some optional embodiments, the first transistor component 221 may include at least one PMOS transistor. The second transistor component 222 may include at least one NMOS transistor. The at least one PMOS transistor has a common gate, and the common gate end serves as the first end d11 of the first transistor component 221. The at least one NMOS transistor has a common gate, and the common gate end serves as the first end d21 of the second transistor component 222. Alternatively, in the case where the first transistor component 221 includes at least two PMOS transistors, the gate of one of the at least two PMOS transistors serves as the enable end, and the other PMOS transistors have a common gate, and the common gate end serves as the first end d11 of the first transistor component 221. In the case where the second transistor component 222 includes at least two NMOS transistors, the gate of one of the at least two NMOS transistors serves as the enable end, and the other NMOS transistors have a common gate, and the common gate end serves as the second end d21 of the second transistor component 222. When Vref1 is too high, the pull-down effect of the second transistor component 222 is higher than the pull-up effect of the first transistor component, so that a smaller adjustment voltage (i.e., the first adjustment voltage Vr1) is output at the second output terminal d2 of the negative feedback module 22 to adjust Vref1 to a smaller Vref2. When Vref1 is too low, the pull-up effect of the first transistor component 221 is higher than the pull-down effect of the second transistor component, so that a larger adjustment voltage (i.e., the second adjustment voltage Vr2) is output at the second output terminal d2 of the negative feedback module 22 to adjust Vref1 to a larger Vref2.

[0070] In the disclosed embodiment, the first transistor component 221 is connected to the power supply voltage VDD, and the second transistor component 222 is grounded, and the bias voltage generated by the bias generating module 21 is applied to the first transistor component 221 and the second transistor component 222. Based on the different pull-up capabilities of the first transistor component 221 and the pull-down capabilities of the second transistor component 222 under different bias voltages, different adjustment voltages are generated, thereby effectively realizing the adjustment of the bias voltage and limiting the bias voltage to a smaller fluctuation range.

[0071] Figure 4 is a schematic diagram of the structure of a negative feedback module provided by an exemplary embodiment of the present disclosure.

[0072] In some optional embodiments, such as Figure 4 As shown, the first transistor component 221 may include: a first PMOS transistor MP1 and a second PMOS transistor MP2.

[0073] The first terminal D11 of the first PMOS transistor MP1 serves as the first enable terminal en1 , and the second terminal D12 of the first PMOS transistor MP1 serves as the second terminal d12 of the first transistor component 221 and is connected to the power supply voltage VDD.

[0074] The first end D21 of the second PMOS transistor MP2 serves as the first end d11 of the first transistor component 221 . The second end D22 of the second PMOS transistor MP2 is connected to the third end D13 of the first PMOS transistor MP2 . The third end D23 of the second PMOS transistor MP2 serves as the third end d13 of the first transistor component 221 .

[0075] The second transistor component 222 includes a first NMOS transistor MN1 and a second NMOS transistor MN2 .

[0076] The first end D31 of the first NMOS transistor MN1 serves as the first end d21 of the second transistor component 222 , and the second end D32 of the first NMOS transistor MN1 serves as the second end d22 of the second transistor component 222 .

[0077] The first terminal D41 of the second NMOS transistor MN2 serves as the second enable terminal en2 , the second terminal D42 of the second NMOS transistor MN2 is connected to the third terminal D33 of the first NMOS transistor MN1 , and the third terminal D43 of the second NMOS transistor MN2 serves as the third terminal d23 of the second transistor component 222 and is grounded (GND).

[0078] The first enable terminal en1 and the second enable terminal en2 are connected to opposite enable signals.

[0079] When the first enabling terminal en1 and the second enabling terminal en2 are both in the enabling state, the negative feedback module 22 is in the working state.

[0080] When the first enabling terminal en1 and the second enabling terminal en2 are both in a non-enabled state, the negative feedback module 22 is in a closed state.

[0081] Among them, the first end D11 of the first PMOS transistor MP1 is a gate, the second end D12 is a source, and the third end D13 is a drain. The first end D21 of the second PMOS transistor MP2 is a gate, the second end D22 is a source, and the third end D23 is a drain. The first end D31 of the first NMOS transistor MN1 is a gate, the second end D32 is a drain, and the third end D33 is a source. The first end D41 of the second NMOS transistor MN2 is a gate, the second end D42 is a drain, and the third end D43 is a source. The first enable end en1 and the second enable end en2 enable the negative feedback module 22 to be started or shut down under the action of opposite enable signals. For example, the first enable end en1 is a low level and the second enable end en2 is a high level, so that the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on, and the negative feedback module 22 enters the working state. The first enable terminal en1 is at a high level, and the second enable terminal en2 is at a low level, so that the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned off, and the negative feedback module 22 enters a closed state. When the negative feedback module 22 is in a working state, if the bias voltage Vref1 is too high, the second PMOS transistor MP2 is turned off or enters a variable resistance stage, the first NMOS transistor MN1 is turned on, and the pull-down effect of the first NMOS transistor is higher than the pull-up effect of the second PMOS transistor, and the voltage at the d2 terminal is pulled down to generate a smaller adjustment voltage. On the contrary, if the bias voltage Vref1 is too low, the first NMOS transistor is turned off or enters a variable resistance stage, the second PMOS transistor is turned on, and the pull-up effect of the second PMOS transistor is higher than the pull-down effect of the first NMOS transistor, and the voltage at the d2 terminal is pulled up to generate a larger adjustment voltage.

[0082] In the disclosed embodiment, two PMOS transistors and two NMOS transistors are used to start and shut down the negative feedback module 22, and different adjustment voltages are generated in response to changes in the bias voltage for adjusting the bias voltage, so that the bias voltage can be limited to a specified smaller fluctuation range as needed, thereby improving the stability of the overall circuit.

[0083] Figure 5 is a structural diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure.

[0084] In some optional embodiments, based on any of the above embodiments, Figure 5 As shown, the bias generating module 21 includes: a start-up control component 211 , a transistor current mirror component 212 , an auxiliary transistor component 213 , a cascade transistor component 214 and a resistor 215 .

[0085] The first terminal D51 of the startup control component 211 serves as the first input terminal r1 of the bias generation module 21 , and the second terminal D52 of the startup control component 211 is connected to the power supply voltage VDD.

[0086] The transistor current mirror component 212 is connected to the third terminal D53 of the startup control component 211 and the second output terminal d2 of the negative feedback module 22 respectively.

[0087] The auxiliary transistor component 213 is connected to the transistor current mirror component 212 and the power supply voltage VDD, respectively.

[0088] The cascode transistor component 214 is connected to the transistor current mirror component, the auxiliary transistor component 213 and the first output terminal d1 of the bias generating module 21 respectively.

[0089] A first terminal r11 of the resistor 215 is connected to the cascode transistor component 214 and the first output terminal d1 of the bias generating module 21 , respectively, and a second terminal r12 of the resistor 215 is grounded (GND).

[0090] The start control component 211 starts the bias generation module 21 under the action of the start signal, provides current to the transistor current mirror component 212, the cascade transistor component 214 and the resistor 215, generates a first bias voltage Vref1 at the first end of the resistor 215, and outputs the first bias voltage Vref1 through the first output terminal d1;

[0091] The transistor current mirror component 212 is used to adjust the current of the transistor current mirror component 212, the cascade transistor component 214 and the resistor 215 under the effect of the adjustment voltage Vr of the negative feedback module 22, so as to adjust the first bias voltage Vref1 of the first end r11 of the resistor 215 to the second bias voltage Vref2.

[0092] In some optional embodiments, the startup control component 211 can be implemented by any switch component. For example, the startup control component can be implemented by a transistor. The specific implementation is not limited.

[0093] In some optional embodiments, when the startup control component 211 adopts a transistor, the startup control component 211 may include at least one transistor. The transistor may be a PMOS transistor or an NMOS transistor. Taking a PMOS transistor as an example, the first terminal D51 of the startup control component 211 is the gate of the PMOS transistor, the second terminal D52 is the source, and the third terminal D53 is the drain.

[0094] In some optional embodiments, the transistor current mirror component (may be referred to as current mirror component for short) 212 may include at least three transistors to form at least two pairs of current mirrors.

[0095] In some optional embodiments, the auxiliary transistor component 213 may include at least two transistors, each of which is connected in a current branch of the current mirror component to provide resistance voltage division for the branch. Optionally, the transistor of the auxiliary transistor component 213 may include at least one of an NMOS transistor and a PMOS transistor.

[0096] In some optional embodiments, the cascade transistor component 214 includes at least two transistors connected in series, and the gate of each transistor is connected to the gate of a transistor in the auxiliary transistor component 213, so that the current of the cascade transistor component 214 and the resistor 215 is associated with the current of the current mirror component, thereby achieving the adjustment of the bias voltage by adjusting the current of the current mirror component 212.

[0097] In some optional embodiments, when the start signal is valid, the start control component 211 starts the bias generating module 21 to provide current to the transistor current mirror component 212, the cascade transistor component 214 and the resistor 215 to generate a first bias voltage Vref1. When Vref1 is too high or too low, the negative feedback module 22 is started to generate a regulating voltage to adjust the gate voltage of the current mirror component 212, thereby adjusting the current of the current mirror component 212. Since the current of the cascade transistor component 214 and the resistor 215 is associated with the current of the current mirror component 212, the current of the resistor 215 is adjusted. The voltage at the first end r11 of the resistor 215 is the bias voltage. The change in current leads to the change in bias voltage, thereby achieving the adjustment of the bias voltage.

[0098] In some optional embodiments, the first end of the transistor current mirror component 212 is connected to the third end D53 of the startup control component 211 and the second output end d2 of the negative feedback module 22 respectively. The first end of the auxiliary transistor component 213 is connected to the power supply voltage VDD, the second end of the auxiliary transistor component 213 is connected to the second end of the transistor current mirror component 212, and the third end of the auxiliary transistor component 213 is connected to the third end of the transistor current mirror component 212. The first end of the cascade transistor component 214 is connected to the second end of the transistor current mirror component 212 and the second end of the auxiliary transistor component 213 respectively. The second end of the cascade transistor component 214 is connected to the third end of the transistor current mirror component 212 and the third end of the transistor current mirror component 212 respectively. The third end of the cascade transistor component 214 is connected to the power supply voltage, and the fourth end of the cascade transistor component 214 is connected to the first end r11 of the resistor 215. The fourth end of the transistor current mirror component 212 is grounded.

[0099] In the disclosed embodiment, the startup control component can effectively control the startup and shutdown of the bias generation module 21, and the transistor current mirror component can provide current for the generation of the bias voltage. The auxiliary transistor component assists in voltage division, combines the cascade transistor component and the current mirror component, and generates the required bias voltage. The cascade transistor component can increase the output impedance of the branch in which it is located, weaken the influence of the drain-source voltage on the current of a single transistor, so that the current of the branch is more stable, that is, the current of the resistor is more stable, which helps to generate a more stable bias voltage.

[0100] Figure 6 is a structural diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure.

[0101] In some optional embodiments, based on any of the above embodiments, Figure 6 As shown, the bias generating module 21 may further include: a capacitor 216 .

[0102] A first end c1 of the capacitor 216 is connected to a first end r11 of the resistor 215 , and a second end c2 of the capacitor 216 is grounded (GND).

[0103] The capacitor 216 and the resistor 215 form a parallel circuit.

[0104] In the embodiment of the present disclosure, by adding a capacitor 216 connected in parallel with the resistor 215, the generated bias voltage can be further stabilized, high-frequency noise can be filtered, and phase compensation can be performed on the negative feedback module 22 to further improve the stability of the loop.

[0105] Figure 7 is a structural diagram of a bias generating module provided by an exemplary embodiment of the present disclosure.

[0106] In some optional embodiments, based on any of the above embodiments, Figure 7 As shown, the transistor current mirror component 212 may include: a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5.

[0107] The first end D61 of the third NMOS transistor MN3 is connected to the second end D62 of the third NMOS transistor and the second output end d2 of the negative feedback module 22 respectively; the second end D62 of the third NMOS transistor MN3 is connected to the third end D53 of the startup control component 211; the third end D63 of the third NMOS transistor MN3 is grounded (GND).

[0108] A first terminal D71 of the fourth NMOS transistor MN4 is connected to the first terminal D61 of the third NMOS transistor MN3 , a second terminal D72 of the fourth NMOS transistor MN4 is connected to the auxiliary transistor component 213 , and a third terminal D73 of the fourth NMOS transistor MN4 is grounded (GND).

[0109] A first terminal D81 of the fifth NMOS transistor MN5 is connected to the first terminal D61 of the third NMOS transistor MN3 , a second terminal D82 of the fifth NMOS transistor MN5 is connected to the auxiliary transistor component 213 , and a third terminal D83 of the fifth NMOS transistor MN5 is grounded (GND).

[0110] For any NMOS tube, the first end is the gate, the second end is the drain, and the third end is the source. Figure 7 As shown, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 form a pair of current mirrors, and the third NMOS transistor MN3 and the fifth NMOS transistor MN5 form another pair of current mirrors, forming three current branches in total. Through the voltage division effect of the auxiliary transistor component 213, the gate voltage of the cascode transistor component 214 is controlled, thereby controlling the current of the cascode transistor component 214 and the resistor 215 branch, and realizing the generation and adjustment of the bias voltage.

[0111] In some optional embodiments, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are gated together, that is, the first end D61 of the third NMOS transistor MN3, the first end D71 of the fourth NMOS transistor MN4 and the first end D81 of the fifth NMOS transistor MN5 are connected, the gate voltages of the three transistors are the same, and the first end D61 of the third NMOS transistor MN3 is connected to the second end D62, so that the gate and drain voltages are the same. The second end D62 of the third NMOS transistor MN3 is connected to the third end D53 of the start control component 211 as the first end of the transistor current mirror component 212. The third end of the third NMOS transistor MN3, the third end of the fourth NMOS transistor MN4 and the third end of the fifth NMOS transistor MN5 are grounded together as the fourth end of the transistor current mirror component 212. The second end D72 of the fourth NMOS transistor MN4 is connected to the second end of the auxiliary transistor component 213 as the second end of the transistor current mirror component 212. The second terminal D82 of the fifth NMOS transistor MN5 serves as the third terminal of the transistor current mirror component 212 and is connected to the third terminal of the auxiliary transistor component 213 .

[0112] In the disclosed embodiment, two pairs of current mirrors are used to provide two current branches, which are respectively used to control and adjust the gate voltage of the cascade transistor component 214, so as to adjust the current of the branch of the cascade transistor component 214, thereby effectively adjusting the generated bias voltage.

[0113] In some optional embodiments, such as Figure 7 As shown, the auxiliary transistor component 213 may include: a third PMOS transistor MP3 and a fourth PMOS transistor MP4.

[0114] The first end D91 of the third PMOS transistor MP3 is connected to the cascode transistor component 214, the second end D92 of the third PMOS transistor MP3 is connected to the power supply voltage VDD, and the third end D93 of the third PMOS transistor MP3 is respectively connected to the first end D91 of the third PMOS transistor MP3 and the second end D72 of the fourth NMOS transistor MN4.

[0115] A first terminal D101 of the fourth PMOS transistor MP4 is connected to the cascode transistor component 214, a second terminal D102 of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD, and a third terminal D103 of the fourth PMOS transistor MP4 is respectively connected to the first terminal D101 of the fourth PMOS transistor MP4 and the second terminal D82 of the fifth NMOS transistor MN5.

[0116] Among them, the first end of any PMOS transistor is a gate, the second end is a source, and the third end is a drain. The second end D92 of the third PMOS transistor MP3 and the second end D102 of the fourth PMOS transistor MP4 are used together as the first end of the auxiliary transistor component 213, connected to the power supply voltage VDD. The third end D93 of the third PMOS transistor MP3 is used as the second end of the auxiliary transistor component 213, and is connected to the second end of the transistor current mirror component 212 (such as the second end D72 of the fourth NMOS transistor MN4 in the figure). The third end D103 of the fourth PMOS transistor MP4 is used as the third end of the auxiliary transistor component 213, and is connected to the third end of the transistor current mirror component 212 (such as the second end D82 of the fifth NMOS transistor MN5). The first end D91 of the third PMOS transistor MP3 is connected to the second end (i.e., D93) of the auxiliary transistor component 214 and the first end of the cascade transistor component 214, that is, the voltage of the first end of the cascade transistor component 213 is the same as the gate voltage and drain voltage of the third PMOS transistor MP3 (without considering the line resistance). The first end D101 of the fourth PMOS transistor MP4 is connected to the third end (i.e., D103) of the auxiliary transistor component 214 and the second end of the cascade transistor component 214, that is, the voltage of the second end of the cascade transistor component 214 is the same as the gate voltage and drain voltage of the fourth PMOS transistor MP4. Since the third end D93 of the third PMOS transistor MP3 is connected to the second end D71 of the fourth NMOS transistor MN4, the voltage of the first end of the cascade transistor component 214 is the result of the voltage division of the third PMOS transistor MP3 and the fourth NMOS transistor component MN4. Similarly, the voltage of the second end of the cascade transistor component 214 is the result of the voltage division of the fourth PMOS transistor MP4 and the fifth NMOS transistor component MN5. As a result, the current magnitudes of the two branches of the current mirror component 212 can affect the current of the branch where the cascade transistor component 214 is located, and then the bias voltage is adjusted by adjusting the current.

[0117] In the disclosed embodiment, two PMOS transistors are used to divide the voltage of two branches of the current mirror component 212, thereby assisting in controlling the branch current of the cascode transistor component 214 and effectively achieving the control of the bias voltage.

[0118] In some optional embodiments, the cascode transistor component 214 includes: a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6 .

[0119] A first end D111 of the fifth PMOS transistor MP5 is connected to the first end D91 of the third PMOS transistor MP3 , and a second end D112 of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD.

[0120] A first end D121 of the sixth PMOS transistor MP6 is connected to the first end D101 of the fourth PMOS transistor MP4, a second end D122 of the sixth PMOS transistor MP6 is connected to the third end D113 of the fifth PMOS transistor MP5, and a third end D123 of the sixth PMOS transistor MP6 is connected to the first output end d1 of the bias generating module and the first end r11 of the resistor 215, respectively.

[0121] Among them, the first end of any PMOS transistor is a gate, the second end is a source, and the third end is a drain. The first end D111 of the fifth PMOS transistor MP5 serves as the first end of the cascade transistor component 214, and the first end D121 of the sixth PMOS transistor MP6 serves as the second end of the cascade transistor component 214. The second end D112 of the fifth PMOS transistor MP5 serves as the third end of the cascade transistor component 214, connected to the power supply voltage. The third end D123 of the sixth PMOS transistor MP6 serves as the fourth end of the cascade transistor component 214, connected to the first end r11 of the resistor 215. The first end r11 of the resistor 215 serves as the first output end d1 of the bias generating module 21, outputting the bias voltage Vref (for example, Vref1 or Vref2). Figure 7 As shown, when the negative feedback module 21 feeds back a smaller adjustment voltage through the second output terminal d2, that is, the voltages at the terminals D62, D71 and D81 are reduced, the gate voltages of the transistors of the current mirror component 212 are reduced, thereby reducing the branch current of the current mirror component 212, and further reducing the branch currents of the cascade transistor component 214 and the resistor 215. The resistance value and current size of the resistor 215 determine the bias voltage, thus reducing the bias voltage, thereby adjusting the bias voltage from the first bias voltage Vref1 to a smaller second bias voltage Vref2. The working process of increasing the bias voltage is opposite to the working process of decreasing the bias voltage, and will not be described in detail here.

[0122] The embodiment of the present disclosure can further improve the stability of the branch current by using two cascaded PMOS transistors, thereby improving the stability of the bias voltage.

[0123] In some optional embodiments, Figure 8 FIG. 1 is a schematic diagram of a bias generation module provided by another exemplary embodiment of the present disclosure. Figure 8 As shown, in Figure 7 Based on the embodiment shown, the bias generating module 21 further includes a capacitor 216. During the bias voltage generation and adjustment process, the capacitor 216 can further stabilize the generated bias voltage, filter high-frequency noise, and can also perform phase compensation on the negative feedback module 22 to further improve the stability of the loop.

[0124] In some optional embodiments, Fig. 9FIG. 1 is a schematic diagram of a bias circuit provided by another exemplary embodiment of the present disclosure. Fig. 9 As shown, based on any of the above embodiments, for example, Figure 7 or Figure 8 Based on the embodiment shown, it can be combined Figure 3 or Figure 4 The negative feedback module 22 shown forms a feedback loop with the bias generating module 21. When the bias voltage generated by the bias generating module 21 is higher than the first voltage threshold, the voltages of D62, D61, D71, and D81 are pulled down through the negative feedback module 22, thereby reducing the bias voltage. When the bias voltage generated by the bias generating module 21 is lower than the second voltage threshold (the second voltage threshold is lower than the first voltage threshold), the voltages of D62, D61, D71, and D81 are pulled up through the negative feedback module 22, thereby increasing the bias voltage. This can avoid the bias voltage being too high or too low, and limit the bias voltage to a smaller fluctuation range between the first voltage threshold and the second voltage threshold.

[0125] Fig.10 is a structural diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure.

[0126] In some optional embodiments, based on any of the above embodiments, Fig.10 As shown, the bias circuit 20 of the embodiment of the present disclosure may further include: a bias adjustment module 23.

[0127] The bias adjustment module 23 includes at least one parallel switch branch 231, each switch branch 231 includes at least one switch component; the first end d31 of each switch branch 231 is connected to the adjustment control signal, the second end d32 of each switch branch 231 is connected to the power supply voltage VDD, and the third end d33 of each switch branch 231 is connected to the bias generation module 21.

[0128] Each switch branch 231 is used for injecting a current into the bias generating module 21 when the adjustment control signal is valid, so as to increase the first bias voltage Vref1 generated by the bias generating module 21 .

[0129] In some optional embodiments, the number of switch branches 231 can be set to any number according to the requirements, which is not limited by the embodiments of the present disclosure. For example, the number of switch branches 231 can be 1, 2, 3, etc. The number of switch components included in each switch branch 231 can be any number, for example, the number of switch components can be 1, 2, 3, etc. The adjustment control signal can include a high level signal and a low level signal. The adjustment control signal is effective means that the adjustment control signal makes the switch branch 231 conductive, and can inject a current into the bias generation module 21. Optionally, the adjustment control signal can be high level effective or low level effective, which can be specifically set according to the characteristics of the switch components on the branch, which is not limited by the embodiments of the present disclosure. The switch component of each branch can be a transistor or other switch component, and the transistor can be, for example, a PMOS transistor or an NMOS transistor.

[0130] In some optional embodiments, the number of switch components of any two switch branches may be the same or different.

[0131] In some optional embodiments, according to the requirement for the size of the bias voltage, m (m=0, 1, 2, ...) switch branches 231 can be controlled to be turned on, so as to inject the current of the corresponding path into the bias generation module 21, so that the bias generation module 21 can generate bias voltages of different sizes. For example, when all switch branches are closed, the bias generation module 21 can generate a bias voltage in the fluctuation range of v1-v2. When one switch branch is turned on, the bias generation module 21 can generate a bias voltage in the fluctuation range of v3-v4, where v3 is greater than v1 and v4 is greater than v2. When two switch branches are turned on, the bias generation module 21 can generate a bias voltage in the fluctuation range of v5-v6, and so on. For each additional switch branch turned on, the bias voltage generated is improved overall. The fluctuation range is caused by factors such as process angle and temperature.

[0132] In some optional embodiments, the third end d33 of each switch branch 231 is further connected to the second output end d2 of the negative feedback module 22 .

[0133] In some optional embodiments, when the bias adjustment module 23 turns on at least one switch branch, the negative feedback module 22 may be turned off, that is, the bias adjustment module 23 and the negative feedback module 22 may be used selectively.

[0134] In some optional embodiments, when the bias adjustment module 23 turns on at least one switch branch, the negative feedback module 22 can be in a working state. In this case, the corresponding first voltage threshold and the second voltage threshold can be set for the case of turning on different numbers of switch branches, so that the generated bias voltages of different levels can have a smaller fluctuation range. For example, when one switch branch is turned on, if the negative feedback module 22 is not turned on, the generated bias voltage fluctuation range is v3-v4, and turning on the negative feedback module 22 reduces the fluctuation range of the bias voltage to v7-v8, satisfying at least one of the conditions that v7 is greater than v3 and v8 is less than v4.

[0135] In the disclosed embodiment, the bias adjustment module 23 can inject one or more currents into the bias generation module 21, so that the bias generation module 21 can generate bias voltages of different levels, which helps to improve the versatility of the bias circuit and enables the bias circuit to be applied to analog circuits with different bias voltage requirements.

[0136] Fig.11 is a structural diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure.

[0137] In some optional embodiments, Fig.10 Based on the embodiment shown, Fig.11 As shown, the bias generating module 21 includes a startup control component 211 , a transistor current mirror component 212 , an auxiliary transistor component 213 , a cascode transistor component 214 and a resistor 215 .

[0138] The third terminal d33 of each switch branch 231 is connected to the third terminal D53 of the start-up control component 211 and the transistor current mirror component 212 respectively.

[0139] Each switch branch 231 is used to inject a current into the transistor current mirror component 212 when the adjustment control signal is valid, so as to increase the gate voltage of the transistor in the transistor current mirror component 212, thereby increasing the current flowing through the resistor 215 and adjusting the first bias voltage Vref1 to a third bias voltage Vref3 greater than the first bias voltage Vref1.

[0140] The specific structure of the bias generating module 21 may refer to any of the above-mentioned related embodiments, for example Figure 5 , Figure 6 , Figure 7Each switch branch 231 is turned on when the adjustment control signal is valid, injecting a current into the transistor current mirror component 212, so that the current of the transistor current mirror component 212 increases, thereby increasing the gate voltage of the transistor in the transistor current mirror component 212, causing the current of the cascade transistor component 214 and the resistor 215 branch to increase, thereby increasing the bias voltage, and realizing the adjustment of the magnitude of the bias voltage.

[0141] Fig.12 is a structural diagram of a bias circuit provided by yet another exemplary embodiment of the present disclosure.

[0142] In some optional embodiments, such as Fig.12 As shown, each switch branch 231 may include:

[0143] At least two switch components T are connected in series; the first end t11 of each switch component T is connected to the first end d31 of the switch branch; each switch component T is turned on when the adjustment control signal is valid to generate current in the switch branch 231. Each switch component T is turned off when the adjustment control signal is invalid to disconnect the current generated by the switch branch 231. The figure only shows the structure of one switch branch 231, and the structures of other switch branches 231 are similar.

[0144] Among them, the second end t12 of the switch component T located on the first side (such as the upper side in the figure) of the at least two switch components T connected in series serves as the second end d32 of the switch branch 231, connected to the power supply voltage VDD. The third end t13 of the switch component T located on the second side (such as the lower side in the figure) of the at least two switch components T connected in series serves as the third end d33 of the switch branch 231, connected to the bias generating module 21.

[0145] In some optional embodiments, the switch component T takes a PMOS transistor as an example. If the switch branch includes n (n is a positive integer) PMOS transistors, the n PMOS transistors have a common gate, and the common gate terminal (t11) serves as the first terminal d31 of the switch branch, the source of the first PMOS transistor (the second terminal t12) serves as the first terminal d32 of the switch branch, connected to the power supply voltage VDD, the source of the second PMOS transistor is connected to the drain of the first PMOS transistor, the source of the third PMOS transistor is connected to the drain of the second PMOS transistor, and so on, the drain of the nth PMOS transistor (the third terminal t13) serves as the third terminal d33 of the switch branch.

[0146] In some optional embodiments, Fig.13 FIG. 1 is a schematic diagram of a bias circuit provided by another exemplary embodiment of the present disclosure. Fig.13As shown, the third end d33 of each switch branch 231 in the bias adjustment module 23 is connected to the third end D53 of the start control component 211 and the second end D62 of the third NMOS transistor MN3. When the switch branch 231 is turned on, a current is injected into the third NMOS transistor MN3 in the transistor current mirror component 212, so that the current of the third NMOS transistor MN3 increases, thereby increasing the voltage at the D61 end, causing the current of the fifth NMOS transistor MN5 to increase, and then the current of the resistor 215 increases, and the resistance value of the resistor 215 remains unchanged, so that the voltage of the first end r11 of the resistor 215 increases, and the bias voltage is adjusted. According to the bias voltage requirement, by controlling the on and off of each switch branch 231, the bias voltage of different voltage levels can be controlled.

[0147] In some optional embodiments, Fig.14 FIG. 1 is a schematic diagram of a bias circuit provided by another exemplary embodiment of the present disclosure. Fig.14 As shown, the bias adjustment module 23 takes two switch branches as an example, Modify0 and Modify1 represent the adjustment control signals of the two switch branches respectively, start represents the start signal, the bias generation module 21 includes 8 MOS transistors M0-M7, a resistor R and a capacitor C, Va and Vb are the real-time voltages of the gates of M6 and M7 respectively. C is a capacitor 216, R is a resistor 215, M0 is a start control component, M1, M2 and M5 form a transistor current mirror component 212, M3 and M4 form an auxiliary transistor component 213, M6 and M7 form a cascade transistor component 214, M8, M9, M10 and M11 form a negative feedback module 22, Feedback_enb and Feedback_en represent the first enable terminal en1 and the second enable terminal en2 respectively. M1 corresponds to the third NMOS transistor MN3 in the above embodiment, M2 corresponds to the fourth NMOS transistor MN4 in the above embodiment, M5 corresponds to the fifth NMOS transistor MN5 in the above embodiment, M3 corresponds to the third PMOS transistor MP3 in the above embodiment, M4 corresponds to the fourth PMOS transistor MP4 in the above embodiment, M6 corresponds to the fifth PMOS transistor MP5 in the above embodiment, M7 corresponds to the sixth PMOS transistor MP6, M8 and M9 correspond to the first PMOS transistor MP1 and the second PMOS transistor MP2 respectively, and M10 and M11 correspond to the first NMOS transistor MN1 and the second NMOS transistor MN2 respectively. Fig.14 The specific working principle of the bias circuit shown can be found in the above-mentioned embodiment and will not be elaborated here.

[0148] In the related art, see Figure 1, T1-T4 form a bias circuit. If T4 is equal to T3 in size, that is, the width W and length L of the MOS tube are the same, the size of T2 is K times that of T1 (that is, the width-to-length ratio W / L of T2 is K times that of T1), and the currents of the two branches (that is, the branch where T3 and T1 are located, and the branch where T4 and T2 are located) are equal, it can be expressed as follows:

[0149] Formula 1

[0150] Since the gate-source voltage difference of T1 (also called drain-source voltage difference because the gate voltage and drain voltage are equal) is equal to the voltage drop of T2 plus resistor R1, the following equation 2 or equation 3 can be obtained:

[0151] Formula 2

[0152] Formula 3

[0153] in, represents the voltage between the gate G and source S of T1 (gate-source voltage difference), Represents the voltage between the gate G and source S of T2. In represents the electron mobility and is a constant. It represents the gate oxide capacitance per unit area, which is a constant. W represents the MOS tube width of T1, L represents the MOS tube length of T1, and N represents NMOS. represents the threshold voltage of T1 conduction, It represents the threshold voltage of T2 turning on. In express or ( ).

[0154] Therefore, we get the following formula 4:

[0155] Formula 4

[0156] According to Formula 4, it can be concluded that the current obtained by this current bias circuit has nothing to do with the power supply voltage. If the channel length modulation effect is ignored, the circuit can show very little power supply correlation. However, in practical applications, the channel modulation effect is inevitable. The lower output impedance brought by the short channel device makes the current generated by it extremely sensitive to the power supply voltage (i.e., VDD), and this design is more obvious to the process angle and temperature. Under different process angles, the output bias voltage Vref fluctuates quite significantly. The bias voltage with excessive fluctuations as the reference voltage of the analog circuit can easily cause the function of other circuit modules in the analog circuit to be abnormal, thereby affecting the stability of the overall analog circuit system. Although the related art also appears to use two groups of common source and common gate tubes to replace T1 and T2, T3 and T4 respectively to reduce the influence of the power supply voltage, so that the short channel effect of the MOS tubes on the two branches is weakened, but this also introduces a new problem, that is, in a more advanced process, since four MOS tubes appear on one branch at the same time, the lower power supply voltage is difficult to ensure that the mirror tube is always in a saturated state, therefore, the optional minimum range of the power supply voltage is limited, which is not friendly to the advanced process. Moreover, the resistance of resistor R1 will also change under different process angles and temperatures. Under lower power supply voltage, the offset of the resistance value can easily cause the mirror MOS tube to fall from the saturation region to the linear region, resulting in inaccurate bias voltage or bias current.

[0157] In view of the above problems, the present disclosure embodiment (see Fig.14 ) By cascading transistor components and resistor voltage dividers in the bias generation module, the situation where the power supply voltage range becomes smaller can be effectively avoided, and the output impedance of this branch is increased, reducing the influence of the drain-source voltage on the current of the transistor M6, making the current of this path more stable. The bias voltage generated by the bias generation module can also be adjusted by the negative feedback module. If the generated bias voltage is too high, the negative feedback loop is started, which will lower the gate-drain voltage of the voltage divider tube M1, thereby reducing the bias current Iref of the resistor R, and achieving the effect of balancing the bias voltage Vref. On the contrary, if the generated bias voltage is too low, the negative feedback loop is started, which will increase the gate-drain voltage of the voltage divider tube M1, thereby increasing the bias current Iref of the resistor R. Through the feedback regulation of the negative feedback loop, the fluctuation range of the bias voltage can be effectively reduced, and the situation where the generated bias voltage is affected by factors such as process angle and temperature and has a large fluctuation range can be avoided. In addition, by connecting a capacitor C in parallel at both ends of the resistor R, the generated bias voltage can be further stabilized, high-frequency noise can be filtered, and the negative feedback loop can be phase compensated to further improve the loop stability.

[0158] After scanning and verifying the process angle and temperature of the PMOS tube, NMOS tube and resistor under a certain process, compared with the current bias circuit of the related art, the bias circuit of the embodiment of the present disclosure can reduce the fluctuation range of the bias voltage generated by a large proportion under a certain process (for example, 7nm process), for example, the fluctuation range can be reduced by 1% to more than 50%. It can be seen that the bias voltage generated by the embodiment of the present disclosure has higher accuracy, is less susceptible to the influence of power supply voltage and process, can greatly improve the overall stability of the analog circuit, and is more friendly to lower power supply voltage (i.e. advanced process) process, and is less susceptible to the influence of resistance value fluctuation.

[0159] The various embodiments and optional examples of the present disclosure may be implemented separately, or may be implemented in combination in any manner without conflict, and may be specifically configured according to actual needs.

[0160] An embodiment of the present disclosure also provides a chip, comprising the bias circuit provided by any of the above embodiments.

[0161] In some optional embodiments, the chip of the embodiment of the present disclosure may also include other circuit modules that require the above-mentioned bias voltage, such as an analog-to-digital converter circuit, an operational amplifier circuit, etc.

[0162] An embodiment of the present disclosure further provides an electronic device, comprising the chip provided by any of the above embodiments.

[0163] In some optional embodiments, the electronic device may further include other circuit modules, such as an analog-to-digital converter circuit, an operational amplifier circuit, etc.

[0164] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0165] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0166] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0167] The bias circuit of the present disclosure may be implemented in many ways. For example, the bias circuit of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps of the method in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0168] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0169] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0170] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A bias circuit comprising: A bias generating module, wherein a first input terminal of the bias generating module is used to input a start signal; The first output terminal of the bias generating module is used to output a first bias voltage; A negative feedback module, wherein a second input end of the negative feedback module is connected to the first output end of the bias generating module, and a second output end of the negative feedback module is connected to the bias generating module; The bias generating module is used for generating the first bias voltage under the action of the start signal, and outputting the first bias voltage from the first output terminal; The negative feedback module is used for feeding back an adjustment voltage to the bias generating module under the action of the first bias voltage, so as to adjust the first bias voltage generated by the bias generating module to a second bias voltage; Wherein, the negative feedback module comprises: a first transistor component, wherein a first terminal of the first transistor component is connected to the second input terminal, a second terminal of the first transistor component is connected to a power supply voltage, and a third terminal of the first transistor component is connected to the second output terminal; a second transistor component, wherein a first terminal of the second transistor component is connected to the second input terminal, a second terminal of the second transistor component is respectively connected to a third terminal of the first transistor component and the second output terminal, and a third terminal of the second transistor component is grounded; The first transistor component and the second transistor component are used to: when the first bias voltage is higher than a first voltage threshold, enable the second output terminal to output a first adjustment voltage to adjust the first bias voltage to the second bias voltage that is lower than the first bias voltage; and when the first bias voltage is lower than a second voltage threshold, enable the second output terminal to output a second adjustment voltage to adjust the first bias voltage to the second bias voltage that is higher than the first bias voltage; The first transistor component comprises: a first PMOS transistor, wherein a first terminal of the first PMOS transistor serves as a first enable terminal, and a second terminal of the first PMOS transistor serves as a second terminal of the first transistor component and is connected to a power supply voltage; a second PMOS transistor, wherein a first end of the second PMOS transistor serves as a first end of the first transistor component, a second end of the second PMOS transistor is connected to a third end of the first PMOS transistor; and a third end of the second PMOS transistor serves as a third end of the first transistor component; The second transistor component comprises: a first NMOS transistor, wherein a first terminal of the first NMOS transistor serves as a first terminal of the second transistor component, and a second terminal of the first NMOS transistor serves as a second terminal of the second transistor component; a second NMOS transistor, wherein a first terminal of the second NMOS transistor serves as a second enable terminal, a second terminal of the second NMOS transistor is connected to a third terminal of the first NMOS transistor, and a third terminal of the second NMOS transistor is grounded as a third terminal of the second transistor component; The first enable terminal and the second enable terminal are connected to opposite enable signals; When the first enabling terminal and the second enabling terminal are both in an enabling state, the negative feedback module is in a working state; When the first enabling terminal and the second enabling terminal are both in a disabled state, the negative feedback module is in a closed state.

2. The bias circuit according to claim 1, wherein: The bias generating module comprises: A start-up control component, wherein a first terminal of the start-up control component serves as a first input terminal of the bias generation module, and a second terminal of the start-up control component is connected to a power supply voltage; A transistor current mirror component is connected to the third terminal of the startup control component and the second output terminal of the negative feedback module respectively; an auxiliary transistor component, connected to the transistor current mirror component and a power supply voltage respectively; a cascade transistor component, connected to the transistor current mirror component, the auxiliary transistor component and the first output terminal respectively; a resistor, wherein a first end of the resistor is respectively connected to the cascade transistor component and the first output end, and a second end of the resistor is grounded; Under the action of the start signal, the start control component starts the bias generation module to provide current to the transistor current mirror component, the cascade transistor component and the resistor, generate the first bias voltage at the first end of the resistor, and output the first bias voltage through the first output end; The transistor current mirror component is used to adjust the current of the transistor current mirror component, the cascade transistor component and the resistor under the action of the adjustment voltage of the negative feedback module, so as to adjust the first bias voltage of the first end of the resistor to the second bias voltage.

3. The bias circuit according to claim 2, wherein: Also includes: A capacitor, a first end of the capacitor is connected to the first end of the resistor, and a second end of the capacitor is grounded.

4. The bias circuit according to claim 2, wherein: The transistor current mirror component comprises: a third NMOS transistor, wherein a first end of the third NMOS transistor is respectively connected to a second end of the third NMOS transistor and a second output end of the negative feedback module; a second end of the third NMOS transistor is connected to a third end of the startup control component; and a third end of the third NMOS transistor is grounded; a fourth NMOS transistor, wherein a first terminal of the fourth NMOS transistor is connected to the first terminal of the third NMOS transistor, a second terminal of the fourth NMOS transistor is connected to the auxiliary transistor component, and a third terminal of the fourth NMOS transistor is grounded; a fifth NMOS transistor, wherein a first terminal of the fifth NMOS transistor is connected to the first terminal of the third NMOS transistor, a second terminal of the fifth NMOS transistor is connected to the auxiliary transistor component, and a third terminal of the fifth NMOS transistor is grounded.

5. The bias circuit according to claim 4, wherein: The auxiliary transistor assembly comprises: a third PMOS transistor, wherein a first end of the third PMOS transistor is connected to the cascade transistor component, a second end of the third PMOS transistor is connected to a power supply voltage, and a third end of the third PMOS transistor is respectively connected to the first end of the third PMOS transistor and the second end of the fourth NMOS transistor; A fourth PMOS transistor, wherein a first end of the fourth PMOS transistor is connected to the cascade transistor component, a second end of the fourth PMOS transistor is connected to a power supply voltage, and a third end of the fourth PMOS transistor is respectively connected to the first end of the fourth PMOS transistor and the second end of the fifth NMOS transistor.

6. The bias circuit according to claim 5, wherein: The cascade transistor assembly comprises: a fifth PMOS transistor, wherein a first end of the fifth PMOS transistor is connected to the first end of the third PMOS transistor, and a second end of the fifth PMOS transistor is connected to a power supply voltage; a sixth PMOS transistor, wherein a first end of the sixth PMOS transistor is connected to a first end of the fourth PMOS transistor, a second end of the sixth PMOS transistor is connected to a third end of the fifth PMOS transistor, and a third end of the sixth PMOS transistor is respectively connected to the first output end and a first end of the resistor.

7. The bias circuit according to any one of claims 1 to 6, further comprising: A bias adjustment module, comprising at least one switch branch connected in parallel, each of the switch branches comprising at least one switch component; The first end of each of the switch branches is connected to the adjustment control signal, the second end of each of the switch branches is connected to the power supply voltage, and the third end of each of the switch branches is connected to the bias generating module; Each of the switch branches is used to inject a current into the bias generating module when the adjustment control signal is valid, so as to increase the first bias voltage generated by the bias generating module.

8. The bias circuit according to claim 7, wherein: The bias generation module includes a startup control component, a transistor current mirror component, an auxiliary transistor component, a cascade transistor component and a resistor; The third end of each of the switch branches is respectively connected to the third end of the start-up control component and the transistor current mirror component; Each of the switch branches is used to inject a current into the transistor current mirror component when the adjustment control signal is valid, so as to increase the gate voltage of the transistor in the transistor current mirror component, thereby increasing the current flowing through the resistor and adjusting the first bias voltage to a third bias voltage greater than the first bias voltage.

9. The bias circuit according to claim 7, wherein: Each of the switch branches comprises: At least two switch components connected in series; a first end of each switch component is connected to a first end of the switch branch; Each switch component is turned on when the adjustment control signal is valid to generate current in the switch branch; Each switch component is closed when the adjustment control signal is invalid to disconnect the current generated by the switch branch.

10. A chip, comprising: The bias circuit according to any one of claims 1 to 9.

11. An electronic device comprising: The chip according to claim 10.

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