Execution of commands addressed to logical blocks

Abstract

The invention relates to executing commands addressed to a logical block. A controller of a memory subsystem may mark a portion of a plurality of commands addressed to a same logical block of a memory device in response to providing a command completion signal to a host, reorder the marked portion of the plurality of commands, wherein a write command given to the tagged portion from the plurality of commands is prioritized over a read command from the tagged portion of the plurality of commands, executing a latest write command from the tagged portion of the plurality of commands before executing a read command from the tagged portion of the plurality of commands addressed to the same logical block, and execute the read command from the marked portion of the plurality of commands in an order of receiving the read command and after the execution of the latest write command, wherein the read command is executed in response to the execution of the latest write command.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with an application date of December 28, 2020, application number 202011577372.2, and invention name “Execution of commands addressed to logic blocks”.

[0003] Priority information

[0004] This application claims priority to U.S. Provisional Application No. 62 / 954,866, filed on December 30, 2019, the contents of which are incorporated herein by reference. Technical Field

[0005] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to executing overlapping commands. Background Art

[0006] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, nonvolatile memory devices and / or volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0007] According to one aspect of the present application, a system for executing commands addressed to the same logical block is provided. The system includes: memory devices 130, 140; a host interface; and a processing device 115, which is coupled to the memory devices and the host interface to perform the following operations: marking a portion of a plurality of commands 221 addressed to the same logical block of the memory device in response to providing a command completion signal 227 to the host 120; executing the latest write command from the marked portion of the plurality of commands before executing a read command addressed to the same logical block from the marked portion of the plurality of commands; and executing the read command from the marked portion of the plurality of commands in the order in which the read commands are received and after the execution of the latest write command, wherein the read command is executed in response to the execution of the latest write command.

[0008] According to another aspect of the present application, a method for executing commands addressed to the same logical block is provided. The method includes: receiving a command 221 addressed to a logical block of a plurality of memory devices 130, 140; determining whether a most recently executed command is addressed to the logical block; marking the command in response to determining that the most recently executed command is addressed to the logical block; adding the command addressed to the logical block to a first-in first-out (FIFO) memory 224 in response to marking the command; and executing a plurality of commands stored in the FIFO memory.

[0009] According to another aspect of the present application, a system for executing commands addressed to the same logical block is provided. The system includes: a processing device 117; memory devices 130, 140; a controller 106, which is coupled to the memory device and the processing device to perform the following operations: intercepting a first command completion signal 227 identifying the completion of a first command 221 addressed to a first logical block; determining that a pending command 221 is to a different logical block other than the first logical block in response to intercepting the first command completion signal; identifying a second command 221 addressed to a second logical block to be executed; marking the command 221 addressed to the second logical block from the pending commands; and providing the marked command to the processing device by the following operations: providing the latest write command from the marked command for execution; and providing a read command from the marked command for execution in the order in which the read command is received. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0011] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0012] Figure 2 An example of command overlay circuitry according to some embodiments of the present disclosure is described.

[0013] Figure 3 is a flow chart of an example method for commanding overlay circuitry according to some embodiments of the present disclosure.

[0014] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure are directed to a memory subsystem that executes commands addressed to the same logical block. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0016] The host system may send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem and read data from a memory device on the memory subsystem. As specified by the host request, the data to be read or written is referred to as "host data" hereinafter. The host request may include logical address information (e.g., logical block address (LBA), name space) for the host data, which is the location that the host system associates with the host data. The logical address information may be part of the metadata for the host data.

[0017] The memory subsystem may receive access requests, referred to as access commands. The memory subsystem may also receive different types of commands, such as management commands. The memory subsystem may execute the commands. However, according to some conventional methods, the memory subsystem may execute the commands out of order. Conventionally, the memory subsystem may execute a read command before executing a write command so that the read command may access outdated data.

[0018] Aspects of the present disclosure address the above and other deficiencies. To provide access to update data, the memory subsystem may identify and execute commands addressed to the same logical block (LB). For example, the memory subsystem may identify and execute commands that read data and / or write data to the same logical block. The memory subsystem may execute a write command before executing a read command. The identification and execution of commands may be based on the completion of different commands addressed to the same LB. The latest write command may be executed before executing a read command. Read commands may also be executed in the order in which they are received by the memory subsystem.

[0019] The figures herein follow a numbering convention in which the first one or more digits correspond to the figure number and the remaining digits identify an element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 106 may refer to Figure 1 Element "06" in , and similar elements can be represented as Figure 2 206 in. As will be appreciated, the elements shown in the various embodiments herein may be added, exchanged and / or eliminated in order to provide several additional embodiments of the present disclosure. In addition, as will be appreciated, the proportions and relative scales of the elements provided in the drawings are intended to illustrate certain embodiments of the present invention and should not be taken in a limiting sense.

[0020] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical connections, optical connections, magnetic connections, and the like.

[0024] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses, for example, the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0025] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to a component (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices 130 and / or volatile memory devices 140. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM) such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130, 140 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory devices 130, 140 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] Although a nonvolatile memory device 130 such as a 3D cross-point nonvolatile memory cell array and a NAND-type memory (e.g., 2D NAND, 3D NAND) and a 3D cross-point nonvolatile memory cell array is described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as a read-only memory (ROM), a phase change memory (PCM), a self-selected memory, other chalcogenide-based memories, a ferroelectric transistor random access memory (FeTRAM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), a spin transfer torque (STT)-MRAM, a conductive bridge RAM (CBRAM), a resistive random access memory (RRAM), an oxide-based RRAM (OxRAM), a NOR flash memory, and an electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. For example, local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may actually rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert commands or operations from the host system 120, and may convert commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0036] Memory subsystem controller 115 may also include command overlay circuitry 106. Command overlay circuitry 106 may identify commands received by memory subsystem 110 that address the same LB of memory device 130 and / or memory device 140 and possibly other memory devices.

[0037] In some embodiments, the memory subsystem controller 115 includes at least a portion of the command overlay circuitry 106. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the command overlay circuitry 106 is part of a host system 120, an application, or an operating system.

[0038] The command may include metadata. The metadata of the command may include namespace, start LB and / or end LB and other types of metadata. If the namespace matches and one of the LBs from one command is between the start LB and the end LB of another command, the command may be described as overlapping. For example, when the first command and the second command have the same start LB and / or the same end LB, the first command may overlap with the second command. In various examples, when at least a portion of the LBs corresponding to each of the first command and the second command overlap, the first command and the second command may also overlap. For example, when the start LB of the second command is greater than the start LB of the first command but less than the end LB of the first command, the first command and the second command may overlap. When the end LB of the second command is greater than the start LB of the first command but less than the end LB of the first command, the first command and the second command may also overlap. When the start LB of the second command is less than the start LB of the first command and the end LB of the second command is greater than the end LB of the first command, the first command and the second command may overlap.

[0039] The namespace of commands may identify a type of command. For example, the namespace of commands may be write or read, as well as other types. The namespace of commands may be used to determine which commands are provided to a processor 117 (e.g., a processing device such as a central processing unit (CPU)) of the memory subsystem 110 for execution. For example, a write command may be provided to the processor 117 before a read command is provided. For example, the most recent write command may be provided to the processor 117 before a read command is provided. The most recent write command may describe the last write command received.

[0040] The commands may be provided from the host system 120 to the memory subsystem controller 115 and to the command overlay circuitry 106. The order associated with the receipt of the commands may be preserved. For example, a first command may be identified as being received before receiving a second command.

[0041] The command may be selected from commands received by the memory subsystem 110. After selecting a command for execution, if the received command addresses the same address to which the selected command addresses, the received command may be marked. Marking the command may identify that the marked command and the selected command address the same address.

[0042] The command may also be marked based on the completion of the command. When the command is executed, the command may be completed. In some embodiments, after the command is completed, a signal is provided to the host system 120, thereby indicating the completion of the execution of the command.

[0043] The commands and / or the order associated with the commands may be stored in the command overlay circuitry 106 (eg, Figure 2 The command overlay circuitry 106 may be configured to store the received commands from the host system 120, the received signals from the host system 120, and / or the overlapped commands and other types of data.

[0044] The marked commands may be executed by the processor 117 before executing the unmarked commands. Within the marked commands, the write command may be executed before executing the read command. Executing the write command before executing the read command allows the read command to access updated data.

[0045] Figure 2An example of command overlay circuitry 206 according to some embodiments of the present disclosure is illustrated. Command overlay circuitry 206 includes command table 222, overlap check circuitry 223, first in first out (FIFO) memory 224, and marked item scanning circuitry 225. Command table 222 and FIFO memory 224 may be coupled to overlap check circuitry 223. Marked item scanning circuitry 225 may be coupled to overlap check circuitry 223. FIFO memory 224 may be further coupled to marked item scanning circuitry 225.

[0046] The command overlay circuitry 206 may be configured to Figure 1 The system host 120 receives the command 221. In various examples, the command 221 can be an NVMe command. The command 221 can be added to the command table 222. The command can also be provided to the overlap check circuit system 223.

[0047] The command table 222 may identify the order in which the commands 221 are received. The command table 222 may also store metadata of the commands 221. For example, the command table 222 may store a namespace, a start LB, and / or an end LB for each of the commands 221.

[0048] Each of the commands 221 may be assigned a tag. The tag may consist of one or more of a namespace, a start LB, and / or an end LB, and other metadata values ​​of the command 221. The tag may be used to identify the command, and thus may be referred to as a tag identification (ID). The tag may also be assigned to the command 221 before the command 221 is being received by the command overlay circuitry 206. For example, the tag may be assigned to the command 221 by Figure 1 The processor 117 in generates and assigns tags. Upon execution of the tagged command, the tag corresponding to the tagged command may be released so that the tag can be used for a different command in the future.

[0049] The overlap check circuitry 223 may utilize tags assigned to the commands 221 to identify which commands 221 address the same logic block (e.g., overlap). For example, overlapping commands 221 may have portions of the same tags or may have the same tags. For example, a first tag represented by a first bit vector may be generated and assigned to a first command. A second tag represented by a second bit vector may be generated and assigned to a second command. A first command and a second command may overlap when the first tag and the second tag have the same one or more bits with the same bit position within the first bit vector and the second bit vector. For example, the first tag and the second tag may have the same one or more bits, where the one or more bits represent a start LB and / or an end LB.

[0050] In various cases, the first command and the second command may be compared to determine whether they overlap without reference to the tags assigned to the first command and the second command. For example, the start LB and end LB of command 221 may be compared to determine whether the commands overlap.

[0051] Overlap check circuitry 223 may identify the earliest command received and stored in command table 222. In response to identifying the earliest command received, overlap check circuitry 223 may compare the identified command to another command stored in command table 222.

[0052] Overlap check circuitry 223 may mark commands that overlap with identified commands. Overlap check circuitry 223 may also mark identified commands. Overlapping commands may be marked in command table 222. For example, each entry in command table 222 may correspond to a command and may include fields for namespace, start LB and end LB, and / or a field for a tag, among other possible fields.

[0053] The overlap check circuitry 223 may store the marked command in the FIFO memory 224. As used herein, marking a command may include identifying the command. The command may be marked by storing data in the command table 222 and / or the FIFO memory 224. For example, a flag (e.g., a bit) may be stored in the command table 222 and / or the FIFO memory 224 to mark the command. In various examples, the overlap check circuitry 223 may delete the marked command from the command table 222 in response to storing the marked command in the FIFO memory 224. In other cases, the overlap check circuitry 223 may delete the marked command from the command table 222 in response to the marked command being executed (e.g., the marked command being completed). Whenever the marked command is deleted from the command table 222, the marked command may be stored in the FIFO memory 224. In various examples, tags are stored for each of the commands in command table 222 , provided that the order in which the commands were received is preserved in command table 222 and provided that the commands were selected for tagging based on that order.

[0054] FIFO memory 224 may store commands and their associated metadata such that the order in which the stored commands are retrieved from command table 222 is preserved. For example, the oldest command stored in FIFO memory 224 may be the first command retrieved from FIFO memory 224.

[0055] The most recent command stored in the FIFO memory 224 may be the last command retrieved from the FIFO memory 224. For example, if a first command is stored in the FIFO memory 224 before a second command is stored in the FIFO memory 224, the first command may be retrieved from the FIFO memory 224 before the second command is retrieved from the FIFO memory 224.

[0056] In some examples, the order in which the tagged commands are stored in the FIFO memory 224 may be separated from the order in which the tagged commands are retrieved from the FIFO memory 224. For example, if a first command is stored in the FIFO memory 224 before a second command is stored in the FIFO memory 224, and a third command is stored in the FIFO memory 224 after the first and second commands are stored in the FIFO memory 224, the first command may be retrieved from the FIFO memory 224 before the second and third commands are retrieved and the third command may be retrieved before the second command is retrieved.

[0057] In addition to marking the commands, the overlap check circuit system 223 may also store the commands in the FIFO memory 224 so that the write command is retrieved from the FIFO memory 224 before the retrieval of the read command. The mark item scanning circuit system 225 may retrieve the command from the FIFO memory 224. Retrieving the write command from the FIFO memory 224 before retrieving the read command from the FIFO memory 224 allows the write command to be executed before the read command is executed. Executing the write command before executing the read command enables reading the latest data. For example, if the first command stored in the FIFO memory 224 is a write command, the second command stored in the FIFO memory 224 is a read command, and the third command stored in the FIFO memory 224 is also a write command, then the third command may be retrieved from the FIFO memory 224 before retrieving the second command but after retrieving the first command. In this way, the first command and the third command may be retrieved from the FIFO memory 224 before retrieving the second command in response to the first command and the third command being a write command and the second command being a read command. In various examples, a first order for sorting the first commands to the FIFO memory 224 may be selected based on commands (e.g., the first command) stored in the command table 222. However, after the first command is stored in the FIFO memory 224, additional commands may be received by the command overlay circuitry 206. The additional commands may be stored in the FIFO memory 224. The tagged item scanning circuitry 225 may retrieve the commands based on a second order, which is selected based on the availability of the first command and the additional commands. The second order may be different from the first order under the condition that the first order may not include the additional commands.

[0058] After the commands have been tagged and stored in the FIFO memory 224, the tagged item scanning circuitry 225 may access the tagged commands stored in the FIFO memory 224 and may retrieve the first tagged command. The tagged item scanning circuitry 225 may cause the first tagged command to be deleted in response to retrieving the first tagged command or may cause the first tagged command to be deleted in response to completing execution of the first tagged command.

[0059] The marked item scanning circuitry 225 may verify whether the commands stored in the FIFO memory 224 are marked. Verifying whether the commands stored in the FIFO memory 224 are marked may be described as scanning. The marked item scanning circuitry 225 may scan the marked commands stored in the FIFO memory 224 to ensure that the marked commands overlap, or may cause the overlap checking circuitry 223 to scan the commands stored in the command table 222 to identify overlapping commands. If the additional commands are not stored in the FIFO memory 224, the marked item scanning circuitry 225 may request the overlap checking circuitry 223 to mark the additional commands and store the newly marked commands to the FIFO memory 224. In various examples, the overlap checking circuitry 223 may mark the additional commands and store the newly marked commands to the FIFO memory 224 without additional input from the marked item scanning circuitry 225. For example, the overlap checking circuitry 223 may mark the commands regardless of whether there are commands stored in the FIFO memory 224.

[0060] The command 226 retrieved from the FIFO memory 224 by the tag item scanning circuitry 225 may be provided to Figure 1 226 to the processor 117 (e.g., memory subsystem CPU). Tagged item scanning circuitry 225 may provide a single command 226 to the processor at a time. Overlap checking circuitry 223 may refrain from storing additional commands from command table 222 to FIFO memory 224 until the processor executes the command provided by tagged item scanning circuitry 225. In various examples, overlap checking circuitry 223 may store additional commands from command table 222 to FIFO memory 224 without waiting for the processor to execute the command provided by tagged item scanning circuitry 225.

[0061] The processor may provide a command completion signal 227 to the marked item scanning circuit system 225 after the command is executed by the processor. In response to receiving the command completion signal 227, the marked item scanning circuit system 225 may scan the commands stored by the FIFO memory 224 to determine whether to mark the command. The marked item scanning circuit system 225 may compare the executed command (e.g., the completed command) and the marked commands stored by the FIFO memory 224 to determine whether they overlap. If they overlap, the marked item scanning circuit system 225 may select the next marked command and may provide the selected command 226 to the processor of the memory subsystem.

[0062] The marked item scanning circuitry 225 may continue to provide commands 226 in response to receiving the command completion signal 227. In response to determining that the FIFO memory 224 does not store the marked command, the marked item scanning circuitry 225 may provide a signal to the overlap checking circuitry 223 to cause the overlap checking circuitry 223 to mark additional commands. In various examples, the overlap checking circuitry 223 may store the command to the FIFO memory 224 without being prompted by the marked item scanning circuitry 225.

[0063] In response to receiving a signal from the marked item scanning circuit system 225, the overlap check circuit system 223 may select the earliest received signal from the command table 222. In response to selecting the earliest received command from the command table 222, the overlap check circuit system 223 may mark the commands that overlap with the selected earliest received command. The overlap check circuit system 223 may then store the marked commands in the FIFO memory 224.

[0064] The marked item scanning circuitry 225 may provide commands stored in the FIFO memory 224 as previously described. After there are no more commands in the FIFO memory 224 and in response to receiving the command completion signal 227, the marked item scanning circuitry 225 may continue to cause overlapping commands to be marked by the overlap check circuitry 223.

[0065] At any time, a new command 221 may be received by the command overlay circuitry 206. For example, the new command 221 may be received after the command table 222 has been populated and / or the FIFO memory 224 has been filled with received commands and / or tagged commands, respectively.

[0066] The newly received command 221 may be provided to the overlap check circuitry 223. The overlap check circuitry 223 may determine whether a command currently being executed overlaps with the newly received command 221 or whether a marked command stored in the FIFO memory 224 overlaps with the newly received command 221. If the newly received command 221 and the most recently executed command overlap, the overlap check circuitry 223 may add the newly received command 221 to the FIFO memory 224. As used herein, the most recently executed command may include the last executed command as opposed to a command executed before the execution of the last executed command. The newly received command 221 may be added to the FIFO 224 so that the newly received command 221 is retrieved after the marked write command if the newly received command 221 is a write command or after the marked read command if the newly received command 221 is a read command. The marked command may continue to be retrieved from the FIFO memory 224 as previously described.

[0067] The newly received command 221 may be assigned a tag. Overlap check circuitry 223 may determine whether to add the newly received command 221 to FIFO memory 224 based on the assigned tag. In some cases, the newly received command 221 may be added to command table 222 and to FIFO memory 224.

[0068] After the tagged command assigned with the same tag is completed, the tag corresponding to the tagged command may be released. Releasing the tag describes the availability of the tag for use with a different command and / or LB. The tagged item scanning circuitry 225 may release the tag, or a different device may release the tag, such as the overlap checking circuitry 223 and / or a processing device of a memory subsystem including the command overlap circuitry 106.

[0069] Figure 3 is a flow chart of an example method for commanding an overlay circuit system according to some embodiments of the present disclosure. Method 303 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 303 is performed by Figure 2 The command overlap circuit system 206 is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0070] At block 342, commands addressed to a logic block of a plurality of memory devices may be received. At block 344, a determination may be made as to whether a recently executed command addressed the logic block. At block 346, the commands may be marked in response to a determination that the recently executed command addressed the logic block. At block 348, commands addressed to the logic block may be added to a FIFO memory in response to marking the commands. At block 350, a plurality of commands stored in the FIFO memory may be executed.

[0071] In various examples, the command may be added to the command table in response to refraining from marking the command. In response to refraining from marking the command, the method 303 may refrain from adding the command to the FIFO memory.

[0072] The command may be determined to be a write command. In response to determining that the command is a write command and in response to marking the command, the command may be added to the FIFO memory so that the command is executed before the read command and after the latest write command of the write command from the plurality of commands.

[0073] The command may be determined to be a read command. In response to determining that the command is a read command and in response to marking the command, the command may be added to the FIFO memory so that the command is executed after the read command and the write command of the plurality of commands. In various cases, the command may be executed by providing the command to a processing device of the memory subsystem.

[0074] Figure 4 An example machine of a computer system 490 is illustrated within which a set of instructions for causing the machine to perform one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 490 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a cloud computing infrastructure or environment.

[0075] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or another machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be performed by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include a collection of machines that individually or collectively execute one (or more) sets of instructions to perform one or more of the methodologies discussed herein.

[0076] The example computer system 490 includes a processing device 492, a main memory 494 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 498 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 499, which communicate with each other via a bus 497.

[0077] Processing device 492 represents one or more general processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 492 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 492 is configured to execute instructions 493 for performing the operations and steps discussed herein. Computer system 490 may further include a network interface device 495 to communicate via a network 496.

[0078] The data storage system 499 may include a machine-readable storage medium 491 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 493 or software embodying one or more of the methods or functions described herein. The instructions 493 may also reside, completely or at least partially, in a main memory 494 and / or in a processing device 492 during execution thereof by the computer system 490, the main memory 494 and the processing device 492 also constituting machine-readable storage media. The machine-readable storage medium 491, the data storage system 499, and / or the main memory 494 may correspond to Figure 1 Memory subsystem 110.

[0079] In one embodiment, instruction 493 includes implementing the Figure 1 The instructions may include instructions for executing overlapping commands (such as Figure 1 The command instructions 489 associated with the command overlay circuit system 106 in the example embodiment are shown as a single medium. Although the machine-readable storage medium 491 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include media that can store or encode sets of instructions for machine execution and cause the machine to perform one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0080] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations leading to a desired result. An operation is one requiring physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. At times, it has proven convenient, primarily for common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0081] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0082] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, a disk type including a floppy disk, an optical disk, a CD-ROM and a magnetic optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or a media type suitable for storing electronic instructions, each connected to a computer system bus.

[0083] The algorithms and displays presented herein are not inherently related to a particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to a particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0084] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes a mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0085] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A system for executing commands addressed to the same logical block, comprising: Memory; Host interface; as well as a processor coupled to the memory and the host interface, the processor being configured to: marking a portion of the plurality of commands in response to providing a command completion signal to the host, wherein the portion includes overlapping commands; executing a most recent write command from the marked portion of the plurality of commands before executing a read command from the marked portion of the plurality of commands; as well as A read command from the marked portion of the plurality of commands is executed subsequent to the execution of the most recent write command, wherein the read command is executed in response to the execution of the most recent write command.

2. The system according to claim 1, further comprising: Command table; and wherein the processor is configured to store the plurality of commands in the command table upon receiving the plurality of commands; and Wherein the processor further comprises overlap checking circuitry configured to mark the portion of the plurality of commands in response to completion of a different command that overlaps with the overlapping command, wherein the portion of the plurality of commands is marked in the command table.

3. The system of claim 1, wherein the processor further comprises overlap checking circuitry configured to mark the portion of the plurality of commands in response to completion of a different command that does not overlap with the overlapping command.

4. The system of claim 3, wherein the overlap checking circuitry is configured to select a next command to be executed from the plurality of commands in response to completion of the different commands, wherein the next command is an earliest command received by the system.

5. The system of claim 3, wherein the overlap checking circuitry is configured to mark a most recent command received by the system in response to the most recent command received overlapping the overlapping command.

6. The system of claim 1, further comprising a first-in-first-out (FIFO) memory, the FIFO memory being configured to: storing the marked portion of the plurality of commands; and Write commands from the marked portion of the plurality of commands are stored before storing read commands from the marked portion of the plurality of commands.

7. The system of claim 6, wherein the FIFO memory is further configured to store the write commands in the order in which they are received by the system.

8. The system of claim 6, wherein the FIFO memory is further configured to store the read commands in the order in which they are received by the system.

9. A method for executing commands addressed to the same logical block, comprising: receiving a write command addressed to a memory device; determining that the earliest command received overlaps with the write command; marking the write command in response to determining that the earliest received command overlaps with the write command; adding the write command to a first-in first-out (FIFO) memory in response to marking the command; as well as A plurality of commands stored in the FIFO memory are executed, wherein the plurality of commands include the write command and a read command, wherein the read command is executed after the write command.

10. The method of claim 9, wherein the write command is addressed to a logical block and the earliest command is addressed to a different logical block, and wherein the earliest command overlaps with the write command if the different logical block and the logical block have the same starting logical block or the same ending logical block.

11. The method of claim 9, wherein the write command is addressed to a logical block and the earliest command is addressed to a different logical block, and wherein the earliest command overlaps with the write command if the different logical block and at least a portion of the logical block are the same logical block.

12. The method of claim 9, wherein the earliest command addresses a different logical block and the write command addresses a logical block, and wherein if: The end logic block of the logic block is larger than the start logic block of the different logic block but smaller than the end logic block of the different logic block, or The end logic block of the different logic block is larger than the start logic block of the logic block but smaller than the end logic block of the logic block, Then the earliest command overlaps with the write command.

13. The method of claim 9, further comprising, in response to determining that the write command is a write command and in response to marking the command, adding the write command to the FIFO memory so that the write command is executed before the read command, and wherein the write command is the most recent write command.

14. The method of claim 9, wherein executing the plurality of commands stored in the FIFO memory further comprises providing the plurality of commands to a processor of a memory subsystem.

15. A system for executing commands addressed to the same logical block, comprising: processor; Memory; as well as a controller coupled to the memory and the processor, the controller being configured to: intercepting a first command complete signal identifying completion of a first command addressed to the memory; determining, in response to intercepting the first command completion signal, that a pending command does not overlap with the first command; identifying a second command to be executed, wherein the second command is a most recently received command; marking commands from the pending commands that overlap with the second command; as well as The marked command is provided to the processor by: providing a most recent write command from the marked commands for execution; and A read command is provided from the marked command for execution.

16. The system of claim 15, wherein the controller is further configured to provide the read command in response to providing the most recent write command to the processor.

17. The system of claim 15, wherein the controller is further configured to: providing a latest write command from a plurality of write commands to a processing device, wherein the latest write command from the plurality of write commands is a last received write command; receiving a second command completion signal in response to the processing device executing the most recent write command; and A read command is provided in response to receiving the second command completion signal.

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