NAND-Flash memory access method and device based on NFI interface protocol

Abstract

The invention discloses an NAND-Flash memory access method based on an NFI (Network Firmware Interface) protocol, which is used for solving the problems that the research and development efficiency of a chip is reduced, the design cost is increased, and the memory access efficiency is increased due to the fact that a corresponding hardware circuit and a memory access method need to be specifically designed each time in order to realize the interconnection access between a Controller and a PHY (Physical Layer) because the designers of the existing Controller and PHY are different. And the memory access efficiency is greatly reduced. The method comprises the following steps: determining a to-be-accessed target and an access type corresponding to a received access request; based on the NFI interface protocol, according to the access target and the access type, an interaction signal and a control time sequence corresponding to the access request are determined, and the NFI interface protocol defines a universal interface between a controller and a physical layer port PHY, a corresponding interaction signal set, a time sequence and an interaction behavior; and controlling the interaction signal according to the control time sequence so as to realize memory access to the to-be-accessed target.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and device for accessing NAND-Flash memory based on the NFI interface protocol. Background Art

[0002] Solid-state drives (SSDs) consist of a controller and storage units (common storage units include FLASH chips or DRAM chips). On the one hand, with the advancement of NAND-Flash technology, the cost of SSDs based on NAND-Flash media is gradually decreasing. On the other hand, with the development of cloud computing and data centers, enterprise-class SSDs are becoming increasingly widely used in servers and data centers.

[0003] In existing technologies, SSDs primarily consist of a controller chip, a cache chip (DRAM), and a flash memory chip (NAND-Flash). The controller chip primarily includes the front-end protocol interface (IP), the flash memory interface (NAND-Flash interface), the physical layer port (PHY), the controller, and the flash translation layer (FTL).

[0004] As NAND-Flash I / O interfaces support increasingly higher speeds, the design requirements for controller chip PHYs are also becoming increasingly stringent. To meet the supported speeds, the controller chip PHY frequency must be continuously increased. However, increasing PHY frequencies require a stable power supply network. However, the controller portion of the controller chip does not necessarily require such high frequencies.

[0005] In this case, if the controller and PHY are still designed as one, that is, the controller and PHY parts are not differentiated at the IP level, the clock and power supply of the controller and PHY parts cannot be clearly separated, and thus power consumption cannot be reduced through multiple clock domains and multiple voltage domains. On the other hand, this integrated design method of the controller and PHY makes it impossible to independently protect the power supply and signals of the PHY circuit.

[0006] To address the above issues, existing technology can separate the controller and PHY into two parts. However, since the designers of the controller and PHY are often different, in order to achieve interconnection between the two for memory access, corresponding hardware circuits and memory access methods need to be designed specifically each time. This not only reduces chip R&D efficiency and increases design costs, but also greatly reduces memory access efficiency.

[0007] It can be seen that how to improve chip memory access efficiency while reducing chip R&D efficiency and design costs has become a technical problem that needs to be solved urgently. Summary of the Invention

[0008] An embodiment of the present application provides a NAND-Flash memory access method based on the NFI interface protocol, which is used to solve the problem that due to the different designers of the existing Controller and PHY parts, in order to achieve interconnection access between the two parts, corresponding hardware circuits and memory access methods need to be designed each time, which in turn leads to reduced chip R&D efficiency, increased design costs, and greatly reduced memory access efficiency.

[0009] An embodiment of the present application also provides a NAND-Flash memory access device based on the NFI interface protocol, which is used to solve the problem that due to the different designers of the existing Controller and PHY parts, in order to achieve interconnection access between the two parts, corresponding hardware circuits and memory access methods need to be designed specifically each time, which leads to reduced chip R&D efficiency, increased design costs, and greatly reduced memory access efficiency.

[0010] An embodiment of the present application also provides a NAND-Flash memory access device based on the NFI interface protocol, which is used to solve the problem that due to the different designers of the existing Controller and PHY parts, in order to achieve interconnection access between the two parts, corresponding hardware circuits and memory access methods need to be designed specifically each time, which leads to reduced chip R&D efficiency, increased design costs, and greatly reduced memory access efficiency.

[0011] An embodiment of the present application also provides a computer-readable storage medium to solve the problem that due to the different designers of the existing Controller and PHY parts, in order to achieve interconnection and access between the two parts, corresponding hardware circuits and memory access methods need to be designed specifically each time, which leads to reduced chip R&D efficiency, increased design costs, and greatly reduced memory access efficiency.

[0012] The embodiments of this application adopt the following technical solutions: A NAND-Flash memory access method based on the NFI interface protocol includes: determining a target to be accessed and an access type corresponding to a received access request; determining, based on the NFI interface protocol and according to the access target and the access type, an interaction signal and a control timing corresponding to the access request, wherein the NFI interface protocol defines a universal interface between a controller and a physical layer port (PHY), a corresponding interaction signal set, a timing, and an interaction behavior; and controlling the interaction signal according to the control timing to achieve memory access to the target to be accessed.

[0013] A NAND-Flash memory access device based on the NFI interface protocol includes: a request receiving unit, used to determine the target to be accessed and the access type corresponding to the received access request; an interaction signal determination unit, used to determine the interaction signal and control timing corresponding to the access request based on the NFI interface protocol and the access target and the access type, wherein the NFI interface protocol defines a common interface, a corresponding interaction signal set, timing, and interaction behavior between a controller Controller and a physical layer port PHY; and an access unit, used to control the interaction signal according to the control timing to achieve memory access to the target to be accessed.

[0014] A NAND-Flash memory access device based on the NFI interface protocol, comprising: A processor; and a memory arranged to store computer-executable instructions, wherein the executable instructions, when executed, cause the processor to perform the following operations: determine a target to be accessed and an access type corresponding to a received access request; based on the NFI interface protocol, determine an interaction signal and a control timing corresponding to the access request according to the access target and the access type, wherein the NFI interface protocol defines a common interface, a corresponding interaction signal set, a timing, and an interaction behavior between a controller Controller and a physical layer port PHY; and control the interaction signal according to the control timing to achieve memory access to the target to be accessed.

[0015] A computer-readable storage medium stores one or more programs, which, when executed by an electronic device including multiple application programs, enable the electronic device to perform the following operations: determine the target to be accessed and the access type corresponding to the received access request; based on the NFI interface protocol, determine the interaction signal and control timing corresponding to the access request according to the access target and the access type, wherein the NFI interface protocol defines a common interface, corresponding interaction signal set, timing and interaction behavior between a controller Controller and a physical layer port PHY; and control the interaction signal according to the control timing to achieve memory access to the target to be accessed.

[0016] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: By adopting the NAND-Flash memory access method based on the NFI interface protocol provided in the embodiment of the present application, a set of universal NFI interface protocols for use between the NAND-Flash Controller and the PHY is defined. After determining the target to be accessed and the access type corresponding to the received access request, the interaction signal and control timing corresponding to the access request can be determined based on the universal NFI interface protocol, and then the interaction signal can be controlled according to the control timing to achieve memory access to the target to be accessed, greatly improving access efficiency; at the same time, the use of the universal NFI interface protocol can realize the interconnection operation between the NAND-Flash Controller and PHY of different manufacturers, avoiding the need to design corresponding hardware circuits and memory access methods for different manufacturers each time, greatly improving chip R&D efficiency and reducing design costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of a specific process of a NAND-Flash memory access method based on the NFI interface protocol provided in an embodiment of the present application; Figure 2 A schematic diagram of interface signal interaction based on the NFI interface protocol provided in an embodiment of the present application; Figure 3 A schematic diagram of interface signal interaction based on the NFI interface protocol provided in an embodiment of the present application; Figure 4A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 5 A schematic diagram of interface signal interaction based on the NFI interface protocol provided in an embodiment of the present application; Figure 6 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 7 A schematic diagram of interface signal interaction based on the NFI interface protocol provided in an embodiment of the present application; Figure 8 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 9 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 10 A schematic diagram of interface signal interaction based on the NFI interface protocol provided in an embodiment of the present application; Figure 11 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 12 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 13 A schematic diagram of interface signal interaction based on the NFI interface protocol provided in an embodiment of the present application; Figure 14 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 15 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 16 A schematic diagram of interface signal interaction based on the NFI interface protocol provided in an embodiment of the present application; Figure 17A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 18 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 19 A schematic diagram of interface signal interaction based on the NFI interface protocol provided in an embodiment of the present application; Figure 20 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 21 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 22 A schematic diagram of interface signal interaction based on the NFI interface protocol provided in an embodiment of the present application; Figure 23 A timing diagram of the interaction between NFI Command Interface and NAND interface signals based on the NFI interface protocol provided in an embodiment of the present application; Figure 24 A schematic diagram of the specific structure of a NAND-Flash memory access device based on the NFI interface protocol provided in an embodiment of the present application; Figure 25 A schematic diagram of the specific structure of a NAND-Flash memory access device based on the NFI interface protocol provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0019] The following describes in detail the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0020] An embodiment of the present application provides a NAND-Flash memory access method based on the NFI interface protocol, which is used to solve the problem that due to the different designers of the existing Controller and PHY parts, in order to achieve interconnection access between the two parts, corresponding hardware circuits and memory access methods need to be designed each time, which in turn leads to reduced chip R&D efficiency, increased design costs, and greatly reduced memory access efficiency.

[0021] The specific implementation flow chart of the NAND-Flash memory access method based on the NFI interface protocol provided in this application is as follows Figure 1 As shown, it mainly includes the following steps: Step 11: Determine the target to be accessed and the access type corresponding to the received access request.

[0022] In the embodiment of the present application, the target to be accessed determined according to the access request may be, for example, a specific NAND chip in the NAND-Flash.

[0023] Step 12: Based on the NFI interface protocol and the access target and access type determined by executing step 11, determine the interaction signal and control timing corresponding to the access request.

[0024] In an embodiment of the present application, a set of universal interface protocols for the NAND-Flash PHY interface (NFI) is defined. The NFI interface protocol defines a universal interface, corresponding interaction signal set, timing, and interaction behavior between the controller and the physical layer port PHY. Based on the NFI interface protocol, even if the design manufacturers of the Controller and PHY are different, the NFI interface protocol can be used to achieve interconnection between the two for memory access, avoiding the need to design corresponding hardware circuits and memory access methods for different manufacturers each time, greatly improving chip R&D efficiency and reducing design costs.

[0025] In addition, it should be noted that the NFI interface protocol defined in the embodiments of the present application can be applicable to the legacy SDR protocol, ONFi (Open NAND-Flash Interface) protocol, Toggle protocol, and the latest JEDC230F, JEDC230G, and SCA protocols.

[0026] In one embodiment, the interactive signal set in the NFI interface protocol mainly includes the following categories: Type a, global interface signal set: In one embodiment, the interface signals and interaction directions included in the global interface signal set provided by the embodiment of the present application are as follows: Figure 2 As shown, it specifically includes the following interface signals: a-1, clock signal nfi_clock, is used to indicate the clock corresponding to the NFI bus processing unit in the Controller and PHY. In this embodiment of the present application, the width of the clock signal nfi_clock is 1.

[0027] a-2, reset signal nfi_reset, used to indicate the corresponding reset of the bus processing unit in the Controller and the PHY. In the embodiment of the present application, the width of the reset signal nfi_reset is 1.

[0028] Type b, command signal set: Among them, the interface signal in the command signal set corresponds to the NFI command interface (Command Interface). Specifically, the interface signal and interaction direction included in the command signal set provided in the embodiment of the present application are as follows: Figure 3 As shown, it specifically includes the following interface signals: b-1, chip select signal nfi_cen, is used to control the NAND-Flash I / O interface CE (chip enable, flash memory CE pin) line, and is associated with the chip enable interface of the NAND particle. In this embodiment of the application, the width of the chip select signal nfi_cen is equal to the width of the flash memory CE pin.

[0029] b-2, send command signal nfi_cle, used to control the I / O interface CLE line of NAND-Flash, and associate the command latch enable interface of NAND particles. In the embodiment of the present application, the width of the command signal nfi_cle is 4.

[0030] b-3, sending address signal nfi_ale, used to control the I / O interface ALE line of NAND-Flash, and the address latch enable interface of the associated NAND particle. In the embodiment of the present application, the width of the sending address signal nfi_ale is 4.

[0031] b-4, write signal nfi_wen, is used to control the I / O interface WEN line of NAND-Flash and the write enable interface of the associated NAND particle. In the embodiment of the present application, the width of the write signal nfi_wen is 4.

[0032] b-5, write protection signal nfi_wpn, is used to control the I / O interface WPn line of the NAND-Flash and the write protection interface of the associated NAND particle. In the embodiment of the present application, the width of the write protection signal nfi_wpn is equal to the width of the WP pin.

[0033] In the embodiment of the present application, taking the command latch command as an example, the timing relationship between the NFI Command Interface and the NAND interface signal is as follows: Figure 4 As shown, the delay from NFI interface to NAND interface is defined as t cmd_delay .

[0034] Type c, read and write signal set, where the read and write signal set further includes the following four signal subsets: Type c1, write control signal subset, the interface signal in the command signal set corresponds to the NFI data write interface (NFI Write Data Interface), the interface signal and interaction direction included in the write control signal subset provided in the embodiment of the present application are as follows Figure 5 As shown, it specifically includes the following interface signals: c1-1, a write enable signal nfi_wrdata_en, is used to indicate that data is written into the memory. The width of the write enable signal nfi_wrdata_en is 1.

[0035] c1-2, direction control signal nfi_wrdata, is used to indicate the data writing direction. The width of the direction control signal nfi_wrdata is equal to the write data width.

[0036] c1-3, DBI write direction control signal nfi_wrdata_dbi, is used to control the DBI line of the NAND-Flash I / O interface, where DBI refers to the data bus inversion pin (full name: Data Bus Inversion, DBI pin), and the width of the DBI write direction control signal nfi_wrdata_dbi is 4.

[0037] c1-4, DQS write direction control signal nfi_wdqs, is used to control the DQS / DQSn differential signal of the NAND-Flash I / O interface. DQS refers to the bidirectional data control pin (Bi-directional Data Strobe, DQS pin), which is used for signal synchronization between the memory and the memory controller. The width of the DQS write direction control signal nfi_wdqs is 4.

[0038] In the embodiment of the present application, the timing relationship between the NFI Write Data Interface and the NAND interface signal is as follows: Figure 6 As shown, the delay from the NFI interface to the NAND interface is defined as twrlat.

[0039] Type c2, SDR read control signal subset, the interface signal in the SDR read control signal subset corresponds to the NFI SDR read data interface (NFI SDR Read Data Interface), the interface signal and interaction direction included in the SDR read control signal subset provided in the embodiment of the present application are as follows Figure 7 As shown, it specifically includes the following interface signals: c2-1, SDR read enable signal nfi_sdr_rddata_en, is used to indicate that data is read out from the memory. The width of the SDR read enable signal nfi_sdr_rddata_en is 1.

[0040] c2-2, SDR read data signals nfi_sdr_rddata and nfi_sdr_rddata_dbi, are used to indicate the data read by the SDR.

[0041] The width of the nfi_sdr_rddata signal is 8, and the width of the nfi_sdr_rddata_dbi signal is 1.

[0042] c2-3, SDR read data valid flag nfi_sdr_rddata_vld, used to indicate the validity of SDR read data, the width of the nfi_sdr_rddata_vld signal is 1.

[0043] In the embodiment of the present application, the timing relationship between the NFI SDR Read Data Interface and the NAND interface signal is as follows: Figure 8 as well as Figure 9 As shown, Figure 8 This shows the NFI SDR Read Data Interface command sending timing diagram. Figure 9 This represents the data receiving timing diagram of the NFI SDR Read Data Interface. The delay from the NAND interface returning data to the NFI interface receiving data is defined as t sdr_rdlat .

[0044] Type c3, DDR read control signal subset, the interface signal in the DDR read control signal subset corresponds to the NFI DDR read data interface (NFI DDR Read Data Interface), the interface signal and interaction direction included in the DDR read control signal subset provided in the embodiment of the present application are as follows Figure 10 As shown, it specifically includes the following interface signals: c3-1, differential line control signal nfi_ren, used to control the REn / RE differential line of the I / O interface of the NAND-Flash. The width of the differential line control signal nfi_ren is 4.

[0045] c3-2, a read enable signal nfi_rddata_en, is used to instruct data to be read from the memory. The width of the read enable signal nfi_rddata_en is 1.

[0046] c3-3, read data signals nfi_rddata and nfi_rddata_dbi, are used to indicate the read data.

[0047] The width of the nfi_rddata signal is equal to the width of the read data, and the width of the nfi_rddata_dbi signal is 4 c3-4, read data valid flag nfi_rddata_vld, is used to indicate the validity of the read data. The width of the read data valid flag nfi_rddata_vld is 1.

[0048] In the embodiment of the present application, the timing relationship between the NFI DDR Read Data Interface and the NAND interface signal is as follows: Figure 11 as well as Figure 12 As shown, Figure 11 This shows the timing diagram of sending the NFI DDR Read Data Interface command. Figure 12 This represents the data receiving timing diagram of the NFI DDR Read Data Interface. The delay from the NAND interface returning data to the NFI interface receiving data is defined as t ddr_rdlat .

[0049] Type c4, SCA interface read control signal subset, the interface signal in the SCA interface read control signal subset corresponds to the NFI SCA read data interface (NFI SCA Read Data Interface), the interface signal and interaction direction included in the SCA interface read control signal subset provided in the embodiment of the present application are as follows Figure 13 As shown, it specifically includes the following interface signals: c4-1, SCA read enable signal nfi_sca_rddata_en, is used to instruct data to be read out from the memory. The width of the SCA read enable signal nfi_sca_rddata_en is 1.

[0050] c4-2, SCA read data signal nfi_sca_rddata, is used to indicate the data read by SCA. The width of the SCA read data signal nfi_sca_rddata is 8.

[0051] c4-3, SCA read data valid flag nfi_sca_rddata_vld, is used to indicate the validity of the SCA read data. The width of the SCA read data valid flag nfi_sca_rddata_vld is 1.

[0052] In the embodiment of the present application, the timing relationship between the NFI SCA Read Data Interface and the NAND interface signal is as follows: Figure 14 as well as Figure 15 As shown, Figure 14 This shows the NFI SCA Read Data Interface command sending timing diagram. Figure 15 This represents the data receiving timing diagram of the NFI SCA Read Data Interface. The delay from the NAND interface returning data to the NFI interface receiving data is defined as t sca_rdlat .

[0053] Type d, update signal set: The interface signal in the update signal set corresponds to an NFI update interface (NFI Update Interface).

[0054] In one embodiment, the interface signals and interaction directions included in the update signal set provided by the embodiment of the present application are as follows: Figure 16 As shown, it specifically includes the following interface signals: d-1, Controller update request signal nfi_ctrlupd_req, sent by the Controller to the PHY for an update request. The width of the nfi_ctrlupd_req signal is 1.

[0055] d-2, Controller update response signal nfi_ctrlupd_ack, sent by the PHY to the Controller as an update response. The width of the nfi_ctrlupd_ack signal is 1.

[0056] d-3, PHY update request signal nfi_phyupd_req, an update request sent by the PHY to the Controller. The width of the nfi_phyupd_req signal is 1.

[0057] d-4, PHY update response signal nfi_phyupd_ack, sent by the Controller to the PHY for an update response. The width of the nfi_phyupd_ack signal is 1.

[0058] d-5, PHY update type signal nfi_phyupd_type, used to indicate the update type of the PHY. The width of the nfi_phyupd_type signal is 2.

[0059] In the embodiment of the present application, the timing relationship of the controller updating is as follows: Figure 17 As shown, the time from the update request initiated by the Controller to the PHY feedback response is defined as t ctrlupd_min .

[0060] In the embodiment of the present application, the timing relationship of PHY updating is as follows: Figure 18 As shown, the time from the update request initiated by PHY to the response fed back by Controller is defined as t phyupd_resp .

[0061] Type e, status signal set: The interface signal in the status signal set corresponds to the NFI status interface (NFI Status Interface).

[0062] The interface signals and interaction directions included in the status signal set provided by the embodiment of the present application are as follows: Figure 19 As shown, it specifically includes the following interface signals: e-1, PHY initialization enable signal nfi_init_start, used to indicate the start of PHY initialization. The width of the nfi_init_start signal is 1.

[0063] e-2, initialization completion signal nfi_init_complete, is used to indicate that PHY initialization is complete. The width of the nfi_init_complete signal is 1.

[0064] e-3, initialization configuration information nfi_init_info, the width of the nfi_init_info signal is 2.

[0065] e-4, PHY status information nfi_status, the width of the nfi_status signal is 2.

[0066] e-5, PHY interrupt signal nfi_int, the width of the nfi_int signal is 1.

[0067] In the embodiment of the present application, the timing relationship of the initialization state is as follows: Figure 20 As shown, the nfi_init_start signal triggers the initialization of the PHY, and the nfi_init_complete signal feedbacks the initialization completion status.

[0068] In the embodiment of the present application, the interrupt (Error) state timing relationship is as follows: Figure 21 As shown, the interrupt signal is initiated by the nfi_int signal, and the interrupt (error) information can be fed back through the nfi_status signal.

[0069] Type f, low power signal set: The interface signal in the low-power signal set corresponds to an NFI low-power interface (NFI Low Power Interface).

[0070] The interface signals and interaction directions included in the low power consumption signal set provided by the embodiment of the present application are as follows: Figure 22 As shown, it specifically includes the following interface signals: f-1, low power request signal nfi_lp_req, sent by the Controller to the PHY to request low power mode. The width of the nfi_lp_req signal is 1.

[0071] f-2, a low-power response signal nfi_lp_ack, is sent by the PHY to the Controller for low-power mode response. The width of the nfi_lp_ack signal is 1.

[0072] f-3, low power exit signal nfi_lp_wakeup, is used to control the exit time of low power mode. The width of the nfi_lp_wakeup signal is 2.

[0073] In the embodiment of the present application, the low power request timing relationship is as follows: Figure 23 As shown, the time from the low power request signal (low power request) initiated by the Controller to the low power response signal (response) fed back by the PHY is defined as t lp_resp At the same time, the time from when the Controller exits low power mode to when the PHY exits low power mode is defined as t lp_wakeup .

[0074] In an embodiment of the present application, access types may include reading data and writing data. For these two types of access types, the access process of the NAND particles is obtained by combining the processes of sending commands, sending addresses, sending data and reading data. According to the above-mentioned interface signal set, the interface signals corresponding to different processes can be determined. After determining the target to be accessed and the access type, the interaction signal and control timing corresponding to the access request can be determined.

[0075] Step 13: Control the interactive signal according to the control timing determined by executing step 12 to achieve memory access to the target to be accessed.

[0076] By adopting the NAND-Flash memory access method based on the NFI interface protocol provided in the embodiment of the present application, a set of universal NFI interface protocols for use between the NAND-Flash Controller and the PHY is defined. After determining the target to be accessed and the access type corresponding to the received access request, the interaction signal and control timing corresponding to the access request can be determined based on the universal NFI interface protocol, and then the interaction signal can be controlled according to the control timing to achieve memory access to the target to be accessed, greatly improving access efficiency; at the same time, the use of the universal NFI interface protocol can realize the interconnection operation between the NAND-Flash Controller and PHY of different manufacturers, avoiding the need to design corresponding hardware circuits and memory access methods for different manufacturers each time, greatly improving chip R&D efficiency and reducing design costs.

[0077] In one embodiment, the present application also provides a NAND-Flash memory access device based on the NFI interface protocol to solve the problem that due to the different designers of the existing Controller and PHY, in order to achieve interconnection access between the two, each time the corresponding hardware circuit and memory access method need to be designed specifically, which leads to reduced chip R&D efficiency, increased design costs, and greatly reduced memory access efficiency. The specific structural diagram of the NAND-Flash memory access device based on the NFI interface protocol is shown in the figure. Figure 24 As shown, it includes: a request receiving unit 31, an interaction signal determining unit 32 and an access unit 33.

[0078] The request receiving unit 31 is used to determine the target to be accessed and the access type corresponding to the received access request; An interaction signal determination unit 32 is configured to determine, based on the NFI interface protocol, the interaction signal and control timing corresponding to the access request according to the access target and the access type, wherein the NFI interface protocol defines a general interface between the controller Controller and the physical layer port PHY, a corresponding interaction signal set, timing, and interaction behavior; The access unit 33 is configured to control the interactive signal according to the control sequence to implement memory access to the target to be accessed.

[0079] In one embodiment, the interface signal set may specifically include: a global interface signal set, a command signal set, a read / write signal set, an update signal set, a status signal set, and a low power signal set.

[0080] In one embodiment, the interface signals in the global interface signal set specifically include: a clock signal nfi_clock, used to indicate the clock corresponding to the bus processing unit in the controller and the PHY; and a reset signal nfi_reset, used to indicate the reset corresponding to the bus processing unit in the controller and the PHY.

[0081] In one embodiment, the interface signals in the command signal set specifically include: a chip select signal nfi_cen, used to control the CE line of the I / O interface of the NAND-Flash; a command signal nfi_cle, used to control the CLE line of the I / O interface of the NAND-Flash; an address signal nfi_ale, used to control the ALE line of the I / O interface of the NAND-Flash; a write signal nfi_wen, used to control the WEN line of the I / O interface of the NAND-Flash; and a write protection signal nfi_wpn, used to control the WPn line of the I / O interface of the NAND-Flash.

[0082] In one embodiment, the read and write signal set may specifically include: a write control signal subset, a single data rate (SDR) read control signal subset, a double data rate (DDR) read control signal subset, and an SCA interface read control signal subset.

[0083] In one embodiment, the interface signals in the write control signal subset may specifically include: a write enable signal nfi_wrdata_en, used to indicate that data is written to the memory; a direction control signal nfi_wrdata, used to indicate the data write direction; a DBI write direction control signal nfi_wrdata_dbi, used to control the DBI line of the I / O interface of the NAND-Flash; and a DQS write direction control signal nfi_wdqs, used to control the DQS / DQSn differential signal of the I / O interface of the NAND-Flash.

[0084] In one embodiment, the interface signals in the SDR read control signal subset may specifically include: an SDR read enable signal nfi_sdr_rddata_en, used to indicate that data is read from the memory; SDR read data signals nfi_sdr_rddata and nfi_sdr_rddata_dbi, used to indicate the data read by the SDR; and an SDR read data valid flag nfi_sdr_rddata_vld, used to indicate the validity of the SDR read data.

[0085] In one embodiment, the interface signals in the DDR read control signal subset may specifically include: a differential line control signal nfi_ren, used to control the REn / RE differential line of the I / O interface of the NAND-Flash; a read enable signal nfi_rddata_en, used to indicate that data is read from the memory; read data signals nfi_rddata and nfi_rddata_dbi, used to indicate the read data; and a read data valid flag nfi_rddata_vld, used to indicate the validity of the read data.

[0086] In one embodiment, the interface signals in the SCA interface read control signal subset may specifically include: an SCA read enable signal nfi_sca_rddata_en, used to indicate that data is read from the memory; an SCA read data signal nfi_sca_rddata, used to indicate the data read by the SCA; and an SCA read data valid flag nfi_sca_rddata_vld, used to indicate the validity of the SCA read data.

[0087] In one embodiment, the interface signals in the update signal set may specifically include: a Controller update request signal nfi_ctrlupd_req, which is an update request sent by the Controller to the PHY; a Controller update response signal nfi_ctrlupd_ack, which is an update response sent by the PHY to the Controller; a PHY update request signal nfi_phyupd_req, which is an update request sent by the PHY to the Controller; a PHY update response signal nfi_phyupd_ack, which is an update response sent by the Controller to the PHY; and a PHY update type signal nfi_phyupd_type, which is used to indicate the update type of the PHY.

[0088] In one embodiment, the interface signals in the status signal set may specifically include: a PHY initialization enable signal nfi_init_start, used to indicate that the PHY starts initialization; an initialization completion signal nfi_init_complete, used to indicate that the PHY initialization is complete; initialization configuration information nfi_init_info; PHY status information nfi_status; and a PHY interrupt signal nfi_int.

[0089] In one embodiment, the interface signals in the low-power signal set may specifically include: a low-power request signal nfi_lp_req, sent by the Controller to the PHY for making a low-power mode request; a low-power response signal nfi_lp_ack, sent by the PHY to the Controller for making a low-power mode response; and a low-power exit signal nfi_lp_wakeup, used to control the exit time of the low-power mode.

[0090] By adopting the NFI interface protocol-based NAND-Flash memory access device provided in the embodiment of the present application, a set of universal NFI interface protocols for use between the NAND-Flash Controller and the PHY is defined. After determining the target to be accessed and the access type corresponding to the received access request, the interaction signal and control timing corresponding to the access request can be determined based on the universal NFI interface protocol, and then the interaction signal can be controlled according to the control timing to achieve memory access to the target to be accessed, thereby greatly improving access efficiency. At the same time, the universal NFI interface protocol can be used to realize the interconnection operation between the NAND-Flash Controller and PHY of different manufacturers, avoiding the need to design corresponding hardware circuits and memory access methods for different manufacturers each time, thereby greatly improving chip R&D efficiency and reducing design costs.

[0091] Figure 25 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. Figure 25 At the hardware level, the electronic device includes a processor and, optionally, an internal bus, a network interface, and memory. The memory may include internal memory, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk drive. Of course, the electronic device may also include other hardware required for its services.

[0092] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, Figure 25 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0093] The memory is used to store programs. Specifically, the program may include program code, which includes computer operating instructions. The memory may include internal memory and non-volatile memory, and provides instructions and data to the processor.

[0094] The processor reads the corresponding computer program from the non-volatile memory into the internal memory and then runs it, forming a NAND-Flash memory access device based on the NFI interface protocol at the logical level. The processor executes the program stored in the memory and is specifically configured to perform the following operations: determine the target to be accessed and the access type corresponding to the received access request; based on the NFI interface protocol, determine the interaction signal and control timing corresponding to the access request according to the access target and the access type, wherein the NFI interface protocol defines the universal interface between the controller and the physical layer port PHY, the corresponding interaction signal set, timing, and interaction behavior; and control the interaction signal according to the control timing to achieve memory access to the target to be accessed.

[0095] The above application Figure 25The method disclosed in the illustrated embodiments for accessing NAND-Flash memory in an electronic device based on the NFI interface protocol can be applied to or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the method described above can be performed by hardware integrated logic circuits within the processor or by software instructions. The processor described above can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of this application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly executed by a hardware decoding processor or by a combination of hardware and software modules within the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0096] Of course, in addition to software implementation, the electronic device of this application does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0097] The embodiment of the present application also provides a computer-readable storage medium, which stores one or more programs, wherein the one or more programs include instructions, which, when executed by a portable electronic device including multiple application programs, can enable the portable electronic device to execute Figure 1 The method of the embodiment shown is specifically used to perform the following operations: Determine the target to be accessed and the access type corresponding to the received access request; based on the NFI interface protocol, determine the interaction signal and control timing corresponding to the access request according to the access target and the access type, wherein the NFI interface protocol defines the general interface, corresponding interaction signal set, timing and interaction behavior between the controller Controller and the physical layer port PHY; control the interaction signal according to the control timing to achieve memory access to the target to be accessed.

[0098] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0100] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0102] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0103] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0104] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can be implemented using any method or technology for information storage. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change RAM (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

[0105] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0106] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0107] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included within the scope of the claims of the present application.

Claims

1. A NAND-Flash memory access method based on the NFI interface protocol, characterized in that: include: Determine the target to be accessed and the access type corresponding to the received access request; Based on the NFI interface protocol, according to the access target and the access type, determine the interaction signal and control timing corresponding to the access request, wherein the NFI interface protocol defines a common interface between a controller Controller and a physical layer port PHY, a corresponding interface signal set, timing, and interaction behavior; The interactive signal is controlled according to the control timing to achieve memory access to the target to be accessed.

2. The method according to claim 1, characterized in that The interface signal set includes: Global interface signal set, command signal set, read / write signal set, update signal set, status signal set, and low power signal set.

3. The method according to claim 2, characterized in that The interface signals in the global interface signal set include: The clock signal nfi_clock is used to indicate the clock corresponding to the bus processing unit in the Controller and the PHY; The reset signal nfi_reset is used to indicate the corresponding reset of the bus processing unit in the Controller and the PHY.

4. The method according to claim 2, characterized in that: The interface signals in the command signal set include: A chip select signal nfi_cen is used to control the CE line of the I / O interface of the NAND-Flash; Sending a command signal nfi_cle to control the CLE line of the I / O interface of the NAND-Flash; Sending an address signal nfi_ale to control the I / O interface ALE line of the NAND-Flash; A write signal nfi_wen is used to control the I / O interface WEN line of the NAND-Flash; The write protection signal nfi_wpn is used to control the I / O interface WPn line of the NAND-Flash.

5. The method according to claim 2, characterized in that: The read / write signal set comprises: Write control signal subset, single data rate SDR read control signal subset, double data rate DDR read control signal subset and SCA interface read control signal subset.

6. The method according to claim 5, characterized in that The interface signals in the write control signal subset include: Write enable signal nfi_wrdata_en, used to indicate that data is written into the memory; Direction control signal nfi_wrdata, used to indicate the data writing direction; DBI write direction control signal nfi_wrdata_dbi, used to control the I / O interface DBI line of the NAND-Flash; The DQS write direction control signal nfi_wdqs is used to control the DQS / DQSn differential signal of the I / O interface of the NAND-Flash.

7. The method according to claim 5, characterized in that The interface signals in the SDR read control signal subset include: SDR read enable signal nfi_sdr_rddata_en, used to indicate that data is read from the memory; SDR read data signals nfi_sdr_rddata and nfi_sdr_rddata_dbi are used to indicate the data read by the SDR; The SDR read data valid flag nfi_sdr_rddata_vld is used to indicate the validity of the SDR read data.

8. The method according to claim 5, characterized in that The interface signals in the DDR read control signal subset include: The differential line control signal nfi_ren is used to control the I / O interface REn / RE differential line of the NAND-Flash; The read enable signal nfi_rddata_en is used to indicate that data is read out from the memory; Read data signals nfi_rddata and nfi_rddata_dbi are used to indicate the read data; The read data valid flag nfi_rddata_vld is used to indicate the validity of the read data.

9. The method according to claim 5, characterized in that The interface signals in the SCA interface read control signal subset include: SCA read enable signal nfi_sca_rddata_en is used to indicate the reading of information from the CA bus and to control the transmission direction of the ALE / CLE signal in SCA mode; SCA read data signal nfi_sca_rddata, used to indicate the data read by SCA; The SCA read data valid flag nfi_sca_rddata_vld is used to indicate the validity of the SCA read data.

10. The method according to claim 2, characterized in that The interface signals in the update signal set include: Controller update request signal nfi_ctrlupd_req, an update request sent by the Controller to the PHY; Controller update response signal nfi_ctrlupd_ack, an update response sent by the PHY to the Controller; PHY update request signal nfi_phyupd_req, an update request sent by the PHY to the Controller; PHY update response signal nfi_phyupd_ack, an update response sent by the Controller to the PHY; The PHY update type signal nfi_phyupd_type is used to indicate the update type of the PHY.

11. The method according to claim 2, characterized in that The interface signals in the status signal set include: A PHY initialization enable signal nfi_init_start is used to instruct the PHY to start initialization; The initialization completion signal nfi_init_complete is used to indicate that the PHY initialization is completed; Initialize configuration information nfi_init_info; PHY status information nfi_status; PHY interrupt signal nfi_int.

12. The method according to claim 2, characterized in that: The interface signals in the low-power signal set include: A low power request signal nfi_lp_req is sent by the Controller to the PHY to request a low power mode; A low power response signal nfi_lp_ack is sent by the PHY to the Controller for low power mode response; The low power exit signal nfi_lp_wakeup is used to control the time to exit the low power mode.

13. A NAND-Flash memory access device based on the NFI interface protocol, characterized in that: include: A request receiving unit, used to determine a target to be accessed and an access type corresponding to a received access request; An interactive signal determination unit, configured to determine the interactive signal and control timing corresponding to the access request based on the NFI interface protocol, according to the access target and the access type, wherein the NFI interface protocol defines a general interface between a controller Controller and a physical layer port PHY, a corresponding interactive signal set, timing, and interactive behavior; An access unit is used to control the interactive signal according to the control timing to achieve memory access to the target to be accessed.

14. A NAND-Flash memory access device based on the NFI interface protocol, comprising: processor; A memory arranged to store computer executable instructions, which, when executed, cause the processor to perform the NAND-Flash memory access method according to any one of claims 1 to 12.

15. A computer-readable storage medium storing one or more programs, which, when executed by an electronic device including a plurality of application programs, enables the electronic device to execute the NAND-Flash memory access method as described in any one of claims 1 to 12.

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