Extended floating point range processors, methods, systems, and instructions

Abstract

The disclosure relates to extended floating point range processors, methods, systems, and instructions. A processor of an aspect includes decoder circuitry to decode an instruction indicating a source floating point operand having floating point data elements and indicating a destination register. The element has sign bits, an N-bit first exponent value, and M bits. An execution circuit of the processor is used for: when N-bit first index values are not all-zero or all-one, interpreting M bits as M-bit valid numbers; and when the N-bit first exponent value is all zero or all, interpreting the M bits as including the second exponent value in at least one of the M bits and less than the M-bit significance in at least another of the M bits. The execution unit is to perform an operation on the source floating point operand to generate a result floating point operand, and to store the result floating point operand in the destination register.

Description

Technical Field

[0001] Embodiments described herein generally relate to processors. In particular, embodiments described herein generally relate to processors for processing floating point data elements. Background Art

[0002] Floating point numbers are commonly used in processors, computer systems, and other electronic devices. One advantage of floating point numbers is that they allow a wide range of values ​​to be represented in a relatively compact format and / or number of bits.

[0003] Floating point numbers are usually defined according to a floating point format. The floating point format allocates the bits used to represent the floating point number into several constituent fields, which are called the sign bit, the significand (also called the mantissa or fraction), and the exponent of the floating point number. The exponent bias value is also usually used to adjust the exponent. The value of a floating point number can be expressed using the sign bit "s", the significand, the exponent, and the exponent bias value "bias value", as shown in the following equation:

[0004] Value = (-1) s *(1+significant number)*2 (指数-偏置值) Equation 1

[0005] The expression "(-1) s " represents -1 raised to the power of the sign bit "s". This expression evaluates whether the floating point number is positive or negative. For example, when the sign bit is zero, the floating point number is positive, and when the sign bit is one, the floating point number is negative. The significand includes a bit string of length that affects the precision of the floating point number. As shown in the expression "(1 + significand)", the significand typically includes an implicit most significant bit (MSB) or leftmost bit whose value is one, called the J bit. This implicit bit or J bit is not one of the explicit bits present in the floating point number, but is an implicit or hidden bit that provides additional precision without explicitly encoding another explicit significand bit. The binary point is typically implicitly assumed to be located at a fixed position just to the right of the J bit or one bit below the J bit.

[0006] Multiplication by 2 to the power of "(exponent - bias value)" is used to shift the binary point exponent minus the exponent bias value. The exponent bias value is used to control which encodings of the exponent bits represent values ​​greater than one and which encodings of the exponent bits represent values ​​between zero and one. The exponent bits are used to encode unsigned integers of different values. Subtracting the exponent bias value from the exponent allows the "exponent - bias value" to be positive or negative, depending on the value of the exponent and the exponent bias value. The exponent bias value of a standard floating point format is typically standardized (fixed) for the format, and the standardized exponent bias value typically has a mapping of approximately equal exponent-encoded numbers to values ​​greater than one and values ​​between zero and one. Summary of the invention

[0007] One aspect of the present disclosure provides a processor, including: a decoder circuit, configured to decode an instruction, the instruction being configured to indicate at least a source floating-point operand and a destination register, the source floating-point operand having at least a floating-point data element, the floating-point data element having a sign bit, an N-bit first exponent value, and M bits; and an execution circuit, coupled to the decoder circuit, configured to perform an operation corresponding to the instruction, the operation comprising: interpreting the M bits as an M-bit significand when the N-bit first exponent value is not all zeros or all ones; interpreting the M bits as including a second exponent value in at least one of the M bits and including less than an M-bit significand in at least another of the M bits when the N-bit first exponent value is all zeros or all ones; performing the operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; and storing the result floating-point operand in the destination register.

[0008] An aspect of the present disclosure provides a method, comprising: decoding an instruction, the instruction indicating at least a source floating-point operand and a destination register, the source floating-point operand having at least a floating-point data element, the floating-point data element having a sign bit, an N-bit first exponent value, and M bits; and performing an operation corresponding to the instruction, the operation comprising: interpreting the M bits as an M-bit significand when the N-bit first exponent value is not all zeros or all ones; interpreting the M bits as including a second exponent value in at least one of the M bits and including less than M bits of significand in at least another of the M bits when the N-bit first exponent value is all zeros or all ones; performing the operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; and storing the result floating-point operand in the destination register.

[0009] One aspect of the present disclosure provides a system for processing instructions, including: a processor, the processor including: a decoder circuit for decoding an instruction, the instruction for indicating at least a source floating-point operand and a destination register, the source floating-point operand having at least a floating-point data element, the floating-point data element having a sign bit, an N-bit first exponent value, and M bits; and an execution circuit coupled to the decoder circuit, the execution circuit for performing an operation corresponding to the instruction, the operation including: interpreting the M bits as an M-bit significand when the N-bit first exponent value is not all zeros or all ones; interpreting the M bits as including a second exponent value in at least one of the M bits and including less than M bits of significand in at least another of the M bits when the N-bit first exponent value is all zeros or all ones; performing the operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; and storing the result floating-point operand in the destination register; and a dynamic random access memory (DRAM) coupled to the processor.

[0010] One aspect of the present disclosure provides a processor, comprising: a device for decoding an instruction, the instruction being used to indicate at least a source floating-point operand and a destination register, the source floating-point operand having at least a floating-point data element, the floating-point data element having a sign bit, an N-bit first exponent value, and M bits; and a device for interpreting the M bits as an M-bit significand when the N-bit first exponent value is not all zeros or all ones; a device for interpreting the M bits as including a second exponent value in at least one of the M bits and including less than an M-bit significand in at least another of the M bits when the N-bit first exponent value is all zeros or all ones; a device for performing an operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; and a device for storing the result floating-point operand in the destination register.

[0011] An aspect of the present disclosure provides a machine-readable medium, the machine-readable medium including machine-readable instructions, the machine-readable instructions, when executed, causing a machine to perform operations, the operations including: decoding an instruction, the instruction being used to indicate at least a source floating-point operand and a destination register, the source floating-point operand having at least a floating-point data element, the floating-point data element having a sign bit, an N-bit first exponent value, and M bits; and causing a processor to perform operations corresponding to the instruction, the operations including: interpreting the M bits as an M-bit significand when the N-bit first exponent value is not all zeros or all ones; interpreting the M bits as including a second exponent value in at least one of the M bits and including less than an M-bit significand in at least another of the M bits when the N-bit first exponent value is all zeros or all ones; performing the operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; and storing the result floating-point operand in the destination register.

[0012] One aspect of the present disclosure provides a processor, including a device for executing the above method.

[0013] One aspect of the present disclosure provides a machine-readable medium, the machine-readable medium comprising machine-readable instructions, which, when executed, cause a machine to perform the above method.

[0014] One aspect of the present disclosure provides a computer program product, the computer program product comprising instructions, which when executed by a processor, causes the processor to perform the above method. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Various examples according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0016] Figure 1 is a table listing several examples of a standard floating point format, one or more extended range floating point formats, and a processor 102 operable to interpret and / or process floating point data elements according to both the standard floating point format and the one or more extended range floating point formats.

[0017] Figure 2 is a block diagram of an embodiment of a processor executing floating point instructions to process floating point data elements according to an extended floating point range.

[0018] Figure 3 is a block diagram of a more detailed example embodiment of a processor executing floating point instructions to process floating point data elements according to an extended floating point range.

[0019] Figure 4 is a diagram illustrating a first example embodiment of interpreting floating point data elements according to either the standard floating point format or the extended exponent range floating point format.

[0020] Figure 5 is a diagram illustrating a second example embodiment of interpreting floating point data elements according to either the standard floating point format or the extended exponent range floating point format.

[0021] Figure 6 is a diagram illustrating a third example embodiment of interpreting floating point data elements according to either the standard floating point format or the extended exponent range floating point format.

[0022] Figure 7 is a table listing several examples of extended exponent ranges for standard and underflow floating-point formats.

[0023] Figure 8 is a diagram illustrating an example embodiment of interpreting floating-point data elements according to the standard floating-point format or the extended exponent range floating-point format.

[0024] Fig. 9 is a table listing several examples of extended exponent ranges for standard and overflow floating-point formats.

[0025] Fig.10 is a block diagram of an embodiment of a processor having one or more registers that store information associated with extending the floating point range.

[0026] Fig.11 is a block diagram of an embodiment of a floating point instruction indicating information associated with extending the floating point range.

[0027] Fig.12 An example embodiment of a method of processing floating point instructions executed by a processor is illustrated.

[0028] Fig.13 Example embodiments of methods of processing floating point instructions using emulation or binary translation are illustrated.

[0029] Fig.14 is a block diagram of an example embodiment of a processor having a floating point arithmetic unit 105 that performs an arithmetic operation on a first floating point data element and a second floating point data element, wherein at least one of the floating point data elements uses a second exponent value.

[0030] Fig.15 is a block flow diagram of an example embodiment of a method of multiplying first and second floating point data elements when at least one of the first and second floating point data elements utilizes a second exponent value.

[0031] Fig.16 is a block diagram of an example embodiment of a floating point multiplier capable of multiplying first and second floating point data elements when at least one of the first and second floating point data elements utilizes a second exponent value.

[0032] FIG. 17A to FIG. 17Bis a block flow diagram of an example embodiment of a method of adding first and second floating point data elements when at least one of the first and second floating point data elements utilizes a second exponent value.

[0033] Fig.18 is a block diagram of an example embodiment of a floating point adder capable of adding first and second floating point data elements when at least one of the first and second floating point data elements utilizes a second exponent value.

[0034] Fig.19 An example computing system is illustrated.

[0035] Fig. 20 A block diagram of an example processor and / or system on a chip (SoC) that may have one or more cores and an integrated memory controller is illustrated.

[0036] 21(A) is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example.

[0037] 21(B) is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example.

[0038] Fig. 22 Examples of execution unit(s) circuitry are illustrated.

[0039] Fig.23 is a block diagram of a register architecture according to some examples.

[0040] Fig.24 An example of the instruction format is illustrated.

[0041] Fig.25 An example of the addressing information field is illustrated.

[0042] Fig.26 An example of the first prefix is ​​illustrated.

[0043] Figures 27(A) to 27(D) illustrate how to use Fig.26 Example of the R, X, and B fields of the first prefix in .

[0044] 28(A) to 28(B) illustrate examples of the second prefix.

[0045] Fig.29 An example of the third prefix is ​​illustrated.

[0046] Fig.30 is a block diagram illustrating converting binary instructions in a source instruction set architecture to binary instructions in a target instruction set architecture using a software instruction converter according to an example. DETAILED DESCRIPTION

[0047] Disclosed herein are embodiments of methods for interpreting and / or processing floating-point data elements according to one or more extended range floating-point formats, embodiments of processors for interpreting and / or processing floating-point data elements according to one or more extended range floating-point formats, embodiments of systems incorporating one or more processors for interpreting and / or processing floating-point data elements according to one or more extended range floating-point formats, embodiments of floating-point instructions utilizing one or more extended range floating-point formats, and embodiments of programs or machine-readable media for storing or otherwise providing floating-point instructions utilizing one or more extended range floating-point formats. In the following description, many specific details (e.g., specific instruction operations, floating-point formats, processor configurations, microarchitecture details, sequences of operations, etc.) are set forth. However, embodiments may be practiced without these specific details. In other cases, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this specification.

[0048] Figure 1 is a table listing several examples of a standard floating point format 100 , one or more extended range floating point formats 101 , and a processor 102 operable to interpret and / or process floating point data elements according to both the standard floating point format 100 and the one or more extended range floating point formats 101 .

[0049] Six example standard floating point formats are shown in different rows. For these six standard floating point formats, the number of explicit significands and the number of exponent bits are listed in the columns. The double precision floating point format (sometimes referred to as FP64) is a 64-bit format that includes a sign bit, fifty-three significands (of which fifty-two are explicit and one is implicit), and eleven exponent bits. The single precision floating point format (sometimes referred to as FP32) is a 32-bit format that includes a sign bit, twenty-four significands (of which twenty-three are explicit and one is implicit), and eight exponent bits. The half precision floating point format (sometimes referred to as FP16) is a 16-bit format that includes a sign bit, eleven significands (of which ten are explicit and one is implicit), and 5 exponent bits. The bfloat16 or bf16 floating point format is a 16-bit format that includes a sign bit, eight significands (of which seven are explicit and one is implicit), and eight exponent bits. The FP8 E5M2 format is an 8-bit format that includes a sign bit, three significand bits (two of which are explicit and one is implicit), and five exponent bits. The FP8 E4M3 format is an 8-bit format that includes a sign bit, four significand bits (three of which are explicit and one is implicit), and four exponent bits. Other standard floating-point formats are also known, such as the extended double-precision floating-point format, the Tensor Float 32 floating-point format (sometimes referred to as TF32), and the like. TF32 is a floating-point format that is not byte-aligned and has a sign bit, eleven significand bits (ten of which are explicit and one is implicit), and eight exponent bits.

[0050] The processor 102 may be operable to interpret and / or process floating point data elements according to and / or in compliance with one or more of these standard floating point formats 100. For example, for a 32-bit single precision floating point format, the processor may understand or know which 8 bits are the exponent bits, which 23 bits are the explicit significand bits, how to represent denormal (also called subnormal) values, how to represent infinity values, and so on.

[0051] Now, a limitation of these standard floating-point formats is that they each have a corresponding fixed number of exponent bits. The number of exponent bits largely determines the range or breadth of the values ​​that can be represented by the floating-point data element. Generally, a format with more exponent bits has a larger range or breadth than a format with fewer exponent bits. For example, the FP64 format can represent numbers larger and smaller than the FP32 format. Generally, the lowest or smallest exponent that can be encoded in the exponent bits (e.g., exponent bits that are all zero) is used to indicate underflow and / or a non-normal number. Therefore, values ​​that are too small to be represented in a given format are generally interpreted or processed as non-normal numbers. Generally, the highest or largest exponent that can be encoded in the exponent bits (e.g., exponent bits that are all one) is used to indicate overflow and / or infinity. For example, an exponent bit that is all one and a valid digit that is all zero can be used to represent overflow and / or infinity. Moreover, an exponent bit that is all one and a valid digit that is not all zero can be used to represent a non-number (Not a Number, NaN).

[0052] A challenge is that current methods for processing non-normal numbers often have certain disadvantages. For example, a way to process non-normal numbers is to implement circuits or hardware that can process non-normal numbers. However, such circuits or hardware are often expensive in terms of additional die area and / or additional power consumption, and / or often increase latency, which may reduce performance. Therefore, many widely used general-purpose processors and other processors do not include circuits or hardware that can process non-normal numbers. Another way to process non-normal numbers is to capture non-normal numbers and process them in software or microcode. However, this method is often undesirably slow and reduces performance. In addition, various different types of applications encounter non-normal numbers, and for some of these applications, it is necessary to efficiently process the ability of this very small number. One such example is in training for machine learning and artificial intelligence, wherein, in training, it is usually necessary to efficiently process the ability of very small numbers to achieve convergence. Therefore, new and different ways to process small numbers will be useful.

[0053] In some embodiments, processor 102 is also operable to interpret and process floating point data elements according to one or more extended range floating point formats 101. Any one or more of the extended range floating point formats discussed further below are suitable. Advantageously, the extended range floating point format can provide an extended range or a larger range than the range provided by the corresponding standard floating point format. In some embodiments, the extended range can expand the range of the smallest number that can be represented. Advantageously, this can allow more efficient processing of small numbers (otherwise it will be a non-normal number), without the challenges and shortcomings associated with processing non-normal numbers. In other embodiments, the extended range can expand the range of the maximum number that can be represented. In other embodiments, the extended range can expand the range of the minimum number that can be represented and the maximum number that can be represented.

[0054] Figure 2 202 executes floating point instructions 203 to process floating point data elements according to an extended floating point range. In some embodiments, the processor may represent a general purpose processor (e.g., a general purpose microprocessor or central processing unit (CPU) used in a desktop computer, a laptop computer, or other computer). Alternatively, the processor may represent a special purpose processor. Examples of suitable special purpose processors include, but are not limited to, coprocessors, machine learning processors, artificial intelligence processors, graphics processors, and digital signal processors (DSPs). The processor may have any of various complex instruction set computing (CISC) architectures, reduced instruction set computing (RISC) architectures, very long instruction word (VLIW) architectures, hybrid architectures, other types of architectures, or a combination of different architectures (e.g., different cores may have different architectures). In some embodiments, the processor may include (e.g., be arranged on) at least one integrated circuit or semiconductor die.

[0055] The processor may be coupled to receive floating point instructions 203. The floating point instructions may represent macro instructions, machine code instructions, or instructions of an instruction set of the processor. The floating point instructions may be in any suitable format, such as reference Fig.11 The format described in the preceding paragraph or other formats below. A more detailed example of at least one instruction format for the instruction will be described in detail later. The instruction includes one or more fields for an opcode. In some examples, the opcode at least partially or completely specifies the operation of the instruction to be performed (e.g., floating point format conversion, addition, multiplication, etc.).

[0056] The instruction may explicitly specify (e.g., via one or more fields or a set of bits) or otherwise indicate (e.g., implicitly) at least a first source floating point operand 206. The first source floating point operand may have at least a floating point data element 207. In various embodiments, the floating point data element may be an 8-bit, 16-bit, 32-bit, or 64-bit floating point data element (e.g., having Figure 1 In various embodiments, the first source floating-point operand may be a scalar operand having only floating-point data elements, or the first source floating-point operand may be a vector operand of floating-point data elements in a vector having floating-point data elements, or the first source floating-point operand may be a matrix operand of floating-point data elements in a matrix having floating-point data elements. For simplicity of description, only floating-point data elements are shown, but the concepts described herein may be optionally applied to other floating-point data elements of a vector or matrix. In some embodiments, the instruction may optionally specify or otherwise indicate an optional second source floating-point operand 212 (e.g., a scalar, vector, or matrix operand such as the first source floating-point operand). The first and optional second source floating-point operands may be stored in registers and / or memory 215. The instruction may also specify or otherwise indicate a destination register 213 where the result floating-point operand 214 is to be stored. As an example, the instruction may have a source and / or destination field or identifier to specify or otherwise indicate such a register / memory location for these operands. Alternatively, one or more of these registers / memory locations may optionally be implicit to the instruction (eg, implicit to the opcode).For example, a source / destination register may be implicitly or implicitly understood as being used for both the first source floating point operand and the result floating point operand.

[0057] The destination register 213 and one or more registers for storing at least one source floating-point operand may represent a storage location on the die (or on an integrated circuit) where data is stored. These registers may represent architectural registers visible to software and / or programmers or architecturally visible registers, and / or registers that are identified by instructions of the processor's instruction set to identify operands. These architectural registers contrast with non-architectural registers (e.g., temporary registers, reorder buffers, retirement registers, etc.) in the microarchitecture. Registers may be implemented in different ways in different microarchitectures and are not limited to any particular type of design. Examples of suitable types of registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, and combinations thereof. Example register types include scalar registers (e.g., general purpose registers (GPRs)), compact data or vector registers, registers for storing matrices or portions of matrices, and the like.

[0058] Decoder circuit 204 is capable of or operates to decode floating-point instructions into one or more lower-level control signals or operations. In some examples, the decoding includes generating a plurality of micro-operations to be performed by execution circuit 205. For some instruction encodings, the decoder circuit can also optionally decode instruction prefixes. In some embodiments, the decoder circuit may include: at least one input structure (e.g., port, interconnection, or interface) coupled to receive floating-point instructions; instruction recognition and decoder circuits coupled to the input structure to recognize and decode floating-point instructions; and at least one output structure (e.g., port, interconnection, or interface) coupled to the instruction recognition and decoder circuit to output one or more low-level control signals or operations or decoded instructions. Instruction recognition and decoder circuits can be implemented using various methods, including but not limited to microcode read-only memory (ROM), lookup tables, hardware implementations, programmable logic arrays (PLA), other mechanisms suitable for implementing decoder circuits, and combinations thereof. In some embodiments, the decoder circuit may be included on a die, an integrated circuit, or a semiconductor substrate.

[0059] Execution circuitry 205 is coupled to decoder circuitry 204 (e.g., to receive one or more low-level control signals or operations). Execution circuitry is also coupled to register / memory 215 (e.g., to receive first and optional second source floating-point operands and store resultant floating-point operands). Execution circuitry is capable of or operable to perform an operation corresponding to floating-point instruction 203 (e.g., as specified by an opcode of the floating-point instruction, as specified by control bits in a floating-point control register, etc.).

[0060] Execution circuit 205 may receive floating point data element 207. The floating point data element may have a sign bit 209, an N-bit first exponent value 210 (eg, where N is Figure 1 The M bits are separate and different from those used for the N-bit first exponent value. N and M may be integers, such as having Figure 1 208. The values ​​of the exponent bits and the explicit significand bits are shown. These bits are explicitly encoded bits in a floating point data element (e.g., an 8-bit, 16-bit, 32-bit, or 64-bit floating point data element). A floating point data element may also have an implicit most significant significand bit or J bit 208 that is not explicitly encoded in the bits of the floating point data element.

[0061] In some embodiments, the execution circuitry is operable to interpret and / or process and / or manipulate the M bits 211 based at least in part on the N-bit first exponent value 210 (e.g., based on its binary value). As shown within the execution circuitry in the illustration, in some embodiments, when the N-bit first exponent value 216 is not all zeros and / or a minimum binary value (e.g., not 00000, 00000000, 00000000000, etc.) or all ones and / or a maximum binary value (e.g., not 11111, 111111111, 11111111111, etc.), then the M bits 211 may be interpreted and / or processed as an M-bit significand 217. In this case, the N-bit first exponent value may be an actual single exponent of a floating-point data element. Typically, this interpretation may conform to a floating-point format having a standard floating-point format (e.g., Figure 1 For example, where floating point data element 207 has a double precision or FP64 format, when the eleven least significant bits of the floating point data element corresponding to the eleven exponent bits are not all zeros or all ones (e.g., not 00000000000 and not 11111111111), then the execution circuitry may interpret the consecutively next more significant fifty-two bits as a 52-bit significand (e.g., an explicit significand, but with an implicit most significant digit or J bit). This may be similarly performed for Figure 1 Other standard formats.

[0062] In contrast, as further illustrated below within the execution circuitry of the diagram, in some embodiments, when the N-bit first exponent value 218 is all zeros and / or a minimum binary value (e.g., 00000, 00000000, 00000000000, etc.) or is all ones and / or a maximum binary value (e.g., 11111, 111111111, 11111111111, etc.), then the M bits 211 may be interpreted and / or processed as including at least one second exponent value 219 in at least one of the M bits 211 and at least one significand 220 (e.g., an explicit significand) in at least one other of the M bits 211. This may be true when the M bits are not all zeros. The at least one second exponent value may be an actual exponent, or may be a value that, when combined with or applied to the actual exponent, is an exponent. For example, where floating point data element 207 otherwise has a double precision or FP64 format, when the eleven least significant bits of the floating point data element corresponding to the eleven exponent bits are all zeros or all ones (e.g., 00000000000 or 111111111111), then the execution circuitry may interpret the successively next more significant fifty-two bits as having both second exponent value 219 and significand 220 (e.g., an explicit significand). This may be similarly performed for Figure 1 This interpretation does not conform to the other standard formats of Figure 1 The floating point data element 207 is one of the standard floating point formats described above and is not consistent therewith. Conventionally, a floating point data element 207 that conforms to Figure 1 A floating point data element of one of the standard floating point formats described will not have a second exponent value. Instead, such an interpretation corresponds to an extended exponent range format used when the N-bit first exponent value 210 of the floating point data element 207 has a special value (e.g., all zeros, all ones, or all zeros or all ones).

[0063] In the case where the N-bit first exponent value is all zeros, this may effectively represent redefining the meaning or interpretation (e.g., the least significant digit of the significand that would otherwise be the significand) to form the second exponent value, thereby allowing expression of a smaller floating point number than would be possible with the associated standard floating point format without the second exponent value. In the case where the N-bit first exponent value is all ones, this may effectively represent utilizing redundant bits of special floating point numbers (e.g., infinity and / or non-number (NaN)) to form the second exponent value, thereby allowing expression of a larger floating point number than would be possible with the associated standard floating point format without the second exponent value.

[0064] In various embodiments, at least one second exponent value 219 can be two, three, four, five, six or more second exponent values. In various embodiments, at least one significand 220 can be two, three, four, five, six or more significands. In some embodiments, at least one second exponent value can optionally have enough bits to be able to shift or cover all bits from at least a majority of at least one significand. At least one second exponent value with at least log^2 (significand)+1 bits will generally allow the at least one significand to shift or cover all bits of the at least one significand. In some embodiments, at least one significand 220 can optionally have at least a majority of M bits 211 to all remaining bits that are not used for at least one second exponent value 219. Generally, it can be advantageous that at least one second exponent value 219 and at least one significand 220 jointly utilize at least a majority of M bits 211 to all bits, to achieve a relatively more extended exponent range and / or higher precision, but some bits can also be left unused for any purpose. Even if all bits are not used, it is also useful to use one or more of the bits. Moreover, it is contemplated that one or more of the M bits may alternatively be used for another purpose (eg, to indicate infinity, to indicate not-a-number (NaN), to provide other information).

[0065] The ability to utilize M bits to include alternative meanings or interpretations of the second exponent value 219 (e.g., rather than just the M-bit significand 217) can always be enabled (e.g., built into or incorporated into the circuit), or can be configurable so that it can be enabled or disabled. When configurable, the configurability can be provided in different ways in different embodiments. In some embodiments, the configurability can be provided via one or more registers. For example, one or more bits can be present in a model-specific register, a processor configuration register, a processor control register, or other such registers to enable or disable the feature. Representatively, such registers can allow the feature to be enabled or disabled on a multi-threaded, multi-core, or entire processor basis. As another example, one or more bits can be present in a floating point control register, etc. to enable or disable the feature. Representatively, such registers can allow the feature to be enabled or disabled on a thread-by-thread basis. In other embodiments, an instruction can have one or more bits to enable or disable the feature. As an example, the opcode of an instruction can enable or disable the feature (e.g., certain opcodes can enable the feature, while other opcodes can disable the feature). As another example, an instruction may have a prefix to enable or disable the feature (e.g., an instruction with the prefix may enable the feature, while an instruction without the prefix may disable the feature, or vice versa). As yet another example, an instruction may have an immediate value or other field or set of one or more bits to enable or disable the feature (e.g., a first value of the immediate value, field, or set of one or more bits may enable the feature, while a second value may disable the feature).

[0066] Moreover, the number of digits of at least one second exponent value, the number of digits of at least one significand, or both can be fixed / static (e.g., constructed or incorporated into a circuit) or dynamically variable, flexible, or configurable. When configurable, configurability can be provided in different ways in different embodiments. In some embodiments, configurability can be provided via one or more registers. For example, one or more bits may be present in a model-specific register, a processor configuration register, a processor control register, or other such registers to specify or configure one or more of these digits. Representatively, such registers may allow configuration of the digits on the basis of multithreading, multi-core, or the entire processor. As another example, one or more bits may be present in a floating-point control register, etc. to specify or configure one or more of these digits. Representatively, such registers may allow configuration of the digits thread by thread. In other embodiments, an instruction may have one or more bits to specify or configure one or more of these digits. For example, an instruction may have a prefix to configure the digits. As an example, an instruction may have an immediate number or other field or a set of one or more bits to configure the digits (e.g., the value of an immediate number, other field, or other set of one or more bits may specify the digits).

[0067] In some embodiments, the extended range format is not a posit format. For example, in contrast to the posit format, the N-bit first exponent value may have the same number of bits in both interpretations, and may have a fixed number of bits regardless of the specific value of the bits of the floating point number, rather than a number of bits that depends on the specific value of the bits of the floating point number (e.g., a flexible number of bits in a regime that depends on the specific value of the bits). Furthermore, in contrast to the posit format, the extended range format may not have a regime.

[0068] Although the interpretation of only a single floating-point data element has been described, it should be understood that other floating-point data elements of the first and optional second source floating-point operands may be similarly interpreted.

[0069] A possible advantage of the extended range floating point format is that an extended range of floating point numbers (e.g., an extended range or a range larger than the range provided by the associated standard floating point format) can be efficiently provided. In one aspect, the extension can be on the underflow side to provide additional range before a small number becomes a denormal number, which can also help to avoid challenges and shortcomings associated with processing denormal numbers. This may potentially provide advantages, especially in machine learning and artificial intelligence. On the other hand, the extension can be on the overflow side to provide additional range before a number becomes infinite. Another possible advantage of the extended range floating point format is that it is generally backward compatible and / or interchangeable with the associated standard floating point format and hardware. For example, if a floating point number is encoded according to the extended range floating point format and is placed in the standard floating point format operation and circuit, the output will generally still be correct. Another possible method is to use posit encoding, but these posit encodings are not compatible with the standard floating point format. Figure 1 The standard floating-point formats are not backwards compatible and / or interchangeable, and pose certain other challenges.

[0070] In some embodiments, floating-point data elements with second exponent values ​​may also be natively processed on conventional floating-point data processing hardware. For example, in the case where the N-bit first exponent value is all zero, the least significant bit (one or more) for at least one second exponent value may optionally be left alone and considered as part of the significand. This may represent a small error value acceptable to the implementation, or may even be used to introduce random rounding, which may be beneficial for some applications such as artificial intelligence training. In some embodiments, conventional floating-point data processing hardware may be changed in a minor manner to allow processing of floating-point data elements with second exponent values. For example, in the case where the N-bit first exponent value is all zero, conventional floating-point data processing hardware may be adapted to include logic for clearing the least significant bit (one or more) for at least one second exponent value. This may sacrifice some precision, but is acceptable for the implementation.

[0071] The execution circuitry is further operable to perform one or more floating point operations specified by and / or corresponding to the instruction on at least one source floating point operand (e.g., a first source floating point operand and an optional second source floating point operand) to generate a result floating point operand 214. This may be based on the interpretation of the M bits as described above. Examples of suitable operations include, but are not limited to: (1) scalar, vector, or matrix floating point format conversion (e.g., conversion from one floating point format (e.g., FP64) to another floating point format (e.g., FP32)); (2) scalar, vector, or matrix addition (e.g., addition of two scalar values, addition of corresponding elements of two vectors); (3) scalar, vector, or matrix multiplication (e.g., multiplication of two scalar values, multiplication of corresponding elements of two vectors, multiplication of two matrices); (4) scalar, vector, or matrix multiplication and accumulation (e.g., multiplication and product of two scalar values ​​and accumulation of a third scalar value, multiplication and product of corresponding elements of two vectors and accumulation of corresponding elements of a third vector, multiplication and product of corresponding elements of two matrices and accumulation of corresponding elements of a third matrix). These are just a few illustrative examples of suitable types of operations. Various other types of arithmetic, logical, or other operations performed on floating point data elements are also suitable (e.g., absolute value, dot product, rounding to integer value, etc.). Vector operations may be masked / predicted or unmasked / unpredicted. By way of example, an unmasked vector operation may include performing an operation (e.g., addition, multiplication, etc.) on each pair of corresponding (e.g., in the same relative bit positions) floating-point data elements of the first and second source floating-point vectors to generate a result floating-point vector having an operation result (e.g., a sum of corresponding pairs of floating-point data elements, a product of corresponding pairs of floating-point data elements, etc.). A masked vector operation may be similar, but may be performed only on those corresponding pairs of floating-point data elements for which corresponding mask bits or mask elements of the mask operand are not masked or have the first value, rather than being masked or having the second value.

[0072] The execution circuitry 205 may store the result floating point operand 214 in the destination register 213. For example, a single result floating point data element may be stored in a scalar general purpose register, or a vector of result floating point data elements may be stored in a vector, packed, or SIMD register, or a matrix of result floating point data elements may be stored in a tile storage device.

[0073] In some embodiments, the execution circuit may be a floating point unit, a floating point arithmetic unit, a floating point arithmetic logic unit, a floating point multiplier, a floating point adder, etc. In some embodiments, the execution circuit may include specific or concrete logic for executing instructions. By way of example, the execution circuit may include a floating point element processing circuit (e.g., an exponent processing circuit (e.g., an exponent adder), a circuit for subtracting or removing an exponent bias value from an exponent, a circuit for evaluating the value of an N-bit first exponent value (e.g., whether it is all zeros or all ones), etc.). In some embodiments, the execution unit may include one or more input structures (e.g., ports, interconnects, or interfaces) coupled to receive a first source floating point operand 206, a circuit coupled to the input structure to receive and process the first source floating point operand and generate a result operand, and one or more output structures (e.g., ports, interconnects, or interfaces) coupled to the circuit to output a result floating point operand 214. Other example execution circuits include (one or more) execution clusters 2160 shown in FIG. 21 (B), etc.

[0074] Figure 3 302 executes a floating point instruction 303 to process a floating point data element according to an extended floating point range. The processor includes a decoder circuit 304 for decoding the floating point instruction, an execution circuit 305 for performing an operation corresponding to the floating point instruction, and a register and / or memory 315 for storing operands of the floating point instruction. In addition to the aspects related to the additional components of the processor, and unless otherwise specified, the floating point instruction 303, the decoder circuit 304, the execution circuit 305, and the register / memory 315 can be optionally respectively described in the previous description of the floating point instruction 303, the decoder circuit 304, the execution circuit 305, and the register / memory 315. Figure 2 The floating point instructions 203, decoder circuit 204, execution circuit 205 and register / memory 215 described in the embodiment are the same or similar. In order to avoid making the description vague, the main description will be given. Figure 3 different and / or additional aspects of the embodiments without repeating what may optionally be described with respect to Figure 2 All aspects described are the same or similar.

[0075] The optional storage device 322 may store floating point instructions. By way of example, the storage device may be a cache (eg, instruction cache, unified cache) or a memory coupled to the processor.

[0076] As previously described, the decoder circuit 304 may receive and decode floating point instructions. For example, the decoder circuit may optionally be coupled to a storage device via an optional fetch circuit (not shown) to receive instructions.

[0077] In some examples, optional register renaming, register allocation and / or scheduling circuitry 323 may provide functionality for one or more of the following: (1) renaming logical operand values ​​to physical operand values ​​(e.g., a register alias table in some examples); (2) assigning status bits and flags to decoded instructions; and (3) scheduling decoded instructions for execution by execution circuitry from an instruction pool (e.g., using a reservation station in some examples).

[0078] As previously mentioned, registers / memory 315 can store operands for floating point instructions. Various numbers and types of operands are still possible.

[0079] The execution circuit 305 is coupled to the decoder circuit 304 and the register / memory 315 via the intermediate register renaming, register allocation and / or scheduling circuit 323. As previously described, the execution circuit 305 can perform operations corresponding to floating-point instructions. Example execution circuits include (one or more) execution clusters 2160 shown in Figure 21 (B), etc.

[0080] Optional retirement / writeback circuitry 324 may architecturally commit the destination register into register / memory 315 and commit the floating point instruction.

[0081] Figure 4 4 is a diagram illustrating a first example embodiment of interpreting a floating point data element according to a standard floating point format 400 or an extended exponent range floating point format 401. In each of the standard and extended exponent range floating point formats, the leftmost bit in the illustration is an implicit most significant bit (MSB) of the significand or J bit, which is not explicitly encoded. Also, for simplicity of illustration, a sign bit is not shown for either the standard or extended exponent range floating point formats, as the sign bit may be interpreted and used in the same conventional manner for both formats.

[0082] As shown for the standard floating point format 400, when the 5-bit first exponent value (X5-X1) 416 is not all zeros or all ones (e.g., X5-X1 is not 00000 or 11111), the execution circuitry may interpret the 10 bits (AJ) as a 10-bit explicit significand 417. This corresponds to the standard half-precision (FP16) floating point format.

[0083] As shown for the extended exponent range floating point format 401, when the 5-bit first exponent value 418 is all zeros (i.e., 00000), the execution circuitry may interpret the same corresponding 10 bits as including a 4-bit second exponent value (Y4-Y1) 419 in the four least significant bits (e.g., corresponding in position to GHIJ) of the 10 bits, and a 6-bit significand 420 in the six most significant bits (AF). In this case, the 6-bit significand includes all 10 bits not used for the 4-bit second exponent value (Y4-Y1). The execution circuitry uses the exponent encoded in the 4-bit second exponent value to shift, move, or otherwise interpret or identify the position of the binary point relative to the 6-bit significand (e.g., because the 5-bit first exponent value is all zeros, it represents a denormal number).

[0084] The lower portion of the figure illustrates the application of different exponents to eleven bits (for this FP16-based embodiment), including an implicit MSB of the significand, six explicit bits of the significand, and one zero for each of the 4-bit exponent value bits. The table shows an example of how the 4-bit second exponent value (Y4-Y1) can be mapped to different exponents, but there are many different ways to achieve this. These exponents correspond to different shifts or movements of the binary point. Each gradually more negative exponent can cause the execution circuit to shift out the next least significant bit. For example, an exponent of -2 can cause the execution circuit to shift out bit E, an exponent of -7 can cause the execution circuit to shift out bit D, and so on. For exponents of -1 to -4, there are four, three, two, and one bits of precision less than the standard denormal value, respectively, but for the remaining exponents, the number of bits of precision is the same as the standard denormal number. In some embodiments, the 4-bit second exponent value (Y4-Y1) has enough bits to be able to map to any of at least ten or in some cases eleven different exponents, which can allow the execution circuitry to shift out each of at least ten bits AJ or in some cases each of ten bits AJ and the implicit MSB of the significand, respectively. In this example, eleven different 4-bit second exponent values ​​(Y4-Y1) are mapped to eleven different negative non-zero exponents ranging from -1 to -11.

[0085] In some embodiments, for the bits of the 6-bit explicit significand and the implicit MSB of the significand, the most significant bit shifted out may be shifted into the sticky bit (S). For example, an exponent of -6 may cause the execution circuit to shift bit E into the sticky bit (S), an exponent of -7 may cause the execution circuit to shift bit D into the sticky bit (S), an exponent of -11 (e.g., when the 4-bit second exponent value (Y4-Y1) has a given value of one of 1011-1111 or 0000 in this example) may cause the execution circuit to shift out all bits of the 6-bit significand and shift the implicit MSB of the significand into the sticky bit (S), and so on. For example, for an exponent of -11, since the implicit MSB of the significand is set to a value of binary one, the sticky bit may be set to a value of binary one. In some embodiments, additional bits (e.g., rounding bits, guard bits) may also optionally be calculated based on the shifted out bits, although this is not required. This illustration is only one possible example. In another embodiment, the F bit may be represented in the encoding, and F may be present in other second exponent cases and eventually form part of the sticky bits.

[0086] In some embodiments, the application of these exponents (e.g., shifts) can be implemented using existing regular range floating point data paths, as opposed to conventional circuitry / hardware that handles denormal numbers in hardware. In some cases (e.g., when the extended exponent is very small), there may be a small reduction in precision compared to strictly calculating denormal numbers.

[0087] Figure 5 5 is a diagram illustrating a second example embodiment of interpreting floating point data elements according to a standard floating point format 500 or an extended exponent range floating point format 501. Except for some different and / or additional aspects that will be described below, and unless otherwise specified, this second example embodiment may optionally be similar to the one already described for Figure 4 In order to avoid making the description vague, the following will be mainly described. Figure 5 different and / or additional aspects of the second exemplary embodiment without repeating the various aspects that may optionally be discussed with respect to the Figure 4 All aspects of the description are similar.

[0088] As shown for the standard floating point format 500, when the 5-bit first exponent value (X5-X1) 516 is not all zeros or all ones (e.g., X5-X1 is not 00000 or 11111), the execution circuitry may interpret the 10 bits (AJ) as a 10-bit explicit significand 517. This corresponds to the standard half-precision (FP16) floating point format.

[0089] As shown for the extended exponent range floating point format 501, when the 5-bit first exponent value 518 is all zeros (i.e., 00000), the execution circuitry may interpret the same corresponding 10 bits as including a 3-bit second exponent value (Y3-Y1) 519 in the three least significant bits (e.g., corresponding in position to HIJ) of the 10 bits, and a 7-bit significand 520 in the seven most significant bits (AG). The execution circuitry uses the exponent encoded in the 3-bit second exponent value to shift, move, or otherwise interpret or identify the position of the binary point relative to the 7-bit significand (e.g., because the 5-bit first exponent value is all zeros, it represents a denormal number).

[0090] The lower portion of the figure illustrates the application of different exponents to eleven bits (for this FP16-based embodiment), which include the implicit MSB of the significand, seven explicit bits of the significand (AJ), and a zero for each of the 3-bit exponent value bits. The table shows one example of how the 3-bit second exponent value (Y3-Y1) can be mapped to different exponents, but there are many different ways this can be accomplished.

[0091] In this second example embodiment, the 3-bit second exponent value (Y3-Y1) does not have enough bits to be able to map to any of the eleven different exponents, thereby allowing the execution circuit to individually shift out each of the ten bits AJ and the implicit MSB of the significand. Instead, the 3-bit second exponent value is only able to encode eight different values. In this second example embodiment, these eight different values ​​are mapped to eight corresponding different negative non-zero exponents ranging from -1 to -8.

[0092] As previously described, for the 7-bit explicit significand bits, the most significant bit shifted out may be shifted into the sticky bit (S). For example, an exponent of -5 may cause the execution circuit to shift bit F into the sticky bit (S), an exponent of -6 may cause the execution circuit to shift bit E into the sticky bit (S), and an exponent of -7 may cause the execution circuit to shift bit D into the sticky bit (S). In this example, for an exponent of -8, since no additional exponent values ​​may be encoded in the 3-bit second exponent value, a hard underflow condition occurs, and the implicit MSB of the significand may be used to set the sticky bit. Alternatively, if desired, the eight 3-bit second exponent values ​​may optionally be mapped to different exponents, including exponents of values ​​other than those ranging from -1 to -8.

[0093] Figure 6 600 or an extended exponent range floating point format 601. Except for some different and / or additional aspects that will be described below, and unless otherwise specified, this third example embodiment may be optionally similar to the one already described for Figures 4 to 5In order to avoid making the description vague, the first and second exemplary embodiments will be mainly described. Figure 6 different and / or additional aspects of the third exemplary embodiment, without repeating the various and / or additional aspects that may be optionally described with respect to the third exemplary embodiment. Figures 4 to 5 All aspects of the description are similar.

[0094] As shown for the standard floating point format 600, when the 5-bit first exponent value (X5-X1) 616 is not all zeros or all ones (e.g., X5-X1 is not 00000 or 11111), the execution circuitry may interpret the 10 bits (AJ) as a 10-bit explicit significand 617. This corresponds to the standard half-precision (FP16) floating point format.

[0095] As shown for the extended exponent range floating point format 601, when the 5-bit first exponent value 618 is all zeros (i.e., 00000), the execution circuitry may interpret the same corresponding 10 bits as including a 2-bit second exponent value (Y2-Y1) 619 in the two least significant bits of the 10 bits (e.g., corresponding in position to IJ), and an 8-bit significand 620 in the eight most significant bits (AG). The execution circuitry uses the exponent encoded in the 2-bit second exponent value to shift, move, or otherwise interpret or identify the position of the binary point relative to the 8-bit significand (e.g., because the 5-bit first exponent value is all zeros, it represents a denormal number).

[0096] The lower portion of the figure illustrates the application of different exponents to eleven bits (for this FP16-based embodiment), which include the implicit MSB of the significand, seven explicit bits of the significand (AJ), and a zero for each of the 2-bit exponent value bits. The table shows one example of how the 2-bit second exponent value (Y2-Y1) can be mapped to different exponents, but there are different ways to achieve this.

[0097] In this third example embodiment, the 2-bit second exponent value (Y2-Y1) does not have enough bits to be able to map to any of the eleven different exponents, thereby allowing the execution circuit to individually shift out each of the ten bits AJ and the implicit MSB of the significand. Instead, the 2-bit second exponent value is only able to encode four different values. In this second example embodiment, these four different values ​​are mapped to four corresponding different negative non-zero exponents ranging from -1 to -4. In this example, for the exponent -4, since no additional exponent values ​​can be encoded in the 2-bit second exponent value, a hard underflow condition occurs, and the implicit MSB of the significand can be used to set the sticky bit. Alternatively, if desired, the eight 2-bit second exponent values ​​can be optionally mapped to different exponents, including exponents of other values ​​in addition to the exponents ranging from -1 to -4.

[0098] Methods similar to those described above can be applied to other standard floating point formats (e.g., double precision (FP64), single precision (FP32), Bfloat16, etc.). The number of bits used for the second exponent value can vary. A number of bits equal to or greater than the upper limit (log2(significand), where the upper limit is the next higher integer number of bits) or equal to or greater than the lower limit (log2(significand)+1, where the lower limit is the next lower integer number of bits) will generally allow the extended exponent range to cover the entire mantissa (e.g., as Figure 4 Alternatively, if the extended exponent range is smaller than this range, a hard underflow may occur on part of the mantissa (e.g., as Figures 5 and 6 shown).

[0099] Figure 7 is a table listing several examples of extended exponent ranges for standard floating point formats 700 and underflow floating point formats 701. For the standard floating point format, the first column lists the name of the format, the second column lists the number of explicit significand bits, and the third column lists the number of first exponent value bits. For the extended exponent ranges for the underflow floating point formats, the fourth column lists the number of second exponent value bits, and the fifth column lists the underflow significand bits.

[0100] The first row lists a 64-bit double precision (FP64) floating point format with 52 explicit significand bits and 11 first exponent value bits, and a corresponding extended exponent range format with 1-6 (or optionally 2-6) second exponent value bits and 46-51 (or optionally 46-50) underflow significand bits. The second row lists a 32-bit single precision (FP32) floating point format with 23 explicit significand bits and 8 first exponent value bits, and a corresponding extended exponent range format with 1-5 (or optionally 2-5) second exponent value bits and 18-22 (or optionally 18-21) underflow significand bits. The third row lists a 16-bit half precision (FP16) floating point format with 10 explicit significand bits and 5 first exponent value bits, and a corresponding extended exponent range format with 1-4 (or optionally 2-4) second exponent value bits and 6-9 (or optionally 6-8) underflow significand bits.

[0101] The fourth row lists a 16-bit Bfloat16 floating point format with 7 explicit significands and 8 first exponent value bits, and a corresponding extended exponent range format with 1-4 (or optionally 2-4) second exponent value bits and 3-6 (or optionally 3-5) underflow significand bits. The fifth row lists an 8-bit FP8E5M2 floating point format with 2 explicit significands and 5 first exponent value bits, and a corresponding extended exponent range format with 1-2 second exponent value bits and 0-1 underflow significand bits. The sixth row lists an 8-bit FP8 E4M3 floating point format with 3 explicit significands and 4 first exponent value bits, and a corresponding extended exponent range format with 1-3 second exponent value bits and 0-2 underflow significand bits.

[0102] The standard floating-point format specifies certain special exponents and significands for representing infinity and non-numbers (NaNs). In general, infinity is represented by the maximum biased exponent allowed by the format and a significand of zero. In general, both signaling and quiet NaNs are represented by the maximum biased exponent allowed by the format and a non-zero significand. The bit pattern of the significand for a signaling NaN has the most significant bit set to zero and at least one of the remaining bits set to one. The bit pattern of the significand for a quiet NaN has the most significant bit set to one. By way of example, for a single-precision floating-point value in which the least significant (rightmost) twenty-three bits are the significand, the next most significant eight bits are the exponent, and the most significant (leftmost) bit is the sign bit: (1) positive infinity can be represented by the bit pattern 7F800000 (01111111100000000000000000000000000); (2) negative infinity can be represented by the bit pattern FF800000 (3) Signaling NaN can be represented by a number between 7F800001 (0111111110000000000000000000000001) and 7FBFFFFF (011111111011111111111111111111) or FF80 Any bit pattern between 0001 (111111111000000000000000000000001) and FFBFFFFF (1111111110111111111111111111111); and (4) a quiet NaN can be represented by 7FC00000 (011111111110000000000000000 The digits in the digits can be represented by any bit pattern between 0000000) and 7FFFFFFF (01111111111111111111111111111111) or between FFC00000 (11111111110000000000000000000000) and 1 ...

[0103] Figure 8 800 or an extended exponent range floating point format 801. In each of the standard and extended exponent range floating point formats, the leftmost bit in the illustration is an implicit most significant bit (MSB) of the significand or J bit, which is not explicitly encoded. Also, for simplicity of illustration, the sign bit is not shown for either the standard and extended exponent range floating point formats, as the sign bit may be interpreted and used in the same conventional manner for both formats.

[0104] As shown for the standard floating point format 800, when the 5-bit first exponent value (X5-X1) 816 is not all zeros or all ones (e.g., X5-X1 is not 00000 or 11111), the execution circuitry may interpret the 10 bits (AJ) as a 10-bit explicit significand 817. This may correspond to a standard half-precision (FP16) floating point format. Typically, according to the standard floating point format, when the 5-bit first exponent value is all ones, this will specify infinity when the 7-bit significand is all zeros or NaN when the 7-bit significand is not all zeros. Conversely, in some embodiments, a 5-bit first exponent value of all ones may be used to invoke an extended range floating point format for overflow.

[0105] As shown for the extended exponent range floating point format 801, when the 5-bit first exponent value 818 is all ones (i.e., 11111), the execution circuitry may interpret the same corresponding 10 bits as including a 3-bit second exponent value (Y3-Y1) 819 in the three least significant bits of the 10 bits (e.g., corresponding in position to HIJ), and a 7-bit significand 820 in the seven most significant bits (AG). In this case, the 7-bit significand includes all of the more significant bits of the 10 bits that are not used for the 3-bit second exponent value (Y3-Y1). The 3-bit second exponent value and the 7-bit significand together include all of the bits of the 10-bit explicit significand. This 3-bit second exponent value is merely an example. Other embodiments may have fewer or more bits for the second exponent value. In some cases, because the significand 817 will be largely ignored for an all-ones first exponent value (except in some NaN implementations) when using the standard floating point format, it is contemplated that in some implementations it may be appropriate that the second exponent value may optionally have approximately the same number of bits as the N-bit first exponent field, thereby providing an effective extended range.

[0106] The lower portion of the figure illustrates how the execution circuit uses the 3-bit second exponent value and the 5-bit first exponent value to determine the extended range index for shifting, moving, or otherwise interpreting or identifying the position of the binary point relative to the significand including the 7-bit significand and the implicit most significant bit or J-bit of the significand. As shown, in some embodiments, the execution circuit can add or otherwise combine the 3-bit second exponent value 819 and the 5-bit first exponent value 818. This allows the extended range index to have an additional value or range based not only on the first exponent value 818 but also on the second exponent value 819. The table shows an example of how the 3-bit second exponent value (Y3-Y1) 819 can be summed to different extended range exponents when added to the 5-bit first exponent value "11111" 818. In this example, Y3Y2Y1 equal to "000" means adding the value one to the 5-bit first exponent value "11111" to obtain the extended range exponent value "100000", Y3Y2Y1 equal to "001" means adding the value two to the 5-bit first exponent value "11111" to obtain the extended range exponent value "100001", and so on. This is just one illustrative example of a possible mapping. Other mappings are also contemplated. For example, Y3Y2Y1 equal to "000" may mean infinity instead of "111", and Y3Y2Y1 equal to "001" may mean adding the value one to the 5-bit first exponent value "11111" to obtain the extended range exponent value "100000", and so on. The meaning of the mapping may be according to various conventions. A small adder or other arithmetic circuit may be incorporated to add or otherwise combine the second exponent value 819 with the first exponent value.

[0107] Infinity and NaN can still be supported for the extended range format, and infinity and NaN can actually be encoded as several different values, which can make it easier to modify the data path of an FP multiplier or ALU designed to handle the format. This can be done in different ways. In some embodiments, if the first exponent value (e.g., 5-bit first exponent value 818) is all ones, and the second exponent value (e.g., 3-bit second exponent value 819) is a certain value (e.g., all ones in one example), then no valid bits for the second exponent value (e.g., 7-bit valid number 820) with a certain first value (e.g., all zeros as one possible example) can represent infinity, otherwise no valid bits for the second exponent value (e.g., 7-bit valid number 820) with a certain second value (e.g., all ones as one possible example) can represent non-number (NaN).

[0108] In the multiplier, the exponent handling circuitry can be increased by 1 bit in width. For example, in the case of FP16 where the exponent has 5 bits, the exponent handling circuitry can have a width of 6 bits to handle the additional exponent range (e.g., first exponent value plus second exponent value). Additional checks for exceptions and errors can be performed on both the input and output sides. The impact on the ALU is similar, with a small adder that modifies the exponent and additional input and output checks.

[0109] If a number with this extended range format is input to a standard IEEE754 operator, the output result will not be affected, e.g., overflow conditions in the new format may simply be handled as infinity or NaN in the standard operators. When dealing with out-of-range numbers, or in the case where one number is out of range and the other is in range, the rounding behavior may not conform to IEEE754 conventions, but the number will have a small maximum error within the range of the mantissa that is still generally more accurate than a number encoded as infinity.

[0110] Fig. 9 is a table listing several examples of extended exponent ranges for the standard floating point format 900 and the overflow floating point format 901. For the standard floating point format, the first column lists the name of the format, the second column lists the number of explicit significand bits, and the third column lists the number of first exponent value bits. For the extended exponent range of the overflow floating point format, the fourth column lists the number of second exponent value bits, and the fifth column lists the overflow significand bits.

[0111] The first row lists a 64-bit double precision (FP64) floating point format with 52 explicit significand bits and 11 first exponent value bits, and a corresponding extended exponent range format with 1-11 (or optionally 3-11) second exponent value bits and 41-51 (or optionally 41-49) overflow significand bits. The second row lists a 32-bit single precision (FP32) floating point format with 23 explicit significand bits and 8 first exponent value bits, and a corresponding extended exponent range format with 1-8 (or optionally 3-8) second exponent value bits and 15-22 (or optionally 15-20) overflow significand bits. The third row lists a 16-bit half precision (FP16) floating point format with 10 explicit significand bits and 5 first exponent value bits, and a corresponding extended exponent range format with 1-5 (or optionally 2-5) second exponent value bits and 5-9 (or optionally 5-8) overflow significand bits.

[0112] The fourth row lists a 16-bit Bfloat16 floating point format with 7 explicit significands and 8 first exponent value bits, and a corresponding extended exponent range format with 1-6 (or optionally 2-6) second exponent value bits and 1-6 (or optionally 1-5) overflow significand bits. The fifth row lists an 8-bit FP8E5M2 floating point format with 2 explicit significands and 5 first exponent value bits, and a corresponding extended exponent range format with 1-2 second exponent value bits and 1-2 overflow significand bits. The sixth row lists an 8-bit FP8 E4M3 floating point format with 3 explicit significands and 4 first exponent value bits, and a corresponding extended exponent range format with 1-2 second exponent value bits and 1-2 overflow significand bits.

[0113] As described above, the ability to utilize M bits to include alternative meanings or interpretations of the second exponent value (e.g., rather than just the M-bit significand) can always be enabled (e.g., built into or incorporated into the circuit), or can be configurable so that it can be enabled or disabled. Moreover, the number of bits of at least one second exponent value, the number of bits of at least one significand, or both can be fixed / static (e.g., built into or incorporated into the circuit), or dynamically variable, flexible, or configurable. Moreover, different numbers of such bits can be optionally provided to extend the underflow range (e.g., when the N-bit first exponent value is all zeros) and extend the overflow range (e.g., when the N-bit first exponent value is all ones).

[0114] Fig.10 1 is a block diagram of an embodiment of a processor 1002 having one or more registers 1015 storing information associated with an extended floating point range. In some embodiments, the information may include an enable and / or disable control that is operable to enable and / or disable the use of an extended floating point range. This may represent different modes of operation, wherein a floating point data element is interpreted or not interpreted according to an extended floating point range format. In some embodiments, the information may include an indication of the number of bits used for a second exponent value to extend an underflow range (e.g., when an N-bit first exponent value is all zero). In some embodiments, the information may include an indication of the number of bits used for a second exponent value to extend an overflow range (e.g., when an N-bit first exponent value is all one). The number of bits used for a second exponent value may be indicated in different ways. One way is to directly indicate the number of bits used for a second exponent value. Another way is to indicate the number of bits used for a corresponding significand when the number of bits used for a second exponent value can be calculated as M bits minus the number of bits indicated for a corresponding significand (e.g., significand 220). If desired, the number of bits used for a second exponent value and the number of bits used for a corresponding significand may be optionally specified. This information may also optionally be stored differently for different types of floating point data elements (e.g., FP64, FP32, FP16, bfloat16, E5M2, E4M3, etc.).

[0115] Such information may be stored in bits or fields of register 1015. Examples of suitable registers include, but are not limited to, processor configuration and / or control registers (e.g., model specific registers), floating point configuration and / or control registers, special purpose registers, or any combination thereof. Generally, storing such information in processor configuration and / or control registers may allow the information to be configured on a multi-threaded, multi-core, or entire processor basis. Storing such information in floating point configuration and / or control registers may allow the information to be configured on a thread-by-thread basis. Examples of suitable floating point configuration and / or control registers include, but are not limited to The MCSCR in the architecture and the floating point control register (FPCR) in the Aarch64 of the ARM architecture. The floating point configuration and / or control registers may also optionally store other information for controlling floating point processing, such as rounding mode information, flush to zero information, denormal processing information, etc.

[0116] Fig.11 is a block diagram of an embodiment of a floating point instruction 1103 indicating information associated with extending the floating point range. Providing an enable / disable control and the number of bits used to extend the floating point range may allow such information to be provided on a per-instruction or instruction-level basis.

[0117] The instruction format includes an operation code or opcode 1137. The opcode may represent a plurality of bits or one or more fields operable to identify the instruction and / or the operation to be performed.

[0118] The instruction format includes: a first source specifier 1138, which is used to explicitly specify the register or memory address information of the first source floating-point operand; an optional second source specifier 1139, which is used to explicitly specify the register or memory address information of the second source floating-point operand; and a destination specifier 1140, which is used to explicitly specify the register or memory address information to be used as the destination for storing the result floating-point operand. Alternatively, one or more of these specifiers can be optionally implicit (for example, source / destination registers can be used and only one specifier is used to specify the source / destination registers).

[0119] In some embodiments, the instruction may have an optional prefix 1135. As shown, in some embodiments, the optional prefix may include an optional enable and / or disable control 1136, which is operable to enable and / or disable the use of the extended floating point range (e.g., an instruction with an opcode 1137 and prefix 1135 may enable the use of the extended floating point range, while an instruction with an opcode 1137 but without prefix 1135 may disable the use of the extended floating point range, or vice versa is also possible). Alternatively, in other embodiments, the enable and / or disable control 1136 may alternatively be part of the opcode 1137 (e.g., certain instructions with certain opcodes may use the extended floating point range, while other instructions with other opcodes may disable or at least not use the extended floating point range). In other embodiments, the enable and / or disable control 1136 may alternatively be specified elsewhere (e.g., in one or more registers as described above).

[0120] In some embodiments, the instruction may have one or more fields or bits (e.g., an immediate number) to provide an optional indication of the number of bits used for the second exponent value to extend the underflow range (e.g., when the N-bit first exponent value is all zeros). In some embodiments, the instruction may have one or more fields or bits (e.g., an immediate number) to provide an optional indication of the number of bits used for the second exponent value to extend the overflow range (e.g., when the N-bit first exponent value is all ones). As described above, the number of bits used for the second exponent value can be indicated in different ways. One way is to directly indicate the number of bits used for the second exponent value. Another way is to indicate the number of bits used for the corresponding significand when the number of bits used for the second exponent value can be calculated as M bits minus the number of bits indicated for the corresponding significand (e.g., significand 220). If necessary, both the number of bits used for the second exponent value and the number of bits used for the corresponding significand can be optionally specified.

[0121] The illustrated instruction format shows an example of a field type that may be included in an embodiment of a floating point instruction. Alternative embodiments may include a subset of the illustrated fields or may add additional fields. The order / arrangement of the illustrated fields is not necessary, but the fields may be rearranged. The fields do not need to include a continuous bit sequence, but may be composed of non-continuous or separated bits. In certain embodiments, the instruction format may use any other instruction format or encoding scheme further mentioned below.

[0122] Figure 10 to Figure 11 Several possible methods of providing information associated with extending the floating point range are illustrated.Other embodiments may provide such information by storing some information in one or more registers and providing other information via floating point instructions.

[0123] Fig.12An example embodiment of a method 1242 for processing floating point instructions executed by a processor is illustrated. By way of example, Figure 2 The method can be performed by a processor as shown in FIG. 21(B), a processor core as shown in FIG. 21(B), a pipeline as described in detail below, etc. Figure 2 The components, features and certain optional details described in the processor shown in FIG. 21(B), the processor core shown in FIG. 21(B), the pipeline described in detail below, etc. are also optionally applicable to the method. Alternatively, the method can be performed by and / or in a similar or different processor. Moreover, Figure 2 The processor shown may execute Fig.12 The method is the same, similar or different.

[0124] At 1243, an instance of a single floating-point instruction (e.g., floating-point instruction 203) is obtained. In some examples, the instruction is obtained from an instruction cache. The instruction may explicitly specify or otherwise indicate at least a first source floating-point operand. The first source floating-point operand may have at least a first floating-point data element. The first floating-point data element may have a sign bit, an N-bit first exponent value, and M additional bits. In some embodiments, the instruction may optionally specify or otherwise indicate an optional second source floating-point operand. The instruction may also specify or otherwise indicate a destination register in which the result floating-point operand is to be stored. These operands and the manner in which they are indicated may be similar to those described elsewhere herein (e.g., as previously described with respect to Figure 2 The operands and methods described are the same or similar.

[0125] At 1244, the fetched floating point instructions may be decoded. For example, the fetched floating point instructions may be decoded by a decoder circuit such as decoder circuit 204 or decode circuit 2140 described in detail herein.

[0126] At 1245, when the decoded instruction is scheduled, at least the first floating point data element and any other floating point data elements associated with the first source floating point operand and the optional second source floating point operand may be retrieved. For example, when one or more of the source operands are memory operands, data may be retrieved from the indicated memory location.

[0127] At 1246, the decoded instruction is executed by execution circuitry (hardware), such as Figure 2 21(B) or the execution cluster(s) 2160 shown. This may include executing operations corresponding to and / or in accordance with floating point instructions.

[0128] In some embodiments, the operations may include interpreting and / or processing and / or handling the M bits of the first floating point data element based at least in part on the N-bit first exponent value of the first floating point data element. In some embodiments, the operations may include interpreting and / or processing and / or handling the M bits of the first floating point data element as an M-bit significand when the N-bit first exponent value is not all zeros or all ones. For example, in some embodiments, this may include interpreting and / or processing and / or handling the M bits of the first floating point data element as an M-bit significand based on the N-bit first exponent value of the first floating point data element. Figure 1 The first floating point data element is interpreted and / or processed and / or handled using one of the standard floating point formats described herein.

[0129] In some embodiments, these operations may include interpreting and / or processing and / or handling the M bits as including at least one bit of the second exponent value in at least one of the M bits and at least one bit of the significand in at least another of the M bits when the N-bit first exponent value is all zeros or all ones. This may be as described elsewhere herein (e.g., for Figure 2 , Figures 4 to 6 , Figure 8 The at least one second exponent value may be used to shift the at least one exponent and / or identify the position of the binary point of the at least one exponent when the N-bit first exponent value is all zeros. As another example, when the N-bit first exponent value is all ones, the at least one second exponent value may be added to the N-bit first exponent value and / or otherwise combined with the N-bit first exponent value and / or otherwise used with the N-bit first exponent value to provide an additional exponent value or range to the first floating point data element. Other floating point data elements in the source operation may optionally be similarly interpreted and / or processed and / or disposed of.

[0130] The operation may also include: performing an operation specified by the instruction on at least the first source floating-point operand and, in some cases, an optional second source floating-point operand to generate a result floating-point operand. As described above, the operation may be performed depending on how the floating-point data elements are interpreted. The operation may be of a type previously described (e.g., scalar, vector, or matrix floating-point format conversion, scalar, vector, or matrix addition, scalar, vector, or matrix multiplication, etc.)

[0131] In some examples, the instruction is committed or retired at 1247. This may cause the resulting floating point operand to be stored in a destination register (eg, a renamed register that was committed to an architectural register).

[0132] Fig.13 An example embodiment of a method 1348 for processing floating point instructions using emulation or binary translation is illustrated. For example, Figure 2 The method can be performed by a processor as shown in FIG. 21(B), a processor core as shown in FIG. 21(B), a pipeline as described in detail below, etc. Figure 2The components, features and certain optional details described in the processor shown in FIG. 21(B), the processor core shown in FIG. 21(B), the pipeline described in detail below, etc. are also optionally applicable to the method. Alternatively, the method can be performed by and / or in a similar or different processor. Moreover, Figure 2 The processor can execute Fig.13 The method is the same, similar or different.

[0133] At 1349, an instance of a single floating-point instruction (e.g., floating-point instruction 203) of a first instruction set architecture is obtained. In some examples, the instruction is obtained from an instruction cache. The instruction may explicitly specify or otherwise indicate at least a first source floating-point operand. The first source floating-point operand may have at least a first floating-point data element. The first floating-point data element may have a sign bit, an N-bit first exponent value, and M additional bits. In some embodiments, the instruction may optionally specify or otherwise indicate an optional second source floating-point operand. The instruction may also specify or otherwise indicate a destination register in which the result floating-point operand is to be stored. These operands and the manner in which they are indicated may be similar to those described elsewhere herein (e.g., as previously described with respect to Figure 2 The operands and methods described are the same or similar.

[0134] At 1350, the obtained single floating point instruction of the first instruction set architecture is translated into one or more instructions of the second instruction set architecture. In some examples, the translation can be performed by a translation and / or emulation layer of the software. In some examples, the translation can be performed by a software such as Fig.30 The instruction converter 3012 is shown to perform. In some examples, the translation can be performed by hardware translation circuitry.

[0135] At 1351, one or more translated instructions of the second instruction set architecture are decoded. For example, the translated instructions may be decoded by a decoder circuit such as decoder circuit 204 or decode circuit 2140 described in detail herein. In some examples, the operations of translating 1350 and decoding 1351 may optionally be combined.

[0136] At 1352, when the decoded instruction is scheduled, at least the first floating point data element and any other floating point data elements associated with the first source floating point operand and the optional second source floating point operand may be retrieved. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0137] At 1353, by such Figure 3Execution circuits (hardware) such as the execution circuit 205 shown or the execution cluster (or clusters) 2160 shown in FIG. 21(B) execute (one or more) decoded instructions of the second instruction set architecture to perform (one or more) operations indicated by and / or corresponding to a single floating-point instruction of the first instruction set architecture.

[0138] In some embodiments, the operations may include interpreting and / or processing and / or handling the M bits of the first floating point data element based at least in part on the N-bit first exponent value of the first floating point data element. In some embodiments, the operations may include interpreting and / or processing and / or handling the M bits of the first floating point data element as an M-bit significand when the N-bit first exponent value is not all zeros or all ones. For example, in some embodiments, this may include interpreting and / or processing and / or handling the M bits of the first floating point data element as an M-bit significand based on the N-bit first exponent value of the first floating point data element. Figure 1 The first floating point data element is interpreted and / or processed and / or handled using one of the standard floating point formats described herein.

[0139] In some embodiments, these operations may include: when the N-bit first exponent value is all zeros or all ones, interpreting and / or processing and / or handling the M bits as including at least one bit of the second exponent value in at least one of the M bits and including at least one bit of the significand in at least another of the M bits. This may be as described elsewhere herein (e.g., for Figure 2 , Figures 4 to 6 , Figure 8 The at least one second exponent value may be used to shift the at least one exponent and / or identify the position of the binary point of the at least one exponent when the N-bit first exponent value is all zeros. As another example, when the N-bit first exponent value is all ones, the at least one second exponent value may be added to the N-bit first exponent value and / or otherwise combined with the N-bit first exponent value and / or otherwise used with the N-bit first exponent value to provide an additional exponent value or range to the first floating point data element. Other floating point data elements in the source operation may optionally be similarly interpreted and / or processed and / or disposed of.

[0140] The operation may also include: performing an operation specified by and / or corresponding to the single first floating-point instruction on at least the first source floating-point operand and, in some cases, also on an optional second source floating-point operand to generate a result floating-point operand. As described above, the operation may be performed depending on how the floating-point data elements are interpreted. The operation may be of a type previously described (e.g., scalar, vector, or matrix floating-point format conversion, scalar, vector, or matrix addition, scalar, vector, or matrix multiplication, etc.)

[0141] In some examples, the decoded instruction(s) of the second instruction set architecture are committed or retired at 1354. This may cause the resultant floating point operand to be stored in an architectural storage location for and / or corresponding to the destination register (e.g., a renamed register that was committed to an architectural register).

[0142] Fig.14 is a block diagram of an example embodiment of a processor 1402 having a floating point arithmetic unit 1405 for performing arithmetic operations on a first floating point data element 1407-1 and a second floating point data element 1407-2. In some embodiments, the processor may perform Fig.15 methods and / or FIG. 17A to FIG. 17B In some embodiments, the processor may include Fig.16 Floating point multipliers and / or Fig.18 Floating point adder.

[0143] The processor has a first storage location 1415-1 for storing a first floating-point data element. The processor has a second storage location 1415-2 for storing a second floating-point data element. Examples of suitable storage locations include, but are not limited to, registers (e.g., general or other scalar registers, and vector, packed or single instruction, multiple data (SIMD) registers), caches, scratchpads, and combinations thereof. Alternatively, one or more of the first floating-point data element and the second floating-point data element may optionally be stored external to the processor (e.g., in system memory).

[0144] The first floating point data element 1415-1 has a sign bit 1409-1, an N-bit first exponent value 1416 that is not all zeros or all ones, and M bits 1411-1 that are and / or represent an M-bit significand 1417. The second floating point data element 1407-2 has the same total number of bits as the first floating point data element. The second floating point data element has a sign bit 1409-2, an N-bit first exponent value 1418 that is all zeros, and M bits 1411-2 that include less than M bits of significand 1420 and a second exponent value 1419. In some embodiments, the second exponent value 1419 may have one or more characteristics as previously described for the second exponent value 219 and / or the 4-bit second exponent value 419 and / or the 3-bit second exponent value 519 and / or the 2-bit second exponent value 619. In some embodiments, the second exponent value 1419 and the significand 1420 may have characteristics for Figure 7 One of the sizes mentioned.

[0145] The floating point arithmetic unit 1405 is coupled to the first and second storage locations (e.g., to receive the first and second floating point data elements). In some embodiments, the floating point arithmetic unit may have the characteristics previously described with respect to the execution circuit 205. The floating point arithmetic unit is used to perform an arithmetic operation on the first floating point data element and the second floating point data element to generate a result floating point data element 1414. In some embodiments, the arithmetic operation is a multiplication. In other embodiments, the arithmetic operation is an addition. In some embodiments, performing the arithmetic operation may include: using the second exponent value 1419 to identify the position of the binary point relative to the significand 1420. In some embodiments, performing the arithmetic operation may include: using the second exponent value 1419 to represent the second floating point data element 1407-2 as a smaller value than the value that can be represented by the N-bit first exponent value 1418.

[0146] Fig.15 15 is a block flow diagram of an example embodiment of a method 1555 for multiplying first and second floating point data elements when at least one of the first and second floating point data elements utilizes a second exponent value (e.g., second exponent value 219 and / or 4-bit second exponent value 419 and / or 3-bit second exponent value 519 and / or 2-bit second exponent value 619). Fig.16 1 is a block diagram of an example embodiment of a floating point multiplier 1605 capable of multiplying first and second floating point data elements when at least one of the first and second floating point data elements utilizes a second exponent value (e.g., second exponent value 219 and / or 4-bit second exponent value 419 and / or 3-bit second exponent value 519 and / or 2-bit second exponent value 619). Fig.16 The floating point multiplier 1605 is described Fig.15 However, Fig.15 The method may alternatively be similar to or different from Fig.16 The floating-point multiplier is used to perform the operation. Fig.16 The floating-point multiplier can perform the same Fig.15 By way of example, method 1555 may be performed in response to and / or as part of the operation of an instruction having an opcode indicating that a floating-point multiplication is to be performed, and one or more instructions or control signals decoded from the instruction may be used to control floating-point multiplier 1605 to perform the method.

[0147] To assist in describing certain concepts, a first floating point data element (X1) may have a sign (S1), a mantissa (M1), a first exponent (E1), and in some cases, optionally a second exponent value (P1). For example, if E1 is not all zeros or all ones, the mantissa (M1) may be an m-bit significand 217, and for X1, the second exponent value (P1) may not exist, or if E1 is all zeros, the mantissa (M1) may be a significand 220, and the second exponent value (P1) may exist. Similarly, a second floating point data element (X2) may have a sign (S2), a mantissa (M2), a first exponent (E2), and in some cases, optionally a second exponent value (P2). For example, if E2 is not all zeros or all ones, the mantissa (M2) may be an m-bit significand 217, and for X2, the second exponent value (P2) may not exist, or if E2 is all zeros, the mantissa (M2) may be a significand 220, and the second exponent value (P2) may exist. The product floating point data element (X3) obtained by multiplying X1 and X2 may have a sign (S3), a mantissa (M3), a first exponent (E3), and optionally a second exponent value (P3) in some cases. For example, if E3 is not all zeros or all ones, the mantissa (M3) may be an m-bit significand 217, and the second exponent value (P3) may not exist for X3, or if E3 is all zeros, the mantissa (M3) may be a significand 220, and the second exponent value (P3) may exist.

[0148] At block 1556, a temporary (eg, subject to subsequent operations) index may be generated based on the first index (eg, E1 and E2) and / or the second index value (eg, P1 and / or P2). Fig.16 , the temporary index generation circuit 1678 can be coupled to receive the first exponent E1 of X1, the second exponent E2 of X2, the second exponent value P1 when used for X1 (e.g., when E1 is all zeros) via the first multiplexer 1673, and the second exponent value P2 when used for X2 (e.g., when E2 is all zeros) via the second multiplexer 1674. When the second exponent value is not used for one or more floating-point data elements, the multiplexer can be controlled to output a zero value. The temporary index generation circuit can be operated to generate the temporary index 1628 based on the first exponent (E1 and E2) and / or the second exponent value (P1 and P2).

[0149] Fig.15 Block 1556 includes several optional sub-operations. At block 1557, a sum of biased exponents (e.g., E1+E2) may be generated by adding the biased first exponent E1 of the first floating point data element X1 and the biased first exponent E2 of the second floating point data element X2. Fig.16, a first exponent adder 1671 may be coupled to receive a first exponent E1 of X1 and a second exponent E2 of X2, and may be operable to add E1 and E2 with a biased exponent and output a sum of the biased exponents (e.g., E1+E2) 1676. The first exponent adder may have a size suitable for adding the biased exponents (e.g., it may be based on a floating point format).

[0150] exist Fig.15 At block 1558 of , if only one floating point data element utilizes the second exponent value (e.g., has a corresponding first exponent of all zeros), the second exponent value may be identified, or if both the first and second floating point data elements utilize the second exponent value (e.g., have corresponding first exponents of all zeros), a sum of the second exponent values ​​of the first and second floating point data elements may be generated. For example, this may include identifying a second exponent P2 of X2 when E2 is zero and E1 is non-zero. As another example, this may include adding P1 and P2 to generate a sum of the second exponent values ​​(e.g., P1+P2) when both E1 and E2 are zero. Reference Fig.16 , the second exponent value adder 1672 may be coupled to receive the second exponent value (P1) when used for X1 (e.g., when E1 is all zero) via the first multiplexer 1673, and the second exponent value (P2) when used for X2 (e.g., when E2 is all zero) via the second multiplexer 1674. When a floating point number does not use the second exponent value, the multiplexer may be controlled to select and output a zero value. The second exponent value adder 1672 may add the second exponent value P1 (or zero when P1 is not used for X1) and the second exponent value P2 (or zero when P2 is not used for X2), and output a value 1677, which is one of the second exponent values ​​P1 or P2 or the sum of the second exponent values ​​(e.g., P1+P2). The second exponent value adder may have a size suitable for adding the second exponent values ​​(e.g., a 3-bit value, a 4-bit value, etc., as described above).

[0151] exist Fig.15 At block 1559 of , a first temporary index may be generated by subtracting the identified second exponent value (e.g., P1) or the sum of the second exponent values ​​(e.g., P1+P2) from the sum of the biased first exponents (e.g., E1+E2). In this embodiment, the subtraction is performed because the second exponent value(s) is used to extend the underflow range provided by the first exponent(s) (e.g., as for Figures 4 to 7 In another embodiment, if the second exponent value(s) is used to extend the overflow range provided by the first exponent(s) (e.g., as for Figures 8 to 9 As described above), then addition can be performed. Fig.16, an adder 1679 can be coupled to receive the sum of the biased first exponent 1676 and the output 1677 , can be operated to perform a subtraction, and can output a first temporary exponent 1680 .

[0152] exist Fig.15 At block 1560 of , a second temporary index may be generated by subtracting an exponent bias value from the first temporary exponent. The exponent bias value is subtracted from the first temporary exponent because the first temporary exponent is based on the sum of biased exponents, which effectively adds the exponent bias value twice, and therefore one of the two exponent bias values ​​should be subtracted in order to achieve the appropriate bias value. The exponent bias value may be defined or specified according to the relevant floating-point standard for the floating-point data elements X1 and X2 (e.g., 127 for single precision (FP32), 1023 for double precision (FP64), etc.). By way of example, the second temporary exponent may be represented as (E1+E2-P1-P2-exponent bias value) or (E1+E2-P1-exponent bias value) or (E1+E2-P2-exponent bias value). Reference Fig.16 , the adder 1682 may be coupled to receive the first temporary exponent 1680 and the exponent bias value 1681 , may be operable to subtract the exponent bias value from the first temporary exponent, and may be operable to output the second temporary exponent 1629 .

[0153] exist Fig.15 At block 1561 of , a product of the mantissa of the first floating point data element and the mantissa of the second floating point data element may be generated. The multiplied mantissa may include explicit mantissa bits and hidden bits or J bits (e.g., the product of the mantissas may be (1.M1*1.M2). As is typical for multiplication, the product of the mantissas may have more bits (e.g., approximately but less than twice, depending on the number of mantissa bits cut out for the extended exponent) than the individual mantissas (including their respective hidden bits or J bits). Reference Fig.16 , a mantissa multiplier 1675 may be coupled to receive the mantissa M1 of X1 and the mantissa M2 of X2. The mantissa multiplier may be operable to multiply the mantissas and output a product of the mantissas 1684. The mantissa multiplier may have a size suitable for multiplying the mantissas (e.g., a 53b×53b multiplier for double precision, a 24b×24b multiplier for single precision, a 11b×11b multiplier for half precision, an 8b×8b multiplier for BFLOAT16, etc.).

[0154] exist Fig.15At block 1562 of , the product of the mantissas may be normalized as needed by shifting the binary / radix point of the product of the mantissas and adjusting the second temporary exponent (e.g., generated at block 1560) to account for the shift of the binary / radix point to generate a third temporary exponent. The product of the mantissas may be considered normalized when there is a single bit to the left of the radix / binary point and the single bit is set to a value of binary one. For example, a normalized floating point number may have the form of 1.0011, 1.1111, 1.1011, while a non-normalized floating point number may have a form such as 100.11, 11.111, 1101.1. The product of the normalized mantissas may include shifting the radix / binary by at least one bit position relative to the actual bit value and adjusting the second temporary exponent to account for the shift / repositioning of the radix / binary point. Each time the radix / binary point is shifted one bit position to the left, the second temporary exponent may be incremented or increased by one. Conversely, each time the base / binary point is shifted one bit position to the right, the second temporary exponent can be decremented or reduced by one. For example, the number 100.11 can be normalized to 1.0011x2^2 by shifting the binary point two positions to the left and increasing the second temporary exponent by two. Fig.16 , a normalization circuit 1683 may be coupled to receive the product of the mantissas 1684 and the second temporary exponent 1629. The normalization circuit may be operable to normalize the product of the mantissas and output a normalized product of the mantissas 1686. The normalization circuit may also be operable to adjust the second temporary exponent accordingly and output a third temporary exponent 1685. By way of example, the normalization circuit may use a shift circuit, a multiplexer, or other circuit to normalize the product of the mantissas, and may use an increment / decrement circuit or an adder to adjust the second temporary exponent.

[0155] exist Fig.15 At block 1563 of , it may be determined whether there are any exceptional conditions. If it is determined that an exceptional condition exists, the method may proceed to block 1564. At block 1564, in some embodiments, the exponent of the product floating point number may be adjusted to indicate the exceptional condition. Alternatively, in other embodiments, an exception may be optionally raised or otherwise signaled without indicating the exceptional condition in the exponent of the product floating point number. By way of example, after the exception is raised or signaled, the software may take over by processing the floating point number. Reference Fig.16, an abnormal condition detection circuit 1690 may be coupled to receive the third temporary index 1685. The abnormal condition detection circuit is operable to detect an abnormal condition. In some embodiments, the abnormal condition detection circuit is operable to raise or signal an exception 1690 without adjusting the third temporary index. In other embodiments, the abnormal condition detection circuit is operable to adjust the third temporary index to generate and output a first exponent E3 of the product floating-point data element X3, and in some cases optionally generate and output a second exponent value P3 of X3.

[0156] To further illustrate certain concepts, an example manner of adjusting the exponent of a product floating point number based on a detected abnormal condition will now be described, but the scope of the present invention is not limited thereto. Some of these operations may also be optionally performed in a different order.

[0157] If overflow occurs, the running exponent may be saturated. For example, if the running exponent value is greater than the maximum exponent representable for the floating point format, the first exponent value may be set to the maximum number (eg, all ones indicating infinity).

[0158] A check may be made to see if the running exponent is zero or negative. If the running exponent is zero or negative, the first exponent value may be set to zero (e.g., to indicate that the second exponent value is to be used), and the second exponent value may be calculated. If the running exponent is negative, this means that the second exponent value is to be used for the extended range. By way of example, the second exponent value may be calculated by calculating the 2's complement of the running exponent and adding one. The second exponent value is the amount of underflow plus one, which may be determined by taking the 2's complement of the running exponent and adding one.

[0159] The second exponent value may be checked to see if it overflows (e.g., if it exceeds the maximum shift it is allowed to specify). Figure 4 In an embodiment, if the second index value specifies a shift of more than eleven bits, the second index value may be set to one of the values ​​1011-1111 or 0000 to indicate a maximum shift of eleven bits.

[0160] Reference again Fig.15, at block 1565, if necessary, the product of the mantissas can be truncated to an appropriate number of digits and rounded. The product of the mantissas can have more digits than each of the mantissas including its hidden digit or J digit (e.g., according to the number cut out for (one or more) extended exponents, at most but less than twice). The more meaningless termination digits of the product of the mantissas can be truncated to the number of explicit significant digits of the floating point format (e.g., 52 for double precision, 23 for single precision, 10 for half precision, 7 for BFLOAT16, etc.). Rounding can also be performed as needed. Different rounding methods are known in the art, such as rounding to the nearest even number, rounding away from zero, rounding to positive infinity upwards, rounding to negative infinity downwards, rounding to zero, etc.

[0161] At block 1566, it may be determined whether the product of the mantissas is still normalized. In some cases (e.g., for some numbers), rounding may result in the product of the rounded mantissas no longer being normalized. If it is determined that the product of the mantissas is not normalized, the method may return to block 1562 and continue. Alternatively, if it is determined that the product of the mantissas is still normalized, the method may proceed to block 1567. Fig.16 , rounding circuit 1688 may be coupled to receive the product of normalized mantissas 1686. The rounding circuit may be operable to truncate and round the product of normalized mantissas. The rounding circuit may be operable to determine whether the product of the truncated and rounded mantissas is still normalized. If not, the unnormalized product of the truncated and rounded mantissas may be returned to the normalization circuit along return 1689. Otherwise, the rounding circuit may output the mantissa (M3) of the product floating point data element X3.

[0162] exist Fig.15 At block 1567, the sign of the product floating point number may be calculated. Each of the original floating point numbers has a sign bit as its most significant bit (MSB). Since floating point numbers are interpreted as (-1) raised to the power of the sign bit, the sign bit may be a binary one to indicate that the floating point number is positive, or may be a binary zero to indicate that the floating point number is negative. The sign bits of the two original floating point numbers may be used to determine the sign of the product floating point number. The sign of the product floating point number will be positive when the sign bits of the original floating point numbers are the same sign (e.g., both are positive or both are negative), or negative when the sign bits of the original floating point numbers are different (e.g., one is positive and the other is negative). Reference Fig.16 , the sign calculation circuit 1670 may be coupled to receive the sign S1 of X1 and the sign S2 of X2, and may be operated to determine and output the sign S3 of the product floating point data element. By way of example, the sign calculation circuit may include an exclusive OR (XOR) circuit (e.g., an exclusive OR gate).

[0163] exist Fig.15At block 1568 of , the product floating point data element X3 may be output. This may include outputting a sign S3, a first exponent E3, a mantissa M3, and optionally, in some cases, a second exponent value P3.

[0164] FIG. 17A to FIG. 17B 17 is a block flow diagram of an example embodiment of a method 1791 for adding first and second floating-point data elements when at least one of the first and second floating-point data elements utilizes a second exponent value (e.g., second exponent value 219 and / or 4-bit second exponent value 419 and / or 3-bit second exponent value 519 and / or 2-bit second exponent value 619). Fig.18 1 is a block diagram of an example embodiment of a floating point adder 1805 capable of adding first and second floating point data elements when at least one of the first and second floating point data elements utilizes a second exponent value (e.g., second exponent value 219 and / or 4-bit second exponent value 419 and / or 3-bit second exponent value 519 and / or 2-bit second exponent value 619). Fig.18 The floating-point adder is described by FIG. 17A to FIG. 17B However, FIG. 17A to FIG. 17B The method may alternatively be similar to or different from Fig.18 The floating point adder is used to perform the operation. Fig.18 The floating-point adder can perform the same FIG. 17A to FIG. 17B By way of example, method 1791 may be executed in response to and / or as part of an operation of an instruction having an opcode indicating that a floating-point addition is to be performed, and one or more instructions or control signals decoded from the instruction may be used to control floating-point adder 1805 to perform method 1791.

[0165] To assist in describing certain concepts, a first floating point data element (X1) may have a sign (S1), a mantissa (M1), a first exponent (E1), and in some cases, optionally a second exponent value (P1). For example, if E1 is not all zeros or all ones, the mantissa (M1) may be an m-bit significand 217, and for X1, the second exponent value (P1) may not exist, or if E1 is all zeros, the mantissa (M1) may be a significand 220, and the second exponent value (P1) may exist. Similarly, a second floating point data element (X2) may have a sign (S2), a mantissa (M2), a first exponent (E2), and in some cases, optionally a second exponent value (P2). For example, if E2 is not all zeros or all ones, the mantissa (M2) may be an m-bit significand 217, and for X2, the second exponent value (P2) may not exist, or if E2 is all zeros, the mantissa (M2) may be a significand 220, and the second exponent value (P2) may exist. The sum floating point data element (X3) obtained by multiplying X1 and X2 may have a sign (S3), a mantissa (M3), a first exponent (E3), and optionally a second exponent value (P3) in some cases. For example, if E3 is not all zeros or all ones, the mantissa (M3) may be an m-bit significand 217, and the second exponent value (P3) may not exist for X3, or if E3 is all zeros, the mantissa (M3) may be a significand 220, and the second exponent value (P3) may exist.

[0166] At block 1792, a base exponent and a right shift amount to be used to implement the addition may be determined based on the first exponent and / or second exponent values ​​of the first and second floating point data elements. Fig.18 , base exponent and right shift amount determination circuit 1811 may be coupled to receive a first exponent (E1) for X1, a first exponent (E2) for X2, a second exponent value (P1) when used for X1 (e.g., when E1 is all zeros), and a second exponent value (P2) when used for X2 (e.g., when E2 is all zeros). When P1 and / or P2 are not used, their bits may be used instead for mantissas M1 and / or M2, respectively. Circuit 1811 may be operable to determine and output a base exponent 1821 and a right shift amount 1815, and in some cases determine and output a second exponent value 1820.

[0167] Fig.17ABox 1792 of includes several optional sub-operations. At box 1793, it can be determined whether both first indices are non-zero (e.g., both E1 and E2 are non-zero). If both first indices are non-zero (e.g., determined as "yes"), the method can proceed to box 1794. At box 1794, a base index can be selected as the larger exponent of the first indices (e.g., the larger exponent of E1 and E2), and the right shift amount can be determined as the difference between the first indices (e.g., E1-E2, if E1 is the larger exponent). Alternatively, if at least one of the first indices is not non-zero (e.g., determined as "no" at box 1793), the method can proceed to box 1795. By way of example, Fig.18 The circuit 1811 may include a comparison circuit, a selection circuit (eg, a multiplexer), and a subtraction circuit (eg, an adder) that perform these operations.

[0168] At block 1795, it may be determined whether both first exponents are zero (e.g., both E1 and E2 are zero). If both first exponents are zero (e.g., a "yes" determination), the method may proceed to block 1796. At block 1796, it may be determined that the base exponent is zero, and the right shift amount may be determined as the absolute value of the difference between the second exponent values ​​(e.g., P1-P2, if P1 is the larger of the second exponent values). If the smaller second exponent value is subtracted from the larger second exponent value, then the absolute value need not be taken. By way of example, Fig.18 The circuit 1811 may include a comparison circuit, a selection circuit (eg, a multiplexer), and a subtraction circuit (eg, an adder) that perform these operations.

[0169] Alternatively, if the two first indices are not both zero (e.g., a "no" determination is made at block 1795), which in the method means that one of the first indices (e.g., E1) is non-zero and the other (e.g., E2) is zero, the method may proceed to block 1797. At block 1797, the base index may be determined to be the non-zero first index, and the right shift amount may be determined to be the sum of the non-zero first index of one of the floating-point data elements and the second index value of the other floating-point data element. By way of example, Fig.18 The circuit 1811 may include a comparison circuit, a selection circuit (eg, a multiplexer), and an addition circuit (eg, an adder) that perform these operations.

[0170] Based on the determinations made at blocks 1793, 1795, the method will proceed to block 1798 via one of blocks 1794, 1796, and 1797. At block 1798, the mantissa of the floating point data element with the smaller exponent may be right shifted relative to the radix / binary point by the determined right shift amount. In some embodiments, if the right shift value is greater than the precision of the mantissa of the floating point data element with the smaller exponent, the second exponent value may be set to its maximum value (e.g., for Figure 4 , if the shift is more than eleven bits, it can be set to one of 1011-1111, 0000), the shift amount can optionally be set to zero (e.g., as an optional optimization, since there is no point in shifting the mantissa if all bits of the mantissa will eventually be shifted out), and the sticky bit can be set to binary one if the mantissa is non-zero.

[0171] refer to Fig.18 , a mantissa shift circuit 1814 may be coupled to receive the mantissa M1 of X1, the mantissa M2 of X2, and the determined right shift amount 1815. The mantissa shift circuit may be operable to right shift the mantissa of the floating point data element with the smaller exponent by the right shift amount relative to the radix / binary point. The mantissa shift circuit may output a right-shifted mantissa 1816 (e.g., right-shifted M1) and other mantissas (e.g., M2) 1817.

[0172] exist Fig.17A At block 1799 of , a sum of the mantissa M1 of the first floating point data element X1 and the mantissa M2 of the second floating point data element X2 may be generated. The added mantissa may include explicit mantissa bits and a hidden bit or J bit (eg, 1.M1+1.M2). Fig.18 , an adder 1819 may be coupled to receive a right-shifted mantissa 1816 (e.g., right-shifted M1) and other mantissas (e.g., M2) 1817, and the adder 1819 may be operable to add the right-shifted mantissa and other mantissas and output a sum of the mantissas 1822. The adder may have a size suitable for adding the mantissas.

[0173] exist Fig.17A At block 1705, the sum of the mantissas may be normalized as needed by shifting the binary / radix point of the sum of the mantissas and adjusting the temporary first exponent E3 of X3 (e.g., the base exponent initially determined at block 1792) and / or the temporary second exponent value P3 of X3 to account for the shift in the binary / radix point. Fig.18, a normalization circuit 1823 may be coupled to receive a sum of mantissas 1822, a base exponent 1821, and, in some cases, optionally a second exponent value 1820. The normalization circuit may be operable to normalize the sum of mantissas and output a normalized sum of mantissas 1826. The normalization circuit may also be operable to adjust a temporary first exponent E3 (e.g., initially a base exponent) and / or a temporary second exponent value P3 to account for a shift in the binary / radix point. By way of example, the normalization circuit may use a shift circuit, a multiplexer, or other circuit to shift the sum of mantissas, and may use an increment / decrement circuit or an adder to adjust E3 and / or P3.

[0174] Fig.17A The square block 1705 includes several optional sub-operations. At the square block 1701, the base / binary point of the sum of the mantissas can be shifted until the sum of the mantissas is normalized. When there is a single bit on the left side of the base / binary point and the single bit is set to the value of binary one, the sum of the mantissas can be normalized. For example, the normalized floating point number can have the form of 1.0011, 1.1111, 1.1011, while the non-normalized floating point number can have the form of 100.11, 11.111, 1101.1 and the like.

[0175] At block 1702, a temporary first exponent E3 (e.g., the initially determined base exponent) may be adjusted to account for the shift of the binary / radix point (e.g., the base exponent is equal to the base exponent minus the left shift). If the mantissa is left-shifted, this is equivalent to multiplying it by a power of two, so the exponent needs to be reduced to ensure that the number remains the same, which can be achieved by subtracting the left shift from the base exponent. For example, each time the radix / binary point is shifted one bit position to the left, the temporary first exponent E3 may be incremented or increased by one. Conversely, each time the radix / binary point is shifted one bit position to the right, the temporary first exponent E3 may be decremented or decreased by one.

[0176] At block 1703, it may be determined whether the temporary first index E3 (e.g., the initially determined base index) is less than zero. If the temporary first index E3 is less than zero (e.g., determined as "yes"), the method may proceed to block 1704. At block 1704, the temporary first index E3 (e.g., the initially determined base index) may be reset to zero, and the underflow caused by the shift may be reflected in the temporary second index value P3. For example, the temporary second index value P3 may be set equal to the negative of the temporary first index E3 plus one. By way of example, this may be accomplished with an adder. The method may proceed from block 1704 to block 1706. Alternatively, if the temporary first index E3 is not less than zero (e.g., determined as "no" at block 1703), the method may proceed to block 1706.

[0177] exist Fig. 17B At block 1706 of , it may be determined whether there are any abnormal conditions. If it is determined that an abnormal condition exists (e.g., a determination of "yes"), the method may proceed to block 1707. At block 1707, in some embodiments, the temporary first exponent E3 and / or the second exponent value P3 of the floating point number may be adjusted to indicate an abnormal condition. For example, in some embodiments, if the second exponent value P3 indicates an underflow amount greater than its maximum underflow amount, the second exponent value P3 may be set to its maximum underflow amount. For example, in Figure 5 In an embodiment of the present invention, if the 3-bit second exponent value 519 is negative nine (-9), then Y3Y2Y1 may be set to 000 to indicate an exponent of -8. Alternatively, in other embodiments, an exception may be optionally raised or otherwise signaled without adjusting E3 and / or P3. For example, as previously described, this may be handled in software.

[0178] refer to Fig.18 , an abnormal condition detection circuit 1827 may be coupled to receive a temporary first exponent E3 1824 and, in some cases, optionally receive a second exponent value P3 1825. The abnormal condition detection circuit is operable to detect an abnormal condition. In some embodiments, the abnormal condition detection circuit is operable to raise or signal an exception 1890 without adjusting E3 and / or P3. In other embodiments, the abnormal condition detection circuit is operable to adjust and output E3 or P3 and the floating point data element X3.

[0179] Reference again Fig. 17B , at block 1708, if necessary, the sum of the mantissas may be truncated to an appropriate number of digits and rounded. Any less meaningful termination digits of the sum of the mantissas may be truncated to the number of explicit significant digits of the floating point format (e.g., fifty-two for double precision, twenty-three for single precision, ten for half precision, seven for BFLOAT16, etc.). Rounding may be performed as needed. Different rounding methods are known in the art, such as rounding to the nearest even number, rounding away from zero, rounding upward to positive infinity, rounding downward to negative infinity, rounding to zero, etc.

[0180] At block 1709, it may be determined whether the sum of the mantissas is still normalized. In some cases (e.g., for some numbers), rounding may result in the sum of the rounded mantissas no longer being normalized. If it is determined that the sum of the mantissas is not normalized (e.g., a "no" determination), the method may return to block 1701 and continue. Alternatively, if it is determined that the sum of the mantissas is still normalized (e.g., a "yes" determination at block 1709), the method may proceed to block 1710. Fig.18, rounding circuit 1828 may be coupled to receive the normalized sum of mantissas 1826. The rounding circuit may be operable to truncate and round the sum of the normalized mantissas. The rounding circuit may be operable to determine whether the sum of the truncated and rounded mantissas is still normalized. If not, the unnormalized sum of the truncated and rounded mantissas may be returned to the normalization circuit along return 1829. Otherwise, the mantissa (M3) of the sum floating point data element may be output.

[0181] At block 1710, the floating point data element X3 may be output (eg, stored in a register). This may include outputting S3, E3, M3, and optionally P3 in some cases.

[0182] Example computer architecture.

[0183] The following describes in detail an example computer architecture. Other system designs and configurations known in the art for laptop, desktop and handheld personal computers (PCs), personal digital assistants, engineering workstations, servers, decomposed servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, various systems or electronic devices that can incorporate processors and / or other execution logic disclosed herein are generally suitable.

[0184] Fig.19 An example computing system is illustrated. Multiprocessor system 1900 is an interface system and includes multiple processors or cores, including a first processor 1970 and a second processor 1980 coupled via an interface 1950 such as a point-to-point (PP) interconnect, structure and / or bus. In some examples, the first processor 1970 and the second processor 1980 are isomorphic. In some examples, the first processor 1970 and the second processor 1980 are heterogeneous. Although example system 1900 is shown as having two processors, the system can have three or more processors, or can be a single processor system. In some examples, the computing system is a system on chip (SoC).

[0185] Processors 1970 and 1980 are shown to include integrated memory controller (IMC) circuits 1972 and 1982, respectively. Processor 1970 also includes interface circuits 1976 and 1978; similarly, second processor 1980 includes interface circuits 1986 and 1988. Processors 1970, 1980 may exchange information via interface 1950 using interface circuits 1978, 1988. IMCs 1972 and 1982 couple processors 1970, 1980 to respective memories, namely memory 1932 and memory 1934, which may be portions of main memory locally attached to the respective processors.

[0186] Processors 1970, 1980 can each use interface circuits 1976, 1994, 1986, 1998 to exchange information with a network interface (NW I / F) 1990 via separate interfaces 1952, 1954. Network interface 1990 (e.g., one or more of an interconnect, bus, and / or fabric, and in some examples a chipset) can optionally exchange information with a coprocessor 1938 via interface circuit 1992. In some examples, coprocessor 1938 is a special-purpose processor, such as a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general-purpose graphics processing unit (GPGPU), a neural network processing unit (NPU), an embedded processor, etc.

[0187] A shared cache (not shown) may be included in either processor 1970, 1980 or external to both processors but connected to the processors via an interface such as a PP interconnect so that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0188] The network interface 1990 may be coupled to the first interface 1916 via the interface circuit 1996. In some examples, the first interface 1916 may be an interface such as a peripheral component interconnect (PCI), a PCI Express interconnect, or another I / O interconnect. In some examples, the first interface 1916 is coupled to a power control unit (PCU) 1917, which may include circuits, software, and / or firmware that perform power management operations with respect to the processors 1970, 1980, and / or the coprocessor 1938. The PCU 1917 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. The PCU 1917 also provides control information that controls the generated operating voltage. In various examples, the PCU 1917 may include various power management logic units (circuits) that perform hardware-based power management. Such power management may be fully processor-controlled (e.g., through various processor hardware, and it may be triggered by workload and / or power, thermal, or other processor constraints) and / or power management may be performed in response to an external source (such as a platform or power management source or system software).

[0189] PCU 1917 is illustrated as existing as logic separate from processor 1970 and / or processor 1980. In other cases, PCU 1917 may execute on a given one or more of the cores (not shown) of processors 1970 or 1980. In some cases, PCU 1917 may be implemented as a microcontroller (dedicated or general purpose) or other control logic that is configured to execute its own dedicated power management code, sometimes referred to as P-code. In other examples, the power management operations to be performed by PCU 1917 may be implemented external to the processor, such as by a separate power management integrated circuit (PMIC) or another component external to the processor. In other examples, the power management operations to be performed by PCU 1917 may be implemented in BIOS or other system software.

[0190] Various I / O devices 1914 may be coupled to the first interface 1916 along with a bus bridge 1918 coupling the first interface 1916 to the second interface 1920. In some examples, one or more additional processors 1915 such as a coprocessor, a high throughput integrated many core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor are coupled to the first interface 1916. In some examples, the second interface 1920 may be a low pin count (LPC) interface. Various devices may be coupled to the second interface 1920, including, for example, a keyboard and / or mouse 1922, a communication device 1927, and a storage circuit 1928. The storage circuit 1928 may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device, which may include instructions / codes and data 1930 and may implement a storage device in some examples. Further, an audio I / O 1924 may be coupled to the second interface 1920. It should be noted that other architectures besides the point-to-point architecture described above are also possible. For example, instead of a point-to-point architecture, a system such as multiprocessor system 1900 may implement a multi-point interface or other such architecture.

[0191] Example core architectures, processors, and computer architectures.

[0192] Processor cores may be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a special-purpose core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special-purpose cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or as dedicated cores); and 4) a system on a chip (SoC), which may be included on the same die as the CPU (sometimes referred to as application core(s) or application processor(s), the coprocessors described above, and additional functionality. An example core architecture is described next, followed by a description of an example processor and computer architecture.

[0193] Fig. 20 A block diagram of an example processor and / or SoC 2000 that may have one or more cores and an integrated memory controller is illustrated. The solid lined box illustrates a processor 2000 having a single core 2002(A), a system agent unit circuit 2010, and a set of one or more interface controller unit circuits 2016, while the optional addition of the dashed lined box illustrates an alternative processor 2000 having multiple cores 2002(A)-(N), a set of one or more integrated memory controller unit circuits 2014 and dedicated logic 2008 in the system agent unit circuit 2010, and a set of one or more interface controller unit circuits 2016. It should be noted that the processor 2000 may be one of the processors 1970 or 1980, or may be one of the processors 1970 or 1980. Fig.19 Coprocessor 1938 or 1915.

[0194] Thus, different implementations of processor 2000 may include: 1) a CPU having: dedicated logic 2008, which is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown); and cores 2002 (A)-(N), which are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of both); 2) a coprocessor having cores 2002 (A)-(N), which are a large number of dedicated cores primarily intended for graphics and / or scientific (throughput); and 3) a coprocessor having cores 2002 (A)-(N), which are a large number of general purpose in-order cores. Thus, processor 2000 may be a general purpose processor, a coprocessor, or a dedicated processor, such as a network or communications processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 2000 may be part of and / or implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0195] The memory hierarchy includes one or more levels of cache unit circuits 2004(A)-(N) within the cores 2002(A)-(N), a set of one or more shared cache unit circuits 2006, and external memory (not shown) coupled to the set of (one or more) integrated memory controller unit circuits 2014. The set of one or more shared cache unit circuits 2006 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache (such as last level cache (LLC)), and / or combinations thereof. While in some examples, the interface network circuit 2012 (e.g., a ring interconnect) interfaces with the dedicated logic 2008 (e.g., integrated graphics logic), the set of (one or more) shared cache unit circuits 2006, and the system agent unit circuit 2010, alternative examples use any number of well-known techniques to interface with such units. In some examples, coherency is maintained between the (one or more) shared cache unit circuits 2006 and one or more of the cores 2002(A)-(N). In some examples, interface controller unit circuit 2016 couples core 2002 to one or more other devices 2018, such as one or more I / O devices, storage devices, one or more communication devices (e.g., wireless networking, wired networking, etc.), and the like.

[0196] In some examples, one or more of the cores 2002(A)-(N) are capable of multithreading. System agent unit circuitry 2010 includes those components that coordinate and operate the cores 2002(A)-(N). System agent unit circuitry 2010 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be or may include logic and components required to regulate the power state of the cores 2002(A)-(N) and / or the dedicated logic 2008 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0197] The cores 2002(A)-(N) may be homogeneous in terms of instruction set architecture (ISA). Alternatively, the cores 2002(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores 2002(A)-(N) may be capable of executing an ISA, while other cores may be capable of executing only a subset of that ISA or another ISA.

[0198] Example core architectures - in-order and out-of-order core block diagrams.

[0199] FIG. 21(A) is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example. FIG. 21(B) is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example. The solid-line boxes in FIG. 21(A) to FIG. 21(B) illustrate the in-order pipeline and the in-order core, while the optional addition of the dashed-line boxes illustrates the register renaming, out-of-order issue / execution pipeline and the core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0200] In FIG. 21(A), the processor pipeline 2100 includes an acquisition stage 2102, an optional length decoding stage 2104, a decoding stage 2106, an optional allocation (Alloc) stage 2108, an optional renaming stage 2110, a scheduling (also called dispatch or issue) stage 2112, an optional register read / memory read stage 2114, an execution stage 2116, a write-back / memory write stage 2118, an optional exception handling stage 2122, and an optional submission stage 2124. One or more operations may be performed in each of these processor pipeline stages. For example, during the acquisition stage 2102, one or more instructions are acquired from the instruction memory, and during the decoding stage 2106, one or more acquired instructions may be decoded, an address using a forwarded register port (e.g., a load storage unit (LSU) address) may be generated, and branch forwarding (e.g., an immediate offset or a link register (LR)) may be performed. In one example, the decoding stage 2106 and the register read / memory read stage 2114 may be combined into one pipeline stage. In one example, during the execute stage 2116, decoded instructions may be executed, LSU address / data pipelining to an advanced microcontroller bus (AMB) interface may be performed, multiplication and addition operations may be performed, arithmetic operations with branch results may be performed, and the like.

[0201] By way of example, the example register renaming, out-of-order issue / execution architecture core of FIG. 21(B) may implement pipeline 2100 as follows: 1) instruction fetch circuit 2138 performs fetch and length decoding stages 2102 and 2104; 2) decoding circuit 2140 performs decoding stage 2106; 3) renaming / allocator unit circuit 2152 performs allocation stage 2108 and renaming stage 2110; 4) (one or more) scheduler circuit 2156 performs scheduling stage 2112; 5) (one or more) physical registers 2114 and 2115 are implemented as pipelines 2100; 6) instruction fetch circuit 2138 performs fetch and length decoding stages 2102 and 2104; 7) decoding circuit 2140 performs decoding stage 2106; 8) renaming / allocator unit circuit 2152 performs allocation stage 2108 and renaming stage 2110; 9) (one or more) scheduler circuit 2156 performs scheduling stage 2112; 10) (one or more) physical registers 2114 and 2115 are implemented as pipelines 2100; 11) instruction fetch circuit 2138 performs fetch and length decoding stages 2102 and 2104; 12) decoding circuit 2140 performs decoding stage 2106; 13) renaming / allocator unit circuit 2152 performs allocation stage 2108 and renaming stage 2110; 14) (one or more) scheduler circuit 2156 performs scheduling stage 2112; 15) (one or more) physical registers 2114 and 2115 are implemented as pipelines 2100; 16) instruction fetch circuit 2138 performs fetch and length decoding stages 2102 and 210 The register stack circuit 2158 and the memory unit circuit 2170 perform a register read / memory read stage 2114; (one or more) execution clusters 2160 execute stage 2116; 6) the memory unit circuit 2170 and (one or more) physical register stack circuits 2158 perform a write back / memory write stage 2118; 7) various circuits may be involved in the exception handling stage 2122; and 8) the retirement unit circuit 2154 and (one or more) physical register stack circuits 2158 perform a commit stage 2124.

[0202] 21(B) shows a processor core 2190, which includes a front end unit circuit 2130 coupled to an execution engine unit circuit 2150, and both are coupled to a memory unit circuit 2170. The core 2190 can be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 2190 can be a dedicated core, such as a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0203] The front end unit circuit 2130 may include a branch prediction circuit 2132 coupled to an instruction cache circuit 2134, which is coupled to an instruction translation lookaside buffer (TLB) 2136, which is coupled to an instruction fetch circuit 2138, which is coupled to a decoding circuit 2140. In one example, the instruction cache circuit 2134 is included in the memory unit circuit 2170 instead of the front end circuit 2130. The decoding circuit 2140 (or decoder) can decode the instruction and generate one or more micro-operations, microcode entry points, microinstructions, other instructions or other control signals as output, which are decoded from the original instruction or otherwise reflect the original instruction or are derived from the original instruction. The decoding circuit 2140 may also include an address generation unit (AGU, not shown) circuit. In one example, the AGU generates an LSU address using a forwarded register port, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decoding circuit 2140 may be implemented using various mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. In one example, core 2190 includes a microcode ROM (not shown) or other medium storing microcode for certain macroinstructions (e.g., in decode circuitry 2140 or otherwise within front-end circuitry 2130). In one example, decode circuitry 2140 includes a micro-op or operation cache (not shown) to hold / cache decode operations, micro-tags, or micro-ops generated during decode or other stages of processor pipeline 2100. Decode circuitry 2140 may be coupled to rename / allocator unit circuitry 2152 in execution engine circuitry 2150.

[0204] The execution engine circuitry 2150 includes a rename / allocator unit circuitry 2152 coupled to a retirement unit circuitry 2154 and a set of one or more scheduler circuits 2156. The scheduler circuitry 2156 represents any number of different schedulers, including reservation stations, a central instruction window, and the like. In some examples, the scheduler circuitry 2156 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an address generation unit (AGU) scheduler / scheduling circuit, an AGU queue, and the like. The scheduler circuitry 2156 is coupled to a physical register file(s) circuitry 2158. Each of the physical register file(s) circuitry 2158 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one example, the (one or more) physical register file circuits 2158 include vector register unit circuits, write mask register unit circuits, and scalar register unit circuits. These register units can provide architectural vector registers, vector mask registers, general registers, etc. The (one or more) physical register file circuits 2158 are coupled to the retirement unit circuits 2154 (also called retirement queues) to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using (one or more) reorder buffers (ROBs) and (one or more) retirement register files; using (one or more) future stacks, (one or more) history buffers, and (one or more) retirement register files; using register maps and register pools, etc.). The retirement unit circuits 2154 and the (one or more) physical register file circuits 2158 are coupled to (one or more) execution clusters 2160. The (one or more) execution clusters 2160 include a set of one or more execution unit circuits 2162 and a set of one or more memory access circuits 2164. The execution unit circuit(s) 2162 may perform various arithmetic, logical, floating point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) on various types of data (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some examples may include multiple execution units or execution unit circuits dedicated to a particular function or set of functions, other examples may include only one execution unit circuit or multiple execution units / execution unit circuits that all perform all functions.The scheduler circuit(s) 2156, physical register file(s) circuit(s) 2158, and execution cluster(s) 2160 are shown as possibly multiple because certain examples create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or memory access pipeline, each with its own scheduler circuit(s), physical register file(s) circuit(s), and / or execution cluster—and in the case of a separate memory access pipeline, certain examples are implemented where only the execution cluster for that pipeline has the memory access unit circuit(s) 2164). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, while the rest are in-order.

[0205] In some examples, execution engine unit circuit 2150 may perform load store unit (LSU) address / data pipelining, as well as address stage and write back, data stage load, store, and branch to an advanced microcontroller bus (AMB) interface (not shown).

[0206] The set of memory access circuits 2164 is coupled to the memory cell circuit 2170, which includes a data TLB circuit 2172 coupled to a data cache circuit 2174, which is coupled to a level 2 (L2) cache circuit 2176. In one example, the memory access circuit 2164 may include a load unit circuit, a store address unit circuit, and a store data unit circuit, each of which is coupled to the data TLB circuit 2172 in the memory cell circuit 2170. The instruction cache circuit 2134 is also coupled to the level 2 (L2) cache circuit 2176 in the memory cell circuit 2170. In one example, the instruction cache 2134 and the data cache 2174 are combined into a single instruction and data cache (not shown) in the L2 cache circuit 2176, the level 3 (L3) cache circuit (not shown), and / or the main memory. The L2 cache circuit 2176 is coupled to one or more other levels of cache and ultimately to the main memory.

[0207] Core 2190 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions that have been added to newer versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, core 2190 includes logic to support packed data instruction set architecture extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0208] Example execution unit circuit(s).

[0209] Fig. 22 An example of (one or more) execution unit circuits such as (one or more) execution unit circuits 2162 of FIG. 21 (B) is illustrated. As illustrated, (one or more) execution unit circuits 2162 may include one or more ALU circuits 2201, optional vector / single instruction multiple data (SIMD) circuits 2203, load / store circuits 2205, branch / jump circuits 2207, and / or floating point unit (FPU) circuits 2209. ALU circuits 2201 perform integer operations and / or Boolean operations. Vector / SIMD circuits 2203 perform vector / SIMD operations on packed data (such as SIMD / vector registers). Load / store circuits 2205 execute load and store instructions to load data from memory into registers or store data from registers to memory. Load / store circuits 2205 may also generate addresses. Branch / jump circuits 2207 cause branches or jumps to memory addresses according to instructions. FPU circuits 2209 perform floating point operations. The width of the execution unit circuit(s) 2162 varies according to the example and may range from, for example, 16 bits to 1024 bits. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0210] Example register architecture.

[0211] Fig.23 2300 is a block diagram of a register architecture 2300 according to some examples. As illustrated, the register architecture 2300 includes a vector / SIMD register 2310 that varies from a 128-bit width to a 1024-bit width. In some examples, the vector / SIMD register 2310 is physically 512 bits, and according to the mapping, only some lower bits are used. For example, in some examples, the vector / SIMD register 2310 is a 512-bit ZMM register: the lower 256 bits are used for the YMM register, and the lower 128 bits are used for the XMM register. It can be seen that there is an overlay of registers. In some examples, the vector length field is selected between the maximum length and one or more other shorter lengths, wherein each such shorter length is half of the previous length. Scalar operations are operations performed on the lowest bit data element position in the ZMM / YMM / XMM register; according to the example, the higher bit data element positions are either the same as they were before the instruction, or are reset to zero.

[0212] In some examples, the register architecture 2300 includes a write mask / predicate register 2315. For example, in some examples, there are 8 write mask / predicate registers (sometimes referred to as k0 to k7), each of which is 16 bits, 32 bits, 64 bits, or 128 bits in size. The write mask / predicate register 2315 may allow merging (e.g., allowing any set of elements in the destination to be protected from update during the execution of any operation) and / or zeroing (e.g., zeroing the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given write mask / predicate register 2315 corresponds to a data element position in the destination. In other examples, the write mask / predicate register 2315 is scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits per 64-bit vector element).

[0213] The register architecture 2300 includes a plurality of general registers 2325. These registers may be 16-bit, 32-bit, 64-bit, etc., and may be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 to R15.

[0214] In some examples, the register architecture 2300 includes a scalar floating point (FP) register file 2345, which is used to perform scalar floating point operations on 32 / 64 / 80-bit floating point data using the x87 instruction set architecture extension, or used as an MMX register to perform operations on 64-bit packed integer data, and to hold operands for some operations performed between MMX and XMM registers.

[0215] One or more flag registers 2340 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operations. For example, one or more flag registers 2340 can store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, one or more flag registers 2340 are referred to as program status and control registers.

[0216] Segment registers 2320 contain segment points for accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

[0217] Machine Specific Registers (MSRs) 2335 control and report processor performance. Most MSRs 2335 handle system-related functions and are not accessible to applications. Machine Check Registers 2360 include control, status, and error reporting MSRs used to detect and report hardware errors.

[0218] One or more instruction pointer registers 2330 store instruction pointer values. Control register(s) 2355 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processor 1970, 1980, 1938, 1915, and / or 2000) and the characteristics of the currently executing task. Debug registers 2350 control and allow monitoring of debug operations of the processor or core.

[0219] Memory (mem) management registers 2365 specify the location of data structures used in protected mode memory management. These registers may include the global descriptor table register (GDTR), the interrupt descriptor table register (IDTR), the task register, and the local descriptor table register (LDTR).

[0220] Alternative examples may use wider or narrower registers. In addition, alternative examples may use more, fewer, or different register files and registers. The register architecture 2300 may be used, for example, in a register file / memory or (one or more) physical register file circuits 2158.

[0221] Instruction set architecture.

[0222] Instruction set architecture (ISA) can include one or more instruction formats. A given instruction format can define various fields (e.g., the number of bits, the position of bits) to specify the operation to be performed (e.g., opcode) and the (one or more) operands and / or (one or more) other data fields (e.g., mask) etc. to be performed on it. Some instruction formats are further decomposed by the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format can be defined as having different subsets of the fields of the instruction format (the included fields are usually in the same order, but at least some fields have different bit positions because fewer fields are included) and / or defined as having given fields interpreted differently. Thus, each instruction of the ISA is expressed using a given instruction format (and if defined, in a given one of the instruction templates of the instruction format), and includes fields for specifying operations and operands. For example, the example ADD instruction has a specific opcode and instruction format, the instruction format includes an opcode field that specifies the opcode and an operand field that selects operands (source 1 / destination and source 2); and the occurrence of this ADD instruction in the instruction stream will have specific content in the operand field that selects the specific operand. In addition, although the following description is made in the context of the x86 ISA, it is within the knowledge of those skilled in the art to apply the teachings of the present disclosure in another ISA.

[0223] Example instruction format.

[0224] The examples of (one or more) instructions described herein may be implemented in different formats. In addition, example systems, architectures, and pipelines are described in detail below. The examples of (one or more) instructions may be executed on such systems, architectures, and pipelines, but are not limited to those described in detail.

[0225] Fig.24 An example of an instruction format is illustrated. As illustrated, an instruction may include multiple components, including, but not limited to, one or more fields for: one or more prefixes 2401, an opcode 2403, addressing information 2405 (e.g., a register identifier, memory addressing information, etc.), a displacement value 2407, and / or an immediate value 2409. It should be noted that some instructions utilize some or all of the fields of the format, while other instructions may only use the opcode 2403 field. In some examples, the illustrated order is the order in which these fields are to be encoded, however, it should be understood that in other examples, these fields may be encoded in a different order, combined, etc.

[0226] (One or more) prefix fields 2401 modify instructions when used. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), to provide partial coverage (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), perform bus lock operations, and / or change operands (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes can be considered "traditional" prefixes. Other prefixes (one or more examples of which are described in detail herein) indicate and / or provide further capabilities, such as specifying specific registers, etc. Other prefixes generally follow the "traditional" prefix.

[0227] The opcode field 2403 is used to at least partially define the operation to be performed when decoding the instruction. In some examples, the length of the primary opcode encoded in the opcode field 2403 is one, two or three bytes. In other examples, the primary opcode can be a different length. Sometimes an additional 3-bit opcode field is encoded in another field.

[0228] The addressing information field 2405 is used to address one or more operands of the instruction, such as a location in memory or one or more registers. Fig.25An example of an addressing information field 2405 is illustrated. In this illustration, an optional MOD R / M byte 2502 and an optional scale, index, base (SIB) byte 2504 are shown. The MOD R / M byte 2502 and SIB byte 2504 are used to encode up to two operands of the instruction, each operand being a direct register or an effective memory address. It should be noted that both fields are optional, as not all instructions include one or more of these fields. The MOD R / M byte 2502 includes a MOD field 2542, a register (reg) field 2544, and an R / M field 2546.

[0229] The content of MOD field 2542 distinguishes between memory access and non-memory access modes. In some examples, when MOD field 2542 has a binary value of 11 (11b), register direct addressing mode is used, otherwise register indirect addressing mode is used.

[0230] Register field 2544 may encode a destination register operand or a source register operand, or may encode an opcode extension and is not used to encode any instruction operand. The contents of register field 2544 specify the location (in a register or in memory) of the source or destination operand directly or through address generation. In some examples, register field 2544 is supplemented with additional bits from a prefix (e.g., prefix 2401) to allow for greater addressing.

[0231] R / M field 2546 may be used to encode an instruction operand that references a memory address, or may be used to encode a destination register operand or a source register operand. Note that in some examples, R / M field 2546 may be combined with MOD field 2542 to indicate an addressing mode.

[0232] SIB byte 2504 includes a scaling field 2552, an index field 2554, and a base address field 2556 used in the generation of the address. Scaling field 2552 indicates a scaling factor. Index field 2554 specifies the index register to be used. In some examples, index field 2554 is supplemented with additional bits from a prefix (e.g., prefix 2401) to allow for larger addressing. Base address field 2556 specifies the base address register to be used. In some examples, base address field 2556 is supplemented with additional bits from a prefix (e.g., prefix 2401) to allow for larger addressing. In practice, the contents of scaling field 2552 allow the contents of index field 2554 to be scaled for memory address generation (e.g., for use with 2 缩放 * address generation of index + base address).

[0233] Some addressing forms use displacement values ​​to generate memory addresses. For example, 缩放The memory address may be generated by using a *index+base+displacement, index*scale+displacement, r / m+displacement, instruction pointer (RIP / EIP)+displacement, register+displacement, etc. The displacement may be a value of 1 byte, 2 bytes, 4 bytes, etc. In some examples, the displacement field 2407 provides the value. Additionally, in some examples, the displacement factor is encoded in the MOD field of the addressing information field 2405, which indicates a compressed displacement scheme for which the displacement value is calculated and stored in the displacement field 2407.

[0234] In some examples, the immediate value field 2409 specifies the immediate value of the instruction. The immediate value may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, etc.

[0235] Fig.26 An example of a first prefix 2401(A) is illustrated. In some examples, the first prefix 2401(A) is an example of a REX prefix. Instructions using this prefix can specify general registers, 64-bit packed data registers (e.g., single instruction multiple data (SIMD) registers or vector registers), and / or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

[0236] Instructions using the first prefix 2401(A) can specify up to three registers using 3-bit fields depending on the format: 1) using the register field 2544 and the R / M field 2546 of the MOD R / M byte 2502; 2) using the MODR / M byte 2502 with the SIB byte 2504, including using the register field 2544 as well as the base address field 2556 and the index field 2554; or 3) using the register field of the opcode.

[0237] In the first prefix 2401 (A), bit positions 7:4 are set to 0100. Bit position 3 (W) can be used to determine the operand size, but can determine more than just the operand width. It can be seen that when W=0, the operand size is determined by the code segment descriptor (CSD), and when W=1, the operand size is 64 bits.

[0238] It should be noted that the addition of another bit allows 16 (24) registers to be addressed, whereas MOD R / M register field 2544 and MOD R / MR / M field 2546 alone can each address only 8 registers.

[0239] In the first prefix 2401(A), bit position 2 (R) may be an extension of the MOD R / M register field 2544 and may be used to modify the MOD R / M register field 2544 when the field encodes a general register, a 64-bit packed data register (e.g., an SSE register), or a control or debug register. When the MOD R / M byte 2502 specifies other registers or defines an extended opcode, R is ignored.

[0240] Bit position 1 (X) may modify the SIB byte index field 2554 .

[0241] Bit position 0 (B) may modify the base address in the MOD R / MR / M field 2546 or the SIB byte base address field 2556; or it may modify the opcode register field used to access a general register (eg, general register 2325).

[0242] 27(A) to 27(D) illustrate examples of how the R, X, and B fields of the first prefix 2401(A) are used. FIG27(A) illustrates the use of R and B from the first prefix 2401(A) to extend the register field 2544 and R / M field 2546 of the MOD R / M byte 2502 when the SIB byte 2504 is not used for memory addressing. FIG27(B) illustrates the use of R and B from the first prefix 2401(A) to extend the register field 2544 and R / M field 2546 of the MOD R / M byte 2502 when the SIB byte 2504 is not used (register-register addressing). 27(C) illustrates that the register field 2544 of the MOD R / M byte 2502 and the index field 2554 and base field 2556 are extended using R, X, and B from the first prefix 2401(A) when the SIB byte 2504 is used for memory addressing. FIG27(D) illustrates that the register field 2544 of the MOD R / M byte 2502 is extended using B from the first prefix 2401(A) when the register is encoded in the opcode 2403.

[0243] Figures 28(A) to 28(B) illustrate examples of second prefix 2401(B). In some examples, second prefix 2401(B) is an example of a VEX prefix. Second prefix 2401(B) encoding allows instructions to have more than two operands, and allows SIMD vector registers (e.g., vector / SIMD registers 2310) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of second prefix 2401(B) provides a three-operand (or more) syntax. For example, the previous two-operand instruction performs an operation such as A=A+B, which overwrites the source operand. The use of second prefix 2401(B) enables operands to perform non-destructive operations such as A=B+C.

[0244] In some examples, the second prefix 2401(B) appears in two forms - a two-byte form and a three-byte form. The two-byte second prefix 2401(B) is primarily used for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 2401(B) provides a compact replacement for the first prefix 2401(A) with 3-byte opcode instructions.

[0245] Figure 28 (A) illustrates an example of a two-byte form of the second prefix 2401 (B). In one example, the format field 2801 (byte 0 2803) contains the value C5H. In one example, byte 1 2805 includes an "R" value in position [7]. This value is the complement of the "R" value of the first prefix 2401 (A). Position [2] is used to indicate the length (L) of the vector (wherein value 0 is a scalar or 128-bit vector and value 1 is a 256-bit vector). Position [1:0] provides an opcode extension equivalent to some traditional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode a first source register operand specified in reverse (1's complement) form and valid for instructions with 2 or more source operands; 2) encode a destination register operand specified in 1's complement form for certain vector shifts; or 3) encode no operand, the field is reserved and should contain some value, such as 1111b.

[0246] Instructions using this prefix may use the MOD R / MR / M field 2546 to encode an instruction operand that references a memory address or to encode a destination register operand or a source register operand.

[0247] Instructions using this prefix may use the MOD R / M register field 2544 to encode a destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand.

[0248] For instruction syntax supporting four operands, vvvv, MOD R / MR / M field 2546, and MOD R / M register field 2544 encode three of the four operands. Bits [7:4] of immediate value field 2409 are then used to encode the third source register operand.

[0249] Figure 28 (B) illustrates an example of a three-byte form of the second prefix 2401 (B). In one example, the format field 2811 (byte 0 2813) contains the value C4H. Byte one 2815 includes "R", "X" and "B" in position [7:5], which are the complements of the same value of the first prefix 2401 (A). The position [4:0] of byte 1 2815 (shown as mmmm) includes the content of one or more implicit leading operation code bytes encoded as needed. For example, 00001 means 0FH leading operation code, 00010 means 0F38H leading operation code, 00011 means 0F3AH leading operation code, etc.

[0250] Bit [7] of byte 2 2817 is used similarly to W of the first prefix 2401 (A), including helping to determine the size of operands that can be promoted. Bit [2] is used to indicate the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector and a value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensions that are equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode a first source register operand that is specified in reverse (inverse) form and is valid for instructions with 2 or more source operands; 2) encode a destination register operand that is specified in inverse form for certain vector shifts; or 3) do not encode any operands, this field is reserved and should contain a value, such as 1111b.

[0251] Instructions using this prefix may use the MOD R / MR / M field 2546 to encode an instruction operand that references a memory address or to encode a destination register operand or a source register operand.

[0252] Instructions using this prefix may use the MOD R / M register field 2544 to encode a destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand.

[0253] For instruction syntax supporting four operands, vvvv, MOD R / MR / M field 2546, and MOD R / M register field 2544 encode three of the four operands. Bits [7:4] of immediate value field 2409 are then used to encode the third source register operand.

[0254] Fig.29 An example of a third prefix 2401(C) is illustrated. In some examples, the third prefix 2401(C) is an example of an EVEX prefix. The third prefix 2401(C) is a four-byte prefix.

[0255] The third prefix 2401(C) may encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some examples, write masks / operation masks are used (see, for example, Fig.23 The prefix is ​​used by instructions that are not intended to be used for conditional processing or selection control (e.g., the discussion of registers in the previous figures of FIG. 2401 ) or predicted by the operator. The operator mask register allows conditional processing or selection control. The second prefix 2401 (B) is used to encode an operator mask instruction whose source / destination operand is an operator mask register and the contents of the operator mask register are treated as a single value.

[0256] The third prefix 2401(C) may encode functionality specific to the instruction class (e.g., a packed instruction with "load+operation" semantics may support an embedded broadcast functionality, a floating-point instruction with rounding semantics may support a static rounding functionality, a floating-point instruction with non-rounding arithmetic semantics may support a "suppress all exceptions" functionality, etc.).

[0257] The first byte of the third prefix 2401 (C) is the format field 2911, which in one example has a value of 62H. The subsequent bytes are referred to as payload bytes 2915-2919 and together form a 24-bit value P[23:0], which provides specific capabilities in the form of one or more fields (described in detail herein).

[0258] In some examples, P[1:0] of payload byte 2919 is the same as the lower two mm bits. In some examples, P[3:2] is reserved. Bit P[4] (R') allows access to the upper 16 vector register groups when combined with P[7] and MOD R / M register field 2544. When SIB type addressing is not required, P[6] can also provide access to the upper sixteen vector registers. P[7:5] includes R, X, and B, which are operand specifier modifier bits for vector registers, general registers, and memory addressing, and when combined with MOD R / M register field 2544 and MOD R / MR / M field 2546, allows access to the next group of 8 registers outside the lower 8 registers. P[9:8] provides an opcode extension equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). In some examples, P

[10] is a fixed value of 1. P[14:11], shown as vvvv, can be used to: 1) encode a first source register operand specified in reverse (inverse) form and valid for instructions with 2 or more source operands; 2) encode a destination register operand specified in inverse form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain some value, such as 1111b.

[0259] P

[15] is similar to W of the first prefix 2401 (A) and the second prefix 2411 (B), and can be used as an opcode extension bit or operand size promotion.

[0260] P[18:16] specifies the index of a register in an operation mask (write mask) register (e.g., write mask / predicate register 2315). In one example, a particular value aaa=000 has special behavior that implies that no operation mask is used for the instruction (this can be implemented in various ways, including using an operation mask that is hardwired to all operation masks or hardware that bypasses the masking hardware). When merged, the vector mask allows any set of elements in the destination to be protected from being updated during the execution of any operation (specified by the base operation and the augmentation operation); in another example, the old values ​​of the respective elements of the destination are retained when the corresponding mask bits have a 0. Conversely, when the vector mask is zeroed, it allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one example, when the corresponding mask bits have a 0 value, the elements of the destination are set to 0. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element modified); however, the modified elements do not have to be consecutive. Thus, the operation mask field enables partial vector operations, including loads, stores, arithmetic, logical, etc. Although examples are described in which the contents of the operation mask field select one of a plurality of operation mask registers containing an operation mask to be used (and whereby the contents of the operation mask field indirectly identify the masking to be performed), alternative examples instead or additionally allow the contents of the mask write field to directly specify the masking to be performed.

[0261] P

[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax that can use P

[19] to access the upper 16 vector registers. P

[20] encodes multiple features that are different across different instruction classes and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge write masking (e.g., when set to 0) or support for zeroing and merge write masking (e.g., when set to 1).

[0262] An example of using the third prefix 2401 (C) to encode a register in an instruction is described in detail in the following table.

[0263]

[0264]

[0265] Table 1: 32-register support in 64-bit mode

[0266]

[0267] Table 2: Encoded register specifiers in 32-bit mode

[0268]

[0269] Table 3: Operation Mask Register Specifier Encoding

[0270] Program code can be applied to input information to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.

[0271] The program code can be implemented in a high-level program or object-oriented programming language to communicate with the processing system. If necessary, the program code can also be implemented in assembly or machine language. In fact, the mechanism described herein is not limited to any specific programming language in scope. In any case, the language can be a compiled or interpreted language.

[0272] Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementation methods. Examples may be implemented as a computer program or program code executed on a programmable system, the programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0273] One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium, which represent various logic within a processor, and when read by a machine, the representative instructions cause the machine to fabricate logic to perform the techniques described herein. Such representations, referred to as "intelligent property (IP) cores," may be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to be loaded into a manufacturing machine that fabricates the logic or processor.

[0274] Such machine-readable storage media may include, but are not limited to, a non-transitory tangible arrangement of an article manufactured or formed by a machine or device, including storage media such as a hard disk, any other type of disk, including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM), such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions.

[0275] Therefore, examples also include non-transitory tangible machine-readable media containing instructions or containing design data, such as hardware description language (HDL), which defines the structures, circuits, devices, processors and / or system features described herein. Such examples may also be referred to as program products.

[0276] Simulation (including binary translation, code deformation, etc.).

[0277] In some cases, the instruction converter can be used to convert instructions from a source instruction set architecture to a target instruction set architecture. For example, the instruction converter can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), deform, simulate or otherwise convert instructions to one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware or a combination thereof. The instruction converter can be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0278] Fig.30 1 is a block diagram illustrating the use of a software instruction converter according to an example to convert binary instructions in a source ISA into binary instructions in a target ISA. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Fig.30 It is shown that a program in a high-level language 3002 can be compiled using a first ISA compiler 3004 to generate first ISA binary code 3006 that can be natively executed by a processor having at least one first ISA core 3016. The processor having at least one first ISA core 3016 represents any processor that can execute programs with the processor having at least one first ISA core in the following manner: Processor substantially the same functionality: compatibly execute or otherwise process (1) a substantial portion of the first ISA or (2) an object code version of an application or other software targeted to run on an Intel processor having at least one first ISA core so as to achieve substantially the same results as a processor having at least one first ISA core. First ISA compiler 3004 represents a compiler operable to generate first ISA binary code 3006 (e.g., object code) that can be executed on a processor having at least one first ISA core 3016 with or without additional link processing. Similarly, Fig.30 It is shown that a program of a high-level language 3002 can be compiled using an alternative ISA compiler 3008 to generate an alternative ISA binary code 3010 that can be natively executed by a processor without a first ISA core 3014. An instruction converter 3012 is used to convert the first ISA binary code 3006 into a code that can be natively executed by a processor without a first ISA core 3014. The converted code does not have to be the same as the ISA binary code 3010 replaced; however, the converted code will complete general operations and consist of instructions from the replacement ISA. Thus, the instruction converter 3012 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first ISA processor or core to execute the first ISA binary code 3006 by simulation, emulation, or any other process.

[0279] against Figure 1 , Figure 3 and Figures 4 to 11 Any of the components, features and details described in may also be optionally applied to Figure 2 , Fig.12 and Fig.13 Any of the processors disclosed herein (e.g., processor 202) may optionally be applied to any method disclosed herein (e.g., method 1342, method 1348), and in an embodiment, these components, features, and details may optionally be performed by and / or using such a processor. Any processor described in an embodiment herein (e.g., processor 202) may optionally be included in any system disclosed herein (e.g., Figure 19 to Figure 20 In some embodiments, any instruction disclosed herein may optionally have the instruction format shown herein (e.g., for Fig.11 or Figure 24 to Figure 29 any features or details of the format described.

[0280] References to "one example," "an example," etc. indicate that the example being described may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure, or characteristic. Moreover, these phrases do not necessarily refer to the same example. Further, when a particular feature, structure, or characteristic is described in conjunction with an example, it is considered to be within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other examples, whether or not explicitly described.

[0281] Processor components disclosed herein may be considered and / or claimed to operate, be operable, be capable of, be configured to be adapted to, or otherwise perform operations. For example, a decoder may be considered and / or claimed to decode instructions, an execution unit may be considered and / or claimed to store results, and so on. As used herein, these expressions relate to characteristics, properties, or attributes of components when they are in a powered-off state, and do not imply that the components or the equipment or devices including them are currently powered on or operated. For the sake of clarity, it should be understood that the processors and devices claimed herein are not required to be powered on or operated.

[0282] In the specification and claims, the terms "coupled" and / or "connected" and their derivatives may be used. These terms are not intended to be synonymous with each other. On the contrary, in an embodiment, "connected" may be used to indicate that two or more elements are in direct physical and / or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical and / or electrical contact with each other. However, "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other. For example, an execution unit may be coupled to a register and / or a decoding unit through one or more intermediate components. In the figure, arrows are used to illustrate connections and couplings.

[0283] Some embodiments include an article (e.g., a computer program product) that includes a machine-readable medium. The medium may include a mechanism for providing (e.g., storing) information in a machine-readable form. The machine-readable medium may provide or have stored thereon instructions or sequences of instructions that, if and / or when executed by a machine, are operable to cause the machine to perform and / or result in the machine performing one or more operations, methods, or techniques disclosed herein.

[0284] In some embodiments, the machine-readable medium may include a tangible and / or non-transient machine-readable storage medium. For example, the non-transient machine-readable storage medium may include a floppy disk, an optical storage medium, an optical disc, an optical data storage device, a CD-ROM, a magnetic disk, a magneto-optical disk, a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a random access memory (RAM), a static RAM (SRAM), a dynamic RAM (DRAM), a flash memory, a phase change memory, a phase change data storage material, a non-volatile memory, a non-volatile data storage device, a non-transient memory, a non-transient data storage device, etc. The non-transient machine-readable storage medium is not composed of a transient propagation signal. In some embodiments, the storage medium may include a tangible medium, which includes a solid-state substance or material, such as a semiconductor material, a phase change material, a magnetic solid material, a solid-state data storage material, etc. Alternatively, a non-tangible transient computer-readable transmission medium may be optionally used, such as an electrical, optical, acoustic or other form of propagation signal - such as a carrier wave, an infrared signal, and a digital signal.

[0285] Examples of suitable machines include, but are not limited to, general purpose processors, special purpose processors, digital logic circuits, integrated circuits, etc. Other examples of suitable machines include computer systems or other electronic devices that include processors, digital logic circuits, or integrated circuits. Examples of such computer systems or electronic devices include, but are not limited to, desktop computers, laptop computers, notebook computers, tablet computers, netbooks, smart phones, cellular phones, servers, network devices (e.g., routers and switches), mobile Internet devices (MIDs), media players, smart televisions, nettops, set-top boxes, and video game controllers.

[0286] Moreover, in the various examples above, unless specifically noted otherwise, disjunctive language such as the phrases "at least one of A, B, or C" or "A, B and / or C" are intended to be understood to mean A, B, or C or any combination thereof (i.e., A and B, A and C, B and C, and A, B, and C).

[0287] In the above description, specific details are set forth to provide a thorough understanding of the embodiments. However, other embodiments may be practiced without some of these specific details. Various modifications and changes may be made to the embodiments without departing from the broader spirit and scope of the present disclosure as set forth in the claims. Therefore, the description and the accompanying drawings should be considered illustrative rather than restrictive. The scope of the present invention is not determined by the specific examples provided above, but only by the claims below. In other cases, well-known circuits, structures, devices, and operations are shown in block diagram form and / or without detail to avoid obscuring the understanding of this specification.

[0288] Example Embodiments

[0289] The following examples relate to further embodiments. In one or more embodiments, the details in the examples may be used anywhere.

[0290] Example 1 is a device including a decoder circuit that decodes an instruction. The instruction indicates at least a source floating-point operand and a destination register. The source floating-point operand has at least a floating-point data element. The floating-point data element has a sign bit, an N-bit first exponent value, and an M-bit. The device also includes an execution circuit coupled to the decoder circuit. The execution circuit performs an operation corresponding to the instruction. The operation includes interpreting the M bits as an M-bit valid number when the N-bit first exponent value is not all zero or all one. The operation includes: when the N-bit first exponent value is all zero or all one, interpreting the M bits as including a second exponent value in at least one of the M bits, and including less than an M-bit valid number in at least another of the M bits. The operation includes performing an operation specified by the instruction on at least the source floating-point operand to generate a result floating-point operand. The operation includes storing the result floating-point operand in a destination register.

[0291] Example 2 includes the apparatus of Example 1, optionally wherein the second exponent value comprises a plurality of least significant bits of M bits, and optionally wherein the less than M bits of the significand comprises a plurality of bits that are more significant than the plurality of least significant bits.

[0292] Example 3 includes the apparatus of Example 2, optionally wherein the second exponent value and the less than M-bit significand together comprise M bits.

[0293] Example 4 includes the apparatus of any of Examples 1 to 3, wherein when the N-bit first exponent value is all zeros, the execution circuit uses the second exponent value to identify a position of a binary point relative to the less than M-bit significand.

[0294] Example 5 includes the apparatus of any of Examples 1 to 4, wherein the second exponent value has sufficient bits to be able to encode any one of at least M different values.

[0295] Example 6 includes the apparatus of any of Examples 1 to 5, wherein the execution circuitry sets the sticky bit equal to an implicit most significant significand bit of the floating point data element when the second exponent value has a given value.

[0296] Example 7 includes the apparatus of any one of Examples 1 to 6, wherein one of the following is true: (1) the floating-point data element is a 64-bit floating-point data element, the N-bit first exponent value is an 11-bit value, the M-bit significand is a 52-bit significand, the second exponent value includes two to six of the M bits, and the less than M-bit significand includes forty-six to fifty of the M bits; (2) the floating-point data element is a 32-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 23-bit significand, the second exponent value includes two to five of the M bits, and the less than M-bit significand includes forty-six to fifty of the M bits. The M-bit significand includes eighteen to twenty-one of the M bits; (3) the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes two to four of the M bits, and the less-than-M-bit significand includes six to eight of the M bits; and (4) the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 7-bit significand, the second exponent value includes two to four of the M bits, and the less-than-M-bit significand includes three to five of the M bits.

[0297] Example 8 includes the apparatus of Example 1, wherein the execution circuit combines the second exponent value with the N-bit first exponent value when the N-bit first exponent value is all ones.

[0298] Example 9 includes the apparatus of any of Examples 1 or 8, wherein one of the following is true: (1) the floating-point data element is a 64-bit floating-point data element, the N-bit first exponent value is an 11-bit value, the M-bit significand is a 52-bit significand, the second exponent value includes three to eleven of the M bits, and the less-than-M-bit significand includes forty-one to forty-nine of the M bits; (2) the floating-point data element is a 32-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 23-bit significand, the second exponent value includes three to eight of the M bits, and the less-than-M-bit significand includes The M-bit significand includes fifteen to twenty of the M bits; (3) the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes two to five of the M bits, and the less-than-M-bit significand includes five to eight of the M bits; and (4) the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 7-bit significand, the second exponent value includes two to six of the M bits, and the less-than-M-bit significand includes one to five of the M bits.

[0299] Example 10 includes the apparatus of any of Examples 1 to 9, wherein the execution circuitry does not interpret the floating point data as a non-number (NaN) or an infinity when the N-bit first exponent value is all ones.

[0300] Example 11 includes the apparatus of any one of Examples 1 to 10, optionally wherein the apparatus uses a value to determine the number of bits of the second exponent value, and optionally wherein the apparatus reads the value from a register or obtains the value from a prefix or immediate value of an instruction.

[0301] Example 12 is a method, comprising decoding an instruction. The instruction indicates at least a source floating-point operand and a destination register. The source floating-point operand has at least a floating-point data element. The floating-point data element has a sign bit, an N-bit first exponent value, and an M-bit. The method also includes performing an operation corresponding to the instruction. The operation includes interpreting the M-bit as an M-bit valid number when the N-bit first exponent value is not all zero or all one. The operation includes: when the N-bit first exponent value is all zero or all one, interpreting the M-bit as including a second exponent value in at least one of the M bits, and including less than an M-bit valid number in at least another of the M bits. The operation includes performing an operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand. The operation includes storing the result floating-point operand in the destination register.

[0302] Example 13 includes the method of Example 12, optionally wherein the second exponent value comprises a plurality of least significant bits of M bits, and optionally wherein the less than M bits of significand comprise a plurality of bits that are more significant than the plurality of least significant bits.

[0303] Example 14 includes the method of any of Examples 12 to 13, wherein when the N-bit first exponent value is all zeros, the execution circuit uses the second exponent value to identify a position of a binary point relative to the less than M-bit significand.

[0304] Example 15 includes the method of any of Examples 12 to 14, wherein the execution circuitry sets the sticky bit equal to an implicit most significant significand bit of the floating point data element when the second exponent value has a given value.

[0305] Example 16 includes the method of any of Examples 12 to 13, wherein the execution circuit combines the second exponent value with the N-bit first exponent value when the N-bit first exponent value is all ones.

[0306] Example 17 is a system for processing instructions, including a processor. The processor includes a decoder circuit that decodes the instruction. The instruction indicates at least a source floating-point operand and a destination register. The source floating-point operand has at least a floating-point data element. The floating-point data element has a sign bit, an N-bit first exponent value, and an M-bit. The processor also includes an execution circuit coupled to the decoder circuit. The execution circuit performs an operation corresponding to the instruction. The operation includes interpreting the M-bit as an M-bit valid number when the N-bit first exponent value is not all zero or all one. The operation includes: when the N-bit first exponent value is all zero or all one, interpreting the M-bit as including a second exponent value in at least one of the M bits, and including less than an M-bit valid number in at least another of the M bits. The operation includes performing an operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand. The operation includes storing the result floating-point operand in the destination register. The system also includes a dynamic random access memory (DRAM) coupled to the processor.

[0307] Example 18 includes the system of Example 17, wherein when the N-bit first exponent value is all zeros, the execution circuit uses the second exponent value to identify a position of a binary point relative to the less than M-bit significand.

[0308] Example 19 includes the system of Example 17, wherein the execution circuit combines the second exponent value with the N-bit first exponent value when the N-bit first exponent value is all ones.

[0309] Example 20 includes the system of any of Examples 17 to 19, optionally wherein the second exponent value comprises a plurality of M least significant bits, and optionally wherein the less than M significand comprises a plurality of bits that are more significant than the plurality of least significant bits.

[0310] Example 21 is a device comprising one of logic, circuits, or devices for decoding an instruction. The instruction indicates at least a source floating-point operand and a destination register. The source floating-point operand has at least a floating-point data element. The floating-point data element has a sign bit, an N-bit first exponent value, and an M-bit. The device also includes one of logic, circuits, or devices for performing an operation corresponding to the instruction. The operation includes interpreting the M bits as an M-bit valid number when the N-bit first exponent value is not all zero or all one. The operation includes: when the N-bit first exponent value is all zero or all one, interpreting the M bits as including a second exponent value in at least one of the M bits, and including less than an M-bit valid number in at least one of the M bits. The operation includes performing an operation specified by the instruction on at least the source floating-point operand to generate a result floating-point operand. The operation includes storing the result floating-point operand in the destination register.

[0311] Example 22 is a processor or other apparatus operable to perform the method of any of Examples 12-16.

[0312] Example 23 is a processor or other apparatus comprising components for performing the method of any of Examples 12-16.

[0313] Example 24 is a processor or other apparatus comprising any combination of modules and / or units and / or logic and / or circuits and / or components operable to perform the method of any of Examples 12 to 16.

[0314] Example 25 is an optionally non-transitory and / or tangible machine-readable medium that optionally stores or otherwise provides instructions including a first instruction that, if and / or when executed by a processor, computer system, electronic device, or other machine, is operable to cause the machine to perform the method of any of Examples 12 to 16.

Claims

1. A processor, comprising: A decoder circuit for decoding an instruction for indicating at least a source floating point operand and a destination register, the source floating point operand having at least a floating point data element having a sign bit, an N-bit first exponent value, and M bits; as well as an execution circuit, the execution circuit being coupled to the decoder circuit, the execution circuit being configured to execute an operation corresponding to the instruction, the operation comprising: When the N-bit first exponent value is not all zeros or all ones, interpreting the M bits as an M-bit significand; When the N-bit first exponent value is all zeros or all ones, interpreting the M bits as including a second exponent value in at least one of the M bits and including less than M bits of significand in at least another of the M bits; performing the operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; and The resulting floating-point operand is stored in the destination register.

2. The processor according to claim 1, wherein: The second exponent value includes a plurality of least significant bits of the M bits, and wherein the less than M-bit significand includes a plurality of bits that are more significant than the plurality of least significant bits.

3. The processor according to claim 2, wherein: The second exponent value and the less than M-bit significand together comprise M bits.

4. The processor according to claim 1, wherein: When the N-bit first exponent value is all zeros, the execution circuit is configured to use the second exponent value to identify a position of a binary point relative to the less than M-bit significand.

5. The processor according to any one of claims 1 to 4, wherein: The second exponent value has sufficient bits to be able to encode any one of at least M different values.

6. The processor according to any one of claims 1 to 4, wherein: The execution circuitry is operative to set a sticky bit equal to an implicit most significant significand bit of the floating point data element when the second exponent value has a given value.

7. The processor according to any one of claims 1 to 4, wherein: Implement one of the following: the floating point data element is a 64-bit floating point data element, the N-bit first exponent value is an 11-bit value, the M-bit significand is a 52-bit significand, the second exponent value includes two to six of the M bits, and the less than M-bit significand includes forty-six to fifty of the M bits; the floating point data element is a 32-bit floating point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 23-bit significand, the second exponent value includes two to five of the M bits, and the fewer than M bits significand includes eighteen to twenty-one of the M bits; the floating point data element is a 16-bit floating point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes two to four of the M bits, and the less than M-bit significand includes six to eight of the M bits; and The floating point data element is a 16-bit floating point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 7-bit significand, the second exponent value includes two to four of the M bits, and the less than M-bit significand includes three to five of the M bits.

8. The processor of claim 1, wherein: When the N-bit first exponent value is all ones, the execution circuit is configured to combine the second exponent value with the N-bit first exponent value.

9. The processor according to claim 1 or 8, wherein: Implement one of the following: the floating point data element is a 64-bit floating point data element, the N-bit first exponent value is an 11-bit value, the M-bit significand is a 52-bit significand, the second exponent value includes three to eleven of the M bits, and the fewer than M bits significand includes forty-one to forty-nine of the M bits; the floating point data element is a 32-bit floating point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 23-bit significand, the second exponent value includes three to eight of the M bits, and the less than M-bit significand includes fifteen to twenty of the M bits; the floating point data element is a 16-bit floating point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes two to five of the M bits, and the less than M-bit significand includes five to eight of the M bits; and The floating point data element is a 16-bit floating point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 7-bit significand, the second exponent value includes two to six of the M bits, and the less than M-bit significand includes one to five of the M bits.

10. The processor according to any one of claims 1 to 4, wherein: The execution circuit is configured to not interpret the floating point data as a non-number (NaN) or an infinity when the N-bit first exponent value is all ones.

11. The processor according to any one of claims 1 to 4, wherein: The processor is configured to use a value to determine the number of bits of the second exponent value, and wherein the processor is configured to read the value from a register or obtain the value from a prefix or an immediate value of the instruction.

12. A method comprising: decoding an instruction, the instruction indicating at least a source floating point operand and a destination register, the source floating point operand having at least a floating point data element having a sign bit, an N-bit first exponent value, and M bits; as well as Execute an operation corresponding to the instruction, the operation comprising: When the N-bit first exponent value is not all zeros or all ones, interpreting the M bits as an M-bit significand; When the N-bit first exponent value is all zeros or all ones, interpreting the M bits as including a second exponent value in at least one of the M bits and including less than M bits of significand in at least another of the M bits; performing the operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; and The resulting floating-point operand is stored in the destination register.

13. The method according to claim 12, wherein: The second exponent value includes a plurality of least significant bits of the M bits, and wherein the less than M-bit significand includes a plurality of bits that are more significant than the plurality of least significant bits.

14. The method according to claim 12, wherein: When the N-bit first exponent value is all zeros, the execution circuit is configured to use the second exponent value to identify a position of a binary point relative to the less than M-bit significand.

15. The method according to claim 14, wherein: The execution circuitry is operative to set a sticky bit equal to an implicit most significant significand bit of the floating point data element when the second exponent value has a given value.

16. The method according to claim 12, wherein: When the N-bit first exponent value is all ones, the execution circuit is configured to combine the second exponent value with the N-bit first exponent value.

17. A system for processing instructions, comprising: A processor, the processor comprising: a decoder circuit for decoding an instruction for indicating at least a source floating point operand and a destination register, the source floating point operand having at least a floating point data element having a sign bit, an N-bit first exponent value, and M bits; and an execution circuit, the execution circuit being coupled to the decoder circuit, the execution circuit being configured to execute an operation corresponding to the instruction, the operation comprising: When the N-bit first exponent value is not all zeros or all ones, interpreting the M bits as an M-bit significand; When the N-bit first exponent value is all zeros or all ones, interpreting the M bits as including a second exponent value in at least one of the M bits and including less than M bits of significand in at least another of the M bits; performing the operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; and storing the resulting floating-point operand in the destination register; and A dynamic random access memory (DRAM) is coupled to the processor.

18. The system of claim 17, wherein: When the N-bit first exponent value is all zeros, the execution circuit is configured to use the second exponent value to identify a position of a binary point relative to the less than M-bit significand.

19. The system of claim 17, wherein: When the N-bit first exponent value is all ones, the execution circuit is configured to combine the second exponent value with the N-bit first exponent value.

20. A system according to any one of claims 17 to 19, wherein: The second exponent value includes a plurality of least significant bits of the M bits, wherein the less than M-bit significand includes a plurality of bits that are more significant than the plurality of least significant bits.

21. A processor, comprising: means for decoding an instruction for indicating at least a source floating point operand and a destination register, the source floating point operand having at least a floating point data element having a sign bit, an N-bit first exponent value, and M bits; as well as means for interpreting the M bits as an M-bit significand when the N-bit first exponent value is not all zeros or all ones; means for interpreting the M bits as including a second exponent value in at least one of the M bits and including less than an M-bit significand in at least another of the M bits when the N-bit first exponent value is all zeros or all ones; means for performing the operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; as well as Means for storing the result floating-point operand in the destination register.

22. A machine-readable medium comprising machine-readable instructions that, when executed, cause a machine to perform operations comprising: decoding an instruction for indicating at least a source floating point operand and a destination register, the source floating point operand having at least a floating point data element having a sign bit, an N-bit first exponent value, and M bits; as well as The processor is caused to perform an operation corresponding to the instruction, the operation comprising: When the N-bit first exponent value is not all zeros or all ones, interpreting the M bits as an M-bit significand; When the N-bit first exponent value is all zeros or all ones, interpreting the M bits as including a second exponent value in at least one of the M bits and including less than M bits of significand in at least another of the M bits; performing the operation specified by the instruction on the at least source floating-point operand to generate a result floating-point operand; and The resulting floating-point operand is stored in the destination register.

23. A processor comprising means for executing the method of any one of claims 12 to 16.

24. A machine-readable medium comprising machine-readable instructions which, when executed, cause a machine to perform the method of any one of claims 12 to 16.

25. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method of any one of claims 12 to 16.

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