Method, device and electronic device for processing accelerator instructions

Abstract

The present application discloses a method, device and electronic device for processing accelerator instructions, which are executed by a processor. The method includes: dispatching the accelerator instruction to a common reservation station of the execution unit of the accelerator and the processor; judging whether the accelerator instruction data transmission unit in the processor has an empty item, and in response to the accelerator instruction data transmission unit having an empty item, transmitting the accelerator instruction from the common reservation station to the execution unit; monitoring the write-back port of the execution unit to determine the configuration information of the execution unit; writing the accelerator instruction back to the reordering buffer according to the configuration information of the execution unit; controlling the accelerator instruction data transmission unit to send the instruction information of the accelerator instruction to the execution unit of the accelerator in sequence. The accelerator disclosed in the present invention can reuse the execution unit of the processor, and the accelerator can focus on the dedicated computing part of a specific field, avoiding the waste of resources, improving the resource utilization of heterogeneous chips, and improving the collaborative efficiency of the processor and the accelerator.

Description

Technical Field

[0001] The present application relates to the field of computer processor technology, and in particular to a method, device and electronic device for processing accelerator instructions. Background Art

[0002] With the rapid development of high-computation-intensive application fields such as artificial intelligence, scientific computing, video processing, network transmission, encryption and decryption processing, and digital signal processing, the requirements for the data processing capabilities of chips are becoming increasingly higher. In order to improve the processing capabilities of computationally intensive applications of domain-specific architectures (DSA), chips generally adopt a heterogeneous form of a combination of processors and accelerators. The processor is responsible for the processing of control streams, and the accelerator is responsible for the processing of data streams. The chip uses artificial intelligence (AI) processors, graphics processing units (GPUs), digital signal processors (DSPs), encryption and decryption accelerators (Cryptographic Accelerators), data processors DPUs (Data Processing Units, DPUs) and stream processors as accelerators and general-purpose processors (Central Processing Units, CPUs) as the processor and accelerator heterogeneous cores of the chip. However, the processor and accelerator have independent control units, which often results in a waste of resources, resulting in low resource utilization of heterogeneous chips. Summary of the invention

[0003] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, the first purpose of the present application is to propose a method for processing accelerator instructions to solve the technical problems of resource waste and low resource utilization in heterogeneous chips in the prior art.

[0005] In order to achieve the above-mentioned objectives, an embodiment of the first aspect of the present application provides a method for processing accelerator instructions, which is executed by a processor, and the method includes: dispatching accelerator instructions to a common reservation station of an execution unit of an accelerator and a processor; judging whether an accelerator instruction data transmission unit in the processor has an empty item, and in response to the accelerator instruction data transmission unit having an empty item, transmitting the accelerator instruction from the common reservation station to the execution unit; monitoring a write-back port of the execution unit to determine configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively occupies a write-back port or that the execution unit shares a write-back port; writing the accelerator instruction back to a reordering buffer according to the configuration information of the execution unit; and controlling the accelerator instruction data transmission unit to send instruction information of the accelerator instruction to the execution unit of the accelerator in sequence, wherein the instruction information includes an opcode and a source operand.

[0006] In order to achieve the above-mentioned purpose, the second aspect of the present application provides an accelerator instruction processing device, which is applied to a processor, and the device includes: a dispatching module, which is used to dispatch the accelerator instruction to the common reservation station of the execution unit of the accelerator and the processor; a transmitting module, which is used to determine whether the accelerator instruction data transmission unit in the processor has an empty item, and in response to the accelerator instruction data transmission unit having an empty item, transmit the accelerator instruction from the common reservation station to the execution unit; a monitoring module, which is used to monitor the write-back port of the execution unit to determine the configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively occupies the write-back port or the execution unit shares the write-back port; a write-back module, which is used to write the accelerator instruction back to the reordering buffer according to the configuration information of the execution unit; and a sending module, which is used to control the accelerator instruction data transmission unit to send the instruction information of the accelerator instruction to the execution unit of the accelerator in sequence, wherein the instruction information includes an opcode and a source operand.

[0007] In order to achieve the above-mentioned purpose, the third aspect embodiment of the present application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the processing method of accelerator instructions as described in any one of the embodiments of the first aspect of the present application.

[0008] In order to achieve the above-mentioned purpose, the fourth aspect embodiment of the present application provides a non-transitory computer-readable storage medium storing computer instructions, which are used to enable a computer to implement a processing method for accelerator instructions as described in any one of the first aspect embodiments of the present application when executing the computer.

[0009] In order to achieve the above-mentioned purpose, the fifth aspect of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the processing method of accelerator instructions as described in any one of the embodiments of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of a method for processing accelerator instructions disclosed in one embodiment of the present application.

[0011] Figure 2 A schematic diagram of processing an accelerator instruction disclosed in another embodiment of the present application.

[0012] Figure 3 A schematic diagram of a method for processing accelerator instructions disclosed in another embodiment of the present application.

[0013] Figure 4 A flowchart of a method for processing accelerator instructions disclosed in another embodiment of the present application.

[0014] Figure 5 A flowchart of a method for processing accelerator instructions disclosed in another embodiment of the present application is shown.

[0015] Figure 6 A schematic diagram of the structure of an accelerator instruction processing device disclosed in one embodiment of the present application.

[0016] Figure 7 A schematic diagram of the structure of an electronic device disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to better understand the above technical solution, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0018] The following describes a method and device for processing accelerator instructions according to an embodiment of the present application with reference to the accompanying drawings.

[0019] Figure 1 It is a flowchart of a method for processing an accelerator instruction according to an embodiment disclosed in the present application.

[0020] like Figure 1 As shown, the method for processing accelerator instructions proposed in the embodiment of the present application specifically includes the following steps:

[0021] S101 , dispatching accelerator instructions to a shared reservation station of an execution unit of an accelerator and a processor.

[0022] Among them, the reservation station (RS) is used by the processor to cache instructions to be executed until the instructions to be executed are assigned to the execution unit for processing.

[0023] It should be noted that the present application does not limit the execution components, which can be selected according to actual conditions.

[0024] Optionally, the execution unit includes but is not limited to an instruction fetch unit, a decoding unit, a register renaming unit and a dispatch unit.

[0025] It should be noted that it is possible to determine whether an instruction is an accelerator instruction based on the instruction opcode, and after confirming that the instruction is an accelerator instruction, the accelerator instruction is dispatched to the shared reservation station of the execution unit of the accelerator and the processor.

[0026] In an embodiment of the present application, instructions can be read from an instruction cache, the instructions can be decoded to obtain the instruction opcode, and the accelerator instruction can be determined from the instruction based on the instruction opcode, and the accelerator instruction can be dispatched to a co-reserved station of the execution unit of the accelerator and the processor.

[0027] S102, determining whether an accelerator instruction data transmission component in the processor has an empty entry, and in response to the accelerator instruction data transmission component having an empty entry, transmitting the accelerator instruction from the shared reservation station to the execution component.

[0028] It should be noted that before the accelerator instruction is transmitted from the shared reservation station to the execution unit for execution, the physical register file is read to determine the source operands required to execute the accelerator instruction, wherein the source operands are stored in the physical register file.

[0029] In an embodiment of the present application, after determining the source operands required to execute the accelerator instruction, it is determined whether the accelerator instruction data transmission component in the processor has an empty item. In response to the accelerator instruction data transmission component having an empty item, the accelerator instruction is transmitted from the shared reservation station to the execution component for execution according to the priority of the accelerator instruction.

[0030] Among them, the accelerator instruction data transmission component is set in the processor for data transmission.

[0031] It should be noted that when there are multiple accelerator instructions to be executed, the priority of the accelerator instructions can be determined, and the accelerator instructions are transmitted from the shared reservation station to the execution component according to the priority of the accelerator instructions.

[0032] S103: Monitor the write-back port of the execution component and determine the configuration information of the execution component, wherein the configuration information of the execution component indicates whether the execution component exclusively occupies the write-back port or whether the execution component shares the write-back port.

[0033] S104. Write the accelerator instructions back to the reorder buffer according to the configuration information of the execution unit.

[0034] In the embodiment of the present application, after the configuration information of the execution component is determined, the accelerator instructions can be written back to the reorder buffer according to the configuration information of the execution component.

[0035] Optionally, if the configuration information indicates that the execution component exclusively occupies the write-back port, a first number of execution components is obtained, a first number of first target accelerator instructions are determined from the accelerator instructions, and the first target accelerator instructions are simultaneously written back to the reorder buffer.

[0036] Optionally, if the configuration information indicates that the execution components share write-back ports, the write-back ports of the execution components are arbitrated, a second number of write-back ports are acquired, a second number of second target accelerator instructions are determined from the accelerator instructions, and the second target accelerator instructions are simultaneously written back to the reordering buffer.

[0037] S105 , controlling the accelerator instruction data transmission component to send instruction information of the accelerator instruction to the execution component of the accelerator in sequence, wherein the instruction information includes an operation code and a source operand.

[0038] In an embodiment of the present application, the opcode and multiple source operands of the accelerator instruction are written into the accelerator instruction data transmission component, and the accelerator instruction data transmission component is controlled to send the opcode and multiple source operands to the execution component of the accelerator in the original order. Accordingly, after receiving the opcode and multiple source operands, the accelerator can obtain the execution result of the execution component of the accelerator by executing the accelerator instruction.

[0039] For example, Figure 2As shown, the accelerator reuses the instruction fetching unit, decoding unit, register renaming unit and dispatching unit of the processor. In the above-mentioned units, the accelerator instructions are executed as the instructions of the processor, and the execution results are written back to the reordering buffer. The accelerator instructions enter the dispatch queue. The accelerator reuses the processor control unit. Each pipeline stage operates as follows: (1) Dispatching to the reservation station: The accelerator instructions are dispatched to the shared reservation station of the execution unit of the accelerator and the processor. The accelerator instructions read the physical register stack; (2) Issuing: The accelerator instructions can reuse the fixed-point execution unit, floating-point execution unit, and memory access execution unit of the processor. The accelerator instruction monitors the write-back port of each execution unit in the processor. The accelerator instruction receives the value of the read physical register stack to determine the source operands required to execute the accelerator instruction. When the accelerator command data transmission unit has an empty item, the accelerator instruction is selected for issuance; (3) Execution and write-back: The accelerator instruction writes back to the reordering buffer, and writes the opcode and multiple source operands to the accelerator command data transmission unit; (4) Submission: Control the accelerator instruction data transmission unit to send the opcode and multiple source operands to the accelerator execution unit in the original order of the accelerator instruction.

[0040] The processing method of accelerator instructions provided in the present application dispatches accelerator instructions to the shared reservation station of the execution unit of the accelerator and the processor, determines whether the accelerator instruction data transmission unit in the processor has an empty item, and in response to the accelerator instruction data transmission unit having an empty item, transmits the accelerator instruction from the shared reservation station to the execution unit, monitors the write-back port of the execution unit, and determines the configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively occupies the write-back port or the execution unit shares the write-back port, writes the accelerator instruction back to the reordering buffer according to the configuration information of the execution unit, and controls the accelerator instruction data transmission unit to send the instruction information of the accelerator instruction to the execution unit of the accelerator in sequence, wherein the instruction information includes an operation code and a source operand, thereby, the accelerator disclosed in the present invention can reuse the execution unit of the processor, and the accelerator focuses on the dedicated computing part of a specific field, thereby avoiding the waste of resources and improving the resource utilization of heterogeneous chips, and at the same time, the operation code and multiple source operands of the accelerator instruction are written into the accelerator instruction data transmission unit, and the accelerator instruction data transmission unit is controlled to send the accelerator instruction to the execution unit of the accelerator, thereby improving the collaborative efficiency of the processor and the accelerator.

[0041] Figure 3 It is a flowchart of a method for processing accelerator instructions according to another embodiment disclosed in the present application.

[0042] like Figure 3 As shown, the method for processing accelerator instructions proposed in the embodiment of the present application specifically includes the following steps:

[0043] S301, reading instructions from an instruction cache, and decoding the instructions to obtain an operation code of the instructions.

[0044] S302 . Determine an accelerator instruction from the instruction according to the operation code of the instruction, and dispatch the accelerator instruction to a shared reservation station of the execution unit of the accelerator and the processor.

[0045] S303: Read the physical register file to determine the source operand required to execute the accelerator instruction.

[0046] S304: In response to the accelerator instruction data transmission component having an empty entry, the accelerator instruction is transmitted from the shared reservation station to the execution component.

[0047] S305: Monitor the write-back port of the execution component and determine the configuration information of the execution component, wherein the configuration information of the execution component indicates whether the execution component exclusively occupies the write-back port or whether the execution component shares the write-back port.

[0048] S306 . Write the accelerator instruction back to the reorder buffer according to the configuration information of the execution component.

[0049] In an embodiment of the present application, if the configuration information indicates that the execution component exclusively occupies the write-back port, in response to completing the execution of the accelerator instruction, the execution result of each execution component is simultaneously written back to the reorder buffer in the original order of the accelerator instruction.

[0050] In an embodiment of the present application, if the configuration information indicates that the execution components share write-back ports, in response to completing the execution of the accelerator instruction, the write-back ports of the execution components are arbitrated, the target number of write-back ports are obtained, and the execution results of the target number of execution components are simultaneously written back to the reordering buffer in accordance with the original order of the accelerator instruction.

[0051] S307 , control the accelerator instruction data transmission component to send instruction information of the accelerator instruction to the execution component of the accelerator in sequence, wherein the instruction information includes an operation code and a source operand.

[0052] For example, for the arithmetic logic unit of the accelerator multiplexing processor, the arithmetic logic unit of the accelerator multiplexing processor, the arithmetic logic unit has N units, and the write-back port is exclusively occupied, and no write-back arbitration is required, such as Figure 4As shown, the pipeline operation of the arithmetic logic unit of the accelerator multiplexing processor is as follows: (1) Dispatching to the reservation station: the accelerator instruction is dispatched to the shared reservation station of the arithmetic logic unit of the accelerator and the processor, and the accelerator instruction reads the physical register stack; (2) Issuing: the accelerator instruction monitors the write-back port of each execution unit, and the accelerator instruction receives the value of the read physical register stack to determine the source operand required to execute the accelerator instruction. When the accelerator command data transmission unit has an empty item, the accelerator instruction is selected for issuance; (3) Execution and write-back: the accelerator instruction writes back to the reordering buffer. If there are N arithmetic logic units, the writing of N accelerator instructions can be completed at the same time, and the operation code and multiple source operands are written to the accelerator command data transmission unit; (4) Submitting: controlling the accelerator instruction data transmission unit to send the operation code and multiple source operands to the execution unit of the accelerator in the original order of the accelerator instruction.

[0053] For example, for the register transfer unit of the accelerator multiplexing processor, there are M register transfer units in the accelerator multiplexing processor, which need to arbitrate with other units to write back ports, such as Figure 5 As shown, the register transfer unit of the accelerator multiplexing processor operates at each pipeline stage as follows: (1) Dispatching to the reservation station: The accelerator instruction is dispatched to the shared reservation station of the register transfer unit of the accelerator and the processor, and the accelerator instruction reads the physical register stack; (2) Issuing: The accelerator instruction monitors the write-back port of each execution unit, and the accelerator instruction receives the value of the read physical register stack to determine the source operand required to execute the accelerator instruction. When the accelerator command data transfer unit has an empty item, the accelerator instruction is selected for issuance; (3) Execution and write-back: The accelerator instruction arbitrates with other execution units and then writes back to the reordering buffer. When there are M register transfer units in total and P write-back ports are obtained through arbitration, the writing of P accelerator instructions can be completed at the same time, and the operation code and multiple source operands are written to the accelerator command data transfer unit; (4) Submitting: Controlling the accelerator instruction data transfer unit to send the operation code and multiple source operands to the accelerator execution unit in the original order of the accelerator instruction.

[0054] The present application provides a method for processing accelerator instructions, which reads instructions from an instruction cache, decodes the instructions to obtain an operation code of the instructions, determines an accelerator instruction from the instructions according to the operation code of the instructions, dispatches the accelerator instruction to a shared reservation station of execution components of the accelerator and the processor, reads a physical register stack, determines a source operand required to execute the accelerator instruction, and in response to an accelerator instruction data transmission component having an empty item, transmits the accelerator instruction from the shared reservation station to the execution component for execution according to the priority of the accelerator instruction, monitors the write-back port of the execution component, obtains configuration information of the execution component, wherein the configuration information of the execution component indicates that the execution component exclusively occupies the write-back port or the execution component shares the write-back port, based on the According to the configuration information of the execution component, in response to completing the execution of the accelerator instruction, the execution result is written back to the reordering buffer in the original order of the accelerator instruction, and the accelerator instruction data transmission component in the processor is controlled to send the instruction information of the accelerator instruction to the execution component of the accelerator in the original order. Therefore, the accelerator disclosed in the present invention can reuse the execution component of the processor, and the accelerator focuses on the dedicated computing part of a specific field, avoiding the waste of resources and improving the resource utilization of heterogeneous chips. At the same time, the operation code and multiple source operands of the accelerator instruction are written into the accelerator instruction data transmission component, and the accelerator instruction data transmission component is controlled to be sent to the execution component of the accelerator, thereby improving the collaborative efficiency of the processor and the accelerator.

[0055] Figure 6 It is a structural diagram of an accelerator instruction processing device according to an embodiment disclosed in the present application.

[0056] like Figure 6 As shown, the accelerator instruction processing device 1000 includes: a dispatching module 11, a transmitting module 12, a monitoring module 13, a writing module 14 and a sending module 15. Among them,

[0057] A dispatch module 11 for dispatching accelerator instructions to a shared reservation station of the execution components of the accelerator and the processor;

[0058] A transmitting module 12, configured to determine whether an accelerator instruction data transmission component in the processor has an empty item, and in response to the accelerator instruction data transmission component having an empty item, transmit the accelerator instruction from the shared reservation station to the execution component;

[0059] A monitoring module 13, configured to monitor the write-back port of the execution component and determine configuration information of the execution component, wherein the configuration information of the execution component indicates that the execution component exclusively occupies the write-back port or the execution component shares the write-back port;

[0060] A write-back module 14, configured to write the accelerator instruction back to the reordering buffer according to the configuration information of the execution component;

[0061] The sending module 15 is used to control the accelerator instruction data transmission component to send the instruction information of the accelerator instruction to the execution component of the accelerator in sequence, wherein the instruction information includes an operation code and a source operand.

[0062] According to one embodiment of the present application, the dispatch module 11 is also used to: read instructions from an instruction cache, decode the instructions to obtain the operation code of the instructions; determine the accelerator instructions from the instructions according to the operation code of the instructions, and dispatch the accelerator instructions to the shared reservation station of the execution unit of the accelerator and the processor.

[0063] According to an embodiment of the present application, before transmitting the accelerator instruction from the shared reservation station to the execution unit, the apparatus 1000 is further used to: read a physical register file to determine a source operand required to execute the accelerator instruction.

[0064] According to an embodiment of the present application, the transmitting module 12 is further used to: obtain the priority of the accelerator instruction, and transmit the accelerator instruction from the shared reservation station to the execution component according to the priority.

[0065] According to one embodiment of the present application, the write-back module 14 is further used to: if the configuration information indicates that the execution component exclusively occupies the write-back port, obtain a first number of the execution components; determine a first number of first target accelerator instructions from the accelerator instructions, and write the first target accelerator instructions back to the reordering buffer at the same time.

[0066] According to one embodiment of the present application, the write-back module 14 is further used to: if the configuration information indicates that the execution components share write-back ports, arbitrate the write-back ports of the execution components to obtain a second number of write-back ports; determine a second number of second target accelerator instructions from the accelerator instructions, and write the second target accelerator instructions back to the reordering buffer at the same time.

[0067] According to one embodiment of the present application, the sending module 15 is also used to: write the opcode and multiple source operands of the accelerator instruction into the accelerator instruction data transmission component; obtain the target order of the accelerator instructions in the reordering buffer, and control the accelerator instruction data transmission component to send the opcode and multiple source operands of the accelerator instruction to the execution component of the accelerator according to the target order.

[0068] An embodiment of the present application provides an accelerator instruction processing device, which dispatches accelerator instructions to a common reservation station of an execution unit of an accelerator and a processor, determines whether an accelerator instruction data transmission unit in the processor has an empty item, and in response to the accelerator instruction data transmission unit having an empty item, transmits the accelerator instruction from the common reservation station to the execution unit, monitors the write-back port of the execution unit, and determines the configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively occupies the write-back port or the execution unit shares the write-back port, writes the accelerator instruction back to a reordering buffer according to the configuration information of the execution unit, and controls the accelerator instruction data transmission unit to send the instruction information of the accelerator instruction to the execution unit of the accelerator in sequence, wherein the instruction information includes an operation code and a source operand, thereby, the accelerator disclosed in the present invention can reuse the execution unit of the processor, and the accelerator focuses on the dedicated computing part of a specific field, thereby avoiding waste of resources and improving the resource utilization of heterogeneous chips, and at the same time, writes the operation code and multiple source operands of the accelerator instruction into the accelerator instruction data transmission unit, and controls the accelerator instruction data transmission unit to send to the execution unit of the accelerator, thereby improving the collaborative efficiency of the processor and the accelerator.

[0069] In order to implement the above embodiment, the present application also proposes an electronic device 2000, such as Figure 7 As shown, it includes a memory 210, a processor 220, and a computer program stored in the memory 210 and executable on the processor 220. When the processor executes the program, the aforementioned accelerator instruction processing method is implemented.

[0070] In order to implement the above embodiments, the present application also proposes a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to implement the aforementioned accelerator instruction processing method when executed by a computer.

[0071] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0072] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0073] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0074] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0075] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0076] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for processing an accelerator instruction, characterized in that: Executed by a processor, the method includes: dispatching accelerator instructions to a common reservation station of the accelerator and the execution unit of the processor; Determine whether an accelerator instruction data transmission component in the processor has an empty entry, and in response to the accelerator instruction data transmission component having an empty entry, transmit the accelerator instruction from the shared reservation station to the execution component; Monitoring the write-back port of the execution component to determine configuration information of the execution component, wherein the configuration information of the execution component indicates that the execution component exclusively occupies the write-back port or the execution component shares the write-back port; writing the accelerator instruction back to the reorder buffer according to the configuration information of the execution unit; Controlling the accelerator instruction data transmission component to send instruction information of the accelerator instruction to the execution component of the accelerator in sequence, wherein the instruction information includes an operation code and a source operand; The controlling the accelerator instruction data transmission component to send the instruction information of the accelerator instruction to the execution component of the accelerator in sequence also includes: Writing the operation code and multiple source operands of the accelerator instruction into the accelerator instruction data transmission component; The target order of the accelerator instructions in the reorder buffer is obtained, and the accelerator instruction data transmission unit is controlled to send the operation code and multiple source operands of the accelerator instructions to the execution unit of the accelerator according to the target order.

2. The method according to claim 1, characterized in that: The method of dispatching accelerator instructions to a common reservation station of an execution unit of an accelerator and a processor comprises: Reading instructions from an instruction cache, and decoding the instructions to obtain an operation code of the instructions; An accelerator instruction is determined from the instruction according to an operation code of the instruction, and the accelerator instruction is dispatched to a common reservation station of an accelerator and an execution unit of a processor.

3. The method according to claim 1, characterized in that: Before transmitting the accelerator instruction from the common reservation station to the execution unit, the method further comprises: A physical register file is read to determine source operands required to execute the accelerator instruction.

4. The method according to claim 1, characterized in that: In response to the accelerator instruction data transmission component having an empty entry, the accelerator instruction is transmitted from the shared reservation station to the execution component, and further includes: The priority of the accelerator instruction is obtained, and the accelerator instruction is issued from the shared reservation station to the execution unit according to the priority.

5. The method according to claim 1, characterized in that: The step of writing the accelerator instruction back to the reorder buffer according to the configuration information of the execution unit further comprises: If the configuration information indicates that the execution component exclusively occupies the write-back port, obtaining a first number of the execution components; A first number of first target accelerator instructions are determined from the accelerator instructions, and the first target accelerator instructions are simultaneously written back to a reorder buffer.

6. The method according to claim 1, characterized in that: The step of writing the accelerator instruction back to the reorder buffer according to the configuration information of the execution unit further comprises: If the configuration information indicates that the execution components share write-back ports, arbitrating the write-back ports of the execution components to obtain a second number of write-back ports; A second number of second target accelerator instructions are determined from the accelerator instructions, and the second target accelerator instructions are simultaneously written back to the reorder buffer.

7. A device for processing accelerator instructions, characterized in that: Applied to a processor, the device comprises: A dispatch module for dispatching accelerator instructions to a common reservation station of the accelerator and the execution unit of the processor; A transmitting module, used for judging whether there is an empty item in the accelerator instruction data transmission component in the processor, and in response to the accelerator instruction data transmission component having an empty item, transmitting the accelerator instruction from the shared reservation station to the execution component; A monitoring module, used for monitoring the write-back port of the execution component, and determining the configuration information of the execution component, wherein the configuration information of the execution component indicates that the execution component exclusively occupies the write-back port or the execution component shares the write-back port; A write-back module, used for writing the accelerator instruction back to the reorder buffer according to the configuration information of the execution component; A sending module, used to control the accelerator instruction data transmission component to send instruction information of the accelerator instruction to the execution component of the accelerator in sequence, wherein the instruction information includes an operation code and a source operand; The sending module is further used for: Writing the operation code and multiple source operands of the accelerator instruction into the accelerator instruction data transmission component; The target order of the accelerator instructions in the reorder buffer is obtained, and the accelerator instruction data transmission unit is controlled to send the operation code and multiple source operands of the accelerator instructions to the execution unit of the accelerator according to the target order.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for processing an accelerator instruction according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method for processing an accelerator instruction as described in any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the method for processing accelerator instructions according to any one of claims 1 to 6.

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