A method, apparatus, electronic device, and storage medium for processing packet entry information.

Abstract

This application provides a packet entry processing method, apparatus, electronic device, and storage medium, relating to the field of network technology. The method involves multiple target storage spaces within the storage space controlled by a forwarding chip. The method includes: obtaining a first packet entry group from the host CPU and storing it in a first storage space within the target storage space; starting to process each packet entry stored in the current first storage space; if it is necessary to continue processing the next packet entry group, obtaining a new second packet entry group from the host CPU and storing it in a second storage space within the target storage space other than the current first storage space; using the current second storage space as the new first storage space, and returning to the step that started processing each packet entry stored in the current first storage space. Applying the solution provided by this application can save storage space controlled by the forwarding chip, thereby improving the utilization rate of packet entry resources.

Description

Technical Field

[0001] This application relates to the field of network technology, and in particular to a method, apparatus, electronic device, and storage medium for processing packet entries. Background Technology

[0002] OAM (Operation, Administration and Maintenance) messages, including BFD (Bidirectional Forwarding Detection), CFD (Connectivity Failure Detection), and TWAMP (Two-way Active Measurement Protocol), play an important role in network probing (such as link connectivity detection, latency jitter measurement, packet loss calculation, etc.) and are indispensable functions for high-performance switching, routing and forwarding chips.

[0003] When forwarding OAM messages, the forwarding chip needs to use packet entry. Due to limitations in chip area and cost, the on-chip storage space of the forwarding chip is very limited. On-chip storage mostly uses SRAM (Static Random Access Memory), while off-chip storage mostly uses DDR (Double Data Rate SDRAM) with larger storage space for data storage.

[0004] In related technologies, when sending OAM messages, taking BFD as an example, each session requires approximately 128 bytes of storage space for packet entry entries. In high-performance routers or switches, the total size of BFD sessions typically reaches thousands or even tens of thousands. The host CPU (Central Processing Unit) cannot support such a large number of sessions using a software solution, so it distributes all OAM session packet entries to the on-chip or off-chip storage space of the forwarding chip to achieve packet entry storage.

[0005] However, the related technical solutions consume a significant amount of table storage space in the forwarding chip. Since OAM sessions send packets periodically, even with a minimum packet interval of 3ms configured for all sessions, each packet entry will only be queried and used once every 3ms. For high-performance switching and routing forwarding chips, the utilization rate of packet entry resources is relatively low. In actual network operation, such a small 3ms packet interval is usually not configured; instead, a larger interval, such as 10ms or longer, is chosen to avoid OAM sessions being overly sensitive to link status, which further reduces the utilization rate of packet entry resources. Summary of the Invention

[0006] The purpose of this application is to provide a packet entry processing method, apparatus, electronic device, and storage medium to save storage space controlled by the forwarding chip, thereby improving the utilization rate of packet entry resources. The specific technical solution is as follows:

[0007] In a first aspect, embodiments of this application provide a packet entry processing method applied to a forwarding chip. The forwarding chip controls a storage space containing multiple target storage spaces, and the host CPU controls a storage space storing packet entries for forwarding operations, management, and maintenance of OAM messages. These packet entries are divided into packet entry groups, with the sequence numbers of the packet entries in each packet entry group sequentially adjacent. The method includes:

[0008] Obtain the first packet entry group from the host CPU and store the current first packet entry group into the first storage space in the target storage space;

[0009] Begin processing the packet sending entries stored in the current first storage space;

[0010] Determine whether to continue processing the next batch of packet entries;

[0011] If it is necessary to continue processing the next packet entry group, a new second packet entry group is obtained from the host CPU, and the current second packet entry group is stored in the second storage space of the target storage space other than the current first storage space. The time required to obtain and store the current second packet entry group is no greater than the time required to process the packet entries in the current first storage space. The sequence number of the first packet entry in the current second packet entry group is: the remainder of the current first value and the total number of packet entries in the host CPU. The first value is: the sum of the sequence number of the last entry in the current first packet entry group and 1.

[0012] The current second storage space is used as the new first storage space, and execution returns to the step of starting to process each packet entry stored in the current first storage space.

[0013] In one embodiment of this application, obtaining a new second packet entry group from the host CPU and storing the current second packet entry group in a second storage space in the target storage space other than the current first storage space includes:

[0014] After starting to process the first packet entry in the current first storage space, a dynamic transfer request is initiated to the host CPU;

[0015] Obtain the new second packet entry group fed back by the host CPU in response to the dynamic transfer request, and store the current second packet entry group in a second storage space in the target storage space other than the current first storage space.

[0016] In one embodiment of this application, the packet sending entry includes a control field, which includes at least one of the following:

[0017] The first field is used to identify whether the packet entry has been stored in the target storage space;

[0018] The second field is used to identify whether a new group of packet entries needs to be obtained and stored in the target storage space after the packet entry is started to be processed.

[0019] The third field, when it is determined that a new packet entry group needs to be obtained and stored in the target storage space, is used to identify the target base address, which is the address of the target storage space to which the new packet entry group to be stored in the forwarding chip belongs.

[0020] In one embodiment of this application, the processing method of the forwarding chip for any packet entry includes:

[0021] Based on the first field, determine whether the packet sending entry has been stored in the target storage space;

[0022] If the first field indicates that the packet entry has been stored in the target storage space, then based on the second field, determine whether it is necessary to obtain a new packet entry group and store it in the target storage space.

[0023] If the second field indicates that a new packet entry group needs to be obtained and stored in the target storage space, a new second packet entry group is obtained from the host CPU. Based on the third field, the target base address of the new second packet entry group is determined, and the new second packet entry group is stored in the target storage space corresponding to the target base address.

[0024] In one embodiment of this application, the sum of the number of packet entry entries that can be stored in the plurality of target storage spaces is divisible by the total number of packet entry entries in the host CPU.

[0025] In one embodiment of this application, the number of target storage spaces is two, and the two target storage spaces are of equal size.

[0026] Secondly, embodiments of this application provide a packet entry processing apparatus applied to a forwarding chip. The forwarding chip controls a storage space containing multiple target storage spaces, and the host central processing unit (CPU) controls a storage space storing packet entries for forwarding operations, management, and maintenance of OAM messages. These packet entries are divided into packet entry groups, with the sequence numbers of the packet entries in each packet entry group being sequentially adjacent. The apparatus includes:

[0027] The first acquisition and storage module is used to acquire the first packet entry group from the host CPU and store the current first packet entry group into the first storage space in the target storage space.

[0028] The first processing module is used to begin processing each packet entry stored in the current first storage space;

[0029] The first judgment module is used to determine whether it is necessary to continue processing the next packet table entry group;

[0030] The second acquisition and storage module is used to, if it is necessary to continue processing the next packet entry group, acquire a new second packet entry group from the host CPU, store the current second packet entry group in a second storage space in the target storage space other than the current first storage space, use the current second storage space as the new first storage space, and return to trigger the execution of the first processing module. The time required to acquire and store the current second packet entry group is no greater than the time required to process the packet entries in the current first storage space. The sequence number of the first packet entry in the current second packet entry group is the remainder of the current first value and the total number of packet entries in the host CPU. The first value is the sum of the sequence number of the last entry in the current first packet entry group and 1.

[0031] In one embodiment of this application, the second acquisition and storage module is specifically used for:

[0032] After starting to process the first packet entry in the current first storage space, a dynamic transfer request is initiated to the host CPU;

[0033] Obtain the new second packet entry group fed back by the host CPU in response to the dynamic transfer request, and store the current second packet entry group in a second storage space in the target storage space other than the current first storage space.

[0034] In one embodiment of this application, the packet sending entry includes a control field, which includes at least one of the following:

[0035] The first field is used to identify whether the packet entry has been stored in the target storage space;

[0036] The second field is used to identify whether a new group of packet entries needs to be obtained and stored in the target storage space after the packet entry is started to be processed.

[0037] The third field, when it is determined that a new packet entry group needs to be obtained and stored in the target storage space, is used to identify the target base address, which is the address of the target storage space to which the new packet entry group to be stored in the forwarding chip belongs.

[0038] In one embodiment of this application, for any packet sending entry, the packet sending entry processing device specifically includes:

[0039] The second judgment module is used to determine, based on the first field, whether the packet sending table entry has been stored in the target storage space;

[0040] The third judgment module is used to determine, based on the second field, whether it is necessary to obtain a new group of packet entries and store it in the target storage space when the first field indicates that the packet entry has been stored in the target storage space.

[0041] The third acquisition and storage module is used to acquire a new second packet entry group from the host CPU when the second field indicates that a new packet entry group needs to be acquired and stored in the target storage space, determine the target base address of the new second packet entry group based on the third field, and store the new second packet entry group in the target storage space corresponding to the target base address.

[0042] In one embodiment of this application, the sum of the number of packet entry entries that can be stored in the plurality of target storage spaces is divisible by the total number of packet entry entries in the host CPU.

[0043] In one embodiment of this application, the number of target storage spaces is two, and the two target storage spaces are of equal size.

[0044] Thirdly, embodiments of this application provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0045] Memory, used to store computer programs;

[0046] When a processor executes a program stored in memory, it implements any of the steps described in the first aspect.

[0047] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the methods described in the first aspect.

[0048] Fifthly, embodiments of this application also provide a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the steps described in the first aspect above.

[0049] Beneficial effects of the embodiments in this application:

[0050] This application provides a method for processing packet entries, wherein multiple target storage spaces exist within the storage space controlled by the forwarding chip, and packet entries from the host CPU are stored only through these target storage spaces. The method provided by this application can dynamically store a portion of packet entries from the host CPU to the storage space controlled by the forwarding chip. During processing, only this portion of packet entries occupies the storage space controlled by the forwarding chip. Furthermore, while processing packet entries in one target storage space, another set of packet entries from the host CPU can be simultaneously stored in another target storage space. Therefore, after processing packet entries in one target storage space, processing of newly stored packet entries can immediately continue without affecting the processing efficiency of packet entries.

[0051] In other words, compared with the methods of the prior art, the method provided in this application embodiment can reduce the number of packet entries stored in the storage space controlled by the forwarding chip. Therefore, within a fixed time period, the number of idle packet entries waiting to be queried and used will be reduced, significantly saving the storage space controlled by the forwarding chip, thereby improving the utilization rate of packet entry resources.

[0052] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0054] Figure 1 This is a schematic diagram illustrating the composition of packet entry entries in a BFD session in related technologies.

[0055] Figure 2 This is an example diagram illustrating the correspondence between BFD session specifications and the table space required for packet sending in related technologies.

[0056] Figure 3 This is a schematic diagram illustrating the arrangement of multiple packet sending entries in the storage space controlled by the host central processing unit in related technologies;

[0057] Figure 4 A flowchart illustrating the first method for processing packet entry provided in this application embodiment;

[0058] Figure 5 A schematic diagram illustrating the arrangement of packet entry entries in the first type of target storage space provided in this application embodiment;

[0059] Figure 6 A flowchart illustrating the second method for processing packet entry provided in this application embodiment;

[0060] Figure 7 A schematic diagram illustrating the arrangement of packet entry entries in the second type of target storage space provided in this application embodiment;

[0061] Figure 8 A schematic diagram illustrating the processing procedure of a packet sending entry provided in an embodiment of this application;

[0062] Figure 9 A schematic diagram of the structure of a packet submission processing device provided in an embodiment of this application;

[0063] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0065] In related technologies, when sending OAM messages, taking BFD as an example, see [link to relevant documentation]. Figure 1This diagram illustrates the composition of packet entries in a BFD session. It includes packet control information, message encapsulation information, and outgoing interface information. The packet control information includes the session index, packet interval, and message length. The message encapsulation information includes Ethernet II frames, Internet Protocol headers (IP header), User Datagram Protocol headers (UDP header), Bidirectional Forwarding Detection headers (BFD header), and Authentication headers. The outgoing interface information includes the outgoing interface index (physical port / aggregated port / tunnel port). The space required to store a single packet entry is 128 bytes. In high-performance routers or switches, the total size of BFD sessions typically reaches thousands or even tens of thousands. See [link to relevant documentation]. Figure 2 This is an example diagram illustrating the correspondence between BFD session specifications and the space required for packet sending entries. Assume the BFD session specification is 2K, meaning there are 2048 packet sending entries, designated as packet sending entry 0, packet sending entry 1, packet sending entry 2, ..., packet sending entry 2047. Since storing a single packet sending entry requires 128B of space, storing 2K packet sending entries requires: 2048 × 128B = 262144B = 256KB. Assume the BFD session specification is 1... 0K means there are 10240 packet entries, namely packet entry 0, packet entry 1, packet entry 2, ..., packet entry 2047, packet entry 2048, packet entry 2049, ..., packet entry 10238, packet entry 10239. Since the space required to store a single packet entry is 128B, the space required to store 10K packet entries is: 10240 × 128B = 1310720B = 1280KB = 1.25MB.

[0066] The packet entry entries for these OAM sessions are initially stored in the host CPU-controlled storage space after they are generated. See [link to OAM session entry]. Figure 3This diagram illustrates the arrangement of multiple packet entries in the storage space controlled by the host CPU. There are N packets in the storage space, designated as packet entry 0, packet entry 1, packet entry 2, ..., packet entry N-1. Each packet entry occupies 128 bytes of storage space. 1, 2, ..., N-1 are the session indices of the packet entries. The storage space controlled by the host CPU also stores the base addresses of each packet entry: packet entry 0 is the base address, packet entry 1 is the base address + 128 bytes, packet entry 2 is the base address + 128 bytes × 2, and packet entry N-1 is the base address + 128 bytes × (N-1). The base address of any packet entry is: base address + 128 bytes × session index. The base address can also be referred to as the base address.

[0067] However, the host CPU cannot support such a large number of sessions using a software solution. In this case, all OAM session packet entries are distributed to the on-chip or off-chip storage space of the forwarding chip to store the packet entries. However, this solution consumes a large amount of table storage space on the forwarding chip, and the utilization rate of packet entry resources is low.

[0068] To save storage space controlled by the forwarding chip and thus improve the utilization rate of packet sending table entries, see [link to relevant documentation]. Figure 4 This is a flowchart illustrating the first packet entry processing method provided in this application embodiment, applied to a forwarding chip. The method includes the following steps S401-S405.

[0069] Step S401: Obtain the first packet entry group from the host central processing unit and store the current first packet entry group into the first storage space in the target storage space.

[0070] The storage space controlled by the aforementioned forwarding chip contains multiple target storage spaces, and the storage space controlled by the host CPU stores packet entries used for forwarding OAM messages. These packet entries are divided into packet entry groups, and the sequence numbers of the packet entries in each packet entry group are sequentially adjacent.

[0071] The aforementioned target storage space is a part of the storage space controlled by the aforementioned forwarding chip. It is used to store packet entry from the storage space controlled by the host CPU for forwarding OAM messages. The storage space controlled by the aforementioned forwarding chip can be the on-chip storage space of the forwarding chip (such as SRAM) or the off-chip storage space of the forwarding chip (such as DDR). The size of each target storage space is not limited, as long as the number of target storage spaces is two or more.

[0072] See Figure 5This is a schematic diagram of the arrangement of packet entries in the first type of target storage space provided in the embodiments of this application. There are n target storage spaces, namely target storage space 1, target storage space 2, ..., target storage space n. The maximum number of packet entries that can be stored in each target storage space is M, and the storage space occupied by each packet entry is 128B. In target storage space 1, the packet entries to be stored are denoted as: packet entry X, packet entry X+1, packet entry X+2, ..., packet entry X+M-1. The base addresses of each packet entry to be stored in target storage space 1 are as follows: packet entry X is base address 0, packet entry X+1 is base address 0+128B, packet entry X+2 is base address 0+128B×2, and packet entry X+M-1 is base address 0+128B×(M-1). The base address of any packet entry to be stored is: base address 0+128B×session index. In target storage space 2, the packet entries to be stored are denoted as: packet entry X+M... Packet entry X+M+1, packet entry X+M+2, ..., packet entry X+2M-1, the base addresses of each packet entry to be stored in target storage space 2 are as follows: packet entry X+M is base address 1, packet entry X+M+1 is base address 1+128B, packet entry X+M+2 is base address 1+128B×2, packet entry X+2M-1 is base address 1+128B×(M-1), and the base address of any packet entry to be stored is: base address 1+128B×session index; the packet entries to be stored in target storage space n are respectively denoted as: packet entry X+(n-1)M, packet entry X+(n-1)M +1, packet entry X+(n-1)M+2, ..., packet entry X+nM-1, the base addresses of each packet entry to be stored in the target storage space n are as follows: packet entry X+(n-1)M is the base address (n-1), packet entry X+(n-1)M+1 is the base address (n-1)+128B, packet entry X+(n-1)M+2 is the base address (n-1)+128B×2, packet entry X+nM-1 is the base address (n-1)+128B×(M-1), and the base address of any packet entry to be stored is: base address (n-1)+128B×session index. In practical applications, the number and capacity of the target storage space can be adjusted according to the performance of the forwarding chip in sending OAM messages and the processing performance of packet entries.

[0073] The space occupied by all entries in the first packet sending table group mentioned above must be less than or equal to the capacity of the first storage space mentioned above.

[0074] Step S402: Begin processing the various packet sending entries stored in the current first storage space.

[0075] The forwarding chip processes each packet entry stored in the current first storage space and can determine the processing method for the packet entry based on the various information contained in the packet entry, such as whether a packet needs to be sent or whether the processing needs to be terminated.

[0076] Step S403: Determine whether it is necessary to continue processing the next packet table entry group.

[0077] During the processing of the packet entries stored in the current first storage space, it is determined whether it is necessary to continue processing the next packet entry group, which is a new group of packet entries obtained from the host CPU.

[0078] If the judgment result is yes, then proceed to step S404; if the judgment result is no, then end the process.

[0079] Step S404: Obtain a new second packet entry group from the host central processing unit and store the current second packet entry group in a second storage space in the target storage space other than the current first storage space.

[0080] The time required to acquire and store the current second packet entry group is no greater than the time required to process the packet entries in the current first storage space. The sequence number of the first packet entry in the current second packet entry group is the remainder of the current first value and the total number of packet entries in the host CPU. The first value is the sum of the sequence number of the last entry in the current first packet entry group and 1.

[0081] Since the scheme in this application is a cyclical process, in order to facilitate the processing of packet entries by the forwarding chip, the sequence number of the first packet entry in the current second packet entry group is set as: the remainder of the current first value and the total number of packet entries in the host CPU. The first value is: the sum of the sequence number of the last entry in the current first packet entry group and 1. In one example, the total number of packet entries in the host CPU is 1024, and the sequence number of the packet entry in the current first packet entry group is 512-1023, that is, the sequence number of the last entry in the current first packet entry group is 1023. Then the current first value is: 1023+1=1024. Therefore, the remainder of the current first value 1024 and the total number of packet entries in the host CPU is 1024 is 0. So the sequence number of the first packet entry in the current second packet entry group is set to 0.

[0082] Step S405: Use the current second storage space as the new first storage space.

[0083] Return to the execution starting from step S402 above.

[0084] As can be seen from the above, the packet entry processing method provided in this application embodiment has multiple target storage spaces in the storage space controlled by the forwarding chip, and only the target storage spaces are used to complete the storage of packet entries from the host CPU. The method provided in this application embodiment can dynamically store a portion of packet entries from the host CPU to the storage space controlled by the forwarding chip. During the processing, only this portion of packet entries occupies the storage space controlled by the forwarding chip. Furthermore, while processing packet entries in one target storage space, another set of packet entries from the host CPU can be stored in another target storage space simultaneously. Thus, after processing packet entries in one target storage space, processing of newly stored packet entries can continue immediately without affecting the processing efficiency of packet entries. In other words, compared with the methods of the prior art, the method provided in this application embodiment can reduce the number of packet entries stored in the storage space controlled by the forwarding chip. Therefore, within a fixed time period, the number of idle packet entries waiting to be queried and used will be reduced, significantly saving the storage space controlled by the forwarding chip, thereby improving the utilization rate of packet entry resources.

[0085] See Figure 6 This is a flowchart illustrating the second method for processing packet entry provided in this application embodiment. The above step S404 can be implemented through the following steps S404A-S404B.

[0086] Step S404A: After starting to process the first packet entry in the current first storage space, a dynamic transfer request is initiated to the aforementioned host central processing unit.

[0087] Step S404A above indicates that when the forwarding chip processes any packet entry in the current first storage space, it can initiate a dynamic transfer request to the host CPU. Since the number of packet entry groups obtained each time is not necessarily equal, it is sufficient to ensure that the storage of the next packet entry group is completed during the processing of packet entries in the current first storage space.

[0088] In one example, the forwarding chip can be configured to initiate a dynamic transfer request to the host CPU when processing the first packet entry in the current first storage space.

[0089] Step S404B: Obtain the new second packet entry group fed back by the host central processing unit in response to the dynamic transfer request, and store the current second packet entry group in the second storage space of the target storage space other than the current first storage space.

[0090] In response to the aforementioned dynamic transfer request, the host CPU will return a new packet entry group, namely the new second packet entry group. After the forwarding chip obtains the new second packet entry group, it needs to store the current second packet entry group in the second storage space of the target storage space, excluding the current first storage space.

[0091] As can be seen from the above, the packet entry processing method provided in this application can quickly and accurately obtain a new packet entry group by initiating a dynamic transfer request to the host CPU after starting to process the first packet entry in the current first storage space.

[0092] In one embodiment of this application, the above-mentioned packet sending entry includes a control field, which includes at least one of the following:

[0093] The first field is used to identify whether the packet entry has been stored in the target storage space;

[0094] The second field is used to identify whether a new group of packet entries needs to be obtained and stored in the target storage space after the packet entry is started to be processed.

[0095] The third field, when it is determined that a new packet entry group needs to be obtained and stored in the target storage space, is used to identify the target base address, which is the address of the target storage space to which the new packet entry group to be stored in the forwarding chip belongs.

[0096] The control fields mentioned above can be set in the reserved free bytes in the packet sending table. Each control field can occupy 1 bit, 2 bits, or even more. In one example, to save fields, each control field occupies 1 bit. For ease of description, the first field can be referred to as the bMoveDone (transfer completed) field, the second field as the bBeginMove (transfer started) field, and the third field as the BaseAddrPos (base address position) field.

[0097] As can be seen from the above, the packet sending entry processing method provided in this application embodiment can accurately determine the real-time status of each packet sending entry by setting a control field in the packet sending entry, thereby achieving accurate processing of the packet sending entry.

[0098] In one embodiment of this application, the processing method of the forwarding chip for any packet entry can be achieved through the following steps A-C.

[0099] Step A: Based on the first field mentioned above, determine whether the packet sending entry has been stored in the target storage space.

[0100] Specifically, the value of the field at the location of the first field in the storage space controlled by the forwarding chip can be read to determine whether the packet entry has been stored in the target storage space. For example, when the first field occupies 1 bit, the following judgment method can be used to determine whether the packet entry has been stored in the target storage space:

[0101] When the first field above is 1, it is determined that the packet entry has been stored in the target storage space;

[0102] When the first field is 0, it is determined that the packet entry has not been stored in the target storage space.

[0103] It's important to note that for any packet entry, the first field mentioned above is 1 in the host CPU. If the forwarding chip acquires this packet entry and stores it in the target storage space, then the first field of the packet entry will be 1, indicating that the packet entry has been stored in the target storage space. After the forwarding chip processes the packet entry, it needs to set the first field to 0. The first field remains 0 until the next time the packet entry needs to be acquired and stored. This is to prevent the first field from being 1 before the next packet entry is actually successfully stored in the target storage space, which could lead to the forwarding chip incorrectly determining that the packet entry has been stored in the target storage space based on the first field being 1.

[0104] It should be noted that a value of 1 in the first field indicating that the packet entry has been stored in the target storage space, and a value of 0 indicating that the packet entry has not been stored in the target storage space, is only one possible embodiment. In another possible embodiment, a value of 0 in the first field indicating that the packet entry has been stored in the target storage space, and a value of 1 indicating that the packet entry has not been stored in the target storage space, are merely different values. This application does not limit the specific value of the first field or the meaning of that value, as long as the values ​​indicating that the packet entry has been stored in the target storage space and has not been stored in the target storage space are different.

[0105] Step B: If the first field indicates that the packet entry has been stored in the target storage space, then based on the second field, determine whether it is necessary to obtain a new packet entry group and store it in the target storage space.

[0106] If the first field indicates that the packet entry has not been stored in the target storage space, it means that the acquisition and storage of the packet entry has failed, and this is recorded as an error. The number of error handling is counted, and the processing of the packet entry ends, then the processing of the next packet entry continues. In addition, the forwarding chip determines whether the packet entry needs to forward OAM messages based on the control information in the packet entry. In the solution provided in this application embodiment, regardless of whether the packet entry needs to forward OAM messages, as long as the first field indicates that the packet entry has been stored in the target storage space, it is necessary to determine whether a new packet entry group needs to be acquired and stored in the target storage space based on the second field.

[0107] Specifically, the value of the field at the location of the second field in the storage space controlled by the forwarding chip can be read to determine whether a new packet table entry group needs to be obtained and stored in the target storage space. For example, when the number of bits occupied by the second field is 1 bit, the following judgment method can be used to determine whether a new packet table entry group needs to be obtained and stored in the target storage space:

[0108] When the second field above is 1, it is determined that a new packet sending table entry group needs to be obtained and stored in the target storage space;

[0109] When the second field above is 0, it is determined that there is no need to obtain a new packet sending table entry group and store it in the target storage space.

[0110] In one example, the second field of the first packet entry in each packet entry group is 1. This indicates that when the forwarding chip processes the first packet entry in the current target storage space, it obtains a new packet entry group and stores it in another target storage space.

[0111] It should be noted that a value of 1 in the second field indicates that a new packet entry group needs to be obtained and stored in the target storage space, while a value of 0 indicates that a new packet entry group does not need to be obtained and stored in the target storage space. This is only one possible embodiment. In another possible embodiment, a value of 0 in the second field indicates that a new packet entry group needs to be obtained and stored in the target storage space, while a value of 1 indicates that a new packet entry group does not need to be obtained and stored in the target storage space. This application does not limit the specific value of the second field or the meaning of the corresponding value, as long as the values ​​indicating that a new packet entry group needs to be obtained and stored in the target storage space and those indicating that a new packet entry group does not need to be obtained and stored in the target storage space are different.

[0112] Step C: If the second field indicates that a new packet entry group needs to be obtained and stored in the target storage space, obtain the new second packet entry group from the host CPU, determine the target base address of the new second packet entry group based on the third field, and store the new second packet entry group in the target storage space corresponding to the target base address.

[0113] Specifically, the target base address of the new second packet sending table entry group can be determined by reading the value of the field at the location of the third field in the storage space controlled by the forwarding chip. For example, when the third field occupies 1 bit and there are two target storage spaces, namely target storage space 1 and target storage space 2, the target base address in target storage space 1 is base address0 and the target base address in target storage space 2 is base address1. The target base address of the new second packet sending table entry group can be determined according to the following judgment method, and the new second packet sending table entry group can be stored in the target storage space corresponding to the target base address:

[0114] When the third field above is 1, the target base address of the new second packet sending table entry group is determined to be baseaddress0, and the new second packet sending table entry group is stored in the target storage space 1.

[0115] When the first field is 0, the target base address of the new second packet sending table entry group is determined to be baseaddress1, and the new second packet sending table entry group is stored in the target storage space 2.

[0116] It should be noted that a value of 1 in the third field indicates that the target base address of the new second packet entry group is baseaddress0, and the new second packet entry group is stored in target storage space 1. A value of 0 in the third field indicates that the target base address of the new second packet entry group is baseaddress1, and the new second packet entry group is stored in target storage space 2. This is only one possible embodiment. In another possible embodiment, a value of 0 in the third field indicates that the target base address of the new second packet entry group is baseaddress0, and the new second packet entry group is stored in target storage space 1; a value of 1 in the third field indicates that the target base address of the new second packet entry group is baseaddress1, and the new second packet entry group is stored in target storage space 2. This application does not limit the specific value of the third field or its corresponding meaning, as long as the value indicating whether a new packet entry group needs to be obtained and stored in the target storage space is different from the value indicating whether a new packet entry group needs to be obtained and stored in the target storage space.

[0117] As can be seen from the above, the packet sending entry processing method provided in this application embodiment can store and process any packet sending entry based on the control field, and after determining that a certain packet sending entry does not need to send packets, it can immediately continue to process the next packet sending entry, thereby improving the processing efficiency of packet sending entries.

[0118] In one embodiment of this application, the sum of the number of packet entries that can be stored in the plurality of target storage spaces can be divided by the total number of packet entries in the host CPU.

[0119] The aforementioned target storage space is a storage space with at least two forwarding chips. In this embodiment, the sum of the number of packet entry entries that can be stored in all target storage spaces is set to be divisible by the total number of packet entry entries in the host CPU. If the total number of packet entry entries in the host CPU is N, then the sum of the number of packet entry entries that can be stored in all target storage spaces must be divisible by N. For example, if the total number of packet entry entries in the host CPU is 1024, then the sum of the number of packet entry entries that can be stored in all target storage spaces can be 512, 256, 128, etc.

[0120] As can be seen from the above, the packet entry processing method provided in this application can further improve the packet entry processing efficiency by saving the storage space controlled by the forwarding chip and setting the sum of the number of packet entries that can be stored in all target storage spaces to be divisible by the total number of packet entries in the host CPU.

[0121] In one embodiment of this application, the number of target storage spaces is two, and the two target storage spaces are of equal size.

[0122] See Figure 7This is a schematic diagram of the arrangement of packet entries in the second type of target storage space provided in the embodiments of this application. In the storage space controlled by the forwarding chip, there are two target storage spaces, which are denoted as target storage space 1 and target storage space 2, respectively. The maximum number of packet entries that can be stored in target storage space 1 and target storage space 2 is M. The packet entries to be stored in target storage space 1 are denoted as: packet entry X, packet entry X+1, packet entry X+2, ..., packet entry X+M-1; the packet entries to be stored in target storage space 2 are denoted as: packet entry X+M, packet entry X+M+1, packet entry X+M+2, ..., packet entry X+2M-1. Target memory space 1 and target memory space 2 can be a large, contiguous block of memory divided into two smaller segments, namely target memory space 1 and target memory space 2; or they can be two independent memory spaces, where the addresses of target memory space 1 and target memory space 2 are not contiguous, but the addresses within each target memory space are contiguous. Furthermore, the target memory space also stores the target base address, which is used to determine the target memory space to which the new packet table entry group belongs after the forwarding chip obtains the new packet table entry group. The target base address in target memory space 1 is base address 0, and the target base address in target memory space 2 is base address 1. The target base addresses of each packet entry to be stored in target storage space 1 are as follows: packet entry X is base address 0, packet entry X+1 is base address 0+128B, packet entry X+2 is base address 0+128B×2, and packet entry X+M-1 is base address 0+128B×(M-1). The target base address of any packet entry to be stored is: base address 0+128B×session index. The target base addresses of each packet entry to be stored in target storage space 2 are as follows: packet entry X+M is base address 1, packet entry X+M+1 is base address 1+128B, packet entry X+M+2 is base address 1+128B×2, and packet entry X+2M-1 is base address 1+128B×(M-1). The target base address of any packet entry to be stored is: base address 1+128B×session index.

[0123] In this embodiment, the specific processing flow of the forwarding chip is as follows:

[0124] When the forwarding chip processes packet entry X in target storage space 1, it initiates a first dynamic transfer request, asynchronously storing the packet entry [(X+M)%N, ((X+M)%N) + M-1] stored in the host CPU-controlled storage space to target storage space 2. During the process of the forwarding chip processing M packet entries in target storage space 1, packet entry [(X+M)%N, ((X+M)%N) + M-1] is stored. Similarly, when the forwarding chip processes packet entry (X+M)%N in target storage space 2, it initiates a second dynamic transfer request, asynchronously storing the packet entry [(X+2M)%N, ((X+2M)%N) + M-1] stored in the host CPU-controlled storage space to target storage space 1. During the process of the chip processing M packet entries in target storage space 2, packet entry [(X+2M)%N, ((X+2M)%N) + M-1] is stored. This process repeats itself continuously, making the entire process of processing the packet entry streamlined.

[0125] In one example, see Figure 8 This is a schematic diagram illustrating the processing of packet entries according to an embodiment of this application. The OAM session specification is N=2K, meaning the number of packet entries stored in the host CPU-controlled storage space is N=2048. The maximum number of packet entries that can be stored in a target storage space is M=512, i.e., 2M=1024. In other words, the 2048 packet entries stored in the host CPU-controlled storage space are divided into four equal parts. These four parts of the packet entries are respectively... The following are the table entries: Item 0, Item 1, Item 2, ..., Item 511 (Part 1); Item 512, Item 513, Item 514, ..., Item 1023 (Part 2); Item 1024, Item 1025, Item 1026, ..., Item 1535 (Part 3); Item 1536, Item 1537, Item 1538, ..., Item 2047 (Part 4). The forwarding chip controls two target storage spaces, each capable of storing M=512 packet entry entries. The packet entry entries to be stored in the two target storage spaces are denoted as packet entry [X, X+511] and packet entry [X+512, X+1023], respectively. The initial packet entry stored in the target storage space of the forwarding chip is packet entry [0, 511] from the host CPU (Part 1). When the forwarding chip starts timed packet transmission, the following steps are executed:

[0126] Step (1): When processing packet entry 0, initiate a dynamic transfer request to asynchronously store packet entry [512, 1023] (Part 2) stored in the storage space controlled by the host central processor to the packet entry [X+512, X+1023] position in the target storage space;

[0127] Step (2): When the forwarding chip processes packet entry 512, it initiates a dynamic transfer request and asynchronously stores packet entry [1024, 1535] (Part 3) stored in the storage space controlled by the host central processor to packet entry [X, X+511] in the target storage space.

[0128] Step (3): When the forwarding chip processes packet entry 1024, it initiates a dynamic transfer request and asynchronously stores packet entry [1536, 2047] (Part 4) stored in the storage space controlled by the host central processor to packet entry [X+512, X+1023] in the target storage space.

[0129] Step (4): When the forwarding chip processes packet entry 1536, it initiates a dynamic transfer request and asynchronously stores packet entry [0,511] (Part 1) stored in the storage space controlled by the host central processor to packet entry [X, X+511] in the target storage space.

[0130] The subsequent forwarding chip executes steps (1), (2), (3), and (4) in a loop, and the entire packet entry processing process becomes streamlined until no new packet entries need to be processed.

[0131] As can be seen from the above, by using the target storage space set in this embodiment to process packet entries, since there are two target storage spaces of equal size, it can be ensured that during the process of processing packet entries in the first target storage space, the forwarding chip stores the newly acquired packet entry group to the second target storage space. After processing the packet entries in the first target storage space, it can immediately process the newly stored packet entries in the second target storage space. Similarly, during the process of processing the newly stored packet entries in the second target storage space, the newly acquired packet entry group is stored to the first target storage space, and so on. The solution of this embodiment can be achieved using only two target storage spaces. Without affecting the processing efficiency of the forwarding chip, it ensures that both target storage spaces always contain packet entries, without wasting storage space, and maximizes the saving of storage space controlled by the forwarding chip.

[0132] Corresponding to the aforementioned packet entry processing method, this application also provides a packet entry processing apparatus applied to a forwarding chip. The forwarding chip controls a storage space containing multiple target storage spaces, and the host CPU controls a storage space storing packet entries for forwarding OAM messages. These packet entries are divided into packet entry groups, with the sequence numbers of the packet entries in each packet entry group sequentially adjacent. (See [reference]). Figure 9 The diagram below illustrates the structure of a packet submission processing device provided in this application embodiment, comprising:

[0133] The first acquisition and storage module 901 is used to acquire the first packet entry group from the host CPU and store the current first packet entry group into the first storage space in the target storage space.

[0134] The first processing module 902 is used to start processing each packet sending table entry stored in the current first storage space;

[0135] The first judgment module 903 is used to determine whether it is necessary to continue processing the next packet table entry group;

[0136] The second acquisition and storage module 904 is used to, if it is necessary to continue processing the next packet entry group, acquire a new second packet entry group from the host CPU, store the current second packet entry group in a second storage space other than the current first storage space in the target storage space, use the current second storage space as the new first storage space, and return to trigger the execution of the first processing module 902. The time required to acquire and store the current second packet entry group is no greater than the time required to process the packet entries in the current first storage space. The sequence number of the first packet entry in the current second packet entry group is the remainder of the current first value and the total number of packet entries in the host CPU. The first value is the sum of the sequence number of the last entry in the current first packet entry group and 1.

[0137] As can be seen from the above, the packet entry processing apparatus provided in this application embodiment has multiple target storage spaces in the storage space controlled by the forwarding chip, and only the target storage spaces are used to complete the storage of packet entries from the host CPU. The apparatus provided in this application embodiment can dynamically move a portion of packet entries from the host CPU to the storage space controlled by the forwarding chip. During the processing, only this portion of packet entries occupies the storage space controlled by the forwarding chip. Furthermore, while processing packet entries in one target storage space, another set of packet entries from the host CPU can be stored in another target storage space simultaneously. Thus, after processing packet entries in one target storage space, processing of newly stored packet entries can continue immediately without affecting the processing efficiency of packet entries. In other words, the apparatus provided in this application embodiment can reduce the number of packet entries stored in the storage space controlled by the forwarding chip. Therefore, within a fixed time period, the number of idle packet entries waiting to be queried and used will be reduced, significantly saving the storage space controlled by the forwarding chip and thereby improving the utilization rate of packet entry resources.

[0138] In one embodiment of this application, the second acquisition and storage module 904 is specifically used for:

[0139] After starting to process the first packet entry in the current first storage space, a dynamic transfer request is initiated to the host CPU;

[0140] Obtain the new second packet entry group fed back by the host CPU in response to the dynamic transfer request, and store the current second packet entry group in a second storage space in the target storage space other than the current first storage space.

[0141] As can be seen from the above, the packet entry processing device provided in this application embodiment can obtain a new second packet entry group by initiating a dynamic transfer request to the host CPU after starting to process the first packet entry in the current first storage space. This enables the device to quickly and accurately obtain a new packet entry group.

[0142] In one embodiment of this application, the packet sending entry includes a control field, which includes at least one of the following:

[0143] The first field is used to identify whether the packet entry has been stored in the target storage space;

[0144] The second field is used to identify whether a new group of packet entries needs to be obtained and stored in the target storage space after the packet entry is started to be processed.

[0145] The third field, when it is determined that a new packet entry group needs to be obtained and stored in the target storage space, is used to identify the target base address, which is the address of the target storage space to which the new packet entry group to be stored in the forwarding chip belongs.

[0146] As can be seen from the above, the packet processing device provided in this application embodiment can accurately determine the real-time status of each packet entry by setting a control field in the packet entry, thereby achieving accurate processing of the packet entry.

[0147] In one embodiment of this application, for any packet sending entry, the packet sending entry processing device specifically includes:

[0148] The second judgment module is used to determine, based on the first field, whether the packet sending table entry has been stored in the target storage space;

[0149] The third judgment module is used to determine, based on the second field, whether it is necessary to obtain a new group of packet entries and store it in the target storage space when the first field indicates that the packet entry has been stored in the target storage space.

[0150] The third acquisition and storage module is used to acquire a new second packet entry group from the host CPU when the second field indicates that a new packet entry group needs to be acquired and stored in the target storage space, determine the target base address of the new second packet entry group based on the third field, and store the new second packet entry group in the target storage space corresponding to the target base address.

[0151] As can be seen from the above, the packet entry processing device provided in this application embodiment can store and process any packet entry based on the control field, and after determining that a certain packet entry does not need to be packetized, it can immediately continue to process the next packet entry, thereby improving the processing efficiency of packet entries.

[0152] In one embodiment of this application, the sum of the number of packet entry entries that can be stored in the plurality of target storage spaces is divisible by the total number of packet entry entries in the host CPU.

[0153] As can be seen from the above, the packet entry processing device provided in this application embodiment can further improve the packet entry processing efficiency by saving the storage space controlled by the forwarding chip and setting the sum of the number of packet entries that can be stored in all target storage spaces to be divisible by the total number of packet entries in the host CPU.

[0154] In one embodiment of this application, the number of target storage spaces is two, and the two target storage spaces are of equal size.

[0155] As can be seen from the above, the packet entry processing device provided in this application embodiment, since there are two target storage spaces of equal size, can ensure that during the process of processing packet entries in the first target storage space, the forwarding chip stores the newly acquired packet entry group into the second target storage space. After processing the packet entries in the first target storage space, it can immediately process the newly stored packet entries in the second target storage space. Similarly, during the process of processing the newly stored packet entries in the second target storage space, the newly acquired packet entry group is stored into the first target storage space again. This cycle continues, and the solution of this application embodiment can be achieved using only two target storage spaces. Without affecting the processing efficiency of the forwarding chip, it ensures that both target storage spaces always contain packet entries, without wasting storage space, and maximizes the saving of storage space controlled by the forwarding chip.

[0156] This application also provides an electronic device, such as... Figure 10 As shown, it includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004, wherein the processor 1001, the communication interface 1002, and the memory 1003 communicate with each other through the communication bus 1004.

[0157] Memory 1003 is used to store computer programs;

[0158] The processor 1001, when executing the program stored in the memory 1003, implements the above-mentioned packet entry processing method.

[0159] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0160] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0161] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0162] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0163] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the above-described packet entry processing methods.

[0164] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the packet entry processing methods in the above embodiments.

[0165] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0166] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0167] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for devices, electronic devices, computer-readable storage media, and computer program products, since they are basically similar to the method embodiments, the descriptions are relatively simple, and relevant parts can be referred to the descriptions of the method embodiments.

[0168] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A method for processing packet sending entries, characterized in that, This is applied to a forwarding chip. The storage space controlled by the forwarding chip contains multiple target storage spaces. The storage space controlled by the host CPU stores packet entries for forwarding operations, management, and maintenance of OAM messages. The packet entries are divided into packet entry groups, and the sequence numbers of the packet entries in each packet entry group are sequentially adjacent. Each packet entry contains a first field, a second field, and a third field. The first field indicates whether the packet entry has been stored in the target storage space. The value of the first field in the packet entry stored in the host CPU indicates that the packet entry has been stored in the target storage space. The second field indicates whether a new packet entry group needs to be obtained and stored in the target storage space after the packet entry is started to be processed. The third field, when it is determined that a new packet entry group needs to be obtained and stored in the target storage space, is used to identify the target base address. The target base address is the address of the target storage space in the forwarding chip to which the new packet entry group to be stored belongs. The method includes: Obtain the first packet entry group from the host CPU and store the current first packet entry group into the first storage space in the target storage space; The processing of each packet entry stored in the current first storage space begins. The processing of packet entries includes packet sending and termination processing. After the forwarding chip finishes processing the packet entry, the first field in the packet entry is set to a value indicating that the packet entry has not been stored in the target storage space. Based on the value of the second field in the currently processed packet entry, determine whether it is necessary to continue processing the next packet entry group; If it is necessary to continue processing the next packet entry group, a new second packet entry group is obtained from the host CPU, and the current second packet entry group is stored in the second storage space other than the current first storage space, corresponding to the target base address identified by the third field in the target storage space. The time required to obtain and store the current second packet entry group is no greater than the time required to process the packet entries in the current first storage space. The sequence number of the first packet entry in the current second packet entry group is: the remainder of the current first value and the total number of packet entries in the host CPU. The first value is: the sum of the sequence number of the last entry in the current first packet entry group and 1. The current second storage space is used as the new first storage space, and execution returns to the step of starting to process each packet entry stored in the current first storage space.

2. The method according to claim 1, characterized in that, The step of obtaining a new second packet sending table entry group from the host CPU and storing the current second packet sending table entry group into a second storage space other than the current first storage space, corresponding to the target base address identified by the third field in the target storage space, includes: After starting to process the first packet entry in the current first storage space, a dynamic transfer request is initiated to the host CPU; Obtain the new second packet entry group fed back by the host CPU in response to the dynamic transfer request, and store the current second packet entry group in the second storage space other than the current first storage space, which is the target base address identified by the third field in the target storage space.

3. The method according to claim 1, characterized in that, For any packet entry, the processing method of the forwarding chip for that packet entry includes: Based on the first field, determine whether the packet sending entry has been stored in the target storage space; If the first field indicates that the packet entry has been stored in the target storage space, then based on the second field, determine whether it is necessary to obtain a new packet entry group and store it in the target storage space. If the second field indicates that a new packet entry group needs to be obtained and stored in the target storage space, a new second packet entry group is obtained from the host CPU. Based on the third field, the target base address of the new second packet entry group is determined, and the new second packet entry group is stored in the target storage space corresponding to the target base address.

4. The method according to any one of claims 1-3, characterized in that, The sum of the number of packet entries that can be stored in the multiple target storage spaces is divisible by the total number of packet entries in the host CPU.

5. The method according to any one of claims 1-3, characterized in that, There are two target storage spaces, and the two target storage spaces are of equal size.

6. A device for processing outgoing data entries, characterized in that, This is applied to a forwarding chip. The storage space controlled by the forwarding chip contains multiple target storage spaces. The storage space controlled by the host CPU stores packet entries for forwarding operations, management, and maintenance of OAM messages. The packet entries are divided into packet entry groups, and the sequence numbers of the packet entries in each packet entry group are sequentially adjacent. Each packet entry contains a first field, a second field, and a third field. The first field indicates whether the packet entry has been stored in the target storage space. The value of the first field in the packet entry stored in the host CPU indicates that the packet entry has been stored in the target storage space. The second field indicates whether a new packet entry group needs to be obtained and stored in the target storage space after the packet entry is started to be processed. The third field, when it is determined that a new packet entry group needs to be obtained and stored in the target storage space, is used to identify the target base address, wherein the target base address is the address of the target storage space in the forwarding chip to which the new packet entry group to be stored belongs. The device includes: The first acquisition and storage module is used to acquire the first packet entry group from the host CPU and store the current first packet entry group into the first storage space in the target storage space. The first processing module is used to start processing each packet entry stored in the current first storage space. The processing method of the packet entry includes packet sending and termination processing. After the forwarding chip finishes processing the packet entry, the first field in the packet entry is set to a value indicating that the packet entry has not been stored in the target storage space. The first judgment module is used to determine whether to continue processing the next group of packet items based on the value of the second field in the currently processed packet item; The second acquisition and storage module is used to, if it is necessary to continue processing the next packet entry group, acquire a new second packet entry group from the host CPU, store the current second packet entry group in the target storage space corresponding to the target base address identified by the third field (excluding the current first storage space), use the current second storage space as the new first storage space, and return to trigger the execution of the first processing module. The time required to acquire and store the current second packet entry group is no greater than the time required to process the packet entries in the current first storage space. The sequence number of the first packet entry in the current second packet entry group is the remainder of the current first value and the total number of packet entries in the host CPU. The first value is the sum of the sequence number of the last entry in the current first packet entry group and 1.

7. The apparatus according to claim 6, characterized in that, The second acquisition and storage module is specifically used for: After starting to process the first packet entry in the current first storage space, a dynamic transfer request is initiated to the host CPU; Obtain the new second packet entry group fed back by the host CPU in response to the dynamic transfer request, and store the current second packet entry group in the second storage space other than the current first storage space, which is the target base address identified by the third field in the target storage space.

8. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method described in any one of claims 1-5.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-5.

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