Interrupt test system and method of PCIe chip, storage medium and electronic equipment

Abstract

The embodiment of the invention provides an interrupt test system and method of a PCIe chip, a storage medium and electronic device.The interrupt test system of the PCIe chip comprises a user mode used for sending a plurality of process identifications to a kernel mode through a plurality of threads, the threads correspond to the process identifications one to one, and the kernel mode is used for sending the process identifications to the kernel mode; the plurality of threads are used for executing an interrupt test task; the kernel mode is used for triggering a plurality of interrupt test tasks according to the plurality of process identifiers, and sending target information corresponding to the plurality of interrupt test tasks to the user mode through a callback function under the condition that the execution of the plurality of interrupt test tasks is completed, the target information at least comprises an interrupt number of an interrupt channel for executing an interrupt test task; and the user mode is also used for determining test results of the plurality of interrupt test tasks according to the plurality of pieces of target information under the condition that the plurality of pieces of target information are received.

Description

Technical Field

[0001] The embodiments of the present application relate to the computer field, and in particular, to a PCIe chip interruption test system and method, a storage medium, and an electronic device. Background Art

[0002] The PCIe (Periphera1 Component Interconnect Express) protocol is widely used in a variety of scenarios and devices due to its low overhead, low latency and high data transfer rate. In order to better serve PCIe devices, dedicated chips for corresponding devices have emerged, such as GPU chips responsible for graphics processing, Raid card chips responsible for storage control, and NIC chips for network communication. These chips all support the MSI-X interrupt feature.

[0003] Among the many features of PCIe, MSI-X (Message Signaled Interrupts-Extened) is an interrupt technology that allows PCIe devices to send up to 2048 independent interrupt vectors to the CPU, greatly improving the efficiency and flexibility of interrupt processing. MSI-X plays an important role in high-performance servers, storage devices, and network devices.

[0004] The existing MSI-X test method initiates the configuration of the DUT in the user state, expects different results for different configurations, and processes the MSI-X interrupt in the kernel state, which increases the difficulty of detecting the expected results.

[0005] Regarding the related technology, the configuration of the test chip is initiated in the user state, and different results are expected for different configurations. However, the MSI-X interrupt is processed in the kernel state, which increases the difficulty of detecting the expected results. No effective solution has been proposed yet. Summary of the invention

[0006] The embodiments of the present application provide a PCIe chip interrupt test system and method, storage medium and electronic device to at least solve the problem in the related art that the configuration of the test chip is initiated in user mode, different results are expected for different configurations, but the MSI-X interrupt is processed in kernel mode, which increases the difficulty of detecting the expected results.

[0007] According to one embodiment of the present application, an interrupt test system for a PCIe chip is provided, comprising: a user state, for sending a plurality of process identifiers to a kernel state through a plurality of threads, respectively, wherein the plurality of threads correspond one-to-one to the plurality of process identifiers, and the plurality of threads are all used to execute interrupt test tasks; the kernel state, for triggering a plurality of interrupt test tasks according to the plurality of process identifiers, and when the plurality of interrupt test tasks are executed, sending target information corresponding to the plurality of interrupt test tasks to the user state through a callback function, wherein the target information includes at least: an interrupt number of an interrupt channel for executing the interrupt test task; the user state, further for determining test results of the plurality of interrupt test tasks according to the plurality of target information when a plurality of the target information is received.

[0008] In an exemplary embodiment, the user state is also used to: establish a binding relationship between multiple interrupt channels and multiple task queues of the PCIe chip, wherein interrupt test tasks are stored in the multiple task queues; determine a verification method for different interrupt test tasks based on the binding relationship, wherein the verification method is used to determine the test result.

[0009] In an exemplary embodiment, the user state also includes: an asynchronous signal processor, used to configure signal processing behaviors for the multiple interrupt channels according to the verification method and the interrupt numbers of the multiple interrupt channels, to obtain multiple signal processing behaviors, wherein each of the multiple interrupt channels corresponds to at least one signal processing behavior.

[0010] In an exemplary embodiment, the user state is also used to: obtain, through multiple first threads, the multiple target information sent by the kernel state to the user state through the callback function, respectively, wherein the multiple threads include the multiple first threads, and the multiple first threads correspond one-to-one to the multiple target information; parse the multiple target information to obtain multiple first interrupt numbers; match a group of first signal processing behaviors corresponding to each first interrupt number according to the multiple first interrupt numbers, to obtain multiple groups of first signal processing behaviors, wherein each group of first signal processing behaviors includes at least one first signal processing behavior; determine the category of the application layer corresponding to the user state; determine the second signal processing behavior in each group of first signal processing behaviors according to the category of the application layer, to obtain multiple second signal processing behaviors, wherein the multiple first interrupt numbers correspond one-to-one to the multiple second signal processing behaviors; execute the multiple second signal processing behaviors respectively through the multiple first threads to obtain multiple signal processing results; determine the test results of the multiple interrupt test tasks according to the multiple signal processing results.

[0011] In an exemplary embodiment, the kernel state further includes: an interrupt controller, which is used to generate a plurality of interrupt vectors, wherein the plurality of interrupt vectors are used to indicate a corresponding relationship between a plurality of kernel state identifiers and a plurality of interrupt channels.

[0012] In an exemplary embodiment, the interrupt controller is further used to: upon receiving the multiple process identifiers, match multiple first task queues in the multiple task queues of the PC 1 chip according to the multiple process identifiers; trigger the interrupt test tasks in the multiple first task queues respectively; and call the callback function when the multiple interrupt test tasks are executed.

[0013] In an exemplary embodiment, the interrupt controller is further used to: convert the multiple process identifiers into multiple kernel state identifiers; generate multiple target information according to the interrupt number and configuration information respectively, and send the multiple target information to the user state.

[0014] According to another embodiment of the present application, a PCIe chip interrupt testing method is provided, which is applied to the user state, including: sending multiple process identifiers to the kernel state through multiple threads respectively, wherein the multiple threads correspond to the multiple process identifiers one by one, and the multiple threads are all used to execute interrupt testing tasks, and the multiple process identifiers are used to indicate that the kernel state triggers multiple interrupt testing tasks, and when the multiple interrupt testing tasks are completed, sending target information corresponding to the multiple interrupt testing tasks to the user state through a callback function, and the target information at least includes: the interrupt number of the interrupt channel that executes the interrupt testing task; when multiple target information are received, determining the test results of the multiple interrupt testing tasks according to the multiple target information.

[0015] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0016] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0017] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0018] The present application provides an interrupt test system for a PCIe chip, comprising: a user state, for sending a plurality of process identifiers to a kernel state through a plurality of threads, wherein the threads correspond to the process identifiers one by one, and the plurality of threads are all used to execute interrupt test tasks; the kernel state is used to trigger a plurality of interrupt test tasks according to the plurality of process identifiers, and when the interrupt test tasks are executed, the target information corresponding to the plurality of interrupt test tasks is sent to the user state through a callback function, wherein the target information at least includes: an interrupt number of an interrupt channel for executing the interrupt test tasks; the user state is also used to determine the test results of the interrupt test tasks according to the plurality of target information when receiving the plurality of target information; by adopting the above system, a tester can make relevant configurations for the MSI-X of the test chip in the user state and detect the test results in the user state, thereby reducing the programming work in the kernel state and improving the accuracy of detecting the expected results; thereby solving the problem in the related art that the configuration of the test chip is initiated in the user state, different results are expected for different configurations, but the MSI-X interrupt is processed in the kernel state, which increases the difficulty of detecting the expected results. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a hardware structure block diagram of a computer terminal according to a PCIe chip interruption test method of an embodiment of the present application;

[0020] Figure 2 This is a flowchart (I) of an optional MSI-X interrupt processing of a PCIe device according to an embodiment of the present application;

[0021] Figure 3 This is a flowchart (II) of an optional MSI-X interrupt processing of a PCIe device according to an embodiment of the present application;

[0022] Figure 4 It is a structural block diagram of an interruption test system of a PCIe chip according to an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of the architecture of an optional PCIe chip interruption test system according to an embodiment of the present application;

[0024] Figure 6 is a flow chart of a PCIe chip interruption test method according to an embodiment of the present application;

[0025] Figure 7 It is a flowchart of an optional MSI-X interrupt testing method according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0028] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 1 is a hardware structure block diagram of a computer terminal for interruption testing of a PCIe chip according to an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0029] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the buffer partition method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0030] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0031] The following is an explanation of the professional terms that appear in this application:

[0032] User mode: In user mode, users can run their own applications. In this mode, applications can only access restricted resources and perform restricted operations, such as accessing the private memory space of the process, executing non-privileged instructions, etc. When applications need to perform privileged operations, such as accessing hardware devices or requesting system services, they must request the operating system to provide services through system calls.

[0033] Kernel state: In kernel state, the operating system kernel runs and has full access to system resources and hardware. In this mode, the operating system can execute arbitrary instructions, access system memory, hardware devices, and handle interrupts and exceptions. The operating system kernel is responsible for managing system resources and performing core functions such as scheduling, memory management, file system relationships, and device drivers.

[0034] PID and VPID: PID (Process Identifier) ​​and VPID (Virtual Process ID) are both numbers used to uniquely identify a process. In the Linux system, PID is a process identification method used by both user space and kernel space, while VPID is an internal identification method introduced by the kernel to manage processes more efficiently. Together, the two form the basis of Linux process management.

[0035] Linux kernel driver: In the Linux kernel, drivers refer to a special type of software that provides an interface for the operating system to communicate with hardware devices. In this application, it refers to the implementation of the MSI-X interrupt part of different application layer protocols such as NVMe / Ethernet in the Linux kernel.

[0036] The Linux kernel code handles the MSI-X interrupt of the PCIe device as follows Figure 2 and Figure 3 As shown, Figure 2This is a flowchart of how NVMe storage devices process MSI-X interrupts. Figure 3 The figure is a flowchart of how the Ethernet network card device handles the MSI-X interrupt.

[0037] The processing flow of the NVMe storage device for the MSI-X interrupt specifically includes the following steps:

[0038] Step 2.1, start;

[0039] Step 2.2, the kernel initializes the MIS-X interrupt controller and allocates interrupt vectors;

[0040] Step 2.3, register MSI-X interrupt and implement interrupt callback function;

[0041] Step 2.4, receiving the NVMe device triggering the MSI-X interrupt and executing the callback function;

[0042] The callback function includes the following steps:

[0043] Step 2.4.1, process CQE or SQE;

[0044] Step 2.4.2, update the CQ Head register or the SQ Head register.

[0045] Step 2.5, end.

[0046] On the other hand, the Ethernet network card device's processing flow for MSI-X interrupts includes the following steps:

[0047] Step 3.1, start;

[0048] Step 3.2, the kernel initializes the MSI-X interrupt controller and allocates interrupt vectors;

[0049] Step 3.3, register MSI-X interrupt and implement interrupt callback function;

[0050] Step 3.4, the receiving Ethernet device triggers the MSI-X interrupt and executes the callback function;

[0051] The callback function includes the following steps:

[0052] Step 3.4.1, process the data packet, copy it to the kernel network buffer, and use the interrupt lower half for processing;

[0053] Step 3.4.2: Update statistics.

[0054] Step 3.5, end.

[0055] Although the devices are different, the kernel implementation is basically the same, and all of them process the content specified by the application protocol in the kernel state. For example, the kernel driver of the NVMe device processes the CQE and SQE of the IO and Admin commands according to the protocol definition, and maintains the Head register of the corresponding queue after processing; the kernel driver of the network card device parses and forwards the network data packets according to the Ethernet protocol and counts the relevant packet receiving information.

[0056] In the process of chip prototype verification, integrating the Linux kernel is the simplest and fastest way from the perspective of the verification box. However, it has the following disadvantages for the verification process: the configuration of the DUT is initiated in user mode, and different results are expected for different configurations. If the MSI-X interrupt is processed in the kernel, it will increase the difficulty of detecting the expected results.

[0057] In order to solve the above problems, a PCIe chip interruption test system is provided in this embodiment. Figure 4 is a structural block diagram of an interruption test system for a PCIe chip according to an embodiment of the present application, such as Figure 4 As shown, the system includes:

[0058] The user state 42 is used to send multiple process identifiers to the kernel state 44 through multiple threads, wherein the multiple threads correspond to the multiple process identifiers one by one, and the multiple threads are all used to execute the interrupt test task;

[0059] The kernel state 44 is used to trigger multiple interrupt test tasks according to the multiple process identifiers, and when the multiple interrupt test tasks are executed, send the target information corresponding to the multiple interrupt test tasks to the user state 42 through a callback function, wherein the target information at least includes: the interrupt number of the interrupt channel that executes the interrupt test task;

[0060] The user state 42 is further used to determine the test results of the multiple interruption test tasks according to the multiple target information when multiple target information are received.

[0061] The present application provides an interrupt test system for a PCIe chip, comprising: a user state, for sending a plurality of process identifiers to a kernel state through a plurality of threads, wherein the threads correspond to the process identifiers one by one, and the plurality of threads are all used to execute interrupt test tasks; the kernel state is used to trigger a plurality of interrupt test tasks according to the plurality of process identifiers, and when the interrupt test tasks are executed, the target information corresponding to the plurality of interrupt test tasks is sent to the user state through a callback function, wherein the target information at least includes: an interrupt number of an interrupt channel for executing the interrupt test tasks; the user state is also used to determine the test results of the interrupt test tasks according to the plurality of target information when receiving the plurality of target information; by adopting the above system, a tester can make relevant configurations for the MSI-X of the test chip in the user state and detect the test results in the user state, thereby reducing the programming work in the kernel state and improving the accuracy of detecting the expected results; thereby solving the problem in the related art that the configuration of the test chip is initiated in the user state, different results are expected for different configurations, but the MSI-X interrupt is processed in the kernel state, which increases the difficulty of detecting the expected results.

[0062] In an exemplary embodiment, the user state is also used to: establish a binding relationship between multiple interrupt channels and multiple task queues of the PCIe chip, wherein interrupt test tasks are stored in the multiple task queues; determine a verification method for different interrupt test tasks based on the binding relationship, wherein the verification method is used to determine the test result.

[0063] According to the provisions of the NVMe protocol, the NVMe interface chip will have one Admin CQ queue and up to 2048 IOCQ queues. Each chip design manufacturer will bind the MSI-X interrupt channel and CQ (i.e., the task queue mentioned above) and support multiple binding methods. Optionally, one Admin CQ queue and n IO CQ queues can be bound to n+1 MSI-X channels respectively, or one Admin CQ queue and n IO CQ queues can be bound to one MSI-X interrupt channel. Different verification schemes (i.e., verification methods) are designed according to different binding methods. The configuration of the DUT is completed in the user state, and the relevant configuration information is recorded to detect subsequent results.

[0064] Through this embodiment, the DUT related configuration is completed before the interrupt test, and the verification plan is designed, so that the test results can be analyzed accurately according to the verification plan after the test is completed.

[0065] Furthermore, the user state also includes: an asynchronous signal processor, which is used to configure signal processing behaviors for the multiple interrupt channels according to the verification method and the interrupt numbers of the multiple interrupt channels to obtain multiple signal processing behaviors, wherein each of the multiple interrupt channels corresponds to at least one signal processing behavior.

[0066] In the embodiment of the present application, an asynchronous signal processor needs to be designed. The processor is provided by the operating system. The asynchronous processing method can release the CPU pressure and will not be actively executed before the signal is triggered. The asynchronous signal processor will bind multiple signal processing behaviors, bind the signal l D (corresponding to the channel number of the interrupt channel) and the signal processing behavior, l D1 corresponds to behavior 1, l D2 corresponds to behavior 2, and so on. The number can be selected according to the verification scheme.

[0067] Through this embodiment, corresponding signal processing behaviors are configured for different interrupt channels respectively. After the corresponding interrupt channel triggers an interrupt, the relevant information of the interrupt channel that triggers the interrupt can be accurately determined according to the triggered behavior.

[0068] Furthermore, the user state is also used to: obtain, through multiple first threads, the multiple target information sent by the kernel state to the user state through the callback function, respectively, wherein the multiple threads include the multiple first threads, and the multiple first threads correspond one-to-one to the multiple target information; parse the multiple target information to obtain multiple first interrupt numbers; match a group of first signal processing behaviors corresponding to each first interrupt number according to the multiple first interrupt numbers, to obtain multiple groups of first signal processing behaviors, wherein each group of first signal processing behaviors includes at least one first signal processing behavior; determine the category of the application layer corresponding to the user state; determine the second signal processing behavior in each group of first signal processing behaviors according to the category of the application layer, to obtain multiple second signal processing behaviors, wherein the multiple first interrupt numbers correspond one-to-one to the multiple second signal processing behaviors; execute the multiple second signal processing behaviors respectively through the multiple first threads to obtain multiple signal processing results; determine the test results of the multiple interrupt test tasks according to the multiple signal processing results.

[0069] After the user state passes the process ID to the kernel state, multiple child threads (i.e., the first threads mentioned above) will wait in the background until they receive multiple target information sent by the kernel state through the callback function; the user state parses the MSI-X interrupt number and other information (i.e., the first interrupt number) from the target information, and then matches the signal processing behavior bound to it according to the interrupt number. Optionally, multiple signal processing behaviors can be bound to one interrupt number and applied to different application scenarios, that is, different signal processing behaviors are bound to different application layer categories. Therefore, at least one first signal processing behavior can be matched to one interrupt number, and then the category of the application layer corresponding to the user state is determined, and further screening is performed according to the application layer category to determine the second signal processing behavior; finally, multiple second signal processing behaviors are executed respectively by these multiple first threads to obtain corresponding signal processing results, and the test results of these interrupt test tasks are determined based on the multiple signal processing results.

[0070] The above signal processing behavior is illustrated by examples: when the application layer is NVMe, the content of CQE in the corresponding CQ queue is detected according to the MSl-X interrupt number of the information; when the application layer is Ethernet, a target address is calculated according to the MSI-X interrupt number of the information and other address information (contained in the target information). Optionally, the other address information is used as the base address, and the offset is determined by the interrupt number to determine a target address, and whether the content of the corresponding data packet is correct is detected at the target address.

[0071] It should be noted that NVMe (Non-Volatile Memory Express) is a high-speed serial protocol used to connect hosts and non-volatile storage devices, mainly used for solid-state drives (SSDs). It has significant advantages in performance, energy efficiency and scalability. In NVMe devices, CQ (Command Queue) and CQE (CompletionQueue Entry) are two key concepts, which are used to manage and track command submission and execution results respectively.

[0072] 1. CQ (Command Queue): A command queue is a first-in, first-out (FIFO) data structure used to store commands to be executed. Each NVMe device has one or more command queues. The command queue transmits commands between the device and the host, such as read, write, erase, and other operations. The creation and configuration of the command queue is completed by the NVMe driver or the operating system.

[0073] 2. CQE (Completion Queue Entry): A completion queue entry is a data structure in the completion queue that is used to store the results of command execution. Each CQE contains relevant information about the execution command, such as status code, amount of data transferred, etc. The completion queue is a FIFO structure that is used to store completed commands and their execution results.

[0074] The functions of CQ and CQE are as follows:

[0075] 1. Efficient command management: The command queue allows the host to submit multiple commands to the NVMe device without waiting for the completion of each command. This improves the efficiency of data transmission because the device can process multiple commands in parallel.

[0076] 2. Error handling: The execution results and status codes in CQE can be used to detect errors during command execution. If a command fails, the host can perform error handling based on the information in CQE.

[0077] 3. Asynchronous operation: NVMe devices support asynchronous operation, which means that the host can perform other operations immediately after the command is submitted without waiting for the command to complete. The completion queue item provides tracking of completed operations, allowing the host to query the execution results of the command at the appropriate time.

[0078] 4. Load balancing: In NVMe devices with multiple command queues, the host can distribute commands to different queues to achieve load balancing. This helps improve the performance and stability of the device.

[0079] In summary, CQ and CQE play a key role in NVMe devices, making command management and execution more efficient, flexible, and reliable.

[0080] Through this embodiment, the user state binds a signal processing task to each interrupt channel based on a pre-configured verification scheme, and then triggers the corresponding signal processing task after receiving the signal fed back by the kernel state, so that the user state can accurately know the execution status of the kernel state interrupt test task and summarize the test results.

[0081] Optionally, the kernel state further includes: an interrupt controller, used to generate multiple interrupt vectors, wherein the multiple interrupt vectors are used to indicate the corresponding relationship between multiple kernel state identifiers and multiple interrupt channels.

[0082] After the kernel state is started, it will initialize the MSl-X interrupt controller (that is, the above-mentioned interrupt controller), allocate interrupt vectors, and register MSl-X interrupts. These operations are consistent with the Linux driver and are necessary steps.

[0083] Based on the above steps, the interrupt controller is also used to: when receiving the multiple process identifiers, match multiple first task queues in the multiple task queues of the PCle chip according to the multiple process identifiers; trigger the interrupt test tasks in the multiple first task queues respectively; and call the callback function when the multiple interrupt test tasks are executed.

[0084] After the interrupt controller receives multiple process identifiers sent by the user state, it will determine which first task queues are triggered by the user state based on the process identifiers, and then trigger the interrupt test tasks in the first task queues respectively. When it is determined that the interrupt test task has been completed and successfully, it calls the callback function to send the target information to the user state.

[0085] Optionally, the interrupt controller is further used to: convert the multiple process identifiers into multiple kernel state identifiers; generate multiple target information according to the interrupt number and configuration information, respectively, and send the multiple target information to the user state.

[0086] The callback function can implement its function through the following steps: 1. Convert the PID (process identifier) ​​of the user state into the VPID (kernel state identifier) ​​of the kernel state; 2. Encapsulate valid information, the content of which is user-defined. Define what information to detect in the kernel state according to the information that the user state needs to detect. In addition, encapsulate it together with the interrupt number to obtain the target information, among which the MSI-X interrupt number must be at the head of the information, and the arrangement position of other information in the user state and the kernel state must be consistent; 3. Trigger the signal generator. Assuming that the user state has set up 3 signal processors, which correspond to the processing behaviors of the 3 MSI-X interrupt numbers respectively, when the kernel state receives MSI-X interrupt 1, it triggers signal 1 and sends the encapsulated information to the corresponding VPID. The sending method uses the standard function provided by the operating system. Different signals will trigger different signal processing behaviors bound in the user state sub-thread.

[0087] Through this embodiment, after the MSI-X interrupt is triggered in the kernel state, the corresponding target information is actively sent to the user state, so that the user state can complete the test result analysis, thereby improving the information processing efficiency.

[0088] Through the above embodiment, the user state processes steps such as detecting the test results through multiple sub-threads (i.e. the above-mentioned multiple threads), and the main thread continues to hold the CPU to execute the test code, thereby ensuring the efficient progress of the test work; and realizes the function of verifying different types of chips in the user state. The tester customizes the information required by different protocols in the user state, which is passed to the user state by the asynchronous signal processing mechanism, and implements NVMe / Ethernet and other protocol contents in user state programming, thereby reducing kernel state programming and reducing test complexity.

[0089] The following combination Figure 5 The overall architecture of the interruption test system of the PCIe chip is explained below. Figure 5 The schematic diagram of the architecture of the interrupt test system of the PCIe chip is shown, including user state and kernel state. In the user state, PID is sent to the kernel state through multiple processes (including process 1, process 2, ..., process n), so as to trigger multiple interrupt test tasks at the same time. After receiving the PID, the kernel state executes the corresponding interrupt test task, obtains the corresponding kernel information (i.e., the above-mentioned target information), and returns the kernel information to the user state. The user state analyzes the test situation according to the kernel information to obtain the final test result.

[0090] Optionally, the embodiment of the present application further provides an optional PCIe chip interruption test method, which is applied to user mode. Figure 6 : is a flowchart of a method for interrupting a PCIe chip according to an embodiment of the present application. Figure 6 As shown, the process includes the following steps:

[0091] Step S602, sending multiple process identifiers to the kernel state through multiple threads respectively, wherein the multiple threads correspond to the multiple process identifiers one by one, the multiple threads are all used to execute interrupt test tasks, the multiple process identifiers are used to indicate that the kernel state triggers multiple interrupt test tasks, and when the multiple interrupt test tasks are executed, sending target information corresponding to the multiple interrupt test tasks to the user state through a callback function, the target information at least includes: the interrupt number of the interrupt channel that executes the interrupt test task;

[0092] Step S604: when a plurality of target information are received, determine the test results of the plurality of interruption test tasks according to the plurality of target information.

[0093] Through the above steps, multiple process identifiers are first sent to the kernel state through multiple threads respectively, and the threads correspond to the process identifiers one by one. These threads are all used to execute interrupt test tasks. The multiple process identifiers are used to instruct the kernel state to trigger multiple interrupt test tasks, and instruct the kernel state to send the target information corresponding to these interrupt test tasks to the user state through the callback function after these interrupt test tasks are completed. The target information at least includes the interrupt number of the interrupt channel that executes the interrupt test task; after receiving these target information, the test results of these interrupt test tasks are determined according to these target information; using the above scheme, the tester can make relevant configurations for the MSI-X of the test chip in the user state and detect the test results in the user state, which reduces the programming work in the kernel state and improves the accuracy of detecting expected results; thereby solving the problem in the related technology that the configuration of the test chip is initiated in the user state, different results are expected for different configurations, but the MSI-X interrupt is processed in the kernel state, which increases the difficulty of detecting the expected results.

[0094] Optionally, the method also includes: establishing a binding relationship between multiple interrupt channels and multiple task queues of the PCIe chip, wherein the multiple task queues all store interrupt test tasks; determining a verification method for different interrupt test tasks based on the binding relationship, wherein the verification method is used to determine the test result.

[0095] According to the provisions of the NVMe protocol, the NVMe interface chip will have an Admin CQ queue and a maximum of 2048 IOCQ queues. Each chip design manufacturer will bind the MSl-X interrupt channel and CQ (i.e., the above-mentioned task queue) and support multiple binding methods. Optionally, one Admin CQ queue and n IO CQ queues can be bound to n+1 MSI-X channels respectively, or one Admin CQ queue and n IO CQ queues can be bound to one MSI-X interrupt channel. Different verification schemes (i.e., verification methods) are designed according to different binding methods. The configuration of the DUT is completed in the user state, and the relevant configuration information is recorded to detect the subsequent results.

[0096] Through this embodiment, the DUT related configuration is completed before the interrupt test, and the verification plan is designed, so that the test results can be analyzed accurately according to the verification plan after the test is completed.

[0097] Optionally, the method further includes: configuring signal processing behaviors for the multiple interrupt channels according to the verification method and the interrupt numbers of the multiple interrupt channels to obtain multiple signal processing behaviors, wherein each of the multiple interrupt channels corresponds to at least one signal processing behavior.

[0098] In the embodiment of the present application, an asynchronous signal processor needs to be designed. The processor is provided by the operating system. The asynchronous processing method can release the CPU pressure and will not be actively executed before the signal is triggered. The asynchronous signal processor will bind multiple signal processing behaviors, bind the signal ID (corresponding to the channel number of the interrupt channel) and the signal processing behavior, ID1 corresponds to behavior 1, ID2 corresponds to behavior 2, and so on. The number can be selected according to the verification scheme.

[0099] Through this embodiment, corresponding signal processing behaviors are configured for different interrupt channels respectively. After the corresponding interrupt channel triggers an interrupt, the relevant information of the interrupt channel that triggers the interrupt can be accurately determined according to the triggered behavior.

[0100] Optionally, the method also includes: obtaining, through multiple first threads, the multiple target information sent from the kernel state to the user state through the callback function, respectively, wherein the multiple threads include the multiple first threads, and the multiple first threads correspond one-to-one to the multiple target information; parsing the multiple target information to obtain multiple first interrupt numbers; matching a group of first signal processing behaviors corresponding to each first interrupt number according to the multiple first interrupt numbers, to obtain multiple groups of first signal processing behaviors, wherein each group of first signal processing behaviors includes at least one first signal processing behavior; determining the category of the application layer corresponding to the user state; determining the second signal processing behavior in each group of first signal processing behaviors according to the category of the application layer, to obtain multiple second signal processing behaviors, wherein the multiple first interrupt numbers correspond one-to-one to the multiple second signal processing behaviors; executing the multiple second signal processing behaviors respectively through the multiple first threads to obtain multiple signal processing results; determining the test results of the multiple interrupt test tasks according to the multiple signal processing results.

[0101] After the user state passes the process ID to the kernel state, multiple child threads (i.e., the first threads mentioned above) will wait in the background until they receive multiple target information sent by the kernel state through the callback function; the user state parses the MSl-X interrupt number and other information (i.e., the first interrupt number) from the target information, and then matches the signal processing behavior bound to it according to the interrupt number. Optionally, multiple signal processing behaviors can be bound to one interrupt number, which are applied to different application scenarios, that is, different signal processing behaviors are bound to different application layer categories. Therefore, at least one first signal processing behavior can be matched to one interrupt number, and then the category of the application layer corresponding to the user state is determined, and further screening is performed according to the application layer category to determine the second signal processing behavior; finally, multiple second signal processing behaviors are executed respectively by these multiple first threads to obtain corresponding signal processing results, and the test results of these interrupt test tasks are determined according to the multiple signal processing results.

[0102] The above signal processing behavior is illustrated by examples: when the application layer is NVMe, the content of CQE in the corresponding CQ queue is detected according to the MSI-X interrupt number of the information; when the application layer is Ethernet, a target address is calculated according to the MSI-X interrupt number of the information and other address information (contained in the target information). Optionally, the other address information is used as the base address, and the offset is determined by the interrupt number to determine a target address, and whether the content of the corresponding data packet is correct is detected at the target address.

[0103] Through this embodiment, the user state binds a signal processing task to each interrupt channel based on a pre-configured verification scheme, and then triggers the corresponding signal processing task after receiving the signal fed back by the kernel state, so that the user state can accurately know the execution status of the kernel state interrupt test task and summarize the test results.

[0104] Optionally, the present application embodiment also provides a method for testing an MSI-X interrupt, such as Figure 7 As shown, the test method specifically includes the following steps:

[0105] In this test process, the kernel executes the following steps 7.1-7.6:

[0106] Step 7.1, start;

[0107] Step 7.2: The kernel initializes the MSI-X interrupt controller and allocates interrupt vectors;

[0108] Step 7.3, register MSI-X interrupt and implement interrupt callback function;

[0109] Step 7.4, the kernel state receives the process ID passed in by the user state;

[0110] Step 7.5, receiving PCIe device triggers MSI-X interrupt and executes callback function;

[0111] The process of executing the callback function includes the following steps:

[0112] Step 7.5.1, convert the user state PID into the kernel state VPID;

[0113] Step 7.5.2, encapsulate valid information, including MSI-X interrupt number, etc.;

[0114] Step 7.5.3: trigger the signal generator to send the encapsulated information (i.e. the above-mentioned target information) to the specified VPID.

[0115] Step 7.6, end.

[0116] The user mode performs the following steps:

[0117] Step 8.1, start;

[0118] Step 8.2: Configure the DUT.

[0119] Step 8.3, create and run the child thread;

[0120] Wherein, running the child thread includes the following steps:

[0121] Step 8.3.1, obtain the current process ID (i.e. the above process ID);

[0122] Some verification schemes will have multi-process tests, that is, multiple terminal windows will be opened to execute test cases. Each process has a different ID. In this embodiment, information needs to be transmitted through the process ID, so different test processes need to obtain the ID of the current process in the child thread.

[0123] Step 8.3.2, pass the process ID into kernel state;

[0124] The process ID number is sent to the kernel state through the system call method. In the operating system, the system call (System Call) between the user state and the kernel state is a mechanism that allows the user state program to request the kernel state service of the operating system. Common system call methods include calling encapsulated C library functions and executing specific interrupt instructions in the user state.

[0125] Step 8.3.3: Set up an asynchronous signal handler and bind the signal processing behavior.

[0126] The asynchronous signal processor is provided by the operating system. The asynchronous processing method can release CPU pressure and will not be actively executed before the signal is triggered. Binding signal processing behavior is to bind the signal ID (corresponding to the interrupt number) and the processing behavior. ID1 corresponds to behavior 1, ID2 corresponds to behavior 2, and so on. You can choose the number according to your own verification plan.

[0127] Step 8.4, obtain the information sent by the kernel state to the process (i.e. the above target information);

[0128] Step 8.5, parse the MSI-X interrupt number and other information from the received information, and perform corresponding signal processing actions, such as verification, inspection, etc.;

[0129] Step 8.6, the child thread waits in the background;

[0130] Step 8.7, the main thread continues;

[0131] Step 8.8, end.

[0132] Through this embodiment, the user can freely implement the content specified by the application layer protocol in the user state, which is closer to the verification work; when the kernel receives an interrupt, it actively notifies the kernel state, and there is no need for the user state to query using polling, thus releasing the CPU main process, and more scenarios can be implemented in the test case.

[0133] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0134] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0135] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0136] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0137] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0138] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0139] An embodiment of the present application further provides a computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program product, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0140] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0141] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0142] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A PCIe chip interruption test system, characterized in that: include: The user state is used to send multiple process identifiers to the kernel state through multiple threads, wherein the multiple threads correspond to the multiple process identifiers one by one, and the multiple threads are all used to execute the interrupt test task; The kernel state is used to trigger multiple interrupt test tasks according to the multiple process identifiers, and when the multiple interrupt test tasks are executed, send the target information corresponding to the multiple interrupt test tasks to the user state through a callback function, wherein the target information at least includes: the interrupt number of the interrupt channel that executes the interrupt test task; The user state is also used to determine the test results of the multiple interruption test tasks according to the multiple target information when multiple target information are received.

2. The PCIe chip interruption test system according to claim 1, characterized in that: The user state is also used for: Establishing a binding relationship between a plurality of interrupt channels and a plurality of task queues of the PCIe chip, wherein the plurality of task queues all store interrupt test tasks; Verification methods for different interruption test tasks are determined according to the binding relationship, wherein the verification methods are used to determine the test results.

3. The PCIe chip interruption test system according to claim 2, characterized in that: The user state further includes: An asynchronous signal processor is used to configure signal processing behaviors for the multiple interrupt channels according to the verification method and the interrupt numbers of the multiple interrupt channels to obtain multiple signal processing behaviors, wherein each of the multiple interrupt channels corresponds to at least one signal processing behavior.

4. The PCIe chip interruption test system according to claim 3, characterized in that: The user state is also used for: Respectively acquiring the plurality of target information sent from the kernel state to the user state through the callback function through a plurality of first threads, wherein the plurality of threads include the plurality of first threads, and the plurality of first threads correspond to the plurality of target information one by one; Parsing the plurality of target information to obtain a plurality of first interrupt numbers; Matching a group of first signal processing behaviors corresponding to each first interrupt number according to the multiple first interrupt numbers, to obtain multiple groups of first signal processing behaviors, wherein each group of first signal processing behaviors includes at least one first signal processing behavior; Determine the type of application layer corresponding to the user state; Determine a second signal processing behavior in each group of first signal processing behaviors according to the category of the application layer, to obtain a plurality of second signal processing behaviors, wherein the plurality of first interrupt numbers correspond one to one to the plurality of second signal processing behaviors; Executing the plurality of second signal processing actions respectively by the plurality of first threads to obtain a plurality of signal processing results; The test results of the plurality of interruption test tasks are determined according to the plurality of signal processing results.

5. The PCIe chip interruption test system according to claim 1, characterized in that: The kernel state further includes: The interrupt controller is used to generate a plurality of interrupt vectors, wherein the plurality of interrupt vectors are used to indicate the corresponding relationship between a plurality of kernel state identifiers and a plurality of interrupt channels.

6. The PCIe chip interruption test system according to claim 5, characterized in that: The interrupt controller is further used for: When the multiple process identifiers are received, matching multiple first task queues in multiple task queues of the PCIe chip according to the multiple process identifiers; Triggering the interruption test tasks in the plurality of first task queues respectively; When the execution of the plurality of interruption test tasks is completed, the callback function is called.

7. The PCIe chip interruption test system according to claim 6, characterized in that: The interrupt controller is further used for: Converting the multiple process identifiers into multiple kernel state identifiers; Generate a plurality of target information according to the interrupt number and the configuration information respectively, and send the plurality of target information to the user state.

8. A PCIe chip interruption test method, characterized in that: The user state applied to any one of claims 1 to 7, include: Sending multiple process identifiers to the kernel state through multiple threads respectively, wherein the multiple threads correspond to the multiple process identifiers one by one, the multiple threads are all used to execute interrupt test tasks, the multiple process identifiers are used to instruct the kernel state to trigger multiple interrupt test tasks, and when the multiple interrupt test tasks are executed, sending target information corresponding to the multiple interrupt test tasks to the user state through a callback function, the target information at least includes: an interrupt number of an interrupt channel that executes the interrupt test task; In the case where a plurality of target information are received, the test results of the plurality of interruption test tasks are determined according to the plurality of target information.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in claim 8 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to claim 8 are implemented.

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