Function-level software simulation model and chip hardware architecture performance evaluation method

Abstract

The invention relates to chip simulation and performance evaluation, in particular to a function-level software simulation model and a chip hardware architecture performance evaluation method, the function-level software simulation model does not have a periodic concept, and each instruction only has a completed state and a non-executed state; in the chip hardware architecture performance evaluation method, the number of execution cycles of a single instruction is estimated according to a calculation cycle, a memory access cycle and a pipeline cycle; according to the execution cycle number of the single instruction, the execution cycle number of the multiple instruction queues with the dependency relationship in the execution sequence is estimated, and the total execution cycle number is obtained; evaluating the performance of the chip hardware architecture according to the total execution cycle number; according to the technical scheme, the defects that in the prior art, the development and verification period of a clock period level software simulation model is long, and the number of execution periods of multiple instruction queues is difficult to accurately estimate on the basis that no period concept exists can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to chip simulation and performance evaluation, and in particular to a function-level software simulation model and a chip hardware architecture performance evaluation method. Background Art

[0002] Chip simulation models are an indispensable part of the modern processor design process, mainly including software simulation models and hardware simulation models. Software simulation models are generally developed based on open source frameworks such as SystemC and other high-level languages. Hardware simulation models are generally established in Verilog / SystemVerilog / VHDL languages. They can be converted into netlists and GDSII layouts after back-end processing, and are the specific representation of chip front-end design.

[0003] In the process of chip development, software simulation models play an important role. For example, in chip structure design, software simulation models can be used as a tool to evaluate the performance of hardware architecture; in chip function verification, software simulation models can be used as a tool to verify the correctness of chip hardware design functions and simulate chip instructions; in the process of chip-related software development, software simulation models can be used as software debugging tools before the actual chip hardware system is developed, so that software and hardware design can be carried out simultaneously.

[0004] Traditional software simulation models are generally accurate in clock cycles, that is, the software simulation model maintains the clock internally, and the clock is also divided into rising and falling edges. A software simulation model with accurate clock cycles needs to ensure that the state of each cycle is consistent with the hardware simulation model during the execution of instructions. This requires the software simulation model to model the chip with high precision, including but not limited to the same instruction fetch and decode logic, the same pipeline length, the same control logic, the same instruction execution process, etc.

[0005] The high precision of the software simulation model with accurate clock cycle can play a huge role in chip verification. It can accurately locate the location of errors during verification, so as to quickly discover and solve problems in the chip verification process. However, the software simulation model with accurate clock cycle also has many disadvantages. Because of the high precision requirement, the development and verification of the software simulation model requires a lot of time and manpower costs. In large-scale chip R&D projects, the development and verification time can even be measured in years. In addition, due to the existence of the pipeline, the software simulation model runs slowly. When the instruction scale is large, this disadvantage is more obvious.

[0006] Traditional clock cycle-level software simulation models require the establishment of a sophisticated pipeline model, such as Figure 3As shown in the figure, the pipeline model also needs to complete pipeline control logic such as flush, stall, branch prediction, jump, interrupt, etc. In addition, in order to make the timing of the chip meet the design requirements, there will be different data read and write times for different types of instruction cores, which in turn involves data correlation and forward push logic. These logics are difficult in the modeling process of software simulation models, and usually take a lot of time to verify. When multiple situations are combined, such as data forward push at the same time as branch jumps, the pressure of verification will be even greater.

[0007] For AI acceleration cores (NNA, Neural Network Accelerator) used in intelligent computing and designed specifically for deep learning computing, the main function of this core is to realize deep neural network model reasoning calculations, input preprocessing and output post-processing, as well as common processing of signals, images and video frames, and at the same time have certain data computing capabilities in vector and matrix form. An instruction of the AI ​​acceleration core NNA may require multi-level loop calculations, and the execution cycle can reach millions of cycles. If a clock cycle-level software simulation model is established, the workload will be huge. Summary of the invention

[0008] 1. Technical issues to be resolved

[0009] In view of the above-mentioned shortcomings of the prior art, the present invention provides a functional-level software simulation model and a chip hardware architecture performance evaluation method, which can effectively overcome the defects of the prior art in that the development and verification cycle of the clock cycle-level software simulation model is long, and it is difficult to accurately estimate the number of execution cycles of multiple instruction queues without the concept of cycles.

[0010] (II) Technical solution

[0011] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0012] A function-level software simulation model, wherein the function-level software simulation model has no concept of cycles, each instruction has only two states: completed and unexecuted, and correspondingly, the pipeline has only one stage, and the instruction fetching, decoding, calculation, and writing back processes are all executed sequentially in the one stage of the pipeline;

[0013] For the instruction stream executed in normal order, it is only necessary to ensure that the PC increases normally when the instruction is fetched; for jump instructions or interrupts, it is only necessary to modify the PC when the instruction is fetched to the destination PC;

[0014] After decoding, the functions corresponding to different instructions are called according to the opcode to achieve data fetching, calculation and writing back;

[0015] Among them, the registers and memory of the function-level software simulation model have left values ​​and right values ​​like the clock cycle-level software simulation model. The right value is used for data retrieval during operation, and the left value is written back. The registers and memory will only be flipped after all instructions in the current instruction line are executed.

[0016] Preferably, when the function-level software simulation model is applied to the AI ​​acceleration core NNA, in order to improve the execution efficiency of instructions, multiple instruction queues are designed internally. If there is no dependency relationship between the instructions in the instruction queue, the instructions in the instruction queue can be executed in parallel; if there is a dependency relationship between the instructions in the instruction queue, the dependent instruction needs to wait until the dependent instruction is executed before it can be executed;

[0017] Among them, the instruction queues include matrix, vector, store, load, l2_store and l2_load. The matrix and vector instruction queues mainly include computing instructions, and the store, load, l2_store and l2_load instruction queues mainly include memory access instructions.

[0018] A chip hardware architecture performance evaluation method comprises the following steps:

[0019] S1. Estimate the number of execution cycles of a single instruction based on the calculation cycle, memory access cycle and pipeline cycle;

[0020] S2. Estimate the number of execution cycles of multiple instruction queues whose execution order has a dependency relationship according to the number of execution cycles of a single instruction, and obtain the total number of execution cycles;

[0021] S3. Evaluate the chip hardware architecture performance based on the total number of execution cycles.

[0022] Preferably, in the function-level software simulation model of the AI ​​acceleration core NNA, the method for estimating the computing cycle of a single instruction includes:

[0023] For the matrix instruction, this instruction is used to control the matrix module to perform matrix multiplication and two-dimensional convolution calculation. The calculation process includes multiple layers of loops and a large amount of data memory access. The innermost loop includes the dot multiplication and accumulation of the ACC array. The execution time of this instruction is related to the number of loops and the amount of data in the multiple layers of loops.

[0024] Since the final operation of the matrix instruction is data multiplication and addition, the estimation of its calculation cycle can be converted into the estimation of the number of calculations and the number of cycles used for a single multiplication and addition;

[0025] Among them, the number of calculations is obtained after instruction decoding, and the number of cycles used for a single multiplication and addition is given by the hardware front-end designer at the beginning of development.

[0026] Preferably, in the function-level software simulation model of the AI ​​acceleration core NNA, the method for estimating the memory access cycle of a single instruction includes:

[0027] By estimating the amount of memory access data, data path width, and bus bandwidth utilization, the memory access cycle Time of a single instruction is obtained:

[0028] Time=(x_size*y_size*channel*batch_size) / bandwidth_rate;

[0029] Among them, x_size and y_size represent the length and width of the sample image used for model training, respectively; channel represents the number of channels of the sample image; batch_size represents the number of training sample images; and bandwidth_rate represents the bus bandwidth utilization configured by the developer.

[0030] Preferably, the bus bandwidth utilization cannot be determined in the modeling stage and is closely related to the real-time task load of the SoC chip. When there are busy CPU software tasks in the system, as well as network communication, video encoding and decoding, and file operation tasks, the bandwidth utilization of the AI ​​acceleration core NNA memory access instructions is low; when only the AI ​​acceleration core NNA is working in the system, the bandwidth utilization of the AI ​​acceleration core NNA memory access instructions is high;

[0031] In the functional-level software simulation model of the AI ​​accelerator core NNA, the bus bandwidth utilization is set as a configurable parameter and passed to the software simulator through the command line. Developers configure the bus bandwidth utilization and estimate the performance of the AI ​​accelerator core NNA under different SoC chip task loads.

[0032] Preferably, in the function-level software simulation model of the AI ​​acceleration core NNA, the method for estimating the pipeline cycle of a single instruction includes:

[0033] By estimating around the pipeline length, the pipeline cycle of a single instruction is obtained;

[0034] Among them, the pipeline cycle is generally a small fixed value, which has little impact on the estimated number of execution cycles of a single instruction.

[0035] Preferably, in S2, the execution cycle numbers of multiple instruction queues having a dependent execution order are estimated according to the execution cycle number of a single instruction to obtain the overall execution cycle number, including:

[0036] When performing software simulation modeling, the C++ systemc framework is used. The framework maintains a master clock internally, and the clock is shared among modules.

[0037] When performing function-level modeling, since there is no concept of cycles, the execution cycle of a single instruction is taken as 1 clock cycle. After the execution of the instruction is completed, the execution cycle of the instruction is estimated through the encapsulated method, and the sc_core::next_trigger function provided by systemc is called to put the corresponding instruction queue into a "sleep" state. Other instruction queues that have no dependency on the instruction queue work normally, and other instruction queues that have a dependency on the instruction queue enter a waiting "idle" state. After several waiting cycles, the notification information of the instruction queue is sent;

[0038] After all instructions are executed, the total execution cycle number is obtained through the main clock;

[0039] The number of waiting cycles is determined by the number of execution cycles of the instruction.

[0040] Preferably, in S2, the execution cycle numbers of multiple instruction queues having a dependent execution order are estimated according to the execution cycle number of a single instruction to obtain the overall execution cycle number, including:

[0041] When there are only two instruction queues L1 and L2 designed inside the AI ​​acceleration core NNA, and there is no dependency between the instruction I1(n) to be executed in the instruction queue L1 and the instruction I2(n) to be executed in the instruction queue L2, the execution cycle number C1(n) of the instruction I1(n) is inserted into V1. After all instructions are executed, max[sum(V1),sum(V2)] is the total execution cycle number.

[0042] When only two instruction queues L1 and L2 are designed inside the AI ​​accelerator core NNA, and there is a dependency between the instruction I1(n) to be executed in the instruction queue L1 and the instruction I2(n) to be executed in the instruction queue L2, the size of sum[C2(0), C2(1), …, C2(n)] and sum(V1) is determined as follows:

[0043] If sum[C2(0), C2(1), …, C2(n)] < sum(V1), then insert the execution cycle number C1(n) of instruction I1(n) into V1;

[0044] If sum[C2(0),C2(1),…,C2(n)]≥sum(V1), then clear V1, insert sum[C2(0),C2(1),…,C2(n)] into V1, and then insert the execution cycle number C1(n) of instruction I1(n) into V1;

[0045] After all instructions are executed, max[sum(V1),sum(V2)] is the total number of execution cycles;

[0046] Among them, V1 and V2 are containers for the instruction queues L1 and L2 to store the execution cycle numbers of each instruction, C1(n) and C2(n) are the execution cycle numbers corresponding to the instructions I1(n) and I2(n), max[·] represents the maximum value function, and sum[·] represents the summation function.

[0047] (III) Beneficial effects

[0048] Compared with the prior art, the functional level software simulation model and chip hardware architecture performance evaluation method provided by the present invention have the following beneficial effects:

[0049] 1) The development process is short and simple. A relatively complete functional-level software simulation model can be formed in the early stage of determining the instruction set and design scheme, which is convenient for the early hardware architecture performance evaluation and algorithm development;

[0050] 2) Convenient verification and improvement. Whether it is the functional correctness verification of the functional-level software simulation model itself or the instruction-level verification between the hardware front-end model, the verification results can be obtained quickly.

[0051] 3) Fast running speed and simple deployment. The running speed of the function-level software simulator can be increased by 50 to 70 times compared with the cycle-level software simulator. In the function-level software simulation model of the AI ​​acceleration core NNA, since the execution cycle of a single instruction can reach millions of cycles, this running speed advantage will be more obvious;

[0052] 4) Two methods for estimating the execution time of multiple instruction queues in the functional-level software simulation model of the AI ​​accelerator core NNA are given. These two methods can "reverse-label" the overall execution time of multiple instruction queues through the instruction execution time formula estimated by hardware personnel, and can accurately estimate the execution time of software programs. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 A schematic diagram of the instruction queue dependency relationship of the AI ​​acceleration core NNA in the present invention;

[0055] Figure 2 A flowchart of estimating the number of execution cycles of multiple instruction queues having a dependency on the execution order in the present invention to obtain the number of overall execution cycles;

[0056] Figure 3 Schematic diagram of the pipeline model established for the traditional clock cycle level software simulation model. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] A function-level software simulation model, in which there is no concept of cycles. Each instruction has only two states: completed and unexecuted. Correspondingly, the pipeline has only one stage, and the instruction fetching, decoding, calculation, and writing back processes are all executed sequentially in the pipeline stage.

[0059] For the instruction stream executed in normal order, it is only necessary to ensure that the PC increases normally when the instruction is fetched; for jump instructions or interrupts, it is only necessary to modify the PC when the instruction is fetched to the destination PC;

[0060] After decoding, the functions corresponding to different instructions are called according to the opcode to achieve data fetching, calculation and writing back;

[0061] Among them, the registers and memory of the function-level software simulation model have left values ​​and right values ​​just like the clock cycle-level software simulation model. The right value is used for data fetching during operation, and the left value is written back. The registers and memory are flipped only after all instructions in the current instruction line have been executed.

[0062] When the function-level software simulation model is applied to the AI ​​accelerator core NNA, multiple instruction queues are designed internally to improve the execution efficiency of instructions, such as Figure 1 As shown, if there is no dependency relationship between the instructions in the instruction queue, the instructions in the instruction queue can be executed in parallel; if there is a dependency relationship between the instructions in the instruction queue, the dependent instruction must wait until the dependent instruction is executed before it can be executed;

[0063] Among them, the instruction queues include matrix, vector, store, load, l2_store and l2_load. The matrix and vector instruction queues mainly include computing instructions, and the store, load, l2_store and l2_load instruction queues mainly include memory access instructions.

[0064] In the technical solution of this application, the function-level software simulation model can only perform instruction-level verification with the hardware front-end model during verification. Since the hardware front-end model generally has multiple write-back opportunities, the instruction write-back information of other instruction lines will affect the register and memory status, so it is impossible to compare and verify the register and memory status after each instruction line is executed. The instruction-level verification between the function-level software simulation model and the hardware front-end model includes the following two methods:

[0065] 1) After all instructions are executed, compare and verify the register and memory status;

[0066] 2) Add multiple nop instructions after the instruction line that needs to compare and verify the register and memory status. The number is determined by the pipeline length.

[0067] In the technical solution of this application, on the basis of disclosing the above-mentioned function-level software simulation model, a chip hardware architecture performance evaluation method is also disclosed, including the following steps:

[0068] S1. Estimate the number of execution cycles of a single instruction based on the calculation cycle, memory access cycle and pipeline cycle;

[0069] S2. Estimate the number of execution cycles of multiple instruction queues whose execution order has a dependency relationship according to the number of execution cycles of a single instruction, and obtain the total number of execution cycles;

[0070] S3. Evaluate the chip hardware architecture performance based on the total number of execution cycles.

[0071] Functional-level software simulation models can be used as a tool to evaluate the performance of hardware architectures, and the performance evaluation criteria largely depend on the instruction execution time of the model. For the functional-level software simulation model of the AI ​​accelerator NNA, since there is no concept of cycles, the performance of the hardware architecture can only be evaluated by estimation. The estimation mainly revolves around the number of execution cycles of a single instruction, which includes calculation cycles, memory access cycles, and pipeline cycles.

[0072] ① In the functional-level software simulation model of the AI ​​accelerator core NNA, the estimation method of the calculation cycle of a single instruction includes:

[0073] For the matrix instruction, this instruction is used to control the matrix module to perform matrix multiplication and two-dimensional convolution calculation. The calculation process includes multiple layers of loops and a large amount of data memory access. The innermost loop includes the dot multiplication and accumulation of the ACC array. The execution time of this instruction is related to the number of loops and the amount of data in the multiple layers of loops.

[0074] Since the final operation of the matrix instruction is data multiplication and addition, the estimation of its calculation cycle can be converted into the estimation of the number of calculations and the number of cycles used for a single multiplication and addition;

[0075] Among them, the number of calculations is obtained after instruction decoding, and the number of cycles used for a single multiplication and addition is given by the hardware front-end designer at the beginning of development.

[0076] ② In the functional-level software simulation model of the AI ​​acceleration core NNA, the estimation method of the memory access cycle of a single instruction includes:

[0077] By estimating the amount of memory access data, data path width, and bus bandwidth utilization, the memory access cycle Time of a single instruction is obtained:

[0078] Time=(x_size*y_size*channel*batch_size) / bandwidth_rate;

[0079] Among them, x_size and y_size represent the length and width of the sample image used for model training, respectively; channel represents the number of channels of the sample image; batch_size represents the number of training sample images; and bandwidth_rate represents the bus bandwidth utilization configured by the developer.

[0080] The bus bandwidth utilization cannot be determined in the modeling stage and is closely related to the real-time task load of the SoC chip. When there are busy CPU software tasks in the system, as well as network communication, video encoding and decoding, and file operation tasks, the bandwidth utilization of the AI ​​acceleration core NNA memory access instructions is low; when only the AI ​​acceleration core NNA is working in the system, the bandwidth utilization of the AI ​​acceleration core NNA memory access instructions is high;

[0081] In the functional-level software simulation model of the AI ​​accelerator core NNA, the bus bandwidth utilization is set as a configurable parameter and passed to the software simulator through the command line. Developers configure the bus bandwidth utilization and estimate the performance of the AI ​​accelerator core NNA under different SoC chip task loads.

[0082] ③ In the functional-level software simulation model of the AI ​​acceleration core NNA, the estimation method of the pipeline cycle of a single instruction includes:

[0083] By estimating around the pipeline length, the pipeline cycle of a single instruction is obtained;

[0084] Among them, the pipeline cycle is generally a small fixed value, which has little impact on the estimated number of execution cycles of a single instruction.

[0085] When the AI ​​accelerator NNA runs a real program, estimating the execution cycle number of a single instruction is far from enough to estimate the execution time of the software program. Since the AI ​​accelerator NNA contains multiple independent, parallel execution instruction queues, and there is a dependency relationship between the execution order of each instruction queue, the relationship between instructions is neither completely parallel nor completely serial. Therefore, when estimating the overall execution cycle number, it is also necessary to fully consider the execution order of instructions, which has a huge impact on the final estimation result.

[0086] ④ In S2, based on the execution cycle number of a single instruction, the execution cycle number of multiple instruction queues with a dependent execution order is estimated to obtain the overall execution cycle number, including the following two methods:

[0087] 1) When performing software simulation modeling, the C++ systemc framework is used. The framework maintains a master clock internally and the clock is shared among modules;

[0088] When performing function-level modeling, since there is no concept of cycles, the execution cycle of a single instruction is taken as 1 clock cycle. After the execution of the instruction is completed, the execution cycle of the instruction is estimated through the encapsulated method, and the sc_core::next_trigger function provided by systemc is called to put the corresponding instruction queue into a "sleep" state. Other instruction queues that have no dependency on the instruction queue work normally, and other instruction queues that have a dependency on the instruction queue enter a waiting "idle" state. After several waiting cycles, the notification information of the instruction queue is sent;

[0089] After all instructions are executed, the total execution cycle number is obtained through the main clock;

[0090] Among them, the number of waiting cycles is determined by the number of execution cycles of the instruction;

[0091] 2) If Figure 2 As shown in the figure, when there are only two instruction queues L1 and L2 designed inside the AI ​​acceleration core NNA, and there is no dependency between the instruction I1(n) to be executed in the instruction queue L1 and the instruction I2(n) to be executed in the instruction queue L2, the execution cycle number C1(n) of the instruction I1(n) is inserted into V1. After all instructions are executed, max[sum(V1),sum(V2)] is the total execution cycle number;

[0092] When only two instruction queues L1 and L2 are designed inside the AI ​​accelerator core NNA, and there is a dependency between the instruction I1(n) to be executed in the instruction queue L1 and the instruction I2(n) to be executed in the instruction queue L2, the size of sum[C2(0), C2(1), …, C2(n)] and sum(V1) is determined as follows:

[0093] If sum[C2(0), C2(1), …, C2(n)] < sum(V1), then insert the execution cycle number C1(n) of instruction I1(n) into V1;

[0094] If sum[C2(0),C2(1),…,C2(n)]≥sum(V1), then clear V1, insert sum[C2(0),C2(1),…,C2(n)] into V1, and then insert the execution cycle number C1(n) of instruction I1(n) into V1;

[0095] After all instructions are executed, max[sum(V1),sum(V2)] is the total number of execution cycles;

[0096] Among them, V1 and V2 are containers for the instruction queues L1 and L2 to store the execution cycle numbers of each instruction, C1(n) and C2(n) are the execution cycle numbers corresponding to the instructions I1(n) and I2(n), max[·] represents the maximum value function, and sum[·] represents the summation function.

[0097] The difference between the total execution cycle number estimated by the above two methods through "reverse labeling" and the actual execution cycle number is very small, which can be used as a standard for evaluating the performance of hardware architecture. By changing the parameters of the hardware architecture, such as data path width, number of ACCs, etc., the total execution cycle number of the software simulation model under different parameters is estimated, so that the performance of various types of hardware architectures can be quickly and accurately evaluated.

[0098] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A function-level software simulation model, characterized in that: The functional level software simulation model has no concept of cycles. Each instruction has only two states: completed and unexecuted. Correspondingly, the pipeline has only one level, and the instruction fetching, decoding, calculation, and writing back processes are all executed sequentially in the pipeline level. For the instruction stream executed in normal order, it is only necessary to ensure that the PC increases normally when the instruction is fetched; for jump instructions or interrupts, it is only necessary to modify the PC when the instruction is fetched to the destination PC; After decoding, the functions corresponding to different instructions are called according to the opcode to achieve data fetching, calculation and writing back; Among them, the registers and memory of the function-level software simulation model have left values ​​and right values ​​like the clock cycle-level software simulation model. The right value is used for data retrieval during operation, and the left value is written back. The registers and memory will only be flipped after all instructions in the current instruction line are executed.

2. The function-level software simulation model according to claim 1, characterized in that: When the function-level software simulation model is applied to the AI ​​acceleration core NNA, in order to improve the execution efficiency of instructions, multiple instruction queues are designed internally. If there is no dependency between the instructions in the instruction queue, the instructions in the instruction queue can be executed in parallel; if there is a dependency between the instructions in the instruction queue, the dependent instruction must wait until the dependent instruction is executed before it can be executed; Among them, the instruction queues include matrix, vector, store, load, l2_store and l2_load. The matrix and vector instruction queues mainly include computing instructions, and the store, load, l2_store and l2_load instruction queues mainly include memory access instructions.

3. A chip hardware architecture performance evaluation method, applied to the function-level software simulation model of claim 1, characterized in that: The following steps are involved: S1. Estimate the number of execution cycles of a single instruction based on the calculation cycle, memory access cycle and pipeline cycle; S2. Estimate the number of execution cycles of multiple instruction queues whose execution order has a dependency relationship according to the number of execution cycles of a single instruction, and obtain the total number of execution cycles; S3. Evaluate the chip hardware architecture performance based on the total number of execution cycles.

4. The chip hardware architecture performance evaluation method according to claim 3, characterized in that: In the function-level software simulation model of the AI ​​acceleration core NNA, the estimation method of the calculation cycle of a single instruction includes: For the matrix instruction, this instruction is used to control the matrix module to perform matrix multiplication and two-dimensional convolution calculation. The calculation process includes multiple layers of loops and a large amount of data memory access. The innermost loop includes the dot multiplication and accumulation of the ACC array. The execution time of this instruction is related to the number of loops and the amount of data in the multiple layers of loops. Since the final operation of the matrix instruction is data multiplication and addition, the estimation of its calculation cycle can be converted into the estimation of the number of calculations and the number of cycles used for a single multiplication and addition; Among them, the number of calculations is obtained after instruction decoding, and the number of cycles used for a single multiplication and addition is given by the hardware front-end designer at the beginning of development.

5. The chip hardware architecture performance evaluation method according to claim 4, characterized in that: In the functional-level software simulation model of the AI ​​acceleration core NNA, the estimation method of the memory access cycle of a single instruction includes: By estimating the amount of memory access data, data path width, and bus bandwidth utilization, the memory access cycle Time of a single instruction is obtained: Time=(x_size*y_size*channel*batch_size) / bandwidth_rate; Among them, x_size and y_size represent the length and width of the sample image used for model training, respectively; channel represents the number of channels of the sample image; batch_size represents the number of training sample images; and bandwidth_rate represents the bus bandwidth utilization configured by the developer.

6. The chip hardware architecture performance evaluation method according to claim 5, characterized in that: The bus bandwidth utilization cannot be determined in the modeling stage and is closely related to the real-time task load of the SoC chip. When there are busy CPU software tasks in the system, as well as network communication, video encoding and decoding, and file operation tasks, the bandwidth utilization of the AI ​​acceleration core NNA memory access instructions is low; when only the AI ​​acceleration core NNA is working in the system, the bandwidth utilization of the AI ​​acceleration core NNA memory access instructions is high. In the functional-level software simulation model of the AI ​​accelerator core NNA, the bus bandwidth utilization is set as a configurable parameter and passed to the software simulator through the command line. Developers configure the bus bandwidth utilization and estimate the performance of the AI ​​accelerator core NNA under different SoC chip task loads.

7. The chip hardware architecture performance evaluation method according to claim 5, characterized in that: In the functional-level software simulation model of the AI ​​acceleration core NNA, the estimation method of the pipeline cycle of a single instruction includes: By estimating around the pipeline length, the pipeline cycle of a single instruction is obtained; Among them, the pipeline cycle is generally a small fixed value, which has little impact on the estimated number of execution cycles of a single instruction.

8. The chip hardware architecture performance evaluation method according to claim 7, characterized in that: In S2, the execution cycles of multiple instruction queues with a dependent execution order are estimated based on the execution cycle number of a single instruction, and the overall execution cycle number is obtained, including: When performing software simulation modeling, the C++ systemc framework is used. The framework maintains a master clock internally, and the clock is shared among modules. When performing function-level modeling, since there is no concept of cycles, the execution cycle of a single instruction is taken as 1 clock cycle. After the execution of the instruction is completed, the execution cycle of the instruction is estimated through the encapsulated method, and the sc_core::next_trigger function provided by systemc is called to put the corresponding instruction queue into a "sleep" state. Other instruction queues that have no dependency on the instruction queue work normally, and other instruction queues that have a dependency on the instruction queue enter a waiting "idle" state. After several waiting cycles, the notification information of the instruction queue is sent; After all instructions are executed, the total execution cycle number is obtained through the main clock; The number of waiting cycles is determined by the number of execution cycles of the instruction.

9. The chip hardware architecture performance evaluation method according to claim 7, characterized in that: In S2, the execution cycles of multiple instruction queues with a dependent execution order are estimated based on the execution cycle number of a single instruction, and the overall execution cycle number is obtained, including: When there are only two instruction queues L1 and L2 designed inside the AI ​​acceleration core NNA, and there is no dependency between the instruction I1(n) to be executed in the instruction queue L1 and the instruction I2(n) to be executed in the instruction queue L2, the execution cycle number C1(n) of the instruction I1(n) is inserted into V1. After all instructions are executed, max[sum(V1),sum(V2)] is the total execution cycle number. When only two instruction queues L1 and L2 are designed inside the AI ​​accelerator core NNA, and there is a dependency between the instruction I1(n) to be executed in the instruction queue L1 and the instruction I2(n) to be executed in the instruction queue L2, the size of sum[C2(0), C2(1), …, C2(n)] and sum(V1) is determined as follows: If sum[C2(0), C2(1), …, C2(n)] < sum(V1), then insert the execution cycle number C1(n) of instruction I1(n) into V1; If sum[C2(0),C2(1),…,C2(n)]≥sum(V1), then clear V1, insert sum[C2(0),C2(1),…,C2(n)] into V1, and then insert the execution cycle number C1(n) of instruction I1(n) into V1; After all instructions are executed, max[sum(V1),sum(V2)] is the total number of execution cycles; Among them, V1 and V2 are containers for the instruction queues L1 and L2 to store the execution cycle numbers of each instruction, C1(n) and C2(n) are the execution cycle numbers corresponding to the instructions I1(n) and I2(n), max[·] represents the maximum value function, and sum[·] represents the summation function.

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