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735results about How to "Avoid resources" patented technology

Wireless access point working channel selecting method and device

The invention provides a wireless access point working channel selecting method and a wireless access point working channel selecting device. The wireless access point working channel selecting method comprises the following steps of: periodically transmitting broadcast signals outwards from an AP which is positioned in a working state; determining the interference level of an adjacent AP according to the signal strength by the AP receiving the broadcast signals; calculating the channel spacing between the working channel used by the adjacent AP and the working channel used by the AP; determining the corresponding interference degree according to the channel spacing and the preset channel spacing and an interference degree comparison table; multiplying the interference level by the interference degree to obtain the distribution information of the interference value; and selecting the working channel with the minimum interference value according to the interference distribution information. The wireless access point working channel selecting method and the wireless access point working channel selecting device can reduce the channel interference and improve the system capacity, does not need to occupy a common channel, avoids the resource waste, can be applied to the common fat AP framework and thin AP framework in the wireless local area network simultaneously, and has wide applicability.
Owner:BEIJING XINWANG RUIJIE NETWORK TECH CO LTD

Instruction classified multi-emitting method based on SPRAC V8 instruction set

The invention provides an instruction classified multi-emitting method based on an SPRAC V8 (Scalable Processor Architecture V8) instruction set. According to the method, SPARC V8 instructions are divided into four classes; an SPRAC V8 processor is divided into five flow stages including an instruction fetching stage, a decoding stage, an execution stage, a memory accessing stage and a writing-back stage; the five flow stages are connected through a common data bus; (n-1) instruction fetching paths are added at the instruction fetching stage; (n-1) decoding units are added at the decoding stage; n groups of reservation stations are added between the decoding stage and the execution stage; reordering buffer regions are added between the execution stage and the memory accessing stage; corresponding execution units are added in the execution stage; a multi-emitting five-stage flow line structure is built for the SPRAC V8 processor; the conflict among parallel instructions is detected through the reservation stations; different instructions are processed through different execution units; finally, the instruction execution results are sequentially submitted by the reordering buffer regions; the parallel execution of the instructions is realized; and the processing performance of the SPRAC V8 processor is improved.
Owner:BEIJING MXTRONICS CORP +1
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