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Method for parallel data processing adopting multi- password chip

A data processing and multi-password technology, applied in the field of data encryption and decryption, can solve problems such as system unavailability, resource occupation, system processing performance decline, etc., to avoid insufficient PCI bus resources and interrupt resources, and improve encryption and decryption speed.

Inactive Publication Date: 2008-10-22
STATE GRID ELECTRIC POWER RES INST +1
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  • Summary
  • Abstract
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Problems solved by technology

However, this method usually requires the use of a very high-performance CPU system, and at the same time needs to customize multiple PCI interfaces, which reduces the flexibility of system design, and with the linear increase in the number of cryptographic cards, the resources of the system CPU will be completely occupied. Causes the processing performance of the system to drop rapidly, causing the system to be unavailable

Method used

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  • Method for parallel data processing adopting multi- password chip

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Embodiment Construction

[0037] Below in conjunction with accompanying drawing and embodiment the present invention will be further described:

[0038] from figure 1 , figure 2 It can be seen that a parallel data processing device based on multiple cipher chips consists of multiple symmetric encryption chips to form multiple encryption and decryption channels, and the interface control circuit controls the timing of the encryption chips. The PCI bus expansion chip is used to expand a PCI BUS1, avoiding the lack of load capacity of the PCI BUS0 device on the host platform. On the PCI BUS1, a plurality of DSP processor chips are connected, and the chips are used to complete the IO processing of the parallel multi-channel encryption chips.

[0039] There is a 64K internal data RAM in the DSP chip, and the host host can access the RAM in a burst mode through the PCI bus, and the DSP has the PCI Master capability. In the actual software design, the CPU puts the original data in a piece of local memory,...

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Abstract

The invention relates to a data encryption and decryption technology, in particular to a method adopting the parallel data processing of multi-crypto chips to improve the encryption and decryption speed of a system. A parallel data processing unit for the multi-crypto chips and a high-speed encryption method for the data have the following advantages that: the operation of the system does not occupy extra resource of a main CPU, all the encryption and decryption operations are performed in a DSP processor, and the extreme improvement of the encryption and decryption speed is realized through the parallel processing of a plurality of crypto chips and the DSP.

Description

Technical field: [0001] The invention relates to data encryption and decryption technology, in particular to a method for improving system encryption and decryption speed by adopting multi-cipher chips for parallel data processing. Background technique: [0002] The efficiency of cryptographic processing has always been a restrictive factor in the use of cryptographic algorithms. Using domestic cryptographic chips instead of software to implement cryptographic algorithms is an effective way to improve cryptographic processing performance. Due to the influence of various factors such as design technology and production level of domestic chips, the data processing speed of cryptographic chips is still far from meeting the rapid growth of large-scale security application needs. At present, there are two commonly used methods for improving the processing speed of cryptographic operations. One is to use multiple cryptographic cards with PIC interfaces, so that in a system with a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38H04L9/00
Inventor 俞刚林峰
Owner STATE GRID ELECTRIC POWER RES INST
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