4 results about "Re-order buffer" patented technology

The invention discloses a CPU security defense method and device and electronic equipment, and relates to the technical field of computer system security. According to the method, a risk score is calculated through a long-short-term memory network model based on a branch historical vector generated in a speculative execution process of a CPU and a to-be-fetched instruction address; if the to-be-fetched instruction address falls into a predefined sensitive address range and the risk score exceeds a dynamic risk threshold value, generating a pollution mark for the microoperation of accessing the sensitive address; in response to the pollution marker, performing a pollution operation on the microarchitecture component; and when the micro-operation is submitted or cancelled by the reordering buffer area, triggering a pollution clearing operation on the micro-architecture component to finish the security defense of the CPU. According to the method, the protection capability on transient execution type attacks is remarkably improved, so that the resistance of a processor to side channel and transient information leakage risks is enhanced, and the safety and reliability of system operation are improved.

The application discloses a memory access queue management method and device, electronic equipment and a readable storage medium. The method comprises the following steps: in the case of receiving a micro-operation, allocating a first table item for the micro-operation and an index for each memory access request in the micro-operation in a first queue; in the case that the memory access request is ready, allocating a second table item for the memory access request in a second queue according to the index; in the case that the instruction to which the micro-operation belongs is submitted in a reordering buffer, releasing the first table item and the second table item, which can realize allocating multiple physical table items for a micro-operation and improve the use efficiency of the physical table items.

This document describes systems and techniques for a low-latency bridge to support out-of-order execution. The described systems and techniques can facilitate out-of-order execution by a memory controller of in-order transaction requests. When it receives transaction responses associated with in-order transaction requests, the bridge can send a first transaction response without storing it in a reorder buffer. Similarly, the bridge can determine whether a next transaction response is available to send to the respective client. The bridge introduces latency to a larger system (e.g., an SoC) only when a secondary response (e.g., not first) of in-order transaction responses is received first. In this way, the memory controller can process transaction requests from one or more clients with minimal latency introduced by the bridge and a smaller reorder buffer.

The invention provides an instruction compression method and device, a processor core and computer equipment, and relates to the technical field of data compression. The instruction compression method comprises the steps of obtaining a plurality of micro-operations corresponding to at least one instruction in a current period; according to the execution unit type corresponding to each of the plurality of microoperations and a plurality of preset compression types, determining a plurality of compression modes for the plurality of microoperations; according to the compression lengths of the various compression modes, selecting a target compression mode from the various compression modes; and compressing the plurality of microoperations into the reordering buffer area by adopting a target compression mode. According to the method, multiple compression modes with the high coverage rate are determined based on execution unit types corresponding to the microoperations and multiple preset compression types, then an optimal target compression mode is determined from the multiple compression modes based on the compression length, and the multiple microoperations are compressed into a reordering buffer area in the target compression mode. In this way, more microoperations can be accommodated for the same reordering buffer area resources, the effective capacity of the reordering buffer area is improved, and then the renaming speed is increased.