10 results about "Re-order buffer" patented technology

The invention provides a processor program address buffering method and device, and belongs to the technical field of processors, and the processor program address buffering device comprises the following components: an instruction fetching unit, a program address comparison unit, a program address buffer area, a program address buffer area tail value register, an instruction transmitting and executing unit and a reordering buffer area; the instruction fetching unit is in control connection with the program address comparison unit, and the program address comparison unit is in control connection with the program address buffer area, the program address buffer area tail value register, the instruction transmitting and executing unit and the reordering buffer area. In order to solve the problem that the disadvantage of the method is obvious in design iteration of instruction fetching and decoding width increasing and assembly line stage increasing of the superscalar processor, the invention provides a judgment basis for whether a program address is written into a program address buffer area or not through a program address comparison unit; the program addresses of all instructions are not written into the program address buffer area, so that the number of implementation table entries of the program address buffer area can be smaller.

The invention provides a high-efficiency matrix engine (RVME) architecture based on RISC-V matrix extension and a calculation method, and the architecture comprises an instruction buffering and decoding module, a matrix loading / storage module, a matrix register file, a parallel outer product array and an element-by-element operation module; the matrix register file comprises a Tile register and an Acculator register; the storage modules are respectively used for storing an input matrix and an accumulation result and supporting efficient data access and parallel computing; the matrix loading / storage module significantly improves the data loading efficiency through cache line alignment and matrix transposition optimization; the instruction buffering and decoding module cooperates with a main processor through a reordering buffer area and an instruction buffer area to ensure efficient scheduling and execution of instructions. The parallel outer product array is adopted to replace a traditional systolic array, the idle period in the calculation process is eliminated through multicast data flow scheduling and a ping-pong buffer read-write mechanism, and matrix multiplication and addition operation with high calculation utilization rate and low delay is achieved.

Disclosed is a connection device between a DMA and a DRAM, which includes a slave interface connected to the DMA of an NPU, a master interface connected to the DRAM having a plurality of slave ports, and a switch that connects the slave interface to the master interface, and the connection device receives a data read request from the DMA of the NPU and transfers the received data read request to the DRAM, receives data or a response corresponding to the received data read request from the plurality of slave ports, and rearranges the data or the response based on an order of the received data read request so as to be transferred to the DMA of the NPU.

The invention discloses a CPU security defense method and device and electronic equipment, and relates to the technical field of computer system security. According to the method, a risk score is calculated through a long-short-term memory network model based on a branch historical vector generated in a speculative execution process of a CPU and a to-be-fetched instruction address; if the to-be-fetched instruction address falls into a predefined sensitive address range and the risk score exceeds a dynamic risk threshold value, generating a pollution mark for the microoperation of accessing the sensitive address; in response to the pollution marker, performing a pollution operation on the microarchitecture component; and when the micro-operation is submitted or cancelled by the reordering buffer area, triggering a pollution clearing operation on the micro-architecture component to finish the security defense of the CPU. According to the method, the protection capability on transient execution type attacks is remarkably improved, so that the resistance of a processor to side channel and transient information leakage risks is enhanced, and the safety and reliability of system operation are improved.

The embodiment of the present application provides a reorder buffer verification method and related equipment, including: obtaining instruction information of a test instruction for verifying the reorder buffer and processing information when the reorder buffer processes the test instruction, wherein the processing information when the reorder buffer processes the test instruction is obtained in real time; based on the instruction information and processing information, predicting the processing result of the reorder buffer on the test instruction, and taking the predicted processing result as the predicted result; when the obtained processing information includes the actual processing result of the test instruction in the reorder buffer, determining the verification result of the reorder buffer based on the actual processing result and the predicted result, wherein, when the verification result is that the test instruction is wrong, extracting the processing information of the test instruction. The reorder buffer verification scheme realizes the fine verification of the reorder buffer and reduces the error probability of the reorder buffer.

The application discloses a memory access queue management method and device, electronic equipment and a readable storage medium. The method comprises the following steps: in the case of receiving a micro-operation, allocating a first table item for the micro-operation and an index for each memory access request in the micro-operation in a first queue; in the case that the memory access request is ready, allocating a second table item for the memory access request in a second queue according to the index; in the case that the instruction to which the micro-operation belongs is submitted in a reordering buffer, releasing the first table item and the second table item, which can realize allocating multiple physical table items for a micro-operation and improve the use efficiency of the physical table items.

One aspect is a method for recovering a rename map table for an out-of-order processor after a flush operation, the method includes executing, by an out-of-order processor, instructions including a flush operation resulting from a branch misprediction of a branch instruction. The out-of-order processor includes a reorder buffer tracking a program order for the instructions and a rename map table mapping multiple logical registers to multiple physical registers. The method also includes, in response to executing the flush operation, grouping the instructions, ordered from oldest to youngest according to the program order tracked in the reorder buffer, into multiple of segments, comparing the multiple segments to identify segments that contain a youngest superset of instructions that wrote to the multiple logical registers between a head of the reorder buffer and the branch instruction, and performing a recovery walk of the identified segments to recover the rename map table.

This document describes systems and techniques for a low-latency bridge to support out-of-order execution. The described systems and techniques can facilitate out-of-order execution by a memory controller of in-order transaction requests. When it receives transaction responses associated with in-order transaction requests, the bridge can send a first transaction response without storing it in a reorder buffer. Similarly, the bridge can determine whether a next transaction response is available to send to the respective client. The bridge introduces latency to a larger system (e.g., an SoC) only when a secondary response (e.g., not first) of in-order transaction responses is received first. In this way, the memory controller can process transaction requests from one or more clients with minimal latency introduced by the bridge and a smaller reorder buffer.

The invention provides an instruction compression method and device, a processor core and computer equipment, and relates to the technical field of data compression. The instruction compression method comprises the steps of obtaining a plurality of micro-operations corresponding to at least one instruction in a current period; according to the execution unit type corresponding to each of the plurality of microoperations and a plurality of preset compression types, determining a plurality of compression modes for the plurality of microoperations; according to the compression lengths of the various compression modes, selecting a target compression mode from the various compression modes; and compressing the plurality of microoperations into the reordering buffer area by adopting a target compression mode. According to the method, multiple compression modes with the high coverage rate are determined based on execution unit types corresponding to the microoperations and multiple preset compression types, then an optimal target compression mode is determined from the multiple compression modes based on the compression length, and the multiple microoperations are compressed into a reordering buffer area in the target compression mode. In this way, more microoperations can be accommodated for the same reordering buffer area resources, the effective capacity of the reordering buffer area is improved, and then the renaming speed is increased.

One aspect is a method for recovering a rename map table for an out-of-order processor after a flush operation, the method includes executing, by an out-of-order processor, instructions including a flush operation resulting from a branch misprediction of a branch instruction. The out-of-order processor includes a reorder buffer tracking a program order for the instructions and a rename map table mapping multiple logical registers to multiple physical registers. The method also includes, in response to executing the flush operation, grouping the instructions, ordered from oldest to youngest according to the program order tracked in the reorder buffer, into multiple of segments, comparing the multiple segments to identify segments that contain a youngest superset of instructions that wrote to the multiple logical registers between a head of the reorder buffer and the branch instruction, and performing a recovery walk of the identified segments to recover the rename map table.