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Computer processing system employing an instruction reorder buffer

a computer processing system and instruction reordering technology, applied in the field of instruction reorder buffers, can solve the problems of cumbersome mapping of ilp applications on one or more tlp cores, requiring highly complex microprocessors that consume a significant amount of power, and consuming a large amount of power

Inactive Publication Date: 2008-07-03
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The trade-off is that ILP extraction requires highly complex microprocessors that consume a significant amount of power.
However, in existing ILP and TLP system architectures it is difficult to optimize the processor for both high-throughput TLP-oriented and ILP-oriented applications.
It is very cumbersome to map ILP applications on one or more TLP cores.

Method used

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  • Computer processing system employing an instruction reorder buffer
  • Computer processing system employing an instruction reorder buffer
  • Computer processing system employing an instruction reorder buffer

Examples

Experimental program
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Embodiment Construction

[0027]One aspect of the exemplary embodiments is a superstructure called SuperROB (Super Re-Order Buffer) that operates across a plurality of TLP cores. Another aspect of the exemplary embodiments is a method of mapping ILP applications on a TLP core by providing for ILP extraction on demand.

[0028]For a long time, the secret to more performance was to execute more instructions per cycle, otherwise known as ILP, or decreasing the effective latency of instructions. To execute more instructions each cycle, more functional units (e.g., integer, floating point, load / store units, etc.) had to be added. In order to more consistently execute multiple instructions, a processing paradigm called out-of-order processing (OOP) may be used. FIG. 1 illustrates one example of an ILP workload using such processing paradigm.

[0029]In FIG. 1, there are three semi-independent chains of dependences that contain load instructions. Key data dependence paths that the processor optimizes are compute-compute ...

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PUM

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Abstract

A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing a Super Re-Order Buffer (SuperROB) in which received instructions are re-ordered after out-of-order execution when at least one of the plurality of processors is in an Instruction Level Parallelism (ILP) mode and at least one of the plurality of processors has a Thread Level Parallelism (TLP) core; detecting an imbalance in a dispatch of instructions of a first dependence chain compared to a dispatch of instructions of a second dependence chain with respect to dependence chain priority; determining a source of the imbalance; and activating the ILP mode when the source of the imbalance has been determined.

Description

GOVERNMENT INTEREST[0001]This invention was made with Government support under contract No.: NBCH3039004 awarded by Defense Advanced Research Projects Agency (DARPA). The government has certain rights in this invention.TRADEMARKS[0002]IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.BACKGROUND OF THE INVENTION[0003]1. Field of the Invention[0004]This invention relates to employing an instruction reorder buffer, and particularly to a technique that takes at least two processors that are optimized to execute dependence chains, and co-locate the processors with a superstructure called SuperROB (Super Re-Order Buffer).[0005]2. Description of Background[0006]Many processors designed today are optimized for execution of tight dependence chains. A dependence chain is a sequence of instructions ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F15/00
CPCG06F9/3806G06F9/3836G06F9/384G06F9/3857G06F9/3838G06F9/3855G06F9/3851G06F9/3858G06F9/3856
Inventor SATHAYE, SUMEDH W.
Owner INT BUSINESS MASCH CORP
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