A functional level software simulation model and chip hardware architecture performance evaluation method

Abstract

The present application relates to chip simulation and performance evaluation, in particular to a functional level software simulation model and a chip hardware architecture performance evaluation method, the functional level software simulation model has no concept of cycle, each instruction only has two states of completed and not executed; in the chip hardware architecture performance evaluation method, according to the calculation cycle, the memory access cycle and the pipeline cycle, the execution cycle number of a single instruction is estimated; according to the execution cycle number of a single instruction, the execution cycle number of a plurality of instruction queues with a dependent relationship in execution sequence is estimated, and the overall execution cycle number is obtained; according to the overall execution cycle number, the chip hardware architecture performance is evaluated; the technical scheme provided by the present application can effectively overcome the defects of the prior art, such as long development and verification period of the clock cycle level software simulation model, and difficulty in accurately estimating the execution cycle number of a plurality of instruction queues on the basis of no cycle concept.

Description

TECHNICAL FIELD

[0001] The present application relates to chip simulation and performance evaluation, in particular to a functional level software simulation model and a chip hardware architecture performance evaluation method. BACKGROUND

[0002] Chip simulation model is an indispensable part in the process of modern processor design, mainly including software simulation model and hardware simulation model, wherein the software simulation model is generally developed based on the open source framework of systemc and the like high-level language, and the hardware simulation model is generally established in verilog / systemverilog / VHDL language and can be converted into netlist and GDSII layout after backend processing, which is a specific representation of chip front-end design.

[0003] In the process of chip research and development, the software simulation model plays an important role. For example, in the process of chip structure design, the software simulation model can be used as a tool for evaluating the performance of hardware architecture; in the process of chip function verification, the software simulation model can be used as a tool for verifying the correctness of the function of chip hardware design, and the instructions of the chip are simulated; in the process of chip related software development, the software simulation model can be used as a software debugging tool before the actual chip hardware system is developed, so that the software and hardware design can be carried out synchronously.

[0004] The traditional software simulation model is generally a clock cycle accurate software simulation model, that is, the clock is maintained inside the software simulation model, and the clock is also divided into rising edge and falling edge. The clock cycle accurate software simulation model needs to ensure that the state of each cycle in the execution process of the instruction is consistent with the hardware simulation model, which requires the software simulation model to model the chip with high precision, including but not limited to the same instruction decoding logic, the same pipeline length, the same control logic, the same instruction execution flow, etc.

[0005] The high precision of the clock cycle accurate software simulation model can play a great role in chip verification, which can accurately locate the position of the error in the verification process, so as to quickly find and solve the problems in the process of chip verification. However, the clock cycle accurate software simulation model also has many shortcomings. Because of the high precision requirement, the development and verification of the software simulation model requires a large amount of time and human cost, and in large chip research and development projects, the development and verification time can even be in years; in addition, due to the existence of the pipeline, the running speed of the software simulation model is slow, and this shortcoming is more obvious when the instruction scale is large.

[0006] The traditional clock cycle level software simulation model needs to establish a fine pipeline model, such as Figure 3The shown while pipeline model also needs to complete pipeline control logic such as flush, stall, branch prediction, jump, interruption and the like. In addition, in order to make the timing of the chip meet the design requirements, different data read-write occasions will be used for different types of instruction kernels, which involves data correlation and forward logic and the like. These logics are the difficulties in the modeling process of the software simulation model, usually a lot of time is spent for verification, and when multiple situations are combined, such as branch jump and data forward at the same time, the verification pressure will be greater.

[0007] For the AI acceleration kernel (NNA, Neural Network Accelerator) designed for intelligent computing and specifically for deep learning computing, the main function of the kernel is to implement deep neural network model inference calculation, input preprocessing and output postprocessing, and common processing of signals, images and video frames, while having certain vector and matrix data calculation capabilities. One instruction of the AI acceleration kernel NNA may need to perform multi-level loop calculation, and the execution period can reach millions of cycles, so if a clock cycle level software simulation model is established, the workload is huge. SUMMARY

[0008] (I) Technical problems solved

[0009] In view of the above defects of the prior art, the present application provides a functional level software simulation model and a chip hardware architecture performance evaluation method, which can effectively overcome the defects of the prior art that the development and verification period of the clock cycle level software simulation model is long, and it is difficult to accurately estimate the number of execution cycles of multiple instruction queues without the concept of cycle.

[0010] (II) Technical solutions

[0011] To achieve the above object, the present application is realized by the following technical solutions:

[0012] A functional level software simulation model, the functional level software simulation model has no concept of cycle, each instruction only has two states of completed and not executed, and correspondingly, the pipeline has only one level, the instruction fetching, decoding, operation and write-back processes are sequentially executed in the one level pipeline stage;

[0013] For the instruction stream normally executed in sequence, only the PC at the instruction fetching time needs to be normally increased; for the jump instruction or interruption, only the PC at the instruction fetching time needs to be modified to the destination PC;

[0014] After decoding, the functions corresponding to different instructions are called according to opcode to realize data fetching, operation and write-back;

[0015] The register and memory of the functional level software simulation model have left values and right values as the clock cycle level software simulation model, and the right value is taken when the data is read, and the left value is written back. The register and memory are flipped only after all instructions in the current instruction line are executed.

[0016] Preferably, when the functional level software simulation model is applied to the AI acceleration core NNA, multiple instruction queues are designed internally to improve the execution efficiency of the instructions. If there is no dependency relationship between the instructions in the instruction queue, the instructions in the instruction queue can be executed in parallel. If there is a dependency relationship between the instructions in the instruction queue, the dependent instructions need to wait for the dependent instructions to be executed before they can be executed.

[0017] The instruction queue includes matrix, vector, store, load, l2_store and l2_load. The matrix and vector instruction queues mainly include calculation instructions, and the store, load, l2_store and l2_load instruction queues mainly include memory access instructions.

[0018] A chip hardware architecture performance evaluation method, comprising the following steps:

[0019] S1, estimating the execution cycle number of a single instruction according to the calculation cycle, the memory access cycle and the pipeline cycle;

[0020] S2, estimating the execution cycle number of multiple instruction queues with a dependency relationship in the execution order according to the execution cycle number of a single instruction, to obtain the total execution cycle number;

[0021] S3, evaluating the performance of the chip hardware architecture according to the total execution cycle number.

[0022] Preferably, in the functional level software simulation model of the AI acceleration core NNA, the estimation method of the calculation cycle of a single instruction comprises:

[0023] For the matrix instruction, the instruction is used to control the matrix module to perform matrix multiplication operation and two-dimensional convolution calculation. The calculation process includes multiple layers of loops and a large amount of data access. The innermost loop includes point multiplication and accumulation of the ACC array. The execution time of the instruction is related to the number of loops and the amount of data of the multiple layers of loops.

[0024] Since the final operation of the matrix instruction is multiplication and addition of data, the estimation of the calculation cycle can be converted into the estimation of the number of calculations, the number of cycles used for single multiplication and addition.

[0025] The number of calculations is obtained after the instruction decoding, and the number of cycles used for single multiplication and addition is given by the hardware front-end designer at the beginning of development.

[0026] Preferably, in the functional-level software simulation model of the AI acceleration core NNA, the estimation method of the memory access cycle of a single instruction comprises:

[0027] By estimating the memory data volume, data path bit width and bus bandwidth utilization, the memory access cycle Time of a single instruction is obtained:

[0028] Time=(x_size*y_size*channel*batch_size) / bandwidth_rate;

[0029] Wherein, x_size and y_size respectively represent the length and width of the sample image used for model training, channel represents the number of channels of the sample image, batch_size represents the number of the batch of training sample images, and bandwidth_rate represents the bus bandwidth utilization configured by the developer.

[0030] Preferably, the bus bandwidth utilization cannot be determined in the modeling stage and is closely related to the real-time task load of the SoC chip. When there are busy CPU software tasks in the system, and there are network communication, video encoding and decoding, and file operation tasks, the bandwidth utilization of the AI acceleration core NNA memory access instruction is low; when only the AI acceleration core NNA works in the system, the bandwidth utilization of the AI acceleration core NNA memory access instruction is high.

[0031] In the functional-level software simulation model of the AI acceleration core NNA, the bus bandwidth utilization is set as a configurable parameter, which is passed to the software simulator through the command line. The developer configures the bus bandwidth utilization to estimate the performance of the AI acceleration core NNA under different SoC chip task loads.

[0032] Preferably, in the functional-level software simulation model of the AI acceleration core NNA, the estimation method of the pipeline cycle of a single instruction comprises:

[0033] By estimating around the pipeline length, the pipeline cycle of a single instruction is obtained;

[0034] Wherein, the pipeline cycle is generally a small fixed value, which has little effect on the estimation of the number of execution cycles of a single instruction.

[0035] Preferably, in S2, according to the number of execution cycles of a single instruction, the number of execution cycles of a plurality of instruction queues having a dependency relationship in execution order is estimated to obtain the total number of execution cycles, comprising:

[0036] When performing software simulation modeling, the systemc framework of C++ is used. The framework internally maintains a master clock, and the clock is shared among modules.

[0037] In the functional level modeling, since there is no concept of cycle, the number of execution cycles of a single instruction is taken as one clock cycle. After the execution of the instruction, the number of execution cycles of the instruction is estimated by the encapsulated method, the sc_core:next_trigger function provided by systemc is called to make the corresponding instruction queue enter the "sleep" state, the instruction queues that do not have a dependency relationship with the instruction queue normally work, and the instruction queues that have a dependency relationship with the instruction queue enter the waiting "idle" state. After a number of waiting cycles, the notification information of the instruction queue is sent again;

[0038] After all the instructions are executed, the total number of execution cycles is obtained by the master clock;

[0039] The number of waiting cycles is determined by the number of execution cycles of the instruction.

[0040] Preferably, in S2, the number of execution cycles of a plurality of instruction queues that have a dependency relationship in the execution order is estimated according to the number of execution cycles of a single instruction, and the total number of execution cycles is obtained, including:

[0041] When there are only two instruction queues L1 and L2 in the AI acceleration core NNA, and the instruction I1(n) to be executed in the instruction queue L1 does not have a dependency relationship with the instruction I2(n) to be executed in the instruction queue L2, the number of execution cycles C1(n) of the instruction I1(n) is inserted into V1. After all the instructions are executed, max[sum(V1), sum(V2)] is the total number of execution cycles;

[0042] When there are only two instruction queues L1 and L2 in the AI acceleration core NNA, and the instruction I1(n) to be executed in the instruction queue L1 has a dependency relationship with the instruction I2(n) to be executed in the instruction queue L2, the sum[C2(0), C2(1), …, C2(n)] and sum(V1) are judged:

[0043] If sum[C2(0), C2(1), …, C2(n)] < sum(V1), the number of execution cycles C1(n) of the instruction I1(n) is inserted into V1;

[0044] If sum[C2(0), C2(1), …, C2(n)] ≥ sum(V1), V1 is emptied, sum[C2(0), C2(1), …, C2(n)] is inserted into V1, and the number of execution cycles C1(n) of the instruction I1(n) is inserted into V1;

[0045] After all the instructions are executed, max[sum(V1), sum(V2)] is the total number of execution cycles;

[0046] Wherein, V1, V2 are respectively containers for storing the execution cycle numbers of each instruction of instruction queues L1, L2, C1(n), C2(n) are respectively the execution cycle numbers corresponding to instructions I1(n), I2(n), max[·] represents a maximum value function, and sum[·] represents a sum function.

[0047] (Three) beneficial effects

[0048] Compared with the prior art, the functional-level software simulation model and the chip hardware architecture performance evaluation method provided by the application have the following beneficial effects:

[0049] 1) The development process is short and the development process is simple, and a functional-level software simulation model with relatively complete functions can be formed at the initial stage of instruction set and design scheme determination, which is convenient for early hardware architecture performance evaluation and algorithm development.

[0050] 2) It is convenient to verify and improve, whether it is the functional correctness verification of the functional-level software simulation model itself or the instruction-level verification between the functional-level software simulation model and the hardware front-end model, the verification result can be quickly obtained;

[0051] 3) The running speed is fast, the deployment is simple, and the running speed of the functional-level software simulator can be improved by 50-70 times compared with the cycle-level software simulator, and in the functional-level software simulation model of the AI acceleration core NNA, the running speed advantage will be more obvious because the execution cycle of a single instruction can reach millions of cycles;

[0052] 4) Two execution time estimation methods for multiple instruction queues in the functional-level software simulation model of the AI acceleration core NNA are given, and the two methods can estimate the total execution time of multiple instruction queues through the instruction execution time formula estimated by hardware personnel, and can accurately estimate the execution time of the software program. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0054] Figure 1 It is an instruction queue dependency diagram of the AI acceleration core NNA in the present application.

[0055] Figure 2 It is a flowchart for estimating the execution cycle numbers of multiple instruction queues with dependency relationship in the execution order and obtaining the total execution cycle number.

[0056] Figure 3 A pipeline model diagram established for a traditional clock cycle level software simulation model. DETAILED DESCRIPTION

[0057] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0058] A function level software simulation model, the function level software simulation model has no concept of cycle, each instruction only has two states of completed and not executed, and correspondingly, the pipeline has only one level, the instruction fetch, decoding, operation and write back processes are sequentially executed in the one level pipeline stage;

[0059] For a normally sequentially executed instruction stream, only the PC at the time of instruction fetch needs to be normally increased; for a jump instruction or an interruption, only the PC at the time of instruction fetch needs to be modified as a destination PC;

[0060] After decoding, the functions corresponding to different instructions are called according to the opcode to implement the data fetch, operation and write back;

[0061] The registers and memory of the function level software simulation model have left values and right values as the clock cycle level software simulation model, the data fetch during operation takes the right value, the write back writes the left value, and only after all instructions in the current instruction line are executed completely, the registers and memory are flipped.

[0062] When the function level software simulation model is applied to an AI acceleration core NNA, in order to improve the execution efficiency of instructions, a plurality of instruction queues are designed inside, such as Figure 1 As shown in the figure, if the instructions in the instruction queue do not have a dependency relationship, the instructions in the instruction queue can be executed in parallel; if the instructions in the instruction queue have a dependency relationship, the dependent instructions need to wait until the dependent instructions are executed completely.

[0063] The instruction queue includes matrix, vector, store, load, l2_store and l2_load, the matrix and vector instruction queues mainly include calculation type instructions, and the store, load, l2_store and l2_load instruction queues mainly include memory access type instructions.

[0064] In the technical solution of the present application, the functional level software simulation model can only perform instruction level verification with the hardware front-end model during verification. Since the hardware front-end model generally has multiple write-back occasions, the instruction write-back information of other instruction lines will affect the register and memory states, so it is impossible to compare and verify the register and memory states after each instruction line is executed. The instruction level verification between the functional level software simulation model and the hardware front-end model includes the following two ways:

[0065] 1) Comparing and verifying the register and memory states after all instructions are executed;

[0066] 2) Adding multiple nop instructions after the instruction line that needs to compare and verify the register and memory state, the number of which is determined according to the pipeline length.

[0067] In the technical solution of the present application, on the basis of the above-mentioned functional level software simulation model, a chip hardware architecture performance evaluation method is also disclosed, including the following steps:

[0068] S1, estimating the execution cycle number of a single instruction according to the calculation cycle, the memory access cycle and the pipeline cycle;

[0069] S2, estimating the execution cycle number of multiple instruction queues with a dependency relationship in execution order according to the execution cycle number of a single instruction, to obtain the total execution cycle number;

[0070] S3, evaluating the performance of the chip hardware architecture according to the total execution cycle number.

[0071] The functional level software simulation model can be used as an evaluation tool for hardware architecture performance, and the performance evaluation standard depends largely on the instruction execution time of the model. For the functional level software simulation model of the AI acceleration core NNA, since there is no concept of cycle, the performance of the hardware architecture can only be evaluated in an estimated manner, and the estimation mainly focuses on the execution cycle number of a single instruction, which includes the calculation cycle, the memory access cycle and the pipeline cycle.

[0072] ①In the functional level software simulation model of the AI acceleration core NNA, the estimation method of the calculation cycle of a single instruction includes:

[0073] For the matrix instruction, this instruction is used to control the matrix module to perform matrix multiplication operation and two-dimensional convolution calculation. The calculation process includes multiple loops and a large amount of data access, and the innermost loop includes the dot product and accumulation of the ACC array. The execution time of the instruction is related to the number of loops and the data volume of the multiple loops;

[0074] Since the final operation of the matrix instruction is multiplication and addition of data, the estimation of the calculation period can be converted into the estimation of the number of calculations, the number of periods used for single multiplication and addition;

[0075] The number of calculations is obtained after instruction decoding, and the number of periods used for single multiplication and addition is given by the hardware front-end designer at the beginning of development.

[0076] ②In the functional-level software simulation model of the AI acceleration core NNA, the estimation method of the memory access period of a single instruction includes:

[0077] By estimating the memory data volume, data path width and bus bandwidth utilization, the memory access period Time of a single instruction is obtained:

[0078] Time=(x_size*y_size*channel*batch_size) / bandwidth_rate;

[0079] Wherein, x_size and y_size represent the length and width of the sample image used for model training respectively, channel represents the number of channels of the sample image, batch_size represents the number of the batch of training sample images, and bandwidth_rate represents the bus bandwidth utilization configured by the developer.

[0080] The bus bandwidth utilization cannot be determined at the modeling stage and is closely related to the real-time task load of the SoC chip. When there are busy CPU software tasks in the system, and there are network communication, video encoding and decoding, and file operation tasks, the bandwidth utilization of the AI acceleration core NNA memory instruction is low; when only the AI acceleration core NNA works in the system, the bandwidth utilization of the AI acceleration core NNA memory instruction is high;

[0081] In the functional-level software simulation model of the AI acceleration core NNA, the bus bandwidth utilization is set as a configurable parameter, which is passed to the software simulator through the command line. The developer configures the bus bandwidth utilization to estimate the performance of the AI acceleration core NNA under different SoC chip task loads.

[0082] ③In the functional-level software simulation model of the AI acceleration core NNA, the estimation method of the pipeline period of a single instruction includes:

[0083] By estimating around the pipeline length, the pipeline period of a single instruction is obtained;

[0084] Wherein, the pipeline period is generally a small fixed value, which has little effect on the estimation of the number of execution periods of a single instruction.

[0085] When the real program is running on the AI acceleration core NNA, only estimating the execution cycle number of a single instruction is far from enough to estimate the execution time of the software program. Since the AI acceleration core NNA contains multiple independent and parallel instruction queues, and there is a dependency relationship between the execution sequences of the instruction queues, the relationship between the instructions is neither completely parallel nor completely serial. Therefore, when estimating the total execution cycle number, the execution sequence of the instructions also needs to be fully considered, which has a huge impact on the final estimation result.

[0086] (4) In S2, the execution cycle number of multiple instruction queues with a dependency relationship in the execution sequence is estimated according to the execution cycle number of a single instruction, and the total execution cycle number is obtained, including the following two methods:

[0087] 1) When performing software simulation modeling, the systemc framework of C++ is used, which maintains a master clock inside and shares the clock between modules;

[0088] When performing functional-level modeling, there is no concept of cycle, so the execution cycle number of a single instruction is taken as 1 clock cycle. After the execution of the instruction is completed, the execution cycle number of the instruction is estimated through a packaged method, the sc_core: next_trigger function provided by systemc is called to make the corresponding instruction queue enter the "sleep" state, other instruction queues that do not have a dependency relationship with the instruction queue work normally, other instruction queues that have a dependency relationship with the instruction queue enter the "idle" state, and after a certain number of waiting cycles, the notification information of the instruction queue is sent;

[0089] After all the instructions are executed, the total execution cycle number is obtained through the master clock;

[0090] Among them, the number of waiting cycles is determined by the execution cycle number of the instruction;

[0091] 2) As shown in Figure 2 When there are only two instruction queues L1 and L2 inside the AI acceleration core NNA, and the instruction I1(n) to be executed in the instruction queue L1 has no dependency relationship with the instruction I2(n) to be executed in the instruction queue L2, the execution cycle number C1(n) of the instruction I1(n) is inserted into V1, and after all the instructions are executed, max[sum(V1), sum(V2)] is the total execution cycle number;

[0092] When there are only two instruction queues L1 and L2 inside the AI acceleration core NNA, and the instruction I1(n) to be executed in the instruction queue L1 has a dependency relationship with the instruction I2(n) to be executed in the instruction queue L2, the sum[C2(0), C2(1), …, C2(n)] and sum(V1) are judged for their sizes:

[0093] If sum[C2(0), C2(1), …, C2(n)] < sum(V1), the execution cycle number C1(n) of the instruction I1(n) is inserted into V1;

[0094] If sum[C2(0), C2(1), …, C2(n)] ≥ sum(V1), V1 is emptied, sum[C2(0), C2(1), …, C2(n)] is inserted into V1, and the execution cycle number C1(n) of the instruction I1(n) is inserted into V1;

[0095] After all instructions are executed, max[sum(V1), sum(V2)] is the total execution cycle number.

[0096] Wherein, V1 and V2 are containers for storing execution cycle numbers of instructions in instruction queues L1 and L2 respectively, C1(n) and C2(n) are execution cycle numbers corresponding to instructions I1(n) and I2(n) respectively, max[·] represents a maximum value function, and sum[·] represents a sum function.

[0097] The difference between the total execution cycle number estimated by the above two methods and the actual execution cycle number is very small, and can be used as a standard for evaluating the performance of a hardware architecture. By changing the parameters of a hardware architecture, such as data path width and ACC number, the total execution cycle number of a software simulation model under different parameters is estimated, so that the performance of each type of hardware architecture can be accurately evaluated quickly.

[0098] The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements will not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A functional level software simulation model, characterized by: The functional-level software simulation model has no concept of cycle, each instruction only has two states of completed and not executed, and the pipeline has only one level, and the instruction fetching, decoding, operation and write-back processes are sequentially executed in the one-level pipeline; For the instruction stream normally executed in sequence, only the PC at the instruction fetching time needs to be ensured to normally increase; for a jump instruction or an interruption, only the PC at the instruction fetching time needs to be modified to the destination PC; After decoding, the functions corresponding to different instructions are called according to the opcode to implement the data fetching, operation and write-back; The registers and memory of the functional-level software simulation model have left values and right values as the clock cycle-level software simulation model, the data fetching during operation takes the right value, and the write-back writes the left value, and only after all instructions in the current instruction line are executed, the registers and memory are flipped; When the functional-level software simulation model is applied to the AI acceleration core NNA, in order to improve the execution efficiency of instructions, a plurality of instruction queues are designed inside, if the instructions in the instruction queue do not have a dependency relationship, the instructions in the instruction queue can be executed in parallel; if the instructions in the instruction queue have a dependency relationship, the dependent instructions need to wait for the dependent instructions to be executed before they can be executed; The instruction queue includes matrix, vector, store, load, l2_store and l2_load, the matrix and vector instruction queues mainly include calculation instructions, and the store, load, l2_store and l2_load instruction queues mainly include memory instructions.

2. A chip hardware architecture performance evaluation method applied to the functional-level software simulation model of claim 1, characterized in that: The method comprises the following steps: S1, estimating the execution cycle number of a single instruction according to the calculation cycle, the memory cycle and the pipeline cycle; S2, estimating the execution cycle number of a plurality of instruction queues having a dependency relationship in execution order according to the execution cycle number of a single instruction, to obtain a total execution cycle number; S3, evaluating the performance of the chip hardware architecture according to the total execution cycle number.

3. The method of claim 2, wherein: In the functional-level software simulation model of the AI acceleration core NNA, the estimation method of the calculation cycle of a single instruction comprises: For the matrix instruction, the instruction is used to control the matrix module to execute matrix multiplication operation and two-dimensional convolution calculation, the calculation process includes multiple loops and a large amount of data access, and the innermost loop includes point multiplication and accumulation of the ACC array, and the execution time of the instruction is related to the loop number and data volume of the multiple loops; Since the final operation of the matrix instruction is multiplication and addition of data, the estimation of the calculation cycle can be converted into the estimation of the calculation number, the cycle number used for single multiplication and addition; The calculation number is obtained after the instruction decoding, and the cycle number used for single multiplication and addition is given by the hardware front-end designer at the initial development stage.

4. The method of claim 3, wherein: In the functional-level software simulation model of the AI acceleration core NNA, the estimation method of the memory cycle of a single instruction comprises: The memory cycle Time of a single instruction is obtained by estimating the memory data volume, the data path bit width and the bus bandwidth utilization rate: Time=(x_size*y_size*channel*batch_size) / bandwidth_rate; Wherein, x_size, y_size respectively represent the length, width of the sample image used for model training, channel represents the channel number of the sample image, batch_size represents the number of this batch of training sample images, bandwidth_rate represents the bus bandwidth utilization rate configured by the developer.

5. The method of claim 4, wherein: The bus bandwidth utilization rate cannot be determined in the modeling stage, and is closely related to the real-time task load of the SoC chip. When there are busy CPU software tasks in the system, and there are network communication, video coding and decoding, and file operation tasks, the bandwidth utilization rate of the AI acceleration core NNA memory instruction is low; when only the AI acceleration core NNA works in the system, the bandwidth utilization rate of the AI acceleration core NNA memory instruction is high; In the functional level software simulation model of the AI acceleration core NNA, the bus bandwidth utilization rate is set as a configurable parameter, which is passed to the software simulator through the command line. The developer configures the bus bandwidth utilization rate to estimate the performance of the AI acceleration core NNA under different SoC chip task loads.

6. The method of claim 4, wherein: In the functional level software simulation model of the AI acceleration core NNA, the estimation method of the pipeline cycle of a single instruction includes: By estimating around the pipeline length, the pipeline cycle of a single instruction is obtained; Wherein, the pipeline cycle is generally a small fixed value, which has little effect on the execution cycle number estimation of a single instruction.

7. The method of claim 6, wherein: In S2, according to the execution cycle number of a single instruction, the execution cycle number of a plurality of instruction queues having a dependency relationship in execution order is estimated to obtain the total execution cycle number, including: When performing software simulation modeling, the systemc framework of C++ is used, which maintains a master clock inside and shares the clock among modules; When performing functional level modeling, since there is no concept of cycle, the execution cycle number of a single instruction is taken as 1 clock cycle. After the execution of the instruction is completed, the execution cycle number of the instruction is estimated through a packaged method, the sc_core:next_trigger function provided by systemc is called to make the corresponding instruction queue enter the "sleep" state, other instruction queues that do not have a dependency relationship with the instruction queue normally work, and other instruction queues that have a dependency relationship with the instruction queue enter the waiting "idle" state. After a number of waiting cycles, the notification information of the instruction queue is sent again; After all instructions are executed, the total execution cycle number is obtained through the master clock; Wherein, the number of waiting cycles is determined by the execution cycle number of the instruction.

8. The method of claim 6, wherein: In S2, according to the execution cycle number of a single instruction, the execution cycle number of a plurality of instruction queues having a dependency relationship in execution order is estimated to obtain the total execution cycle number, including: When the AI acceleration core NNA is internally designed with only two instruction queues L1 and L2, and there is no dependency between the instruction I1(n) to be executed in the instruction queue L1 and the instruction I2(n) to be executed in the instruction queue L2, the execution cycle number C1(n) of the instruction I1(n) is inserted into V1, and after all instructions are executed, max[sum(V1), sum(V2)] is the total execution cycle number; When the AI acceleration core NNA is internally designed with only two instruction queues L1 and L2, and there is a dependency between the instruction I1(n) to be executed in the instruction queue L1 and the instruction I2(n) to be executed in the instruction queue L2, the sum[C2(0), C2(1), …, C2(n)] and the sum(V1) are compared: If sum[C2(0), C2(1), …, C2(n)] < sum(V1), the execution cycle number C1(n) of the instruction I1(n) is inserted into V1; If sum[C2(0), C2(1), …, C2(n)] ≥ sum(V1), V1 is emptied, sum[C2(0), C2(1), …, C2(n)] is inserted into V1, and the execution cycle number C1(n) of the instruction I1(n) is inserted into V1; After all instructions are executed, max[sum(V1), sum(V2)] is the total execution cycle number; Wherein, V1 and V2 are containers for storing the execution cycle numbers of each instruction of the instruction queues L1 and L2 respectively, C1(n) and C2(n) are the execution cycle numbers corresponding to the instructions I1(n) and I2(n) respectively, max[·] represents the maximum value function, and sum[·] represents the sum function.

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