A multi-channel priority arbitration allocation method, system, device and medium

Abstract

The present application provides a multi-channel priority arbitration allocation method, system, device and medium thereof, wherein a read-write arbitrator responds to asynchronous read-write requests of each of the read-write channels, initializes the count value of each of the counters to a preset initial value, and obtains the priority level value and channel number of each of the read-write channels. Then, according to each count value, each priority level value and each channel number, periodic polling priority arbitration processing is performed on each of the read-write channels to obtain the highest priority channel of each cycle. Finally, according to the highest priority channel of each cycle, the bandwidth resources of the AXI bus are periodically allocated to the corresponding read-write channels, and each count value is periodically updated, thereby evenly allocating the bandwidth of the AXI bus to multiple read-write channels of the same priority, thereby solving the problem of uneven bandwidth allocation between channels of the same priority and improving the rationality of bandwidth resource allocation.

Description

Technical Field

[0001] The present application relates to the field of multi-channel request arbitration mechanism, and in particular to a multi-channel priority arbitration allocation method, system, device and medium. Background Art

[0002] In current technology, arbitration mechanisms for multiple requests are generally divided into the following categories: 1. Fixed priority arbitration mechanism, which conducts arbitration according to a predetermined priority response principle. However, this arbitration mechanism often results in low-priority channel requests not being responded to for a long time when high-priority channel requests occur frequently, and even causes low-priority channels to be paralyzed. 2. Polling priority arbitration mechanism, each time a requested channel participates in arbitration, the counter value is increased by 1, and then the priority of the next arbitration is determined based on the counter value, so that the arbitration priority of the unresponded channel can be continuously raised so that it can eventually get a response. However, this arbitration mechanism often results in each channel responding to requests unevenly, so that the total bandwidth is not evenly distributed among multiple channels with the same priority. When several channels with the same priority send requests at the same time and the requests occur frequently, it is easy to cause insufficient bandwidth for some channels. Summary of the invention

[0003] The main purpose of the embodiments of the present application is to propose a multi-channel priority arbitration allocation method, system, device and medium, which can evenly distribute the bandwidth of the AXI bus to multiple read and write channels of the same priority, thereby solving the problem of uneven bandwidth distribution between channels of the same priority. At the same time, it also avoids the problem that requests from low-priority read and write channels are not responded to for a long time, thereby improving the rationality of bandwidth resource allocation.

[0004] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application proposes a multi-channel priority arbitration allocation method, which is applied to a multi-channel priority arbitration allocation system. The multi-channel priority arbitration allocation system includes an AXI bus, a read-write arbitrator, and multiple read-write channels. The read-write arbitrator includes multiple counters, each counter corresponds to each read-write channel one by one, and the count value of the counter is used to characterize the number of times the read-write channel gives up arbitration opportunities. The AXI bus is communicatively connected to the read-write arbitrator, and the read-write arbitrator is communicatively connected to each read-write channel respectively. The multi-channel priority arbitration allocation method includes:

[0005] The read / write arbiter responds to the asynchronous read / write requests of each read / write channel, initializes the count value of each counter to a preset initial value, and obtains the priority level value and channel number of each read / write channel, wherein the preset initial value is used to indicate that the number of arbitration opportunities granted by the corresponding read / write channel is zero;

[0006] The read / write arbitrator performs periodic polling priority arbitration processing on each read / write channel according to each count value, each priority level value and each channel number to obtain the highest priority channel of each cycle; the highest priority channel of the cycle is the read / write channel arbitrated as the highest priority among all the read / write channels in the same polling cycle;

[0007] The read / write arbiter periodically allocates the bandwidth resources of the AXI bus to the corresponding read / write channels according to the highest priority channel in each cycle, and periodically updates each count value so that the asynchronous read / write requests in each read / write channel are processed asynchronously;

[0008] Among them, in a polling cycle of periodically polling priority arbitration processing for each read and write channel, the following steps are included:

[0009] Get each target cycle count value; the target cycle count value is the count value of the corresponding counter in the current polling cycle;

[0010] Determine one or more target cycle priority arbitration channels according to each target cycle count value, where the target cycle priority arbitration channel is a read / write channel whose target cycle count value is equal to a preset initial value;

[0011] Count the number of target cycle priority arbitration channels to obtain the total number of target cycle priority arbitration channels;

[0012] The highest priority channel of the cycle is determined according to the total number of the target cycle priority arbitration channels and the priority level values ​​and channel numbers corresponding to the target cycle priority arbitration channels.

[0013] Further, in some embodiments, determining the highest priority channel of the cycle according to the number of the target cycle priority arbitration channels and the channel numbers corresponding to the target cycle priority arbitration channels includes:

[0014] When the total number of target cycle priority arbitration channels is one, the target cycle priority arbitration channel is determined as the cycle highest priority channel under the current polling cycle;

[0015] Alternatively, when there are a plurality of target cycle priority arbitration channels in total, one or more target cycle priority arbitration channels having the highest priority level values ​​among the target cycle priority arbitration channels are determined as the reserve highest priority channels;

[0016] If the number of the prepared highest priority channels is one, the prepared highest priority channel is determined as the periodic highest priority channel under the current polling cycle;

[0017] If there are multiple prepared highest priority channels, among the prepared highest priority channels, the prepared highest priority channel with the smallest channel number is determined as the periodic highest priority channel in the current polling cycle.

[0018] Further, in some embodiments, in a polling cycle of periodically allocating bandwidth resources of the AXI bus to corresponding read / write channels and updating corresponding count values, the method includes:

[0019] According to the current polling cycle, obtain the corresponding cycle's highest priority channel and the total number of target cycle priority arbitration channels;

[0020] Allocate the bandwidth resources of the AXI bus to the channel with the highest cycle priority;

[0021] According to the total number of target cycle priority arbitration channels, the target cycle count values ​​corresponding to the relevant read and write channels are updated.

[0022] Further, in some embodiments, the target cycle count value corresponding to the relevant read / write channel is updated according to the total number of target cycle priority arbitration channels, including:

[0023] When the total number of target cycle priority arbitration channels is one, the target cycle count values ​​corresponding to all read and write channels are synchronously updated to preset initial values.

[0024] Furthermore, in some embodiments, updating the target cycle count value corresponding to the relevant read / write channel according to the total number of target cycle priority arbitration channels also includes:

[0025] When the total number of target cycle priority arbitration channels is multiple, the target cycle count value corresponding to the read / write channel determined as the cycle highest priority channel is updated to the cycle maximum count threshold;

[0026] Synchronously updating the target cycle count value corresponding to the read / write channel that is not determined as the target cycle priority arbitration channel to the cycle decrement count value;

[0027] Among them, the cycle decrement count value is the difference between the target cycle count value corresponding to the read / write channel of the target cycle priority arbitration channel that is not determined and the preset cycle decrement value. The cycle decrement value is used to represent that the number of times the corresponding read / write channel gives up arbitration opportunities is once. The cycle maximum count threshold is used to represent that in the current polling cycle, the number of times the corresponding read / write channel gives up arbitration opportunities is the maximum upper limit.

[0028] To achieve the above object, a second aspect of an embodiment of the present application proposes a multi-channel priority arbitration allocation system, including:

[0029] AXI bus, a read-write arbiter and multiple read-write channels. The read-write arbiter includes multiple counters. Each counter corresponds to each read-write channel. The count value of the counter is used to represent the number of times the read-write channel gives up arbitration opportunities. The AXI bus is connected to the read-write arbiter in communication. The read-write arbiter is connected to each read-write channel in communication, wherein:

[0030] The read / write arbiter is configured to, in response to the asynchronous read / write request of each read / write channel, initialize the count value of each counter to a preset initial value, and obtain the channel number of each read / write channel, wherein the preset initial value is used to indicate that the number of times the corresponding read / write channel has given arbitration opportunities is zero;

[0031] The read / write arbitrator is further configured to perform periodic polling priority arbitration processing on each read / write channel according to each count value and each channel number to obtain the highest priority channel of each cycle; the highest priority channel of the cycle is the read / write channel arbitrated as the highest priority among the read / write channels in the same polling cycle;

[0032] The read / write arbiter is further configured to periodically allocate bandwidth resources of the AXI bus to corresponding read / write channels according to the highest priority channel in each cycle, and periodically update each count value so that asynchronous read / write requests in each read / write channel are processed asynchronously;

[0033] Among them, in a polling cycle of periodically polling priority arbitration processing for each read and write channel, the following steps are included:

[0034] Get each target cycle count value; the target cycle count value is the count value of the corresponding counter in the current polling cycle;

[0035] Determine one or more target cycle priority arbitration channels according to each target cycle count value, where the target cycle priority arbitration channel is a read / write channel whose target cycle count value is equal to a preset initial value;

[0036] Count the number of target cycle priority arbitration channels to obtain the total number of target cycle priority arbitration channels;

[0037] The highest priority channel of the cycle is determined according to the total number of the target cycle priority arbitration channels and the channel numbers corresponding to the target cycle priority arbitration channels.

[0038] To achieve the above-mentioned purpose, the third aspect of the embodiments of the present application proposes an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the multi-channel priority arbitration allocation method of the above-mentioned first aspect embodiment is implemented.

[0039] To achieve the above-mentioned purpose, the fourth aspect of the embodiments of the present application proposes a computer-readable storage medium, which stores a program executable by a processor. When the computer program is executed by the processor, the multi-channel priority arbitration allocation method of the above-mentioned first aspect embodiment is implemented.

[0040] The embodiments of the present application have the following beneficial effects: the present application responds to the asynchronous read and write requests of each of the read and write channels through a read and write arbitrator, initializes the count value of each of the counters to a preset initial value, and obtains the priority level value and channel number of each of the read and write channels, wherein the preset initial value is used to indicate that the number of times the corresponding read and write channel gives up arbitration opportunities is zero, and then, according to each count value, each priority level value and each channel number, performs periodic polling priority arbitration processing on each of the read and write channels to obtain the highest priority channel of each cycle, the highest priority channel of the cycle is the read and write channel arbitrated as the highest priority among the read and write channels in the same polling cycle, and finally, according to the highest priority channel of each cycle, periodically allocates the bandwidth resources of the AXI bus to the corresponding read and write channels, and periodically updates each count value so that the asynchronous read and write requests in each read and write channel are processed asynchronously; wherein, in a polling cycle of periodic polling priority arbitration processing on each of the read and write channels, by obtaining each target cycle count value, the target cycle count is obtained. The value is the count value of the corresponding counter in the current polling cycle. According to each target cycle count value, one or more target cycle priority arbitration channels are determined. The target cycle priority arbitration channel is a read-write channel whose target cycle count value is equal to the preset initial value. The number of target cycle priority arbitration channels is counted to obtain the total number of target cycle priority arbitration channels. According to the total number of target cycle priority arbitration channels and the priority level value and channel number corresponding to the target cycle priority arbitration channel, the highest priority channel of the cycle is determined. In this way, there is no need to continuously raise the read-write channels that have not participated in the priority arbitration in each polling cycle. Instead, the read-write channels characterized by the number of arbitration opportunities being zero are directly selected in each polling cycle for priority arbitration, so that all read-write channels have equal arbitration opportunities in each polling cycle, and the bandwidth of the AXI bus can be evenly distributed to multiple read-write channels with the same priority, solving the problem of uneven bandwidth distribution between channels with the same priority. At the same time, it also avoids the problem that the requests of low-priority read-write channels cannot be responded to for a long time, thereby improving the rationality of bandwidth resource allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a flowchart of a multi-channel priority arbitration allocation method provided by some embodiments of the present application;

[0042] Figure 2is a working principle diagram of a multi-channel priority arbitration allocation method provided by some embodiments of the present application;

[0043] Figure 3 is a flowchart of a polling priority arbitration process of a polling cycle provided by some embodiments of the present application;

[0044] Figure 4 Some embodiments of the present application provide Figure 3 Flow chart of step S340;

[0045] Figure 5 is a flowchart of periodically allocating bandwidth resources provided by some embodiments of the present application;

[0046] Figure 6 Some embodiments of the present application provide Figure 5 Flow chart of step S530;

[0047] Figure 7 Other embodiments of the present application provide Figure 5 Flow chart of step S530;

[0048] Figure 8 A schematic diagram of the structure of a multi-channel priority arbitration allocation system provided in some embodiments of the present application;

[0049] Fig. 9 It is a schematic diagram of the hardware structure of an electronic device provided in some embodiments of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0052] It should also be noted that in the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used to distinguish the technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0054] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0055] First, some nouns involved in this application are analyzed:

[0056] The AXI (Advanced eXtensible Interface) bus protocol is an on-chip bus protocol designed to meet the communication requirements of high bandwidth and low latency. It provides multi-channel, independent addressing and data transmission capabilities.

[0057] In current technology, arbitration mechanisms for multiple requests are generally divided into the following categories: 1. Fixed priority arbitration mechanism, which conducts arbitration according to a predetermined priority response principle. However, this arbitration mechanism often results in low-priority channel requests not being responded to for a long time when high-priority channel requests occur frequently, and even causes low-priority channels to be paralyzed. 2. Polling priority arbitration mechanism, each time a requested channel participates in arbitration, the counter value is increased by 1, and then the priority of the next arbitration is determined based on the counter value, so that the arbitration priority of the unresponded channel can be continuously raised so that it can eventually get a response. However, this arbitration mechanism often results in each channel responding to requests unevenly, so that the total bandwidth is not evenly distributed among multiple channels with the same priority. When several channels with the same priority send requests at the same time and the requests occur frequently, it is easy to cause insufficient bandwidth for some channels.

[0058] Based on this, the embodiments of the present application provide a multi-channel priority arbitration allocation method, system, device and medium thereof, wherein a read-write arbitrator obtains each target cycle count value in a polling cycle in which each read-write channel is periodically polled for priority arbitration, the target cycle count value is the count value of the corresponding counter in the current polling cycle, and one or more target cycle priority arbitration channels are determined according to each target cycle count value, the target cycle priority arbitration channel is a read-write channel whose target cycle count value is equal to a preset initial value, the number of target cycle priority arbitration channels is counted, and the total number of target cycle priority arbitration channels is obtained; and according to the total number of target cycle priority arbitration channels and the target cycle priority First, the priority level value and channel number corresponding to the arbitration channel are determined to determine the highest priority channel in the cycle. There is no need to continuously raise the read-write channels that have not participated in the priority arbitration in each polling cycle. Instead, the read-write channels characterized by zero arbitration opportunities are directly selected in each polling cycle for priority arbitration. This ensures that all read-write channels have equal arbitration opportunities in each polling cycle, and thus the bandwidth of the AXI bus can be evenly distributed among multiple read-write channels of the same priority, solving the problem of uneven bandwidth distribution between channels of the same priority. At the same time, it also avoids the problem of long-term unresponsiveness of requests from low-priority read-write channels, thereby improving the rationality of bandwidth resource allocation.

[0059] A multi-channel priority arbitration allocation method and medium provided in an embodiment of the present application are specifically described through the following embodiments. First, a multi-channel priority arbitration allocation method in an embodiment of the present application is described.

[0060] It should be noted that the multi-channel priority arbitration allocation method is applied to a multi-channel priority arbitration allocation system, which includes multiple resource processing channels, an AXI bus and a cache management device. The cache management device includes an AXI bus, a read-write arbitrator and multiple read-write channels. The read-write arbitrator includes multiple counters, each counter corresponds to each read-write channel one by one, and the count value of the counter is used to represent the number of times the read-write channel gives up arbitration opportunities. The AXI bus is communicatively connected to the read-write arbitrator, and the read-write arbitrator is communicatively connected to each read-write channel respectively.

[0061] Reference Figure 1 and Figure 2 As shown, Figure 1 is a flowchart of a multi-channel priority arbitration allocation method provided by some embodiments of the present application, Figure 2 1 is a working principle diagram of a multi-channel priority arbitration allocation method provided in some embodiments of the present application. The multi-channel priority arbitration allocation method may include but is not limited to steps S110 to S130.

[0062] Step S110: the read / write arbitrator initializes the count value of each counter to a preset initial value in response to the asynchronous read / write request of each read / write channel, and obtains the priority level value and channel number of each read / write channel.

[0063] The preset initial value is used to indicate that the number of times the corresponding read / write channel grants arbitration opportunities is zero.

[0064] Assume that there are 4 read-write channels, namely ch0 read-write channel, ch1 read-write channel, ch2 read-write channel, and ch3 read-write channel. The channel number of ch0 read-write channel is "0" and the priority level value is 1, the channel number of ch1 read-write channel is "1" and the priority level value is 2, the channel number of ch2 read-write channel is "2" and the priority level value is 2, the channel number of ch3 read-write channel is "3" and the priority level value is 0, and the read-write arbitrator includes counter ch0_cnt, counter ch1_cnt, counter ch2_cnt, and counter ch3_cnt.

[0065] In some possible implementation examples, when the read-write arbiter responds to the asynchronous read-write requests of the above-mentioned four read-write channels, the count value of the counter ch0_cnt corresponding to the ch0 read-write channel is initialized to 0, the count value of the counter ch1_cnt corresponding to the ch1 read-write channel is initialized to 0, the count value of the counter ch2_cnt corresponding to the ch2 read-write channel is initialized to 0, and the count value of the counter ch3_cnt corresponding to the ch3 read-write channel is initialized to 0, and the priority level value [1, 2, 2, 0] corresponding to each read-write channel and the corresponding channel number ["0", "1", "2", "3"] are obtained.

[0066] Step S120: the read / write arbitrator performs periodic polling priority arbitration processing on each read / write channel according to each count value, each priority level value and each channel number to obtain the highest priority channel in each period.

[0067] The highest priority channel in the cycle is the read / write channel arbitrated as the highest priority among all the read / write channels in the same polling cycle.

[0068] Specifically, the read / write arbitrator performs periodic polling priority arbitration processing on each read / write channel according to each count value, each priority level value and each channel number to obtain the highest priority channel in each period.

[0069] In some possible implementation examples, in a polling cycle, the channel numbers of each read-write channel are ["0", "1", "2", "3"] respectively, the count value corresponding to the ch0 read-write channel is 0, the count value corresponding to the ch1 read-write channel is 0, the count value corresponding to the ch2 read-write channel is 0, the count value corresponding to the ch3 read-write channel is 0, the priority level value corresponding to the ch0 read-write channel is 2, the priority level value corresponding to the ch1 read-write channel is 2, the priority level value corresponding to the ch2 read-write channel is 1, and the priority level value corresponding to the ch3 read-write channel is 0. Then, the read-write arbitrator performs a polling priority arbitration process on the ch0 read-write channel, ch1 read-write channel, ch2 read-write channel, and ch3 read-write channel according to each count value, each priority level value and each channel number to obtain the highest priority channel in the polling cycle.

[0070] In some other possible implementation examples, in a polling cycle, the channel numbers of each read-write channel are ["0", "1", "2", "3"], the count value corresponding to the ch0 read-write channel is 3, the count value corresponding to the ch1 read-write channel is 0, the count value corresponding to the ch2 read-write channel is 0, the count value corresponding to the ch3 read-write channel is 0, the priority level value corresponding to the ch0 read-write channel is 1, the priority level value corresponding to the ch1 read-write channel is 2, the priority level value corresponding to the ch2 read-write channel is 2, and the priority level value corresponding to the ch3 read-write channel is 0. Then, the read-write arbitrator performs a polling priority arbitration process on the ch0 read-write channel, ch1 read-write channel, ch2 read-write channel, and ch3 read-write channel according to each count value and each channel number to obtain the highest priority channel in the polling cycle.

[0071] In some other possible implementation examples, in a polling cycle, the channel numbers of each read-write channel are ["0", "1", "2", "3"], the count value corresponding to the ch0 read-write channel is 2, the count value corresponding to the ch1 read-write channel is 2, the count value corresponding to the ch2 read-write channel is 0, the count value corresponding to the ch3 read-write channel is 0, the priority level value corresponding to the ch0 read-write channel is 1, the priority level value corresponding to the ch1 read-write channel is 1, the priority level value corresponding to the ch2 read-write channel is 2, and the priority level value corresponding to the ch3 read-write channel is 0. Then, the read-write arbitrator performs a polling priority arbitration process on the ch0 read-write channel, ch1 read-write channel, ch2 read-write channel, and ch3 read-write channel according to each count value and each channel number to obtain the highest priority channel in the polling cycle.

[0072] In some other possible implementation examples, in a polling cycle, the channel numbers of each read-write channel are ["0", "1", "2", "3"] respectively, the count value corresponding to the ch0 read-write channel is 1, the count value corresponding to the ch1 read-write channel is 1, the count value corresponding to the ch2 read-write channel is 1, and the count value corresponding to the ch3 read-write channel is 0. The priority level value corresponding to the ch0 read-write channel is 0, the priority level value corresponding to the ch1 read-write channel is 0, the priority level value corresponding to the ch2 read-write channel is 0, and the priority level value corresponding to the ch3 read-write channel is 1. Then, the read-write arbitrator performs a polling priority arbitration process on the ch0 read-write channel, ch1 read-write channel, ch2 read-write channel, and ch3 read-write channel according to each count value and each channel number to obtain the highest priority channel in the polling cycle.

[0073] Step S130: the read / write arbiter periodically allocates bandwidth resources of the AXI bus to corresponding read / write channels according to the highest priority channel in each cycle, and periodically updates each count value so that asynchronous read / write requests in each read / write channel are processed asynchronously.

[0074] In some possible implementation examples, in a polling cycle, if the highest priority channel of the cycle is the ch0 read-write channel, the read-write arbitrator allocates the bandwidth resources of the AXI bus to the ch0 read-write channel, and updates the count value of the ch0 read-write channel to 3, while the count values ​​of other read-write channels remain 0.

[0075] In some other possible implementation examples, in a polling cycle, if the highest priority channel of the cycle is the ch1 read-write channel, the read-write arbitrator allocates the bandwidth resources of the AXI bus to the ch1 read-write channel, and updates the count value of the ch1 read-write channel to 2, updates the count value of the ch0 read-write channel to 2, and the count values ​​of other read-write channels remain 0.

[0076] In other possible implementation examples, in a polling cycle, if the highest priority channel of the cycle is the ch2 read-write channel, the read-write arbiter allocates the bandwidth resources of the AXI bus to the ch2 read-write channel, and updates the count value of the ch2 read-write channel to 1, updates the count value of the ch1 read-write channel to 1, updates the count value of the ch0 read-write channel to 1, and the count values ​​of other read-write channels remain 0.

[0077] In other possible implementation examples, in a polling cycle, if the highest priority channel of the cycle is the ch3 read-write channel, the read-write arbiter allocates the bandwidth resources of the AXI bus to the ch3 read-write channel, and updates the count value of the ch3 read-write channel to 0, updates the count value of the ch2 read-write channel to 0, updates the count value of the ch1 read-write channel to 0, and updates the count value of the ch0 read-write channel to 0.

[0078] in, Figure 3 This is a flowchart of a polling priority arbitration process of a polling cycle provided by some embodiments of the present application. In a polling cycle of performing periodic polling priority arbitration process on each read / write channel, it may include but is not limited to steps S310 to S340.

[0079] Step S310: Obtain each target cycle count value.

[0080] The target cycle count value is the count value of the corresponding counter in the current polling cycle.

[0081] In some possible implementation examples, in a polling cycle, the target cycle count value corresponding to each read-write channel, where the target cycle count value corresponding to the ch0 read-write channel is 0, the target cycle count value corresponding to the ch1 read-write channel is 0, the target cycle count value corresponding to the ch2 read-write channel is 0, and the target cycle count value corresponding to the ch3 read-write channel is 0.

[0082] In some possible implementation examples, in a polling cycle, the target cycle count value corresponding to each read-write channel, where the target cycle count value corresponding to the ch0 read-write channel is 2, the target cycle count value corresponding to the ch1 read-write channel is 2, the target cycle count value corresponding to the ch2 read-write channel is 0, and the target cycle count value corresponding to the ch3 read-write channel is 0.

[0083] In some possible implementation examples, in a polling cycle, the target cycle count value corresponding to each read-write channel, where the target cycle count value corresponding to the ch0 read-write channel is 1, the target cycle count value corresponding to the ch1 read-write channel is 1, the target cycle count value corresponding to the ch2 read-write channel is 1, and the target cycle count value corresponding to the ch3 read-write channel is 0.

[0084] Step S320: Determine one or more target cycle priority arbitration channels according to each target cycle count value.

[0085] The target cycle priority arbitration channel is a read / write channel whose target cycle count value is equal to a preset initial value.

[0086] In some possible implementation examples, since the preset initial value is 0, according to the target cycle count value corresponding to the ch0 read-write channel being 0, the target cycle count value corresponding to the ch1 read-write channel being 0, the target cycle count value corresponding to the ch2 read-write channel being 0, and the target cycle count value corresponding to the ch3 read-write channel being 0, it can be determined that the ch0 read-write channel, the ch1 read-write channel, the ch2 read-write channel, and the ch3 read-write channel are target cycle priority arbitration channels.

[0087] In some possible implementation examples, since the preset initial value is 0, according to the target cycle count value corresponding to the ch0 read-write channel is 2, the target cycle count value corresponding to the ch1 read-write channel is 2, the target cycle count value corresponding to the ch2 read-write channel is 0, and the target cycle count value corresponding to the ch3 read-write channel is 0, it can be determined that the ch2 read-write channel and the ch3 read-write channel are target cycle priority arbitration channels.

[0088] In some possible implementation examples, since the preset initial value is 0, according to the target cycle count value corresponding to the ch0 read-write channel is 1, the target cycle count value corresponding to the ch1 read-write channel is 1, the target cycle count value corresponding to the ch2 read-write channel is 1, and the target cycle count value corresponding to the ch3 read-write channel is 0, it can be determined that the ch3 read-write channel is the target cycle priority arbitration channel.

[0089] Step S330: Count the number of target cycle priority arbitration channels to obtain the total number of target cycle priority arbitration channels.

[0090] In some possible implementation examples, since ch0 read / write channel, ch1 read / write channel, ch2 read / write channel and ch3 read / write channel are target cycle priority arbitration channels, the number of target cycle priority arbitration channels is counted, and the total number of target cycle priority arbitration channels is 4.

[0091] In some possible implementation examples, since the ch2 read / write channel and the ch3 read / write channel are target cycle priority arbitration channels, the number of target cycle priority arbitration channels is counted, and the total number of target cycle priority arbitration channels is 2.

[0092] In some possible implementation examples, since the ch3 read / write channel is a target cycle priority arbitration channel, the number of target cycle priority arbitration channels is counted, and the total number of target cycle priority arbitration channels is 1.

[0093] Step S340: Determine the highest priority channel of the cycle according to the total number of priority arbitration channels of the target cycle and the priority level values ​​and channel numbers corresponding to the priority arbitration channels of the target cycle.

[0094] In some possible implementation examples, since the ch0 read-write channel, ch1 read-write channel, ch2 read-write channel and ch3 read-write channel are target cycle priority arbitration channels, the total number of target cycle priority arbitration channels is 4, the priority level value corresponding to the ch0 read-write channel is 2, the priority level value corresponding to the ch1 read-write channel is 2, the priority level value corresponding to the ch2 read-write channel is 1, the priority level value corresponding to the ch3 read-write channel is 0, and the channel numbers of the total number of target cycle priority arbitration channels are ["0", "1", "2", "3"] respectively, it is determined that the highest priority channel in the current polling cycle is the ch0 read-write channel.

[0095] In some possible implementation examples, since the ch2 read-write channel and the ch3 read-write channel are the target cycle priority arbitration channels, the total number of target cycle priority arbitration channels is 2, the priority level value corresponding to the ch0 read-write channel is 1, the priority level value corresponding to the ch1 read-write channel is 1, the priority level value corresponding to the ch2 read-write channel is 2, the priority level value corresponding to the ch3 read-write channel is 0, and the channel numbers of the total number of target cycle priority arbitration channels are ["2", "3"] respectively, it is determined that the highest priority channel in the current polling cycle is the ch2 read-write channel.

[0096] In some possible implementation examples, since the ch3 read-write channel is the target cycle priority arbitration channel, the total number of target cycle priority arbitration channels is 1, the priority level value corresponding to the ch0 read-write channel is 0, the priority level value corresponding to the ch1 read-write channel is 0, the priority level value corresponding to the ch2 read-write channel is 0, the priority level value corresponding to the ch3 read-write channel is 1, and the channel numbers of the total number of target cycle priority arbitration channels are ["3"] respectively, determining that the highest priority channel in the current polling cycle is the ch3 read-write channel.

[0097] Reference Figure 4 As shown, Figure 4 Some embodiments of the present application provide Figure 3 In the flowchart of step S340, the multi-channel priority arbitration allocation method may include but is not limited to steps S410 to S420.

[0098] Step S410: when the total number of target cycle priority arbitration channels is one, determine the target cycle priority arbitration channel as the cycle highest priority channel in the current polling cycle.

[0099] The target period working channel list includes one or more resource processing channels that need to work synchronously in the current period.

[0100] In some possible implementation examples, since only the ch3 read-write channel is the target cycle priority arbitration channel, that is, the total number of cycle priority arbitration channels is 1, and when the total number of target cycle priority arbitration channels is one, the target cycle priority arbitration channel (that is, the ch3 read-write channel) is determined as the cycle highest priority channel under the current polling cycle, that is, the ch3 read-write channel is the cycle highest priority channel under the current polling cycle.

[0101] Step S420: Alternatively, when there are a plurality of target cycle priority arbitration channels, one or more target cycle priority arbitration channels having the highest priority level values ​​among the target cycle priority arbitration channels are determined as the reserve highest priority channels.

[0102] In some possible implementation examples, since only the ch0 read-write channel, ch1 read-write channel, ch2 read-write channel and ch3 read-write channel are target cycle priority arbitration channels, that is, the total number of cycle priority arbitration channels is 4, and the priority level value corresponding to the ch0 read-write channel is 2, the priority level value corresponding to the ch1 read-write channel is 2, the priority level value corresponding to the ch2 read-write channel is 1, and the priority level value corresponding to the ch3 read-write channel is 0, then the target cycle priority arbitration channels with the highest priority level values ​​are ch0 read-write channel and ch1 read-write channel, that is, ch0 read-write channel and ch1 read-write channel are determined as the reserve highest priority channels.

[0103] In some possible implementation examples, since only the ch2 read-write channel and the ch3 read-write channel are target cycle priority arbitration channels, that is, the total number of cycle priority arbitration channels is 2, and the priority level value corresponding to the ch0 read-write channel is 1, the priority level value corresponding to the ch1 read-write channel is 1, the priority level value corresponding to the ch2 read-write channel is 2, and the priority level value corresponding to the ch3 read-write channel is 0, then the target cycle priority arbitration channel with the highest priority level value is the ch2 read-write channel, that is, the ch2 read-write channel is determined as the reserve highest priority channel.

[0104] Step S440: If the number of the prepared highest priority channel is one, the prepared highest priority channel is determined as the periodic highest priority channel in the current polling cycle.

[0105] In some possible implementation examples, since only the ch2 read-write channel is the prepared highest priority channel, that is, the number of prepared highest priority channels is one, the prepared highest priority channel is determined as the periodic highest priority channel under the current polling cycle, that is, the ch2 read-write channel is the periodic highest priority channel under the current polling cycle.

[0106] Step S450: If there are multiple prepared highest priority channels, among the prepared highest priority channels, the prepared highest priority channel with the smallest channel number is determined as the periodic highest priority channel in the current polling cycle.

[0107] In some possible implementation examples, since the ch0 read-write channel and the ch1 read-write channel are the prepared highest priority channels, that is, the total number of prepared highest priority channels is 2, and the channel number ("0") corresponding to the ch0 read-write channel is the smallest channel number among the channel numbers ["0", "1"] corresponding to each prepared highest priority channel, and when the number of prepared highest priority channels is multiple, the target cycle priority arbitration channel (i.e., the ch0 read-write channel) whose corresponding channel number is the smallest is determined as the cycle highest priority channel under the current polling cycle, that is, the ch0 read-write channel is the cycle highest priority channel under the current polling cycle.

[0108] Reference Figure 5 As shown, Figure 5 This is a flowchart of periodically allocating bandwidth resources provided by some embodiments of the present application. The periodic allocation of bandwidth resources may include but is not limited to steps S510 to S530.

[0109] Step S510: According to the current polling cycle, the highest priority channel of the corresponding cycle and the total number of priority arbitration channels of the target cycle are obtained.

[0110] In some possible implementation examples, according to the current polling cycle, the corresponding cycle highest priority channel (ch3 read / write channel) and the total number of target cycle priority arbitration channels are obtained as 1.

[0111] In some other possible implementation examples, according to the current polling cycle, the corresponding cycle highest priority channel (ch0 read / write channel) and the total number of target cycle priority arbitration channels are obtained to be 4.

[0112] In some other possible implementation examples, according to the current polling cycle, the corresponding cycle highest priority channel (ch2 read / write channel) and the total number of target cycle priority arbitration channels are obtained to be 2.

[0113] Step S520: Allocate bandwidth resources of the AXI bus to the channel with the highest cycle priority.

[0114] Specifically, the bandwidth resources of the AXI bus are allocated to the channel with the highest cycle priority, for example: the bandwidth resources of the AXI bus are allocated to the channel with the highest cycle priority (ch3 read-write channel); the bandwidth resources of the AXI bus are allocated to the channel with the highest cycle priority (ch0 read-write channel); the bandwidth resources of the AXI bus are allocated to the channel with the highest cycle priority (ch2 read-write channel).

[0115] Step S530: updating the target cycle count values ​​corresponding to the relevant read / write channels according to the total number of target cycle priority arbitration channels.

[0116] In some possible implementation examples, according to the total number of target cycle priority arbitration channels being 1, the target cycle count values ​​corresponding to the ch0 read / write channel, the ch1 read / write channel, the ch2 read / write channel, and the ch3 read / write channel are updated.

[0117] In some possible implementation examples, according to the total number of target cycle priority arbitration channels being 4, the target cycle count value corresponding to the ch0 read / write channel is updated.

[0118] In some possible implementation examples, according to the total number of target cycle priority arbitration channels being 2, the target cycle count values ​​corresponding to the ch0 read / write channel, the ch1 read / write channel, and the ch2 read / write channel are updated.

[0119] Reference Figure 6 As shown, Figure 6 Some embodiments of the present application provide Figure 5 In the flowchart of step S530, the periodic allocation of bandwidth resources may include but is not limited to step S610.

[0120] Step S610: When the total number of target cycle priority arbitration channels is one, the target cycle count values ​​corresponding to all read and write channels are synchronously updated to a preset initial value.

[0121] In some possible implementation examples, the total number of target cycle priority arbitration channels is 1. At this time, the target cycle count value corresponding to the ch0 read-write channel is 1, the target cycle count value corresponding to the ch1 read-write channel 1 is 1, the target cycle count value corresponding to the ch2 read-write channel is 1, and the target cycle count value corresponding to the ch3 read-write channel is 0. The target cycle count values ​​corresponding to all read-write channels (ch0 read-write channel, ch1 read-write channel, ch2 read-write channel, ch3 read-write channel) are synchronously updated to the preset initial value 0.

[0122] Reference Figure 7 As shown, Figure 7 Other embodiments of the present application provide Figure 5 In the flowchart of step S530, the periodic allocation of bandwidth resources may include but is not limited to steps S710 to S730.

[0123] Step S710: When the total number of target cycle priority arbitration channels is multiple, the target cycle count value corresponding to the read / write channel determined as the cycle highest priority channel is updated to the cycle maximum count threshold.

[0124] The cycle maximum count threshold is used to indicate that the number of times the corresponding read / write channel releases arbitration opportunities in the current polling cycle is the maximum upper limit.

[0125] In some possible implementation examples, when the total number of target cycle priority arbitration channels is 4, the read-write channels determined as target cycle priority arbitration channels include ch0 read-write channel, ch1 read-write channel, ch2 read-write channel and ch3 read-write channel, and the read-write channel determined as the highest priority channel of the cycle is ch0 read-write channel, then the target cycle count value corresponding to the ch0 read-write channel is updated from the preset initial value 0 to the cycle maximum count threshold 3, where, in the current polling cycle, the cycle maximum count threshold = 3.

[0126] In some possible implementation examples, when the total number of target cycle priority arbitration channels is 3, the read-write channels determined as target cycle priority arbitration channels include ch1 read-write channel, ch2 read-write channel and ch3 read-write channel, and the read-write channel determined as the highest cycle priority channel is ch1 read-write channel, then the target cycle count value corresponding to the ch1 read-write channel is updated from the preset initial value 0 to the cycle maximum count threshold 2, where, in the current polling cycle, the cycle maximum count threshold = 2.

[0127] In some possible implementation examples, when the total number of target cycle priority arbitration channels is 2, the read-write channels determined as target cycle priority arbitration channels include the ch2 read-write channel and the ch3 read-write channel, and the read-write channel determined as the highest cycle priority channel is the ch2 read-write channel, then the target cycle count value corresponding to the ch2 read-write channel is updated from the preset initial value 0 to the cycle maximum count threshold 1, where, in the current polling cycle, the cycle maximum count threshold = 1.

[0128] Step S720: Synchronously update the target cycle count value corresponding to the read / write channel that is not determined as the target cycle priority arbitration channel to the cycle decrement count value.

[0129] The cycle decrement count value is the difference between the target cycle count value corresponding to the read / write channel whose target cycle priority arbitration channel is not determined and the preset cycle decrement value. The cycle decrement value is used to indicate that the number of times the corresponding read / write channel gives up arbitration opportunities is once.

[0130] In some possible implementation examples, when the total number of target cycle priority arbitration channels is 4, the read-write channels determined as target cycle priority arbitration channels include ch0 read-write channel, ch1 read-write channel, ch2 read-write channel and ch3 read-write channel, and the number of read-write channels that are not determined as target cycle priority arbitration channels is 0, and step S720 does not need to be executed.

[0131] In some possible implementation examples, when the total number of target cycle priority arbitration channels is 3, the read-write channels determined as target cycle priority arbitration channels include ch1 read-write channel, ch2 read-write channel and ch3 read-write channel, and the read-write channels that are not determined as target cycle priority arbitration channels include ch0 read-write channel, and the target cycle count value corresponding to the ch0 read-write channel is 3, then the ch0 read-write channel is updated to the cycle decrement count value 2, wherein the cycle decrement count value corresponding to the ch0 read-write channel = 3 (target cycle count value) - 1 (preset cycle decrement value) = 2.

[0132] In some possible implementation examples, when the total number of target cycle priority arbitration channels is 2, the read-write channels determined as target cycle priority arbitration channels include the ch2 read-write channel and the ch3 read-write channel, and the read-write channels that are not determined as target cycle priority arbitration channels include the ch0 read-write channel and the ch1 read-write channel, and the target cycle count value corresponding to the ch0 read-write channel is 2, and the target cycle count value corresponding to the ch1 read-write channel is 2, then the ch0 read-write channel is updated to the cycle decrement count value 1, and the ch1 read-write channel is updated to the cycle decrement count value 1, wherein the cycle decrement count value corresponding to the ch0 read-write channel = 2 (target cycle count value) - 1 (preset cycle decrement value) = 1, and the cycle decrement count value 1 corresponding to the ch1 read-write channel = 2 (target cycle count value) - 1 (preset cycle decrement value) = 1.

[0133] In a second aspect, the present application embodiment also provides a multi-channel priority arbitration allocation system, referring to Figure 8 , Figure 8 This is a schematic diagram of the structure of a multi-channel priority arbitration allocation system provided in some embodiments of the present application. The multi-channel priority arbitration allocation system 800 includes:

[0134] AXI bus 810, read / write arbiter 820 and multiple read / write channels 830, the read / write arbiter 820 includes multiple counters 821, each counter 821 corresponds to each read / write channel 830, the count value of counter 821 is used to represent the number of times the read / write channel 830 gives up arbitration opportunities, the AXI bus 810 is connected in communication with the read / write arbiter 820, and the read / write arbiter 820 is connected in communication with each read / write channel 830, wherein:

[0135] The read / write arbiter 820 is configured to, in response to the asynchronous read / write request of each read / write channel 830, initialize the count value of each counter 821 to a preset initial value, and obtain the channel number of each read / write channel 830, wherein the preset initial value is used to indicate that the number of times the corresponding read / write channel 830 has given up arbitration opportunities is zero;

[0136] The read / write arbiter 820 is further configured to perform periodic polling priority arbitration processing on each read / write channel 830 according to each count value and each channel number to obtain the highest priority channel of each cycle; the highest priority channel of each cycle is the read / write channel 830 arbitrated as the highest priority among the read / write channels 830 in the same polling cycle;

[0137] The read / write arbiter 820 is further configured to periodically allocate bandwidth resources of the AXI bus 810 to corresponding read / write channels 830 according to the highest priority channel in each cycle, and periodically update each count value so that the asynchronous read / write requests in each read / write channel 830 are processed asynchronously;

[0138] Among them, in a polling cycle in which periodic polling priority arbitration processing is performed on each read-write channel 830, the following steps are included: obtaining each target cycle count value; the target cycle count value is the count value of the corresponding counter 821 in the current polling cycle; according to each target cycle count value, determining one or more target cycle priority arbitration channels, the target cycle priority arbitration channel is the read-write channel 830 whose target cycle count value is equal to a preset initial value; counting the number of target cycle priority arbitration channels to obtain the total number of target cycle priority arbitration channels; determining the highest priority channel of the cycle according to the total number of target cycle priority arbitration channels and the channel number corresponding to the target cycle priority arbitration channel.

[0139] The above-mentioned multi-channel priority arbitration allocation system 800 and the above-mentioned multi-channel priority arbitration allocation method are based on the same inventive concept. The above-mentioned process describes the multi-channel priority arbitration allocation system 800 of the embodiment of the present application. The read-write arbitrator responds to the asynchronous read-write requests of each of the read-write channels, initializes the count value of each of the counters to a preset initial value, and obtains the channel number of each of the read-write channels, wherein the preset initial value is used to represent that the number of times the corresponding read-write channel gives up arbitration opportunities is zero, and then, according to each count value and each channel number, periodically polling priority arbitration processing is performed on each of the read-write channels to obtain the highest priority channel of each cycle, and the highest priority channel of the cycle is the read-write channel arbitrated as the highest priority among the read-write channels in the same polling cycle. Finally, according to each of the highest priority channels of the cycle, the bandwidth resources of the AXI bus are periodically allocated to the corresponding read-write channels, and each count value is periodically updated so that the asynchronous read-write requests in each read-write channel are asynchronously processed; wherein, when each read-write channel is periodically polled, priority arbitration processing is performed on each of the read-write channels. In a polling cycle of the polling priority arbitration processing, by obtaining each target cycle count value, the target cycle count value is the count value of the corresponding counter in the current polling cycle, and according to each target cycle count value, one or more target cycle priority arbitration channels are determined, the target cycle priority arbitration channel is a read-write channel whose target cycle count value is equal to a preset initial value, and the number of target cycle priority arbitration channels is counted to obtain the total number of target cycle priority arbitration channels. According to the total number of target cycle priority arbitration channels and the channel numbers corresponding to the target cycle priority arbitration channels, the highest priority channel of the cycle is determined, and then there is no need to continuously raise the read-write channels that have not participated in the priority arbitration in each polling cycle, but directly select the read-write channels characterized by the number of arbitration opportunities being zero in each polling cycle for priority arbitration, so that all read-write channels have equal arbitration opportunities in each polling cycle, and then the bandwidth of the AXI bus can be evenly distributed to each read-write channel, avoiding the long-term failure to respond to the requests of low-priority read-write channels, and improving the rationality of bandwidth resource allocation.

[0140] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above multi-channel priority arbitration allocation method when executing the computer program. The electronic device can be any smart terminal including a mobile phone, a tablet computer, a car computer, etc.

[0141] See also Fig. 9 , Fig. 9 : is a schematic diagram of the hardware structure of an electronic device provided in some embodiments of the present application, and the electronic device includes:

[0142] The processor 901 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the multi-channel priority arbitration allocation method provided in the embodiment of the present application;

[0143] The memory 902 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 902 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 902, and the processor 901 calls and executes the multi-channel priority arbitration allocation method provided in the embodiment of this application;

[0144] Input / output interface 903, used to implement information input and output;

[0145] Communication interface 904, used to realize communication interaction between the device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.);

[0146] A bus 905 that transmits information between various components of the device (e.g., the processor 901, the memory 902, the input / output interface 903, and the communication interface 904);

[0147] The processor 901 , the memory 902 , the input / output interface 903 and the communication interface 904 are connected to each other in communication within the device via a bus 905 .

[0148] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the multi-channel priority arbitration allocation method provided in the embodiment of the present application is implemented.

[0149] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0150] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0151] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0152] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0153] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0154] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0155] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0156] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0157] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0158] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0159] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0160] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A multi-channel priority arbitration allocation method, applied to a multi-channel priority arbitration allocation system, the multi-channel priority arbitration allocation system comprising an AXI bus, a read-write arbitrator and a plurality of read-write channels, the read-write arbitrator comprising a plurality of counters, each of the counters corresponding to each of the read-write channels, the count value of the counter being used to characterize the number of times the read-write channel gives up arbitration opportunities, the AXI bus being communicatively connected to the read-write arbitrator, the read-write arbitrator being communicatively connected to each of the read-write channels, characterized in that: The multi-channel priority arbitration allocation method comprises: The read / write arbiter initializes the count value of each counter to a preset initial value in response to the asynchronous read / write request of each read / write channel, and obtains the priority level value and channel number of each read / write channel, wherein the preset initial value is used to indicate that the number of times the corresponding read / write channel gives up arbitration opportunities is zero; The read / write arbitrator performs periodic polling priority arbitration processing on each of the read / write channels according to each of the count values, each of the priority level values ​​and each of the channel numbers to obtain a channel with the highest priority in each cycle; the channel with the highest priority in each cycle is the read / write channel arbitrated as the highest priority among the read / write channels in the same polling cycle; The read / write arbiter periodically allocates bandwidth resources of the AXI bus to the corresponding read / write channels according to the highest priority channels of each period, and periodically updates each count value so that the asynchronous read / write requests in each read / write channel are processed asynchronously; Wherein, in a polling cycle of periodically performing polling priority arbitration processing on each of the read-write channels, the following steps are included: Obtaining each target cycle count value, wherein the target cycle count value is a count value corresponding to the counter in the current polling cycle; According to each target cycle count value, one or more target cycle priority arbitration channels are determined, wherein the target cycle priority arbitration channel is the read / write channel whose target cycle count value is equal to the preset initial value; the number of the target cycle priority arbitration channels is counted to obtain the total number of the target cycle priority arbitration channels; when the total number of the target cycle priority arbitration channels is one, the target cycle priority arbitration channel is determined as the highest priority channel of the cycle under the current polling cycle; Alternatively, when there are a plurality of target cycle priority arbitration channels in total, among the target cycle priority arbitration channels, one or more target cycle priority arbitration channels with the highest priority level values ​​are determined as the reserve highest priority channels; If the number of the prepared highest priority channels is one, determining the prepared highest priority channel as the periodic highest priority channel in the current polling cycle; If there are multiple prepared highest priority channels, the prepared highest priority channel with the smallest channel number among the prepared highest priority channels is determined as the periodic highest priority channel in the current polling cycle.

2. The multi-channel priority arbitration allocation method according to claim 1, characterized in that: In a polling cycle of periodically allocating the bandwidth resources of the AXI bus to the corresponding read / write channel and updating the corresponding count value, the method includes: According to the current polling cycle, obtain the corresponding highest priority channel of the cycle and the total number of priority arbitration channels of the target cycle; Allocating bandwidth resources of the AXI bus to the highest priority channel of the cycle; According to the total number of the target cycle priority arbitration channels, the target cycle count value corresponding to the relevant read / write channel is updated.

3. The multi-channel priority arbitration allocation method according to claim 2, characterized in that: The updating of the target cycle count value corresponding to the relevant read / write channel according to the total number of the target cycle priority arbitration channels includes: When the total number of the target cycle priority arbitration channels is one, the target cycle count values ​​corresponding to all the read-write channels are synchronously updated to the preset initial value.

4. The multi-channel priority arbitration allocation method according to claim 2, characterized in that: The updating of the target cycle count value corresponding to the relevant read / write channel according to the total number of the target cycle priority arbitration channels also includes: When the total number of the target cycle priority arbitration channels is multiple, the target cycle count value corresponding to the read / write channel determined as the highest priority channel of the cycle is updated to the cycle maximum count threshold; Synchronously updating the target cycle count value corresponding to the read / write channel that is not determined as the target cycle priority arbitration channel to a cycle decrement count value; Among them, the cycle decrement count value is the difference between the target cycle count value corresponding to the read-write channel of the target cycle priority arbitration channel that is not determined and the preset cycle decrement value, the cycle decrement value is used to represent that the number of times the corresponding read-write channel gives up arbitration opportunities is once, and the cycle maximum count threshold is used to represent that under the current polling cycle, the number of times the corresponding read-write channel gives up arbitration opportunities is the maximum upper limit.

5. A multi-channel priority arbitration allocation system, characterized in that: include: An AXI bus, a read-write arbiter and a plurality of read-write channels, wherein the read-write arbiter comprises a plurality of counters, each of the counters corresponds to each of the read-write channels one by one, and the count value of the counter is used to characterize the number of times the read-write channel gives up arbitration opportunities, the AXI bus is communicatively connected to the read-write arbiter, and the read-write arbiter is communicatively connected to each of the read-write channels respectively, wherein: The read / write arbiter is configured to, in response to the asynchronous read / write request of each of the read / write channels, initialize the count value of each of the counters to a preset initial value, and obtain the channel number of each of the read / write channels, wherein the preset initial value is used to indicate that the number of times the corresponding read / write channel grants arbitration opportunities is zero; The read / write arbitrator is further configured to perform periodic polling priority arbitration processing on each of the read / write channels according to each of the count values ​​and each of the channel numbers to obtain a channel with the highest priority in each cycle; the channel with the highest priority in each cycle is the read / write channel arbitrated as the highest priority among the read / write channels in the same polling cycle; The read / write arbiter is further configured to periodically allocate bandwidth resources of the AXI bus to the corresponding read / write channels according to the highest priority channels of each period, and periodically update each count value so that the asynchronous read / write requests in each read / write channel are processed asynchronously; Wherein, in a polling cycle of periodically performing polling priority arbitration processing on each of the read-write channels, the following steps are included: Obtaining each target cycle count value; the target cycle count value is the count value corresponding to the counter in the current polling cycle; According to each target cycle count value, one or more target cycle priority arbitration channels are determined, and the target cycle priority arbitration channel is the read / write channel whose target cycle count value is equal to the preset initial value; the number of the target cycle priority arbitration channels is counted to obtain the total number of the target cycle priority arbitration channels; according to the total number of the target cycle priority arbitration channels and the channel number corresponding to the target cycle priority arbitration channel, the highest priority channel of the cycle is determined.

6. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the multi-channel priority arbitration allocation method according to any one of claims 1 to 4 when executing the computer program.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program executable by a processor, and when the program executable by the processor is executed by the processor, the multi-channel priority arbitration allocation method according to any one of claims 1 to 4 is implemented.

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