System on chip, computing system and storage method

Abstract

A system on chip includes: a plurality of processors; a system level cache shared by the plurality of processors; and a cache controller that, when the system-level cache receives first data from at least one of the plurality of processors, transmits the first data to another chip if an atomic operation has been performed on the first data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0076407 filed in the Korean Intellectual Property Office on June 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a system on chip, a computing system and a stashing method. Background Art

[0004] Multi-chip computing systems can be implemented using a variety of architectures. Two common architectures for these systems are unified memory access (UMA) and non-uniform memory access (NUMA). In a UMA system, multiple chips access a single memory through a bus, and all of these chips have the same access rate to the memory. However, as the number of chips increases, potential bottlenecks may occur, resulting in reduced memory access performance. In a NUMA system, the chips have their own internal memories. These internal memories are interconnected through a network so that each chip can access not only its own memory but also the memories of other chips.

[0005] In a NUMA system, a chip's memory access rate may differ depending on the location of the target memory. For example, accessing external memory may be slower than accessing its own internal memory, potentially reducing overall memory access performance. Furthermore, as the number of chips in a NUMA system increases, these differences in access rates may occur more frequently, resulting in further performance degradation. Summary of the invention

[0006] The present disclosure provides a system on chip, a computing system and a storage method, which can reduce the read waiting time when a chip in a non-uniform memory access (NUMA) system accesses shared data in another chip.

[0007] An embodiment of the present disclosure provides a system on chip, comprising: multiple processors; a system-level cache shared by the multiple processors; and a cache controller, wherein when the system-level cache receives first data from at least one of the multiple processors, if an atomic operation has been performed on the first data, the cache controller sends the first data to another chip.

[0008] An embodiment of the present disclosure provides a computing system, including: a first chip, which sends the first data to a second chip when an atomic operation has been performed on the first data; and a second chip, which shares the first data with the first chip and sends information about whether the first data has been read to the first chip in response to receiving the first data.

[0009] An embodiment of the present disclosure provides a storage method of a system on chip, including: obtaining the address of a cache line subjected to an atomic operation; incrementing a stash value when the cache line has been read by other systems on chip, and decrementing the stash value when the cache line has not been read by other systems on chip; and determining whether to store the cache line based on the address and the stash value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic block diagram of a multi-chip computing system according to an embodiment of the present disclosure.

[0011] Figure 2 is based on Figure 1 A block diagram of a first chip of an embodiment of the present invention.

[0012] Figure 3 Is used to explain the Figure 1 FIG. 4 is a diagram of an internal cache of an embodiment.

[0013] Figure 4 is based on Figure 1 A block diagram of a second chip of an embodiment of the present invention.

[0014] Figure 5 Is used to explain the Figure 1 A diagram of the operation of the first chip of an embodiment.

[0015] Figure 6 is a flowchart for explaining a cache line processing method performed by a system level cache according to an embodiment of the present disclosure.

[0016] Figure 7 is a flowchart for explaining a cache line processing method performed by a system level cache according to an embodiment of the present disclosure.

[0017] Figure 8 is a flowchart for explaining a deposit value determination method performed by a system-level cache according to an embodiment of the present disclosure.

[0018] Fig. 9 is a flowchart for explaining a deposit value determination method performed by a system-level cache according to an embodiment of the present disclosure.

[0019] Fig.10 is a diagram for explaining the operation of a system-level cache according to an embodiment of the present disclosure.

[0020] Fig.11 is a diagram for explaining the operation of the first chip according to an embodiment of the present disclosure.

[0021] Fig.12 is a diagram for explaining the operation of a computing system according to an embodiment of the present disclosure.

[0022] Fig.13 is a diagram for explaining the operation of a computing system according to an embodiment of the present disclosure.

[0023] Fig.14 is a diagram for explaining the operation of the second chip according to an embodiment of the present disclosure.

[0024] Fig.15 is a schematic block diagram of a multi-chip computing system according to an embodiment of the present disclosure.

[0025] Fig.16 is a block diagram of a mobile device according to an embodiment of the present disclosure.

[0026] Fig.17 is a block diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In this specification, only certain embodiments of the present disclosure are shown and described. As those skilled in the art will appreciate, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0028] Therefore, the drawings and the present specification should be considered to be illustrative and non-restrictive in nature. Throughout the specification, the same reference numerals may indicate the same elements. In the flowcharts described with reference to the drawings, the order of operations may be changed, several operations may be combined, an operation may be split, and some operations may not be performed.

[0029] In addition, unless an explicit expression such as "one" or "single" is used, an expression written in the singular may be interpreted as a singular form or a plural form. Terms including ordinal numbers (such as first and second) are used to describe various constituent elements, but the constituent elements are not limited by these terms. For example, these terms are used to distinguish one constituent element from other constituent elements.

[0030] Figure 1 is a schematic block diagram of a multi-chip computing system according to an embodiment of the present disclosure.

[0031] See also Figure 1, the computing system 10 according to the embodiment may be a multi-chip computing system. For example, the computing system 10 may include a first chip 100 and a second chip 200. The first chip 100 and the second chip 200 are multi-processor chips and may be a system on chip (SOC). However, the present embodiment is not necessarily limited thereto, and at least one of the first chip 100 and the second chip 200 may be implemented as a single processor chip.

[0032] The computing system 10 may be arranged in an electronic device and operated in the electronic device. The electronic device may be implemented as a personal computer (PC), a data server, a laptop computer, an automotive electronic component, or a portable device. The portable device may be implemented as a mobile phone, a smart phone, a tablet PC, a wearable device, a personal digital assistant (PDA), an enterprise digital assistant (EDA), an image processing device equipped with an image sensor, a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, or an electronic book.

[0033] The first chip 100 and the second chip 200 may share data. The data shared by the first chip 100 and the second chip 200 may be an independent variable used to synchronize execution between threads in situations such as parallel computing. In other words, in parallel computing, the data shared between the first chip 100 and the second chip 200 may be used as an independent variable to synchronize thread execution. Examples of independent variables used for synchronization may include lock independent variables that ensure mutual exclusion of other threads, conditional variable independent variables that keep threads in a waiting state based on a logical condition, barrier independent variables that require all threads to wait until a specific execution time point, etc.

[0034] The first chip 100 and the second chip 200 may share the first data and the second data. In this case, the first chip 100 may manage the first data, and the second chip 200 may manage the second data. In other words, the first chip 100 may be a master node of the first data and a remote node of the second data. The second chip 200 may be a remote node of the first data and a master node of the second data. The waiting time required for the second chip 200 to access the first data may be longer than the waiting time required for the first chip 100 to access the first data. Similarly, the waiting time required for the first chip 100 to access the second data may be longer than the waiting time required for the second chip 200 to access the second data. As the remote node accesses the data in the master node more frequently, the performance of the computing system 10 may be reduced. The computing system 10 may be a non-uniform memory access (NUMA) system.

[0035] The first chip 100 may pre-send the first data to the second chip 200 as a remote node. The action of the first chip 100 pre-sending the first data may be referred to as a deposit operation. The first chip 100 may determine a deposit value of the first data and determine whether to pre-send the first data based on the deposit value.

[0036] The first chip 100 may determine the deposited value based on the feedback response from the second chip 200. The first chip 100 may send the first data to the second chip 200 and the second chip 200 may send positive feedback or negative feedback to the first chip 100 in response to the first data. In addition, in the case where the first chip 100 does not send the first data to the second chip 200, the first chip 100 may update the deposited value according to whether a read request for the first data has been received from the second chip 200. The first chip 100 may send the first data in advance, thereby reducing the waiting time required for the second chip 200 to access the first data.

[0037] In this embodiment, the first chip 100 as the master node can update the first data. Based on the stored value of the updated first data, the first chip 100 can determine whether to send the updated first data to the second chip 200. According to the determination, the first chip 100 can send the updated first data to the second chip 200 or not send the updated first data to the second chip 200.

[0038] In this embodiment, the second chip 200 as a remote node may update the first data. In other words, the second chip 200 may have received the first data from the first chip 100 before updating the first data. The second chip 200 may send the updated first data to the first chip 100. In the case where the computing system 10 also includes chips other than the first chip 100 and the second chip 200, the first chip 100 may determine whether to send the updated first data to other chips as remote nodes based on the stored value of the updated first data. According to the determination, the first chip 100 may send the updated first data to other chips or may not send the updated first data to other chips.

[0039] Figure 2 is based on Figure 1 A block diagram of a first chip of an embodiment, Figure 3 Is used to explain the Figure 1 Figure 1. An internal cache diagram of an embodiment, Figure 4 is based on Figure 1 A block diagram of a second chip of an embodiment of the present invention.

[0040] See also Figure 2, the first chip 100 may include a plurality of processors 110 and 120, a memory 130, a system level cache (SLC) 140, and a directory cache (DRC) 150. The plurality of processors 110 and 120, the memory 130, the system level cache 140, and the directory cache 150 may perform communication with each other and with other chips through a bus 160. In other words, the bus 160 may be used as an interface for supporting communication between components.

[0041] The plurality of processors 110 and 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a microprocessor, an application processor (AP), etc. The plurality of processors 110 and 120 may include a first processor to an Mth processor, where M is an integer greater than 1. According to the present embodiment, the first processor 110 to the Mth processor 120 may be implemented as different processing units. The plurality of processors 110 and 120 may be a single-core processor or may be a multi-core processor.

[0042] The memory 130 may store data used in the first chip 100. The memory 130 may be a volatile memory such as a dynamic random access memory (DRAM) and / or a non-volatile memory such as a flash memory. For example, the memory 130 may be configured with a DRAM, a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistance random access memory (ReRAM), a ferroelectric random access memory (FRAM), a spin transfer torque RAM (STT-RAM), a conductive bridge RAM (CBRAM), a NOR flash memory, a NAND flash memory, a vertical NAND flash memory, a bonded vertical NAND (BVNAND) flash memory, a fusion flash memory (e.g., a memory in which an SRAM (static random access memory) buffer, a NAND flash memory, and a NOR interface logic are combined), etc. A plurality of processors 110 and 120 may access the data in the memory 130 and perform operations based on the data. The first chip 100 may also include a memory controller for controlling the memory 130 in response to instructions from the plurality of processors 110 and 120. In some embodiments, the memory controller may be disposed inside the memory 130.

[0043] The plurality of processors 110 and 120 may include internal caches (INC) 111 and 121. The internal caches 111 and 121 may include a cache hierarchy, each of which is composed of two or more cache levels. For example, the internal caches 111 and 121 may include a level 1 (L1) cache, a level 2 (L2) cache, and the like. Here, the size of the L2 cache may be larger than the size of the L1 cache. In the internal caches 111 and 121, data of the memory 130, the system-level cache 140, or the directory cache 150 may be cached. The internal caches 111 and 121 may be dedicated caches used by the processors 110 and 120, respectively, and the system-level cache 140 and the directory cache 150 may be shared caches used in common by the plurality of processors 110 and 120. The internal cache 121 may have the same structure as the internal cache 111. In other words, the internal cache 121 may include a cache controller and a plurality of cache lines.

[0044] See also Figure 3 In the internal cache 111, the L1 cache may include a cache controller (ICTR) 112 and a plurality of cache lines 113. The plurality of cache lines 113 may include a first cache line 113_1 to an Rth cache line 113_R. Here, R is an integer greater than 1 and may be determined in advance based on the size of the L1 cache.

[0045] The cache controller 112 may control the plurality of cache lines 113 in response to instructions from the first processor 110. For example, the cache controller 112 may perform a read transaction, a write transaction, etc. on the plurality of cache lines 113. In the case of a read transaction, the cache controller 112 may output data of a cache line (e.g., a first cache line 113_1). In the case of a write transaction, the cache controller 112 may write data in a cache line (e.g., a second cache line 113_2). When the cache controller 112 successfully performs a read transaction or a write transaction, the cache controller 112 may set a flag in a cache line (e.g., the Rth cache line 113_R). For example, the cache controller 112 may store a bit (e.g., "1") in a field of the Rth cache line 113_R.

[0046] The cache controller 112 may check atomic loads and atomic stores for data consistency of write transactions. In other words, the cache controller 112 may verify the data consistency of write transactions by checking both atomic load and atomic store operations. For atomic loads, when the first processor 110 reads data of the cache line 113, the cache controller 112 may set an exclusive flag in a field of the cache line 113. In the case where an atomic store is performed after a read operation of the first processor 110, the exclusive flag set in the cache line 113 may be used to determine the success or failure of the atomic store.

[0047] The atomic store may refer to an operation in which the first processor 110 performs an atomic update on the data of the cache line 113. If the first processor 110 performs the atomic store, the cache controller 112 may check the value of the exclusive flag and determine that the atomic store has succeeded when the exclusive flag has been set. When the atomic store succeeds, the cache controller 112 may set the atomic flag. When the atomic store succeeds, the cache controller 112 may clear (or reset) the exclusive flag.

[0048] The cache controller 112 may check a read hit flag of a cache line for which a read transaction has occurred. The read hit flag may be used to check whether the data of the cache line has actually been read. For example, the first chip 100 may receive data from the second chip 200 whose master node is the second chip 200. If the first processor 110 reads the data received from the second chip 200, the cache controller 112 may set a read hit flag. If the first processor 110 does not read the data of the second chip 200 until the data of the second chip 200 is invalidated or evicted, the cache controller 112 may set a read miss flag.

[0049] The plurality of cache lines 113 may include a status field (STT) 114, a tag field (TAG) 115, and a data field (DATA) 116. The status field 114 may include information about characteristics of the data, etc. The information about the characteristics of the data may include an exclusive flag, an atomic flag, a read hit flag, a read miss flag, etc. Each status field 114 may be composed of a plurality of fields including first to third fields (F1, F2, and F3) 117, 118, and 119. For example, the first field 117 may store an atomic flag, the second field 118 may store a read hit flag, and the third field 119 may store a read miss flag. However, the structure of the plurality of cache lines 113 is not limited to Figure 3The structure shown in the figure may be changed, and the number of fields, their positions, etc. For example, the order of the first field 117 to the third field 119 may be implemented differently, and the status field 114 may be implemented to be arranged between the tag field 115 and the data field 116.

[0050] The tag field 115 may include information about a memory address where data is stored in the memory 130. The data field 116 may store data corresponding to the memory address.

[0051] If the first processor 110 performs an atomic operation on the data in the data field 116, the cache controller 112 may set an atomic flag in the first field 117. In other words, if the first processor 110 successfully performs an atomic load and an atomic store, the cache controller 112 may set an atomic flag. According to the present embodiment, if the first processor 110 performs an atomic load on the data in the data field 116, the cache controller 112 may set an exclusive flag in a field of the status field 114. The cache controller 112 may store and manage the address of the cache line 113_R subjected to the atomic load in the address monitor. The cache controller 112 may reset (or unset) the exclusive flag when it receives an invalid message. For example, the second chip 200 may perform an atomic store on the data and send an invalid message to the first chip 100. For data consistency, the first chip 100 and the second chip 200 should not perform an atomic store on a piece of data at the same time. In other words, to ensure data consistency, the first chip 100 and the second chip 200 should not perform an atomic store on the same data at the same time. Therefore, the cache controller 112 may reset the exclusive flag in the first field 117 in response to the invalidation message. Therefore, when the first processor 110 performs atomic storage on the data thereafter, the corresponding atomic storage may fail. In other words, when the exclusive flag in the first field 117 is reset, the first processor 110 may not be able to perform atomic storage on the data. When the exclusive flag is set in the first field 117, the first processor 110 may successfully perform atomic storage on the data. When the first processor 110 successfully performs atomic storage, the cache controller 112 may reset the exclusive flag and set the atomic flag.

[0052] When the data is read by the first processor 110, the cache controller 112 may set a read hit flag in the second field 118. For example, even if the first chip 100 does not request the data, the second chip 200 may send data whose master node is the second chip 200 to the first chip 100. If the first processor 110 reads the received data, the cache controller 112 may set a read hit flag in the second field 118 and send information about the cache line for which the read hit flag has been set to the second chip 200.

[0053] When the data has not been read by the first processor 110, the cache controller 112 may set a read miss flag in the third field 119. For example, even if the first chip 100 does not request the data, the second chip 200 may send data whose master node is the second chip 200 to the first chip 100. If the first processor 110 does not read the received data, the cache controller 112 may set a read miss flag in the third field 119 and send information about a cache line in which the read miss flag has been set to the second chip 200. For example, when the data of the second chip 200 is not read until the data of the second chip 200 is evicted or until an invalid message is received from the second chip 200, the cache controller 112 may set a read miss flag for the data of the second chip 200.

[0054] When all cache lines in the plurality of indexed cache lines 113 contain data, the cache controller 112 may evict the cache line 113_R according to a cache replacement policy. For example, the cache replacement policy may include a policy of randomly replacing cache lines, a policy of replacing the cache line that has not been used the longest, a policy of replacing the earliest stored cache line, or a policy of replacing the cache line that has been accessed the least number of times.

[0055] When the data of the cache line 113_R is the data of the home node, the cache controller 112 may send the cache line 113_R to the system-level cache 140, and when the data of the cache line 113_R is the data of the remote node, the cache controller 112 may send the cache line 113_R to the directory cache 150. When the data of the cache line 113_R is the data of the home node, it may mean that the data is contained in the address area of ​​the home node. In addition, when the data of the cache line 113_R is the data of the remote node, it may mean that the data is contained in the address area of ​​the remote node. See Figures 2 to 4, the first chip 100 and the second chip 200 can share the first data and the second data, and the cache controller 112 can determine that the first data is the data of the main node, and determine that the second data is the data of the remote node. The cache controller 112 can send the first data to the system-level cache 140 based on the cache replacement policy. The cache controller 112 can send the second data to the directory cache 150 based on the cache replacement policy. The operation of the cache controller 112 sending the cache line 113_R to the system-level cache 140 or the directory cache 150 is called a data eviction operation. Here, the cache controller 112 can send the data of the cache line 113_R to the system-level cache 140 or the directory cache 150 through the L1 cache and the L2 cache.

[0056] The system-level cache 140 may be related to first data whose master node is the first chip 100, and may not be related to second data whose remote node is the first chip 100. For example, the system-level cache 140 may receive the first data from the internal caches 111 and 121 of the first chip 100 or the directory cache of the second chip 200. The configuration in which the directory cache of the second chip 200 sends the first data to the system-level cache 140 will be described below with reference to Fig.14 Description The system level cache 140 may include an SLC controller (SCTR) 141 for controlling the operation of the system level cache 140 .

[0057] The SLC controller 141 may determine a storage value of the first data. For example, the SLC controller 141 may determine "0" as an initial storage value of the first data. In some embodiments, the SLC controller 141 may determine a storage value of the first data based on a feedback response of the second chip 200 related to the first data. The SLC controller 141 may include a counter for each cache line. The counter may increase or decrease the storage value based on the feedback response. The SLC controller 141 may determine "0" as an initial storage value of the first data.

[0058] When positive feedback is received from the second chip 200, the SLC controller 141 may maintain or increment the storage value. Positive feedback may be a response indicating that the operation of the first chip 100 to send the first data to the second chip 200 in advance is correct. For example, when the first chip 100 sends the first data to the second chip 200 and the second chip 200 sends information indicating that it has read the first data to the first chip 100, the first chip 100 may maintain or increment the storage value of the first data. When the second chip 200 reads the first data, it may set a read hit flag in the status field of the first data. The second chip 200 may send a read hit flag to the first chip 100 by expelling the first data to the first chip 100. Alternatively, the first chip 100 may receive a write request from another chip and send an invalid message to the second chip 200. The second chip 200 may send a read hit flag to the first chip 100 in response to the invalid message.

[0059] Furthermore, when the first chip 100 has not yet transmitted the first data to the second chip 200 and the second chip 200 transmits a signal requesting the first data to the first chip 100 , the first chip 100 may increment the stored value of the first data.

[0060] When the SLC controller 141 receives negative feedback from the second chip 200, the SLC controller 141 may maintain or decrement the storage value. Negative feedback may be a response indicating that the operation of the first chip 100 to send the first data to the second chip 200 in advance is incorrect. For example, when the first chip 100 has sent the first data to the second chip 200 but the second chip 200 has not read the first data, the first chip 100 may decrement the storage value of the first data. In an embodiment, the second chip 200 may evict the first data to the first chip 100 without reading the first data. This may correspond to weak negative feedback. The second chip 200 may set a read miss flag in the status field of the first data and evict the first data to the first chip 100. If the read miss flag is in the status field, the first chip 100 may decrement the storage value by the first value. When the read miss flag is received from all chips sharing the first data, the first chip 100 may decrement the storage value by the first value. In other words, when the first chip 100 receives a read miss flag from the second chip 200 and receives positive feedback from another chip, the first chip 100 may maintain or increment the existing stored value instead of decrementing the stored value.

[0061] In an embodiment, the second chip 200 may receive an invalid message without reading the first data. In response to the invalid message, the second chip 200 may send a signal including a read miss flag to the first chip 100. This may correspond to a strong negative feedback. In response to the signal including the read miss flag, the first chip 100 may decrement the stored value by a second value. Here, the second value may be greater than the first value. Alternatively, the first chip 100 may reset the stored value.

[0062] In addition, when the first chip 100 has sent the first data to the second chip 200 but the second chip 200 sends a write request to the first chip 100, the first chip 100 may decrement the stored value of the first data. In addition, when the first chip 100 does not send the first data to the second chip 200 and the second chip 200 does not send a signal requesting the first data, the first chip 100 may maintain or decrement the stored value of the first data.

[0063] The SLC controller 141 may determine whether to send the first data to the second chip 200 based on the stored value. In an embodiment, when the stored value is a third value, the SLC controller 141 may not send the first data to the second chip 200, and when the stored value is a fourth value, the SLC controller 141 may send the first data to the second chip 200. In an embodiment, when the stored value is less than a fifth value, the SLC controller 141 may not send the first data to the second chip 200, and when the stored value is equal to or greater than the fifth value, the SLC controller 141 may send the first data to the second chip 200.

[0064] The directory cache 150 may receive the second data from the second chip 200, update the second data, and send the updated second data to the second chip 200. The directory cache 150 may be related to the second data whose remote node is the first chip 100, or may not be related to the first data whose main node is the first chip 100. In other words, the directory cache 150 may process data having a remote address.

[0065] The directory cache 150 may include a DRC controller (DCTR) 151 for controlling the operation of the directory cache 150. The DRC controller 151 may transmit second data processed by the plurality of processors 110 and 120 to the second chip 200 and provide the plurality of processors 110 and 120 with second data received from the second chip 200.

[0066] The second chip 200 according to the present embodiment may include a plurality of processors 210 and 220, a memory 230, a system level cache (SLC) 240, and a directory cache (DRC) 250. The plurality of processors 210 and 220, the memory 230, the system level cache 240, and the directory cache 250 may perform communication with each other and with other chips through a bus 260. The plurality of processors 210 and 220 may include a first processor to an N-th processor, where N is an integer greater than 1. Figure 2 The description of the plurality of processors 110 and 120, the memory 130, the system-level cache 140, and the directory cache 150 of the first chip 100 in the same manner can be applied to Figure 4 The second chip 200 includes a plurality of processors 210 and 220, a memory 230, a system-level cache 240, and a directory cache 250. The system-level cache 240 may include an SLC controller 241, and the directory cache 250 may include a DRC controller 251. In the following, redundancy will be omitted.

[0067] The system-level cache 240 may relate to the second data whose main node is the second chip 200, and may not relate to the first data whose remote node is the second chip 200. The system-level cache 240 may receive the second data from the internal caches 211 and 221 of the plurality of processors 210 and 220. The internal caches 211 and 221 may send the second data to the system-level cache 240 based on a cache replacement policy. The system-level cache 240 may receive the second data from the directory cache 150 of the first chip 100.

[0068] The system-level cache 240 may determine the storage value of the second data. For example, the system-level cache 240 may determine the storage value of the second data based on the feedback response from the first chip 100. The configuration in which the system-level cache 240 determines the storage value of the second data may be substantially the same as the configuration in which the system-level cache 140 determines the storage value of the first data.

[0069] The directory cache 250 may relate to first data whose remote node is the second chip 200, and may not relate to second data whose main node is the second chip 200. The directory cache 250 may receive the first data from the system-level cache 140 of the first chip 100. The directory cache 250 may receive the first data from the internal caches 211 and 221 of the plurality of processors 210 and 220. The internal caches 211 and 221 may send the first data to the directory cache 250 based on a cache replacement policy.

[0070] Figure 5 Is used to explain the Figure 1FIG. 1 is a diagram of the operation of the first chip of an embodiment, Figure 6 is a flowchart for explaining a cache line processing method performed by a system level cache according to an embodiment of the present disclosure.

[0071] See also Figure 5 , the first chip 100 according to the present embodiment may include a plurality of processors 110 and 120, a memory 130, a system-level cache 140, and a directory cache 150. The plurality of processors 110 and 120 may include internal caches 111 and 121.

[0072] The internal cache 111 may store first data whose master node is the first chip 100, and the processor 110 may perform an atomic operation on the first data. The atomic operation may be an operation including atomic load and atomic store. The internal cache 111 may set an atomic flag in a state field of the first data.

[0073] The internal cache 111 may send the first data subjected to the atomic operation to the system-level cache 140 based on the cache replacement policy (reference symbol "S510"). The internal cache 111 may send the first data to the system-level cache 140 through the bus 160. In an embodiment, the internal cache 111 may include an L1 cache and an L2 cache. In this case, the L1 cache may send the first data to the L2 cache based on the cache replacement policy. In addition, the L2 cache may send the first data to the system-level cache 140 based on the cache replacement policy. In other words, the first data may be moved from the L1 cache to the L2 cache, and from the L2 cache to the system-level cache 140. This movement of the first data may be referred to as an eviction operation based on the cache replacement policy.

[0074] The system-level cache 140 may include an SLC controller 141, and the SLC controller 141 may control the overall operation of the system-level cache 140. The system-level cache 140 may determine a deposit value of the first data. The system-level cache 140 may determine whether to send the first data to the second chip 200 based on the deposit value of the first data. Figure 6 The operation of system level cache 140 is described.

[0075] If the system-level cache 140 determines to send the first data to the second chip 200, the system-level cache 140 may send the first data to the directory cache 250 of the second chip 200 (reference symbol "S520"). In other words, the first data may be moved from the system-level cache 140 to the directory cache 250. This movement of the first data may be referred to as a deposit operation. The system-level cache 140 may use the bus 160 to send the first data.

[0076] exist Figure 5 In the embodiment, it has been described that the internal cache 111 performs the atomic operation; however, the present invention is not necessarily limited thereto, and the internal cache 121 may be implemented to perform the atomic operation and send data to the system-level cache 140 .

[0077] See also Figure 6 , the system-level cache 140 may receive the cache line (S610). In other words, the internal cache 111 of the processor 110 may send the first data to the system-level cache 140 in the form of a cache line. The cache line may include a status field, a tag field, and a data field. The status field may include an exclusive flag, an atomic flag, a read hit flag, a read miss flag, and the like. For example, if an atomic load is performed on the cache line, the internal cache 111 may set an exclusive flag. If an atomic store is performed on the cache line, the internal cache 111 may set an atomic flag. The read hit flag, the read miss flag, and the like may be set by the SLC controller 141 or the DRC controller 151.

[0078] The system-level cache 140 may determine whether the atomic flag has been set in the received cache line (S620). In other words, the system-level cache 140 may determine whether the atomic operation has been successfully performed on the cache line received from the internal cache 111. The system-level cache 140 may check whether the atomic flag is in the status field of the cache line received from the internal cache 111.

[0079] When the atomic flag has been set in the cache line, the system-level cache 140 may send the cache line to another chip (S630). For example, the other chip may refer to a chip different from the first chip 100 and may be the second chip 200. In an embodiment, the system-level cache 140 may determine a deposit value and determine whether to send the cache line based on the deposit value. Figure 7 A configuration is described in which system level cache 140 determines whether to transmit a cache line.

[0080] The system-level cache 140 may process the cache line (S640). When the atomic flag is not set in the cache line, the system-level cache 140 may process the cache line without sending the cache line to other chips. In addition, even when the atomic flag is set in the cache line, the system-level cache 140 may send the cache line to other chips and process the cache line. The system-level cache 140 may process the cache line according to instructions from the plurality of processors 110 and 120 or instructions from another chip.

[0081] Figure 7 is a flowchart for explaining a cache line processing method performed by a system level cache according to an embodiment of the present disclosure.

[0082] See also Figure 7 , the cache line processing method performed by the system-level cache according to the embodiment is in addition to Figure 6 In addition to the steps of the cache line processing method, the method may also include steps S710 and S720. Figure 6 The description of steps S610, S620, S630 and S640 can be applied to Figure 7 Cache line processing method.

[0083] The system-level cache 140 according to an embodiment may perform steps S610 and S620, and determine the storage value of the cache line when the atomic flag has been set in the cache line (S710). The system-level cache 140 may manage the storage value of the cache line received from the internal cache 111. For example, the system-level cache 140 may store the address and storage value of the cache line. The system-level cache 140 may determine the storage value corresponding to the address of the cache line.

[0084] The system-level cache 140 may determine whether the stored value is greater than a reference value (REF VALUE) (S720). The reference value may be a value used to predetermine whether to send data of one chip to other chips and may be predetermined. For example, the system-level cache 140 may use a 2-bit saturation counter, and the reference value may be "01". In other words, when the stored value is "11" or "10", the system-level cache 140 may determine that the stored value is greater than the reference value, and when the stored value is "01" or "00", the system-level cache 140 may determine that the stored value is not greater than the reference value.

[0085] When the stored value is greater than the reference value, the system level cache 140 may send the cache line to other chips (S630). When the stored value is not greater than the reference value, the system level cache 140 may process the cache line (S640). In this case, the system level cache 140 may not send the cache line to other chips.

[0086] exist Figure 7 In the description, it has been described that the system level cache 140 determines whether the stored value is greater than the reference value; however, the embodiment is not necessarily limited thereto, and the system level cache 140 may be implemented to determine whether the stored value is greater than or equal to the reference value.

[0087] Figure 8 is a flowchart for explaining a storage value determination method performed by a system-level cache according to an embodiment of the present invention.

[0088] See also Figure 8 , the system-level cache may send a cache line to other chips (S810). The data of the cache line may be shared data of a chip whose master node is a chip in which the system-level cache is located in the multi-chip. When the storage value of the cache line is greater than the reference value, the system-level cache may send a cache line to other chips. For example, the system-level cache 140 of the first chip 100 may send a cache line to the second chip 200. In this case, the cache line may include a status field, a tag field, and a data field, and the status field may contain information about an exclusive flag, an atomic flag, a read hit flag, a read miss flag, and the like.

[0089] The system-level cache may receive feedback from other chips (S820). The feedback may be about whether the sent cache line has been read, and may include positive feedback or negative feedback. Positive feedback corresponds to a read hit flag, and negative feedback corresponds to a read miss flag. The feedback is received as an electrical signal, and there is no particular limitation on the type of signal. As an example, the second chip 200 may send feedback to the system-level cache 140 of the first chip 100 in the form of a request message, a response message, or the like. In this case, the request message or the response message may include a read hit flag or a read miss flag. As another example, the second chip 200 may set a read hit flag or a read miss flag in the status field of the cache line, and send a cache line with the flag to the system-level cache 140 of the first chip 100.

[0090] The system-level cache may determine whether the feedback is positive feedback (S830). For example, when the system-level cache receives a read hit flag from other chips, it may determine that the feedback is positive feedback. When the system-level cache receives a read miss flag from other chips, it may determine that the feedback is negative feedback. The system-level cache may receive a read hit flag or a read miss flag through a message or a cache line.

[0091] When the feedback is positive feedback, the system-level cache may increment the storage value of the cache line (S840). In other words, the system-level cache may increase the storage value. The system-level cache may set "0" as the initial storage value. The system-level cache may use a counter to increment or decrement the storage value. In some embodiments, when the feedback is positive feedback, the system-level cache may maintain the storage value.

[0092] When the feedback is not positive feedback, the system-level cache may decrement the storage value of the cache line (S850). In other words, the system-level cache may reduce the storage value. For example, in the first case where the cache line has not been read in the remote node until the cache line is evicted to the master node, the system-level cache may decrement the storage value of the cache line. In the second case where the remote node does not read the cache line and receives an invalid message, the system-level cache may decrement the storage value of the cache line. In the third case where the remote node sends a write request to the master node, the system-level cache may decrement the storage value of the cache line. The system-level cache may perform a weak decrement on the storage value in the first and third cases, and a strong decrement on the storage value in the second case. The strong decrement may include an operation of decrementing the storage value by 2 or more, or an operation of resetting the storage value. The weak decrement may include an operation of decrementing the storage value by 1. In an embodiment, when the system-level cache receives negative feedback corresponding to the first or third case from all remote nodes, the storage value may be weakly decremented. When the system level cache receives positive feedback from any remote node, it may not decrement the stored value of the cache line or it may increment the stored value of the cache line.

[0093] Fig. 9 is a flowchart for explaining a storage value determination method performed by a system-level cache according to an embodiment of the present disclosure.

[0094] See also Fig. 9 , the system-level cache may not send the cache line to other chips (S910). The cache line may be shared data whose master node is the first chip 100 equipped with the system-level cache 140 among the multiple chips constituting the NUMA system. When the storage value of the cache line is not greater than the reference value, the system-level cache may not send the cache line to other chips. In some embodiments, step S910 may be omitted.

[0095] The system-level cache may detect whether any read request for a cache line has been received from other chips (S920). Other chips as remote nodes may send a read request to the master node to access shared data in the master node. For example, the second chip 200 as a remote node among the plurality of chips may send a read request for a cache line with shared data to the first chip 100 as a master node. The first chip 100 may receive a read request before evicting the cache line.

[0096] When the system-level cache has received a read request for a cache line from another chip, it may increment the stored value of the cache line (S930). For example, the system-level cache may use a counter to increment the stored value. The counter may increment the stored value by one bit.

[0097] When the system-level cache does not receive any read request for the cache line from other chips, it can detect whether any write request has been received from other chips (S940). For example, a third chip among multiple chips can send a write request for the cache line to the first chip 100. The third chip can perform atomic operations (e.g., atomic loads and atomic stores) on the cache line. The first chip 100 can send an invalid signal to other chips except the third chip among the multiple chips. In other words, when one chip among the multiple chips has performed an atomic operation on the shared data, the first chip 100 can send an invalid signal to the other chips for data consistency. More specifically, if one chip among the multiple chips performs an atomic operation on the shared data, the first chip 100 can send an invalid signal to the other chips to maintain data consistency.

[0098] When the system level cache has not received any write request from other chips, it may detect whether any read request for the cache line has been received from other chips (S920).

[0099] When the system-level cache has received a write request from another chip, it may decrement the stored value of the cache line (S950). In other words, when the system-level cache has not received any read request from other chips in the plurality of chips other than the first chip 100 and has received a write request from another chip, it may decrement the stored value. In some embodiments, when the system-level cache receives a write request from another chip, it may maintain the stored value.

[0100] Fig.10 is a diagram for explaining the operation of a system-level cache according to an embodiment of the present disclosure.

[0101] See also Fig.10 According to an embodiment, a system-level cache may manage a storage table 1000 corresponding to a plurality of stored cache lines. The storage table 1000 may store addresses ADDR_1 to ADDR_T and storage values ​​STV_1 to STV_T of a plurality of cache lines. Here, T may be an integer greater than 1. In an embodiment, the system-level cache may use a hash function to index entries associated with addresses ADDR_1 to ADDR_T of a plurality of cache lines. In this case, the system-level cache may store entries of a plurality of cache lines and storage values ​​STV_1 to STV_T in the storage table 1000.

[0102] The system-level cache may update the stored values ​​STV_1 to STV_T based on feedback received from other chips. For example, the system-level cache may receive positive feedback or negative feedback. When the system-level cache receives positive feedback, it may increment the stored values ​​STV_1 to STV_T, and when the system-level cache receives negative feedback, it may decrement the stored values ​​STV_1 to STV_T. In some embodiments, the system-level cache may maintain the stored values ​​STV_1 to STV_T in response to positive feedback or negative feedback.

[0103] The system-level cache may check the stored value of the cache line (eg, the first cache line) subjected to the atomic operation. For example, the first cache line may have a first address ADDR_1 and a first stored value STV_1. The system-level cache may use the storage table 1000 to check the first stored value STV_1.

[0104] The system-level cache may determine whether the first storage value STV_1 is greater than a reference value. When the first storage value STV_1 is greater than the reference value, the system-level cache may send the first cache line to other chips. When the first storage value STV_1 is not greater than the reference value, the system-level cache may not send the first cache line to other chips.

[0105] The system-level cache may receive feedback on the first cache line from other chips and update the first storage value STV_1. For example, when the system-level cache sends the first cache line to other chips and receives a read hit flag, it may increment the first storage value STV_1. When the system-level cache sends the first cache line to other chips and receives a read miss flag, it may decrement the first storage value STV_1. In addition, when the system-level cache does not send the first cache line to other chips and receives a read request, it may increment the first storage value STV_1. When the system-level cache does not send the first cache line to other chips and does not receive any read request, it may decrement or maintain the first storage value STV_1.

[0106] Fig.11 is a diagram for explaining the operation of the first chip according to an embodiment of the present disclosure.

[0107] See also Fig.11 , the first chip 100 according to the present embodiment may include a plurality of processors 110 and 120, a memory 130, a system-level cache 140, and a directory cache 150. The plurality of processors 110 and 120 may include internal caches 111 and 121.

[0108] The first chip 100 may receive the second data. The first chip 100 is a remote node for the second data, and the second chip 200 as a master node of the second data may send the second data to the first chip 100. The internal cache 111 may perform an atomic operation on the second data. The atomic operation may be an operation including an atomic load and an atomic store. The internal cache 111 may set an atomic flag in a status field of the second data.

[0109] The internal cache 111 may send the second data subjected to the atomic operation to the directory cache 150 based on the cache replacement policy (reference symbol "S1110"). The internal cache 111 may send the second data to the directory cache 150 through the bus 160. In an embodiment, the internal cache 111 may include an L1 cache and an L2 cache. In this case, the L1 cache may send the second data to the L2 cache based on the cache replacement policy. In addition, the L2 cache may send the second data to the directory cache 150 based on the cache replacement policy. In other words, the second data may be moved from the L1 cache to the L2 cache, and then moved from the L2 cache to the directory cache 150. The movement of the second data may be referred to as an eviction operation according to the cache replacement policy.

[0110] When the directory cache 150 receives the second data, it can determine whether the second data is data subject to atomic operation. The directory cache 150 may include a DRC controller 151, and the DRC controller 151 may control the overall operation of the directory cache 150. The directory cache 150 may check whether the atomic flag has been set based on the status field of the second data. When the second data is data subject to atomic operation, the directory cache 150 may send the second data to the system-level cache 240 of the second chip 200 as the master node of the second data (S1120). The directory cache 150 may use the bus 160 to send the second data to the system-level cache 240.

[0111] In FIG. 11 , it has been described that the internal cache 111 performs an atomic operation; however, the present disclosure is not limited thereto, and the internal cache 121 may be implemented to perform an atomic operation and send data to the directory cache 150 .

[0112] Fig.12 and Fig.13 is a diagram for explaining the operation of a computing system according to an embodiment of the present disclosure.

[0113] See also Fig.12 , the computing system 1200 according to the embodiment may include a first chip 1210 and a second chip 1220. Fig.12 and Fig.13, the path indicated by the arrow may be a path for data movement shared by the first chip 1210 and the second chip 1220. The first chip 1210 may include a plurality of processors (PR) 1211 and 1212, a switch 1213, a directory cache (DRC) 1214, a system-level cache (SLC) 1215, and a memory (MEM) 1216. The second chip 1220 may include a plurality of processors (PR) 1221 and 1222, a switch 1223, a directory cache (DRC) 1224, a system-level cache (SLC) 1225, and a memory (MEM) 1226. Figure 1 , Figure 2 and Figure 4 The description made can be applied to the components of the first chip 1210 and the second chip 1220. For example, the description of the processors 110 and 120 can be applied to the processors 1211 and 1212. The switches 1213 and 1223 can be used as an interface to implement communication between the first chip 1210 and the second chip 1220 and between the components in each chip. The switches 1213 and 1223 can set a path for electrical signal propagation.

[0114] The system-level cache 1215 of the first chip 1210 may determine whether to pre-send data shared by the first chip 1210 and the second chip 1220 to the second chip 1220. The pre-sending operation may refer to an operation in which the first chip 1210 sends the shared data without a request from the second chip 1220. In this case, the first chip 1210 may be a master node of the shared data, and the second chip 1220 may be a remote node of the shared data. The system-level cache 1215 may receive shared data evicted from the internal cache of the processor 1211 or 1212.

[0115] The system-level cache 1215 may include an SLC controller 1217. The SLC controller 1217 may determine whether to send based on the atomic flag and the stored value of the shared data. For example, the SLC controller 1217 may check whether the atomic flag is set in the status field of the shared data. The internal cache of the processor 1211 or 1212 may perform atomic operations on the shared data. When the internal cache successfully performs the atomic operation, it may set the atomic flag in the status field of the shared data.

[0116] When the atomic flag is set in the shared data, the SLC controller 1217 may check the storage value of the shared data. For example, the SLC controller 1217 may check the storage value based on a storage table managed by the SLC controller 1217. When the storage value is greater than the reference value, the SLC controller 1217 may send the shared data to the second chip 1220.

[0117] The system level cache 1215 may send the shared data to the directory cache 1224 of the second chip 1220 using the switch 1213. The shared data sent in advance by the first chip 1210 to the second chip 1220 may be read by the multiple processors 1221 and 1222 of the second chip 1220 or may not be read.

[0118] The processor 1221 may send a read request for shared data to the directory cache 1224. The processor 1221 may include an L1 cache and an L2 cache as internal caches. The processor 1221 may send a read request for shared data to the L1 cache, and the L1 cache may send a read request for shared data to the L2 cache. The L2 cache may send a read request for shared data to the directory cache 1224.

[0119] The directory cache 1224 may include a DRC controller 1227. The DRC controller 1227 may receive a read request for shared data from the L2 cache. The DRC controller 1227 may set a read hit flag in a status field of the shared data in response to the read request. In some embodiments, the DRC controller 1227 may set a read hit flag in a status field of the shared data and then send a signal including the read hit flag to the system-level cache 1215. The SLC controller 1217 of the system-level cache 1215 may update the storage value of the shared data based on the read hit flag. For example, the SLC controller 1217 may maintain or increment the storage value of the shared data.

[0120] The DRC controller 1227 may send the shared data to the processor 1221. For example, the processor 1221 may send the shared data to the L2 cache, and the L2 cache may send the shared data to the L1 cache. The processor 1221 may read the shared data in the L1 cache.

[0121] See also Fig.13 , the processor 1221 may send the shared data to the directory cache 1224. For example, the shared data in the L1 cache may be evicted to the L2 cache, and the shared data in the L2 cache may be evicted to the directory cache 1224. The L1 cache and the L2 cache may perform the eviction operation based on a cache replacement policy.

[0122] When the DRC controller 1227 receives the shared data from the processor 1221, it can determine whether an atomic operation has been performed on the shared data. For example, the DRC controller 1227 can check whether an atomic flag is set in the status field of the shared data. When an atomic operation has been performed on the shared data, the DRC controller 1227 can use the switch 1223 to send the shared data to the system-level cache 1215 of the first chip 1210. When an atomic operation has not been performed on the shared data, the DRC controller 1227 can use the switch 1223 to send a signal including a read hit flag to the system-level cache 1215. Based on the read hit flag, the SLC controller 1217 of the system-level cache 1215 can update the stored value of the shared data.

[0123] exist Fig.12 and Fig.13 , a configuration has been described in which the processor 1221 reads the shared data in the directory cache 1224 and the DRC controller 1227 sets a read hit flag; however, the present disclosure is not necessarily limited thereto, and the processor 1221 may not read the shared data in the directory cache 1224, and the DRC controller 1227 may set a read miss flag. For example, when the shared data is not read until the DRC controller 1227 receives an invalidation message from the first chip 1210, the DRC controller 1227 may set a read miss flag. When the DRC controller 1227 receives an invalidation message from the first chip 1210, the DRC controller 1227 may send a read miss flag to the first chip 1210 in response to the invalidation message.

[0124] Fig.14 is a diagram for explaining the operation of the second chip according to an embodiment of the present disclosure.

[0125] See also Fig.14 , the second chip 200 according to the embodiment may include a plurality of processors 210 and 220, a memory 230, a system-level cache 240, and a directory cache 250. The plurality of processors 210 and 220 may include internal caches 211 and 221.

[0126] The internal cache 211 may send the first data whose remote node is the second chip 200 to the directory cache 250 based on the cache replacement policy (S1410). The internal cache 211 may send the first data to the directory cache 250 through the bus 260. In an embodiment, the internal cache 211 may include an L1 cache and an L2 cache. In this case, the L1 cache may send the first data to the L2 cache based on the cache replacement policy. In addition, the L2 cache may send the first data to the directory cache 250 based on the cache replacement policy. In other words, the first data may be moved from the L1 cache to the L2 cache and from the L2 cache to the directory cache 250. The movement of the first data may be referred to as an eviction operation according to the cache replacement policy.

[0127] When the directory cache 250 receives the first data, it can determine whether the first data is data subject to an atomic operation. The directory cache 250 may include a DRC controller 251, and the DRC controller 251 may control the overall operation of the directory cache 250. The directory cache 250 may check whether the atomic flag has been set based on the status field of the first data. When the first data is data subject to an atomic operation, the directory cache 250 may send the first data to the system-level cache 140 of the first chip 100 as a master node (S1420). The directory cache 250 may use the bus 260 to send the first data.

[0128] In FIG. 14 , it has been described that the internal cache 211 performs an atomic operation; however, the present disclosure is not limited thereto, and the internal cache 221 may be implemented to perform an atomic operation and send data to the directory cache 250 .

[0129] Fig.15 is a schematic block diagram of a multi-chip computing system according to an embodiment of the present disclosure.

[0130] See also Fig.15 , the computing system 1500 according to the embodiment may be a multi-chip computing system. For example, the computing system 1500 may include the first to P-th chips 1510, 1520, 1530, and 1540. Here, P may be an integer greater than 2. The first chip 1510 to the P-th chip 1540 are multi-processor chips and may be a system on chip (SOC). However, the present disclosure is not necessarily limited thereto, and at least one of the first chip 1510 to the P-th chip 1540 may be implemented as a single processor chip. The first chip 1510 to the P-th chip 1540 may communicate with each other through the switch 1600.

[0131] The first chip 1510 to the P-th chip 1540 may share data. In this case, the first chip 1510 to the P-th chip 1540 may be a master node that manages the shared data, and the second chip 1520 to the P-th chip 1540 may be a remote node. Since the first chip 1510 manages the shared data, the waiting time required for the second chip 1520 to the P-th chip 1540 to access the shared data through the switch 1600 may be longer than the waiting time required for the first chip 1510 to access the shared data. As the number of times the remote node accesses the data in the master node increases, the performance of the computing system 1500 may decrease. The computing system 1500 may be a non-uniform memory access (NUMA) system.

[0132] In an embodiment, the first chip 1510 may perform an atomic operation on the shared data. In an embodiment, any one chip (e.g., the Pth chip 1540) of the second chip 1520 to the Pth chip 1540 may perform an atomic operation on the shared data and send the shared data subjected to the atomic operation to the first chip 1510. The first chip 1510 may detect the shared data on which the atomic operation has been successfully performed and check the stored value of the shared data. When the stored value is greater than the reference value, the first chip 1510 may send the shared data to the second chip 1520 to the Pth chip 1540 in advance.

[0133] The second chip 1520 to the P-th chip 1540 may receive the shared data from the first chip 1510 without a request. When the second chip 1520 to the P-th chip 1540 read the shared data, they may set a read hit flag in a state field of the shared data. In an embodiment, the second chip 1520 to the P-th chip 1540 may send a signal including the read hit flag to the first chip 1510. In an embodiment, when the second chip 1520 to the P-th chip 1540 evict the shared data to the first chip 1510, they may send the read hit flag together with the shared data to the first chip 1510. According to the state of the read hit flag, the first chip 1510 may increment the deposited value of the shared data.

[0134] When the second chip 1520 to the Pth chip 1540 do not read the shared data, they may set a read miss flag in the status field of the shared data. For example, the second chip 1520 may send a write request to the first chip 1510. In response to the write request, the first chip 1510 may generate an invalid message. The first chip 1510 may send an invalid message to the (P-1)th chip 1530 and the Pth chip 1540 so that the second chip 1520 can update the shared data. Since the (P-1)th chip 1530 and the Pth chip 1540 do not read the shared data until the invalid message is received, they may set a read miss flag in the status field of the shared data. The (P-1)th chip 1530 and the Pth chip 1540 may send a read miss flag to the first chip 1510 in response to the invalid message. Depending on the state of the read miss flag, the first chip 1510 may decrement the storage value of the shared data. Furthermore, in response to a write request from the second chip 1520 , the first chip 1510 may decrement the stored value of the shared data.

[0135] The first chip 1510 may update the storage value based on the flag received from the second chip 1520 to the P-th chip 1540. The first chip 1510 may increase the storage value by one bit based on the read hit flag, and decrease the storage value by one bit based on the read miss flag. In an embodiment, the first chip 1510 may determine whether all chips from the second chip 1520 to the P-th chip 1540 have not read the shared data or whether there is a system-on-chip in which the shared data has been invalidated and not read in the second chip 1520 to the P-th chip 1540 based on the flag. According to the result of the determination, the first chip 1510 may update the storage value of the shared data. For example, when all chips from the second chip 1520 to the P-th chip 1540 have not read the shared data or when there is a system-on-chip in which the shared data has been invalidated and not read in the second chip 1520 to the P-th chip 1540, the first chip 1510 may decrease the storage value of the shared data.

[0136] In an embodiment, the first chip 1510 may calculate the storage offset by subtracting the number of chips that have not read the shared data from the number of chips that have read the shared data in the (P-1) chips. Based on the storage offset, the first chip 1510 may update the storage value. For example, the first chip 1510 may receive read hit flags from five chips and read miss flags from three chips. The first chip 1510 may determine 2 bits as the storage offset and increment the storage value by 2 bits.

[0137] Fig.16 is a block diagram of a mobile device according to an embodiment of the present disclosure.

[0138] See also Fig.16, a mobile device 2000 according to an embodiment may include a multi-chip system 2010 , a radio frequency (RF) transceiver 2020 , an antenna 2030 , an input device 2040 , and a display 2050 .

[0139] The multi-chip system 2010 may be a non-uniform memory access (NUMA) system and include multiple chips that share data. The multiple chips may be a system on chip (SOC). For the multi-chip system 2010, refer to Figures 1 to 15 The explanations made may be equally applicable. For example, the master node of the shared data may predetermine whether to send the shared data to the remote node based on the storage value of the shared data. The master node may receive feedback from the remote node about the pre-send operation or feedback about the non-pre-send operation. The master node may update the storage value based on the feedback. The master node may pre-send the shared data to the remote node so that the waiting time required for the remote node to read the shared data is reduced.

[0140] The RF transceiver 2020 may transmit and receive wireless signals through the antenna 2030. For example, the RF transceiver 2020 may receive wireless signals through the antenna 2030 and convert the wireless signals into signals that may be processed by the multi-chip system 2010.

[0141] Therefore, the multi-chip system 2010 may process the signal output from the RF transceiver 2020 and transmit the processed signal to the display 2050. In addition, the RF transceiver 2020 may convert the signal output from the multi-chip system 2010 into a wireless signal and output the converted wireless signal to an external device through the antenna 2030.

[0142] The input device 2040 is a device for inputting a control signal for controlling the operation of the multi-chip system 2010 or data to be processed by the multi-chip system 2010 , and may be implemented as a pointing device such as a touch pad and a computer mouse, a keypad, or a keyboard.

[0143] Fig.17 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0144] See also Fig.17 , the electronic device 3000 according to the embodiment may be implemented as a PC, a data server, a laptop computer, an automotive electronic component, or a portable device.

[0145] The electronic device 3000 may include a multi-chip system 3010 , an input device 3020 , a display 3030 , a memory device 3040 , and a memory controller 3050 capable of controlling a data processing operation of the memory device 3040 .

[0146] The multi-chip system 3010 may be a non-uniform memory access (NUMA) system and include multiple chips that share data. The multiple chips may be system-on-chip (SOC). For the multi-chip system 3010, refer to Figures 1 to 15 The explanations made above may also apply. For example, the master node of the shared data may predetermine whether to send the shared data to the remote node based on the storage value of the shared data. The master node may receive feedback from the remote node about the pre-sending operation or feedback about the non-pre-sending operation. The master node may update the storage value based on the feedback. The master node may pre-send the shared data to the remote node so that the waiting time required for the remote node to read the shared data is reduced.

[0147] The multi-chip system 3010 may receive data input through the input device 3020. The data stored in the memory device 3040 may be arranged on the display 3030 according to the control and processing operation of the multi-chip system 3010. For example, the input device 3020 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. The multi-chip system 3010 may control the overall operation of the electronic device 3000 and control the operation of the memory controller 3050.

[0148] The memory controller 3050 capable of controlling the operation of the memory device 3040 may be implemented as a part of the multi-chip system 3010 , and may also be implemented separately from the multi-chip system 3010 .

[0149] In some embodiments, reference Figure 1 and Fig.17 Each component described or a combination of two or more components may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), and the like.

[0150] Although the present disclosure has been described in conjunction with a number of embodiments, it should be understood that the present disclosure is not limited to the disclosed embodiments. On the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A system on a chip, include: Multiple processors; System-wide cache shared by multiple processors; as well as The cache controller, when the system-level cache receives first data from at least one processor among the plurality of processors, sends the first data to another chip if an atomic operation has been performed on the first data.

2. The system on chip according to claim 1, in: The system on chip is a master node that manages first data, and The other chip is a remote node that accesses the first data.

3. The system on chip according to claim 2, in: The cache controller sends the first data to a directory cache of another chip.

4. The system on chip according to claim 1, in: If an atomic operation is performed on the first data, at least one processor among the plurality of processors sets an atomic flag in a status field of the first data, and The cache controller determines whether an atomic operation has been performed on the first data based on an atomic flag of the first data.

5. The system on chip according to claim 1, in: When the atomic operation has been performed on the first data, the cache controller sends the first data to another chip based on the stored value of the first data.

6. The system on chip according to claim 5, in: When the stored value of the first data is greater than the reference value, the cache controller sends the first data to another chip.

7. The system on chip according to claim 5, in: The cache controller determines a deposited value based on a signal associated with the first data received from another chip.

8. The system on chip according to claim 7, in: The cache controller performs the following operations: When the signal associated with the first data received from the other chip is a positive signal, incrementing the stored value; and When the signal associated with the first data received from another chip is a negative signal, the stored value is decremented.

9. The system on chip according to claim 8, in: The positive signal includes a read hit flag indicating that another chip has read the first data, and The negative signal includes a read miss flag indicating that another chip has not read the first data.

10. A computing system, include: The first chip, when an atomic operation has been performed on the first data, sends the first data to the second chip; as well as The second chip shares the first data with the first chip and transmits information on whether the first data has been read to the first chip in response to receiving the first data.

11. The computing system according to claim 10, in: The second chip does the following: recording information about whether the first data has been read in a status field of the first data; as well as When the first data is read, a read hit flag is set in a first field of the status field, and when the first data is not read, a read miss flag is set in a second field of the status field.

12. The computing system according to claim 11, in: If the second chip does not read the first data until the first data is evicted or an invalid message is received from the first chip, the second chip sets a read miss flag in the second field of the status field.

13. The computing system of claim 12, further comprising: include: The third chip shares the first data with the first chip and the second chip, wherein: The first chip sends an invalidation message to the second chip in response to receiving a write request from the third chip, and updates a stored value of the first data based on a read hit flag or a read miss flag.

14. The computing system according to claim 10, in: The second chip records information about whether the first data has been read in a status field of the first data, and If the first data is evicted from the second chip, the first chip updates the stored value of the first data based on the status field.

15. The computing system of claim 10, further comprising: include: The third chip shares the first data with the first chip and the second chip, wherein: The first data is subjected to an atomic operation of the first chip, or is subjected to an atomic operation of a third chip.

16. A method for storing a system on a chip, include: Get the address of the cache line subject to the atomic operation; incrementing the stored value when the cache line has been read by other systems-on-chip, and decrementing the stored value when the cache line has not been read by other systems-on-chip; and Based on the address and the stored value, a determination is made whether to store the cache line.

17. The storage method according to claim 16, further comprising: include: The entries associated with the addresses of the cache lines are indexed using a hash function, where Determining whether to deposit the cache line includes determining whether to deposit the cache line based on the entry and the deposit value.

18. The storage method according to claim 16, in: Determining whether to store the cache line includes storing the cache line when the stored value is greater than a reference value, and not storing the cache line when the stored value is not greater than the reference value.

19. The storage method according to claim 16, in: Acquiring the address includes not acquiring the address when the cache line is data in the remote node, and acquiring the address when the cache line is data in the home node.

20. The storage method according to claim 16, in: Incrementing a stored value when a cache line has been read by another system-on-chip and decrementing a stored value when a cache line has not been read by another system-on-chip comprises the following steps: storing the cache line in other on-chip systems and receiving response signals from other chips; determining, based on the response signal, whether all other systems-on-chip have not read the cache line or whether there is a system-on-chip in which the cache line has been invalidated and not read among the other systems-on-chip; as well as The stored value is updated based on the result of the determination.

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