Multi-programmable die module

Abstract

The invention relates to a multi-programmable die module. Die configuration types are provided that can be used with other instances of the design to create a multi-die module.

Description

Technical Field

[0001] The present disclosure relates generally to multi-chip packages, and more particularly to improved techniques for reducing the number of die design types required for multi-chip package implementations. Background Art

[0002] Programmable devices such as FPGAs can be used to create multi-chip computing systems, for example to prototype a system design before committing to a fixed CPU, GPU, ASIC, etc. Typically, several different programmable die designs are required to implement the system. Unfortunately, this can cost an inordinate amount of money and time to create and verify the different masks and manufacturing processes required for the multiple different die designs. Summary of the invention

[0003] According to one aspect of the present disclosure, a multi-chip module is provided, comprising: a first die and a second die, each having a first side and a second side, the first side including a peripheral area having both a transceiver block and a D2D block, the second side including a peripheral area having both a transceiver block and a D2D block; wherein the first die is arranged adjacent to the second die so that the second side of the first die is adjacent to the first side of the second die, at least a portion of the D2D block on the second side of the first die is coupled to at least a portion of the D2D block on the first side of the second die; and wherein at least some of the D2D blocks are not used when on a side without an adjacent die, and wherein some of the transceiver blocks are not used when on a side of the die with an adjacent die.

[0004] According to one aspect of the present disclosure, a programmable integrated circuit die device is provided, comprising: an internal processing area; and a peripheral area including an internal general IO block and an external transceiver block, wherein the internal general IO block is arranged between the external transceiver block and the internal processing area.

[0005] According to one aspect of the present disclosure, there is provided an apparatus comprising: a substrate; and a first FPGA die and a second FPGA die having the same design and mounted to the substrate, the first die and the second die having adjacent sides, the adjacent sides each comprising (i) D2D blocks within a peripheral area and (ii) unused transceiver blocks within the peripheral area, wherein the D2D blocks are coupled to each other and the transceiver blocks are coupled to a reference rail to make them inert.

[0006] According to one aspect of the present disclosure, a programmable device module is provided, comprising: a substrate; a first FPGA die and a second FPGA die having the same design and mounted to the substrate, the first die and the second die having adjacent sides, the adjacent sides each comprising (i) a D2D block within a peripheral area and (ii) an unused transceiver block within the peripheral area; and a coupling device for coupling the D2D blocks to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention may be best understood by referring to the following description and accompanying drawings which are used to illustrate embodiments of the invention. In the drawings:

[0008] Figures 1A to 1C is a diagram showing a conventional programmable die and a multi-die module.

[0009] FIG. 2A to FIG. 2C is a diagram illustrating a programmable die and multi-die module configuration according to some embodiments.

[0010] Figure 3 is a top view of a programmable die layout according to some embodiments.

[0011] Figure 4 is a top view of a programmable die layout according to other embodiments.

[0012] Figure 5 is a side view illustrating a multi-chip programmable die configuration according to some embodiments.

[0013] Figure 6 A data processing system having one or more programmable device modules according to some embodiments is shown. DETAILED DESCRIPTION

[0014] In some embodiments, programmable devices such as FPGAs can be used to create multi-chip computing systems before submitting with fixed CPUs, GPUs, ASICs, etc., such as to prototype system designs. Typically, several different programmable die designs are required to implement the system. Unfortunately, this may cost too much money and time to create and verify the different masks and manufacturing processes required for multiple different die designs. Therefore, in some embodiments, a new die configuration type is provided that can be used with other instances of the design to create a multi-die module that only requires a single die type. For example, in some embodiments, a module can use a bridge or insert with through silicon via (TSV) capability to facilitate a single die into a film (tape-in), rather than requiring multiple unique dies into a film. A reduction in the number of required die types can result in a reduction in the number of required tape-ins, which can result in mask cost savings and improvements in design turnaround time. In addition, test program development can be simplified, and product costs can be improved because volume is provided by reducing the number of die types and wafers, resulting in increased yields.

[0015] Figures 1A to 1C A conventional single-chip FPGA (field programmable gate array) integrated circuit (IC) device 105 is shown. Figure 1A , FPGAs can generally be divided into two basic areas: a peripheral external area (also referred to as a "coastline") and an internal processing and communication area 120. In this description, the peripheral area has a transceiver section (XCVR) 110 and a general input / output (I / O) area 115. External communication with the FPGA 105 typically occurs through (one or more) transceivers 110 and / or through general IO blocks 115, but it may be more convenient to use a high-speed differential XCVR (transceiver) interface 110 to communicate with external devices for bandwidth-intensive and / or lengthy communications. Standard protocols including but not limited to Ethernet, PCI Express (PCIe), USB, etc. can be used for such high-speed interfaces 110. Moreover, they can be implemented with TMD (Transition Minimized Differential) signal transmission (e.g., for HDMI), MGT (Multi-Gigabit Transceiver) signal transmission (e.g., PCIe, Display Port) and / or other suitable physical signal transmission schemes.

[0016] The general IO blocks 115 can be used for die-to-die (D2D) connections, such as using PAM, single-ended, differential, serial deserializer and / or parallel interface implementations. In addition, they can also be used to implement external communication interfaces, such as for off-chip memory (e.g., DDR, GDDR) or programming, testing or monitoring (e.g., I2C, SPI), depending on the specific design goals.

[0017] The internal processing region 120 generally includes a plurality of functional circuit blocks 122 coupled together by a programmable interconnect structure 124. As indicated, the functional blocks 122 may include a variety of different processing block types, including configurable logic blocks (CLBs), intellectual property (e.g., hardened IP, HIP) blocks for performing specific functions, and memory blocks (Mx).

[0018] CLBs typically include three elements: a lookup table (LUT), a multiplexer, and a flip-flop. IP blocks are typically used to implement specialized logic, mixed-signal, and / or analog circuits for implementing basic arithmetic functions, such as adders, MACs (multiply-accumulate), security, DSPs, GPUs, and CPU cores, memory and IO controllers, clock generation circuits, etc. As technology advances, more and more functional block options become available for FPGA incorporation.

[0019] With programmable logic, LUTs are the primary element for implementing configurable logic functions. For example, they can be arranged and controlled to generate truth table operations for any desired combinational logic function. Flip-flops are used for sequential logic implementation. They can also be used to efficiently incorporate adders / multipliers and DSP logic, for example, into the CLB itself to reduce latency, facilitate faster computation, reduce routing, and increase throughput. Multiplexers are particularly used to select data outputs and paths between LUTs and flip-flops to configure desired logic functions.

[0020] The memory blocks may include a combination of volatile and non-volatile memory, such as RAM (random access memory), ROM (read only memory), flash memory, etc. The memory may be used for various purposes, such as for storing programmable logic configuration, implementing processor architecture memory (e.g., distributed and block RAM for cache functions), buffering data, etc.

[0021] The functional blocks 122 are coupled to each other and to the IO interface via a programmable interconnect structure 124. The interconnect structure can be implemented in any suitable manner. For example, it can be formed as a routing matrix including programmable switches, wires, clock network elements, etc. The routing elements provide connections between the IO blocks 110, 115 and the data processing portion 120, as well as connections between the functional blocks 122 themselves.

[0022] Figure 1B A simplified top view of a conventional multi-chip programmable device system is shown. For example, it can be used to implement a computing system prototype. FPGAs are often used to prototype computing systems such as servers, data center computing blocks, high-performance computers, etc. They can be useful because they can be relatively flexible for implementing various design functions, and they are reconfigurable, which makes them useful for isolating design problems and optimizing performance.

[0023] Figure 1B The multi-chip FPGA device has three different monolithic FPGA dies 105A, 105B, and 105C. The left die (105A) has a transceiver block 110A on its left edge and a die-to-die IO on its right edge. The upper and lower edges include general IO blocks 115A, which can be used for die-to-die or other IO interface functions. In contrast, the second die (105B) does not incorporate an XCVR block, but instead uses its coastline edge for general IO blocks 115B, which include D2D blocks on its left and right edges. Finally, the third die (105C) has an XCVR block on its right edge, a D2D block on its left edge, and general IO blocks on its upper and lower coastline edges. Using conventional techniques, these separate die layouts allow the three chips to be coupled together using a bridge 135, such as Figure 1C As can be seen in the side view of FIG. 1 , the bridge is arranged in the multi-chip substrate 130. The D2D blocks are aligned adjacent to each other, which allows them to be coupled together using the bridge. Likewise, the XCVR blocks 110 are arranged on the outer edges (the left edge of the left die and the right edge of the right die) so that they can be accessed for off-chip communication.

[0024] Unfortunately, these conventional methods require the use of different die designs (e.g., layouts), which can significantly increase the time and resources required to manufacture all dies. They require multiple waferings, resulting in significant mask costs. In addition, when multiple different designs are fault checked, repairing defects for different die types may result in additional waferings.

[0025] Figure 2A 2 is a top view of a programmable die (e.g., FPGA) 205 design with transceiver and D2D layout according to some embodiments. The design allows multiple instances of the same die type to be used together to form a multi-chip system, such as a computing system using multiple FPGAs. The die 205 has an internal processing area 220, which has functional blocks 222 and a programmable fabric network 224. It also has transceiver blocks 210, 211 and IO blocks 216-219, some or all of which can be used as D2D blocks for coupling to adjacent dies. The (one or more) remaining portions may not be used or may be used for other off-chip IO functions, such as DDR.

[0026] Figure 2B According to some embodiments, the use of Figure 2AA top view of a multi-chip system 200 with three instances (205A, 205B, 205C) of a common die design 205 of a die design. In this embodiment, IO blocks 217 and 219 are used for adjacent D2D connections. In particular, D2D block 217A is coupled to D2D block 219B, and D2D block 217B is coupled to D2D block 219C. Transceiver blocks 210A and 211C are used for off-chip communication, while "internal" transceiver blocks 211A, 210B, 211B, and 210C are not used. In some embodiments, they can be coupled to a reference rail (e.g., ground) to ensure that they are inert, thereby avoiding unnecessary power loss from leakage or other reasons.

[0027] It should be understood that any suitable technology for implementing multi-chip packaging of dies (e.g., multiple FPGA dies, or even multiple CPU, GPU, or ASIC dies) can be used, including 2D, 2.5D, and / or 3D approaches. For example, wafer-level fan-out redistribution can be used in a 2D or 2.5D implementation, which uses a reconstructed wafer substrate of a molding compound as a surface for interconnection between dies. Similarly, with some approaches, a separate, typically silicon-based interconnect layer for redistribution can be used. For example, an insert (passive and / or active, typically formed of silicon) or a die-to-die bridge (e.g., a silicon bridge) embedded in an organic surface (e.g., a substrate surface or an insert) can be used.

[0028] The interposer is typically formed from a piece of silicon that is large enough to accommodate multiple chips, where the chips are bonded to the interposer. The interposer typically includes multiple signal lines (eg, data lines), and as data moves from silicon to silicon, power loss can be minimized.

[0029] A bridge may also be used, such as EMIB (Embedded Multi-die Interconnect Bridge) developed by Intel Corporation. EMIB is an example of a 2.5D MCP bridge interconnect technology. In some forms, EMIB may be a combination of an insert and a substrate. This technology may use a small piece of silicon (bridge) embedded in the substrate, rather than simply using a large insert. Such a bridge may include hundreds or thousands of connections that couple the adjacent sides of two chips together. In this way, data between chips can be transmitted through silicon without undue restrictions. Moreover, if more bandwidth is required, multiple bridges may be used between the two chips, or multiple bridges may be used for designs using more than two chips.

[0030] Any suitable architecture for implementing the general IO blocks may be employed. For example, for D2D implementations, proprietary or standard protocols such as the Advanced Interface Bus (AIB) or Universal Chiplet Interconnect Express (UCIe) may be used. In any case, the physical layer architecture may be SerDes-based or parallel-based. SerDes-based architectures typically include parallel-to-serial (serial-to-parallel) data conversion, impedance matching circuits, and in some cases clock data recovery or clock forwarding functionality. The primary effect of using a SerDes architecture may be to minimize the number of IO interconnects in a simple 2D type multi-chip package, for example, as with an organic substrate employing a bridge or the like for D2D connections.

[0031] On the other hand, parallel-based architectures typically include many parallel, low-speed, simple IO channels, each consisting of a driver and receiver using forwarding clock technology to further simplify the architecture. It supports DDR-type signal transmission and may be well suited for D2D applications for certain multi-chip designs. For example, parallel architectures may be well suited to minimizing power in dense 2.5D-type packaging, such as with the use of silicon interposers.

[0032] Figure 2C yes Figure 2B 2 is a side view of a multi-chip system 200. System 200 includes a passive insert 240 mounted on top of substrate 230 as shown. Passive insert 240 includes a conductive "reference" layer 242 (e.g., a ground plane layer) and conductive signal lines 244. Ball contacts (e.g., microbumps) conductively couple internal unused transceiver blocks (211A, 210B, 211B, 210C) to the reference layer (e.g., ground) 242 via contacts 226, which are coupled to the Vss contacts of the insert via TSVs. These insert Vss contacts are coupled to the substrate Vss contacts via conductive lines 237. Similarly, active transceiver blocks 210A and 211C are coupled to external package connections via chip contacts 227, insert TSVs, insert contacts ("IO"), and substrate IO lines 236, as shown. It should be noted that for this embodiment, the internal passive transceiver blocks are coupled to ground in order to minimize parasitic effects and power losses, but any suitable alternative connections or even no connections may be used. That is, they may be left open, or even coupled to other or multiple different reference or device planes depending on the design goals.

[0033] Signal lines 244 couple adjacent pairs of D2D blocks (217A-219B and 217B-219C) to each other for chip-to-chip communication. From a top view perspective (not shown), reference layer 242 may have gaps or openings to accommodate signal lines and possible other signals (e.g., IOs from active transceivers). Alternatively, signal lines may be formed by vias or micro vias with insulating sides.

[0034] Figure 3 Another programmable device die 305 that can be used to generate a multi-chip system with a single die design according to some embodiments is shown. The die includes a peripheral (or coastline) area consisting of an inner peripheral portion and an outer peripheral portion. The inner peripheral portion is composed of general IO (e.g., D2D) blocks 316-319, while the outer peripheral portion is composed of transceiver blocks 310, 311 and off-chip IO blocks (e.g., DDR, USB) 312, 313. With this design, the die can be coupled together from any of its four sides. This may be convenient for systems with a large number of dies, allowing arrays with multiple rows and columns of dies to be configured in a multi-chip package.

[0035] Figure 4 Another device die 405 that can be used to generate a multi-chip system with a single die design according to some embodiments is shown. The die (e.g., FPGA) 400 includes a peripheral area, which includes D2D blocks 416-419 and transceiver blocks 410a, 410b and 411a, 411b, as shown. The transceiver blocks and D2D blocks are staggered around the peripheral area, rather than simply using inner and outer parts. In this way, adjacent D2D blocks from side-by-side dies can be coupled together, thereby simplifying the packaging method used in some cases.

[0036] Figure 5 is a side view showing another multi-chip system 500 according to some embodiments. System 500 includes die instances 505A, 505B, and 505C mounted to an organic insert 535, which is mounted on top of an intermediate substrate portion 532 (which can be a portion of substrate 530). The intermediate substrate 532 and the organic insert 535 accommodate a bridge structure 542, which includes a bridge conductor 543 for coupling adjacent D2D blocks (517A-519B and 517B-519C) together. The package also includes TSVs that pass through the bridge to couple the passive transceiver blocks to the passive device reference plane (Vss). Copper pillars and TSVs are also included, which are used to couple the transceiver blocks (510A, 511C) to IO contacts through the organic insert and substrate portion, and to couple the passive IO blocks (D2D portions) (519A, 517C) to the Vss reference plane. In some embodiments, the organic interposer may be omitted, wherein the bridge structure is arranged directly within the intermediate substrate portion. Additionally, the intermediate substrate portion may be formed as a separate layer from the substrate, or it may be part of the substrate itself.

[0037] Figure 6An exemplary computing system 650 is shown formed by one or more FPGA modules 660, each having one or more dies of a single design instance, as described herein. (They may also include other components, such as power supplies, ASICs, or even other FPGA designs.) Each FPGA module 660 also has an associated external memory module 665. The FPGA modules 660 are coupled to each other via a communication bridge 675. A host processor 605 with associated memory 608 is also illustrated. The host processor is coupled to the computing system 650 via a host interface bridge 610 for controlling and communicating with the FPGA system 650. The host 605 in cooperation with the memory 608 can be used to program one or more FPGA modules 660, as well as control and program the system for tasks such as computing system prototyping and for other possible functions.

[0038] According to some embodiments, computing system prototyping can be a very beneficial use of FPGA module 660. Hardware platforms such as FPGA prototyping are increasingly popular due to their relatively low cost and ability to test system designs quickly (compared to simulations that are too slow and generally cannot provide accurate evaluations of design behavior). FPGA-based prototyping can be well suited for even the largest designs. FPGA-based prototyping systems allow engineers to use the same software as the final product in the prototype system, thereby allowing early start of software development. Compared to the final architecture, the architecture of the prototype only needs to include a small amount of additions. Therefore, the evaluation of different configurations and functional verification can be simple, reliable and fast. It also allows the evaluation of larger systems on a chip using one or more multi-FPGA modules (such as multi-FPGA modules 200, 500 and / or 660), as previously discussed. When combined with the ability to control the timing of various components, this configuration allows analysis of both software and hardware. Another benefit is that FPGA-based computing system prototypes can use synthesizable RTL (register transfer language) developed for actual hardened designs to provide cycle-accurate, high-performance execution and real-world interface connections. This performance can scale with the complexity of the design due to the flexibility of the prototyping solution, which allows the use of design partitioning across multiple FPGAs in order to handle very large design sizes that require a lot of verification throughput. This also brings the additional benefit of having more time to perform exhaustive verification of large designs or allowing additional exploration of design options. Although verification may be the primary use, physical prototyping supports other use cases, including proof-of-concept studies, test pattern generation, IP development, end-user evaluation, and even as a highly configurable computer system for a variety of applications.

[0039] It should be understood that FPGA module 660 may be included in any suitable data processing system (such as Figure 6The data processing system 600 shown in FIG. 6 may include a FPGA system 650. The data processing system 600 may include more or fewer components (e.g., an electronic display, a user interface structure, an application specific integrated circuit (ASIC)). Furthermore, Figure 6 Any circuit components depicted may include an FPGA module (e.g., 200, 500, 660) as discussed herein. The host processor 605 may include any of the aforementioned processors that can manage data processing requests for the data processing system 600 (e.g., to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, spatial navigation, cryptocurrency operations, hardware prototyping, etc.). The memory 608, 665 may include a random access memory (RAM), a read-only memory (ROM), one or more hard disk drives, flash memory, etc. The memory and / or storage circuit may store data to be processed by the data processing system 600. In some cases, the memory and / or storage circuit may also store a configuration program (bitstream) for programming the FPGA module 660. The host interface 610 may allow the data processing system 600 to communicate with other electronic devices. The data processing system 600 may include several different packages, or may be contained in a single package on a single package substrate. For example, components of the data processing system 600 may be located on several different packages at one location (e.g., a data center) or multiple locations. For example, components of data processing system 600 may be located in separate geographic locations or regions, such as cities, states, or countries.

[0040] In some embodiments, data processing system 600 may be part of a data center that processes a variety of different requests. For example, data processing system 600 may receive data processing requests via host / network interface 610 to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, spatial navigation, digital signal processing, or some other specialized task.

[0041] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more of the examples described below and any compatible combination.

[0042] Example 1 is a multi-chip module comprising first and second dies, each having a first side and a second side, the first side including a peripheral area having both a transceiver block and a D2D block, and the second side including a peripheral area having both a transceiver block and a D2D block. The first die is arranged adjacent to the second die so that the second side of the first die is adjacent to the first side of the second die, and at least a portion of the D2D block on the second side of the first die is coupled to at least a portion of the D2D block on the first side of the second die. Moreover, at least some of the D2D blocks are not used when on a side without an adjacent die, and wherein some of the transceiver blocks are not used when on a side of the die with an adjacent die. It should be understood that in this example and in other examples presented throughout the specification, any suitable die type (e.g., PLD, FPGA, CPU, GPU, ASIC, etc.) can be used to implement these dies.

[0043] Example 2 includes the subject matter of Example 1, and wherein the coupled together general purpose IO block from the first die and the second die includes a die-to-die IO interface for communicatively coupling the first die to the second die.

[0044] Example 3 includes the subject matter of any of Examples 1-2, and wherein the first die and the second die are field programmable gate array dies.

[0045] Example 4 includes the subject matter of any of Examples 1 to 3, and wherein the first die and the second die are separate instances of the same die design.

[0046] Example 5 includes the subject matter of any of Examples 1 to 4, and wherein the general IO blocks are disposed between the transceiver blocks.

[0047] Example 6 includes the subject matter of any of Examples 1 to 5, and wherein the transceiver blocks and general purpose IO blocks in respective peripheral regions are staggered such that respective blocks are at an outer edge of their die.

[0048] Example 7 includes the subject matter of any of Examples 1 to 6, and wherein the first die and the second die are mounted on an interposer having signal lines for coupling the GPIO block portion from the second side of the first die to the first side of the second die.

[0049] Example 8 includes the subject matter of any of Examples 1 to 7, and wherein the interposer has a reference plane coupled to the second side of the first die and the transceiver blocks on the first side of the second die to make them inert.

[0050] Example 9 includes the subject matter of any of Examples 1 to 8, and wherein the first die and the second die are mounted atop an organic substrate portion, the organic substrate portion comprising at least one bridge for coupling the general IO block portion from the second side of the first die to the first side of the second die.

[0051] Example 10 is a device, comprising a programmable integrated circuit die. The die has an internal processing area and a peripheral area, the peripheral area includes an internal general IO block and an external transceiver block. The internal general IO block is arranged between the external transceiver block and the internal processing area.

[0052] Example 11 includes the subject matter of Example 10, and wherein the GPIO block comprises a D2D circuit.

[0053] Example 12 includes the subject matter of any of Examples 10-11, and wherein the D2D circuit comprises a SerDes circuit.

[0054] Example 13 includes the subject matter of any of Examples 10 to 12, and wherein the peripheral regions occupy opposite sides of the die.

[0055] Example 14 includes the subject matter of any of Examples 10 to 13, and further includes a second die that is a separate instance of the programmable integrated circuit die that is the first die.

[0056] Example 15 includes the subject matter of any of Examples 10 to 14, and wherein the first die and the second die are mounted on an interposer having signal lines for coupling the GPIO block portion from the first die to the second die.

[0057] Example 16 includes the subject matter of any of Examples 10 to 15, and wherein the interposer has a reference plane coupled to the otherwise inert transceiver blocks from the first die and the second die.

[0058] Example 17 includes the subject matter of any of Examples 10 to 16, and wherein the first die and the second die are mounted atop an organic substrate portion, the organic substrate portion comprising at least one bridge for coupling general purpose IO block portions from the first die and the second die to each other.

[0059] Example 18 is an apparatus comprising: a substrate; and first and second FPGA dies. The first FPGA die and the second FPGA die have the same design and are mounted to the substrate. The first die and the second die have adjacent sides, each of which includes (i) D2D blocks within a peripheral area and (ii) unused transceiver blocks within the peripheral area. The D2D blocks are coupled to each other, and the transceiver blocks are coupled to a reference rail to make them inert.

[0060] Example 19 includes the subject matter of Example 18, and wherein the first die and the second die are mounted to the substrate by an organic material.

[0061] Example 20 includes the subject matter of any of Examples 18 to 19, and wherein the D2D blocks are coupled together by at least one bridge having a plurality of signal lines.

[0062] Example 21 includes the subject matter of any of Examples 18 to 20, and further includes through silicon vias (TSVs) passing through at least one bridge to couple an unused transceiver block to the reference rail.

[0063] Example 22 includes the subject matter of any of Examples 18 to 21, and wherein the reference rail is a ground plane.

[0064] Example 23 includes the subject matter of any of Examples 18 to 22, and wherein the first die and the second die are mounted to an interposer.

[0065] Example 24 includes the subject matter of any of Examples 18 to 23, and wherein the interposer is a silicon interposer.

[0066] Example 25 is a data processing device comprising at least one FPGA module having a first die and a second die according to the examples of Examples 18 to 24.

[0067] Example 26 is a programmable device module comprising a substrate and first and second FPGA dies. The first FPGA die and the second FPGA die have the same design and are mounted to the substrate. Moreover, the first die and the second die have adjacent sides, each of which includes (i) a D2D block within a peripheral area and (ii) an unused transceiver block within the peripheral area. The module also includes means for coupling the D2D blocks to each other.

[0068] Example 27 includes the subject matter of Example 26, and wherein the transceiver blocks are coupled to a reference rail such that they are inert.

[0069] Example 28 includes the subject matter of any of Examples 26 to 27, and wherein the first die and the second die are mounted to the substrate through an organic layer.

[0070] Example 29 includes the subject matter of any of Examples 26 to 28, and the coupling device includes at least one bridge.

[0071] Example 30 includes the subject matter of any of Examples 26 to 29, and wherein the coupling means comprises a through silicon via (TSV) passing through the at least one bridge to couple the unused transceiver block to the reference rail.

[0072] Example 31 includes the subject matter of any of Examples 26 to 30, and wherein the reference rail is a ground plane.

[0073] Example 32 includes the subject matter of any of Examples 26 to 31, and wherein the first die and the second die are mounted to an interposer.

[0074] Example 33 includes the subject matter of any of Examples 26 to 32, and wherein the interposer is a silicon interposer.

[0075] Example 34 is a computing system having at least one module having the subject matter of any of Examples 26-33.

[0076] Example 35 includes the subject matter of Example 34, and further includes at least one FPGA module that prototypes the hardware system.

[0077] Example 36 is a multi-chip module including identical first and second dies having a perimeter region on at least two sides of the die containing die-to-die IOs. When that side of the die does not have an adjacent die, at least some of the die-to-die IOs in the package are unused, and when that side of the die has an adjacent die, some of the out-of-package IOs are unused.

[0078] References in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least some embodiments, but not necessarily in all embodiments. Various appearances of "an embodiment," "one embodiment," or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not necessarily included. If the specification or claims refer to "one" or "an" element, this does not mean that there is only one element. If the specification or claims refer to "additional" elements, this does not exclude the presence of more than one additional element.

[0079] Throughout the specification and claims, the term "connected" means a direct connection between the things that are connected, such as an electrical, mechanical or magnetic connection, without any intermediary devices.

[0080] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between the things being connected or an indirect connection through one or more passive or active intermediary devices.

[0081] The term "circuit" or "module" may refer to one or more passive and / or active components that are arranged to cooperate with each other to provide a desired function. Different circuits or modules may share common components or even be composed of common components. For example, a controller circuit may be a circuit that performs a first function, while the same controller circuit may also be a circuit that performs another function that may be related or unrelated to the first function.

[0082] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on".

[0083] Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates that different instances of similar objects are referenced and are not intended to imply that the objects so described must be in a given order temporally, spatially, in sequence, or in any other manner.

[0084] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0085] It is noted that those elements in the drawings having the same reference numbers (or names) as elements of any other drawings may operate or function in any manner similar to that described, but are not limited thereto.

[0086] In addition, specific features, structures, functions or characteristics can be combined in one or more embodiments in any suitable manner. For example, the first embodiment can be combined with the second embodiment wherever the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0087] In addition, for simplicity of illustration and discussion, and in order not to obscure the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Furthermore, the arrangements may be shown in block diagram form in order to avoid obscuring the present disclosure, and also in view of the fact that details regarding the implementation of such block diagram arrangements depend on the platform in which the present disclosure will be implemented.

Claims

1. A multi-chip module, comprising: a first die and a second die, each having a first side including a peripheral area having both a transceiver block and a D2D block, and a second side including a peripheral area having both a transceiver block and a D2D block; wherein the first die is arranged adjacent to the second die such that the second side of the first die is adjacent to the first side of the second die, and at least a portion of the D2D block on the second side of the first die is coupled to at least a portion of the D2D block on the first side of the second die; and Wherein at least some of the D2D blocks are unused when on a side without an adjacent die, and wherein some of the transceiver blocks are unused when on a side of the die with an adjacent die.

2. The module according to claim 1, wherein: The first die and the second die are field programmable gate array dies.

3. The module according to claim 1, wherein: The first die and the second die are separate instances of the same die design.

4. The module according to claim 1, wherein: General purpose IO blocks are arranged between the transceiver blocks.

5. The module according to claim 1, wherein: The transceiver blocks and the general purpose IO blocks in each peripheral region are staggered so that each block is at the outer edge of its die.

6. The module according to any one of claims 1 to 5, wherein: The first die and the second die are mounted on an interposer having signal lines for coupling a general purpose IO block portion from the second side of the first die to the first side of the second die.

7. The module according to claim 6, wherein: The interposer has a reference plane coupled to the second side of the first die and the transceiver block on the first side of the second die to make them inert.

8. The module according to claim 1, wherein: The first die and the second die are mounted atop an organic substrate portion, the organic substrate portion comprising at least one bridge for coupling a general purpose IO block portion from the second side of the first die to the first side of the second die.

9. A programmable integrated circuit die device comprising: Internal processing areas; as well as The peripheral area includes an internal general purpose IO block and an external transceiver block, wherein the internal general purpose IO block is arranged between the external transceiver block and the internal processing area.

10. The device according to claim 9, wherein: The general IO block includes a D2D circuit.

11. The apparatus of claim 9 or 10, further comprising a second die that is a separate instance of the programmable integrated circuit die, the programmable integrated circuit die being the first die.

12. The device according to claim 11, wherein The first die and the second die are mounted on an interposer having signal lines for coupling a general purpose IO block portion from the first die to the second die.

13. The device according to claim 11, wherein: The first die and the second die are mounted atop an organic substrate portion that includes at least one bridge for coupling general purpose IO block portions from the first die and the second die to each other.

14. An apparatus comprising: substrate; as well as A first FPGA die and a second FPGA die having the same design and mounted to the substrate, the first die and the second die having adjacent sides, the adjacent sides each comprising (i) D2D blocks within a peripheral area and (ii) unused transceiver blocks within the peripheral area, wherein the D2D blocks are coupled to each other and the transceiver blocks are coupled to a reference rail to make them inert.

15. The device according to claim 14, wherein: The first die and the second die are mounted to the substrate by organic materials.

16. The device according to claim 15, wherein: The D2D blocks are coupled together by at least one bridge having a plurality of signal lines.

17. The apparatus of claim 16, comprising through silicon vias (TSVs) passing through the at least one bridge to couple the unused transceiver block to the reference rail.

18. The device according to claim 14, wherein: The first die and the second die are mounted to an interposer.

19. A data processing device comprising at least one FPGA module having a first die and a second die according to any one of claims 14 to 18.

20. A programmable device module, comprising: substrate; a first FPGA die and a second FPGA die having the same design and mounted to the substrate, the first die and the second die having adjacent sides, the adjacent sides each comprising (i) a D2D block within a peripheral region and (ii) an unused transceiver block within the peripheral region; as well as The coupling device is used to couple the D2D blocks to each other.

21. The module according to claim 20, wherein: The transceiver blocks are coupled to a reference rail to make them inert.

22. A module according to claim 20 or 21, wherein The first die and the second die are mounted to the substrate through an organic layer.

23. The module according to claim 22, wherein: The coupling means comprises at least one bridge.

24. The module according to claim 23, wherein The coupling means includes a through silicon via (TSV) passing through the at least one bridge to couple the unused transceiver block to a reference rail.

25. A module according to any one of claims 20 to 24, wherein The first die and the second die are mounted to an interposer.

Images