Chip operation simulation system using chip test data

Abstract

The present invention discloses a chip operation simulation system using chip test data, relates to the field of chip operation simulation technology, and effectively improves the accuracy of chip simulation operation test. The present invention obtains multiple operation data intervals of each operation component node according to the historical test data set of each chip test instruction, obtains the alternation probability of each operation data interval between each operation component node, and then establishes a dynamic operation state transition network according to the alternation probability between each operation component node, inputs the real-time chip test instruction into the dynamic operation state transition network to match the operation component node path, inputs the real-time test data into the component distribution structure tree and the target chip according to the matching result, performs multiple operation simulations to obtain the real-time test data set and the actual test data set, and judges whether to modify the dynamic operation state transition network according to the similarity between the actual test data set and the real-time test data set.

Description

Technical Field

[0001] The present invention relates to the technical field of chip operation simulation, and in particular to a chip operation simulation system using chip test data. Background Art

[0002] In modern electronic devices, the performance and reliability of chips directly affect the function and stability of the overall system. With the rapid development of integrated circuit technology, the complexity of chips is increasing, and the operation of simulation test chips has become increasingly important. Existing chip simulation test methods usually rely on hardware test equipment to monitor and analyze the operation status of the actual chip.

[0003] The existing chip simulation test method has the following defects:

[0004] Insufficient test data analysis: Existing simulation systems often rely on theoretical data generated during the design phase and lack sufficient collection and utilization of test data in actual application scenarios, resulting in a large gap between simulation results and actual operating status.

[0005] Insufficient complexity processing capabilities: As chip functions continue to expand, existing simulation tools may encounter performance bottlenecks when processing high-complexity chips, resulting in slow simulation speeds and high resource consumption.

[0006] Therefore, how to improve the simulation speed of complex chip structures while improving the accuracy of chip simulation operation tests is a difficulty in the prior art. For this purpose, a chip operation simulation system using chip test data is provided. Summary of the invention

[0007] In order to solve the above technical problems, the purpose of the present invention is to provide a chip operation simulation system using chip test data.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] A chip operation simulation system using chip test data includes a control center, wherein the control center is communicatively connected to a test data acquisition module, a component data association analysis module, and a chip operation simulation module;

[0010] The test data acquisition module is used to set several chip test instructions, and call several identical target chips to execute multiple chip test instructions at the same time, and then collect the historical operation data after the execution of each chip test instruction, and generate a corresponding historical test data set;

[0011] The component data association analysis module is used to establish a number of operating component nodes according to the distribution of operating components in the target chip, and connect each operating component node in sequence to obtain a component distribution structure tree, and then traverse the corresponding operating component node path in the component distribution structure tree according to each chip test instruction, and at the same time obtain a variety of operating data intervals of each operating component node according to the historical test data set corresponding to each chip test instruction, and then obtain the alternation probability of each operating data interval between each operating component node under different chip test instructions and different data processing paths, and then integrate the operating component node paths according to the alternation probability between each operating component node to obtain a dynamic operating state migration network;

[0012] The chip operation simulation module is used to obtain real-time chip test instructions, and input the real-time chip test instructions into the dynamic operation state transition network to match the relevant operation component node path, set the operation state offset probability between each operation component node in the component distribution structure tree according to the matched operation component node path, and then input the real-time test data into the component distribution structure tree to perform multiple operation simulations to obtain a real-time test data set, and input the real-time test data into the target chip to obtain an actual test data set, and determine whether to correct the dynamic operation state transition network according to the similarity between the actual test data set and the real-time test data set.

[0013] Furthermore, the process of setting the multiple chip test instructions includes:

[0014] The target chip is composed of n operating components and a circuit board, wherein the operating components are embedded in the circuit board, and then the test data acquisition module sets a number a1, a2, a3, ..., a n , where n is a natural number greater than 0;

[0015] The test data acquisition module sets i different test data and j data processing paths, where i and j are natural numbers greater than 0;

[0016] Each piece of test data is paired with a data processing path to obtain i*j chip test instructions, and a data monitoring node is installed in each operating component to generate historical operating data of the process of each operating data executing the chip test instruction.

[0017] Furthermore, the generation process of the historical test data set includes:

[0018] The test data acquisition module sends the chip test instructions to the central processing units of k target chips of the same model at the same time. When the test data passes through each operating component along the data processing path, when the test data enters any operating component, the data monitoring node built into the corresponding operating component is automatically started, and then the data monitoring node simultaneously monitors the working status of each pin of the operating component and generates corresponding historical operating data;

[0019] When the central processing unit determines that the test data passes through each operating component in the data processing path, the historical operating data of each operating component corresponding to each data processing path is collected;

[0020] The test data acquisition module integrates each chip test instruction with the corresponding historical operation data to obtain the corresponding historical test data set and sets the number s k，1，1，1 、s k，1，1，1 ,……,s k，i，j，m , where s k，i，j，m Represents a historical test data set of the kth target chip executing the i*jth chip test execution instruction for the mth time, where k and m are natural numbers greater than 0.

[0021] Furthermore, the process of establishing the component distribution structure tree includes:

[0022] The component data association module establishes n operation component nodes according to the number of operation components in the target chip, and connects each operation component node in sequence according to the actual distribution of each operation component in the target chip to obtain a component distribution structure tree corresponding to the target chip, and marks each operation component node with a corresponding number, and sets the same number of pin data nodes for each operation component node according to the number of pins of the operation component corresponding to each operation component node;

[0023] Then, the component data association analysis module first extracts the historical operating data of each operating component based on the historical test data set with the same middle two digits of the serial number subscript, and maps the historical operating data of the same operating component with different data processing paths to the pin data node of the corresponding operating component node.

[0024] Furthermore, the process of acquiring the operation data interval of the operation component node includes:

[0025] A multidimensional coordinate system is established in each pin data node, and then historical operation data of the same type from different historical test data sets in the pin data node are simultaneously mapped to the multidimensional coordinate system, a coordinate axis associated with the historical operation data on the multidimensional coordinate system is randomly selected, and a number of numerical points with equal intervals are divided on the corresponding coordinate axis;

[0026] Each historical operation data is divided into operation data points by numerical points, and the operation data points corresponding to the same numerical point are normally distributed. Then, according to the horizontal coordinate of the normal distribution, the data interval of 30% of the coordinate value center is selected as the normal coordinate interval of the corresponding type of data at the corresponding numerical point, and the rest is recorded as the abnormal coordinate interval;

[0027] The normal coordinate intervals and abnormal coordinate intervals corresponding to each numerical point are connected in sequence, so as to obtain a normal operating data interval and multiple abnormal operating data intervals of a historical operating data of the corresponding operating component node under the corresponding test data and data processing path.

[0028] Furthermore, the establishment process of the dynamic operation state migration network includes:

[0029] Traverse the operation component node paths corresponding to each data processing path in the component distribution structure tree, and map the normal operation data intervals and multiple abnormal operation data intervals between each operation component generated corresponding to each historical test data set to the operation component nodes in the corresponding operation component node paths according to the middle two digits of the subscript number of each historical test data set number;

[0030] Then, the alternation probability of normal operation data interval and abnormal operation data interval between each operation component node under different test data and different data processing paths is counted;

[0031] Repeat the above operation of obtaining the alternation probability, map the alternation probability of various operating data intervals between various operating component nodes under various test data and various data processing paths to the pin data nodes between the relevant operating component nodes in the corresponding operating component node path, integrate all the operating component node paths and associate the corresponding chip test instructions to obtain a dynamic operating state migration network.

[0032] Furthermore, the process of matching the real-time test data with the dynamic operation state migration network includes:

[0033] The real-time test data is divided into several real-time test data segments, and each real-time test data segment is traversed starting from the first data code of each test data. If there is a part in the test data that is the same as the real-time test data segment, the same part is marked in the real-time test data segment until all the real-time test data segments are traversed with the test data;

[0034] Set a matching threshold, count the proportion of the annotated parts of each real-time test data segment in the real-time test data, and then obtain the correlation matching degree between the real-time test data and each test data, compare the correlation matching degree between the real-time test data and each test data and select the individual with the largest value, and then determine whether the maximum correlation matching degree is greater than or equal to the matching threshold, and retrieve all running component node paths corresponding to the corresponding test data based on the determination result.

[0035] Furthermore, the process of determining whether to modify the dynamic running state transition network includes:

[0036] According to the retrieved running component node path, the running state offset probability is set between each running component node in the component distribution structure tree, and the real-time test data is input into the component distribution structure tree to perform m times of running simulations with different data processing paths, and a corresponding real-time test data set is generated at the end of each running simulation;

[0037] At the same time, the real-time test data is input to each target chip, and the data processing path corresponding to each simulation run is executed, thereby obtaining the actual test data set of each simulation run;

[0038] Using the matching results between similar real-time test data and test data, and setting a similarity threshold, the similarity between the actual test data set and the real-time test data set of each simulation run is determined;

[0039] According to the judgment result, the actual test data set and the data processing path of the simulation run are retrieved, and the running component node path of the same data processing path in the test data matched by the real-time test data is updated until the similarity between the actual test data set of all simulation runs and the real-time test data set is greater than or equal to the similarity threshold.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] The present invention obtains multiple operating data intervals of each operating component node according to the historical test data set of each chip test instruction, obtains the alternation probability of each operating data interval between each operating component node, and then establishes a dynamic operating state transition network according to the alternation probability between each operating component node, inputs the real-time chip test instruction into the dynamic operating state transition network to match the operating component node path, inputs the real-time test data into the component distribution structure tree and the target chip according to the matching result, performs multiple operating simulations to obtain the real-time test data set and the actual test data set, and judges whether to correct the dynamic operating state transition network according to the similarity between the actual test data set and the real-time test data set, thereby improving the simulation speed of the complex chip structure while improving the accuracy of the chip simulation operation test. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention.

[0043] Figure 1 It is a schematic diagram of the present invention. DETAILED DESCRIPTION

[0044] To make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described in detail below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other implementation methods obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0045] like Figure 1 As shown, a chip operation simulation system using chip test data includes a control center, and the control center is communicatively connected to a test data acquisition module, a component data association analysis module, and a chip operation simulation module;

[0046] The test data acquisition module is used to set several chip test instructions, and call several identical target chips to execute multiple chip test instructions at the same time, and then collect the historical operation data after the execution of each chip test instruction, and generate a corresponding historical test data set;

[0047] The component data association analysis module is used to establish a number of operating component nodes according to the distribution of operating components in the target chip, and connect each operating component node in sequence to obtain a component distribution structure tree, and then traverse the corresponding operating component node path in the component distribution structure tree according to each chip test instruction, and at the same time obtain a variety of operating data intervals of each operating component node according to the historical test data set corresponding to each chip test instruction, and then obtain the alternation probability of each operating data interval between each operating component node under different chip test instructions and different data processing paths, and then integrate the operating component node paths according to the alternation probability between each operating component node to obtain a dynamic operating state migration network;

[0048] The chip operation simulation module is used to obtain real-time chip test instructions, and input the real-time chip test instructions into the dynamic operation state transition network to match the relevant operation component node path, set the operation state offset probability between each operation component node in the component distribution structure tree according to the matched operation component node path, and then input the real-time test data into the component distribution structure tree to perform multiple operation simulations to obtain a real-time test data set, and input the real-time test data into the target chip to obtain an actual test data set, and determine whether to correct the dynamic operation state transition network according to the similarity between the actual test data set and the real-time test data set.

[0049] Further, the working principle of the present invention is specifically described below through embodiments:

[0050] The target chip is composed of n operating components and a circuit board, wherein the operating components are embedded in the circuit board, and then the test data acquisition module sets a number a1, a2, a3, ..., a n , where n is a natural number greater than 0;

[0051] The operating components include a central processing unit, an image processor, a storage controller, a memory, an I / O interface, etc.;

[0052] The test data acquisition module sets i different test data and j data processing paths, where i and j are natural numbers greater than 0;

[0053] Pair each test data with the data processing path to obtain i*j chip test instructions, and install a data monitoring node in each operation component to generate historical operation data of each operation data executing the chip test instruction process;

[0054] The test data acquisition module sends the chip test instructions to the central processing units of k target chips of the same model through the I / O interface in sequence. The central processing unit traverses the locations of various operating components according to the data processing path in the chip test instructions, and then sends the test data to the corresponding operating components in sequence along the data processing path.

[0055] In the process of the test data passing through each operating component along the data processing path, when the test data enters any operating component, the data monitoring node built into the corresponding operating component is automatically started, and then the data monitoring node simultaneously monitors the working status of each pin of the operating component and generates corresponding historical operating data, and the types of historical operating data include, for example, historical clock signals, historical voltage change data, and historical test result data before and after the test data enters the operating component;

[0056] When the central processor determines that the test data passes through each operating component in the data processing path, it collects the historical operating data of each operating component corresponding to each data processing path, and after marking each historical operating data with the corresponding operating component number, the central processor sends all the historical operating data to the test data acquisition module through the I / O interface;

[0057] For any data processing path, the test data acquisition module repeats m times and obtains the corresponding historical operation data. Then, the test data acquisition module integrates each chip test instruction with the corresponding historical operation data to obtain the corresponding historical test data set and sets the number s. k，1，1，1 、s k，1，1，1 ,……,s k，i，j，m , where s k，i，j，m Represents a historical test data set of the kth target chip executing the i*jth chip test execution instruction for the mth time, where k and m are natural numbers greater than 0.

[0058] Further, the test data collection module sends all historical test data sets to the component data association analysis module;

[0059] The component data association module establishes n operation component nodes according to the number of operation components in the target chip, and connects each operation component node in sequence according to the actual distribution of each operation component in the target chip to obtain a component distribution structure tree corresponding to the target chip, and marks each operation component node with a corresponding number, and sets the same number of pin data nodes for each operation component node according to the number of pins of the operation component corresponding to each operation component node;

[0060] Then, the component data association analysis module first extracts various historical operation data of each operating component from the historical test data set with the same middle two digits of the serial number subscript, and maps various historical operation data of the same operating component with different data processing paths to the pin data node of the corresponding operating component node;

[0061] A multidimensional coordinate system is established in each pin data node, and then historical operation data of the same type from different historical test data sets in the pin data node are simultaneously mapped to the multidimensional coordinate system, a coordinate axis associated with the historical operation data on the multidimensional coordinate system is randomly selected, and a number of numerical points with equal intervals are divided on the corresponding coordinate axis;

[0062] Each historical operation data is divided into operation data points by numerical points, and the operation data points corresponding to the same numerical point are normally distributed. Then, according to the horizontal coordinate of the normal distribution, the data interval of 30% of the coordinate value center is selected as the normal coordinate interval of the corresponding type of data at the corresponding numerical point, and the rest is recorded as the abnormal coordinate interval;

[0063] The normal coordinate intervals and abnormal coordinate intervals corresponding to each numerical point are connected in sequence, so as to obtain a normal operating data interval and multiple abnormal operating data intervals of a historical operating data of the corresponding operating component node under the corresponding test data and data processing path.

[0064] Further, the operation component node paths corresponding to each data processing path are traversed in the component distribution structure tree, and according to the middle two digits of the subscript number of each historical test data set number, the normal operation data intervals and multiple abnormal operation data intervals between each operation component generated corresponding to each historical test data set are mapped between the operation component nodes in the corresponding operation component node paths;

[0065] Then, the alternation probability θ of the normal operation data interval and the abnormal operation data interval between each operation component node under different test data and different data processing paths is counted, where the calculation formula of the alternation probability θ is: ,in: represents the probability of alternation between the a-th operation data interval and the b-th operation data interval of two operation component nodes, Indicates the number of times the a-th operation data interval and the b-th operation data interval of two operation component nodes appear at the same time, where a and b are natural numbers greater than 0;

[0066] Repeat the above operation of obtaining the alternation probability θ, map the alternation probability θ of various operating data intervals between various operating component nodes under various test data and various data processing paths to the pin data nodes between the relevant operating component nodes in the corresponding operating component node path, integrate all operating component node paths and associate corresponding chip test instructions, and then obtain a dynamic operating state transition network.

[0067] Further, the component data association analysis module sends the dynamic operation state transition network to the chip operation simulation module;

[0068] The staff uploads a real-time chip test instruction to the chip operation simulation module, and then the chip operation simulation module extracts real-time test data from the real-time chip test instruction, and inputs the real-time test data into the dynamic operation state transition network to match the test data closest to it. The matching process includes:

[0069] The real-time test data is divided into several real-time test data segments, and each real-time test data segment is traversed starting from the first data code of each test data. If there is a part in the test data that is the same as the real-time test data segment, the same part is marked in the real-time test data segment until all the real-time test data segments are traversed with the test data;

[0070] Set a matching degree threshold, count the proportion of the annotated part of each real-time test data segment in the real-time test data, and then obtain the correlation matching degree between the real-time test data and each test data, compare the correlation matching degree between the real-time test data and each test data and select the individual with the largest value, and then determine whether the maximum correlation matching degree is greater than or equal to the matching degree threshold;

[0071] If the maximum correlation matching degree is less than the matching degree threshold, it is determined that there is no matching result, and the corresponding real-time test data is sent to the test data acquisition module to generate the corresponding historical test data set, and then the corresponding running component node path is generated;

[0072] If the maximum correlation matching degree is greater than or equal to the matching degree threshold, the match is determined to be successful, and then all running component node paths corresponding to the corresponding test data are retrieved;

[0073] According to the retrieved running component node path, the running state offset probability is set between each running component node in the component distribution structure tree, and the real-time test data is input into the component distribution structure tree to perform m times of running simulations with different data processing paths, and a corresponding real-time test data set is generated at the end of each running simulation;

[0074] At the same time, the real-time test data is input to each target chip, and the data processing path corresponding to each simulation run is executed, thereby obtaining the actual test data set of each simulation run;

[0075] Using the matching results between similar real-time test data and test data, and setting a similarity threshold, the similarity between the actual test data set and the real-time test data set of each simulation run is determined;

[0076] If the similarity is greater than or equal to the similarity threshold, no action is taken;

[0077] If the similarity is less than the similarity threshold, the running component node path of the same data processing path in the test data matched by the real-time test data is updated according to the actual test data set and the data processing path of the simulation run, until the similarity between the actual test data set of all simulation runs and the real-time test data set is greater than or equal to the similarity threshold.

[0078] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A chip operation simulation system using chip test data, including a control center, characterized in that: The control center is communicatively connected to a test data acquisition module, a component data association analysis module, and a chip operation simulation module; The test data acquisition module is used to set several chip test instructions, and call several identical target chips to execute multiple chip test instructions at the same time, and then collect the historical operation data after the execution of each chip test instruction, and generate a historical test data set; The component data association analysis module is used to establish a number of operating component nodes according to the distribution of operating components in the target chip, and connect each operating component node in sequence to obtain a component distribution structure tree, and then traverse the corresponding operating component node path in the component distribution structure tree according to each chip test instruction, and at the same time obtain a variety of operating data intervals of each operating component node according to the historical test data set of each chip test instruction, and then obtain the alternation probability of each operating data interval between each operating component node under different chip test instructions and different data processing paths, and then integrate the operating component node paths according to the alternation probability between each operating component node to obtain a dynamic operating state migration network; The chip operation simulation module is used to obtain real-time chip test instructions, and input the real-time chip test instructions into the dynamic operation state transition network to match the relevant operation component node path, set the operation state offset probability between each operation component node in the component distribution structure tree according to the matched operation component node path, and then input the real-time test data into the component distribution structure tree to perform multiple operation simulations to obtain a real-time test data set, and input the real-time test data into the target chip to obtain an actual test data set, and determine whether to correct the dynamic operation state transition network according to the similarity between the actual test data set and the real-time test data set.

2. The chip operation simulation system using chip test data according to claim 1, characterized in that: The process of setting the multiple chip test instructions includes: The target chip is composed of n operating components, and each operating component is numbered a1, a2, a3, ..., a n , where n is a natural number greater than 0; Set i different test data and j data processing paths, where i and j are natural numbers greater than 0, and pair each test data with the data processing path to obtain i*j chip test instructions. At the same time, install a data monitoring node in each running component to generate historical running data of the process of each running data executing the chip test instruction.

3. The chip operation simulation system using chip test data according to claim 2, characterized in that: The generation process of the historical test data set includes: Send chip test instructions to k target chips of the same model at the same time. When the test data enters any running component, the data monitoring node built into the corresponding running component is automatically started, and then the data monitoring node collects historical running data. When it is determined that the test data passes through each running component in the data processing path, the historical running data of each running component corresponding to each data processing path is collected; Integrate each chip test instruction with all corresponding historical operation data to obtain the corresponding historical test data set, and set the number s k，1，1，1 、s k，1，1，1 ,……,s k，i，j，m , where s k，i，j，m Represents a historical test data set of the kth target chip executing the i*jth chip test execution instruction for the mth time, where k and m are natural numbers greater than 0.

4. The chip operation simulation system using chip test data according to claim 3, characterized in that: The process of establishing the component distribution structure tree includes: According to the number of operating components in the target chip, n operating component nodes are established, and according to the actual distribution of each operating component in the target chip, each operating component node is sequentially connected to obtain a component distribution structure tree corresponding to the target chip, and at the same time, each operating component node is marked with a corresponding number, and according to the number of pins of each operating component node corresponding to the operating component, the same number of pin data nodes are set for each operating component node; Then, the historical operation data of each operating component are extracted from the historical test data set with the same middle two digits of the serial number subscript, and the historical operation data of the same operating component with different data processing paths are mapped to the pin data node of the corresponding operating component node.

5. The chip operation simulation system using chip test data according to claim 4, characterized in that: The process of obtaining the operation data interval of the operation component node includes: A multidimensional coordinate system is established in each pin data node, and then historical operation data of the same type from different historical test data sets in the pin data node are simultaneously mapped to the multidimensional coordinate system, a coordinate axis associated with the historical operation data on the multidimensional coordinate system is randomly selected, and a number of numerical points are divided on the corresponding coordinate axis; Each historical operation data is divided into operation data points by numerical points, and the operation data points corresponding to the same numerical point are normally distributed. Then, according to the horizontal coordinate of the normal distribution, the data interval of 30% of the coordinate value center is selected as the normal coordinate interval of the corresponding type of data at the corresponding numerical point, and the rest is recorded as the abnormal coordinate interval; The normal coordinate intervals and abnormal coordinate intervals corresponding to each numerical point are connected in sequence, so as to obtain a normal operating data interval and multiple abnormal operating data intervals of a historical operating data of the corresponding operating component node under the corresponding test data and data processing path.

6. The chip operation simulation system using chip test data according to claim 5, characterized in that: The establishment process of the dynamic operation state migration network includes: Traverse the operation component node paths corresponding to each data processing path in the component distribution structure tree, and map the normal operation data intervals and multiple abnormal operation data intervals between each operation component generated corresponding to each historical test data set to the operation component nodes in the corresponding operation component node paths according to the middle two digits of the subscript number of each historical test data set number; Then, the alternation probability of normal operation data interval and abnormal operation data interval between each operation component node under different test data and different data processing paths is counted; The alternation probability of various operation data intervals between various operation component nodes is mapped to the pin data nodes between the relevant operation component nodes in the corresponding operation component node path, and all operation component node paths are integrated and associated with the corresponding chip test instructions to obtain a dynamic operation state migration network.

7. The chip operation simulation system using chip test data according to claim 6, characterized in that: The process of matching real-time test data with the dynamic running state migration network includes: The real-time test data is divided into several real-time test data segments, and each real-time test data segment is traversed starting from the first data code of each test data. If there is a part in the test data that is the same as the real-time test data segment, the same part is marked in the real-time test data segment until all the real-time test data segments are traversed with the test data; A matching threshold is set, and the proportion of the annotated parts of each real-time test data segment in the real-time test data is counted, so as to obtain the correlation matching degree between the real-time test data and each test data. The correlation matching degree between the real-time test data and each test data is compared and the individual with the largest value is selected, so as to determine whether the maximum correlation matching degree is greater than or equal to the matching threshold, and all running component node paths corresponding to the corresponding test data are retrieved according to the determination result.

8. The chip operation simulation system using chip test data according to claim 7, characterized in that: The process of determining whether to modify the dynamic running state migration network includes: According to the retrieved running component node path, the running state offset probability is set between each running component node in the component distribution structure tree, and the real-time test data is input into the component distribution structure tree to perform m times of running simulations with different data processing paths, and a corresponding real-time test data set is generated at the end of each running simulation; At the same time, the real-time test data is input to each target chip, and the data processing path corresponding to each simulation run is executed, thereby obtaining the actual test data set of each simulation run; The same process of obtaining the matching results between the real-time test data and the test data is adopted, and a similarity threshold is set to determine the similarity between the actual test data set and the real-time test data set for each simulation run; According to the judgment result, the actual test data set and the data processing path of the simulation run are retrieved, and the running component node path of the same data processing path in the test data matched by the real-time test data is updated until the similarity between the actual test data set of all simulation runs and the real-time test data set is greater than or equal to the similarity threshold.

Images