A SOC prototype automatic regression verification method and system based on FPGA

Abstract

The present invention belongs to the field of FPGA prototype verification technology, and particularly relates to an automatic regression verification method and system of SOC prototype based on FPGA. The method comprises the following steps: Step 1: Use the traditional method to perform the first verification, and save the verified program and waveform data to the eMMC storage chip; Step 2: During the regression verification process, read the verification program and waveform data from the eMMC storage chip, automatically download the verification program to the SOC system for operation, use the waveform data to perform functional verification, and upload the results to the PC after all functions are completed; The present invention can avoid repeated operations of the functions that have been verified to be correct during the regression verification process, improve the verification efficiency, and reduce the verification time.

Description

Technical Field

[0001] The invention belongs to the technical field of FPGA prototype verification, and in particular relates to a SOC prototype automatic regression verification method based on FPGA and a system thereof. Background Art

[0002] As the scale of SOC chips becomes larger and larger, FPGA-based prototype verification is widely used to ensure chip quality and shorten the software and hardware development cycle. During the design and verification process of SOC chips, if problems are found in the verification process, design modifications need to be made. In order to ensure the quality of SOC chips and reduce the failure rate of tape-out, after the design modification, not only the modified functions must be verified, but all functions must be regressed. Therefore, how to reduce the time of regression verification has become the key point to shorten the development cycle of SOC chips.

[0003] In the traditional FPGA-based SOC prototype verification process, the verification personnel generally use the integrated development environment IDE to write the verification program of the system function, download it to the SOC system, debug and run the program, and observe whether the function is correct. For output functions, such as PWM module output, an external oscilloscope is generally required to observe the waveform with the naked eye to see if it is correct; for input capture functions, such as CAP module capture, an external signal generator is generally required to provide signal excitation. The above operations must be repeated every time the regression verification process is performed, which consumes a lot of time and energy. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art. The present invention provides a SOC prototype automatic regression verification method and system based on FPGA, which can avoid repeated operations of verified correct functions during the regression verification process, improve verification efficiency, and reduce verification time.

[0005] To solve the above technical problems, the present invention provides a SOC prototype automatic regression verification method based on FPGA, comprising the following steps:

[0006] Step 1: Use the traditional method to perform the first verification and save the verified program and waveform data to the eMMC storage chip;

[0007] Step 2: During the regression verification process, the verification program and waveform data are read from the eMMC storage chip, the verification program is automatically downloaded to the SOC system for operation, and the waveform data is used for functional verification. After all functions are run, the results are uploaded to the PC.

[0008] Also includes:

[0009] SOC prototype verification is divided into the following three types of SOC functions according to whether external input stimulation or external output waveform is required:

[0010] Type I function: To verify this function, no external input stimulus is required, and no waveform is output to the outside. For type I function regression verification, after the verification program is run, the verification program determines whether the function is correct by itself, and after the judgment is completed, it notifies the control system through the notification signal pin to read the verification result. After reading the notification signal, the control system obtains the verification result through the reading result feedback signal, saves the verification result to the information storage table, and then performs regression test on the next function.

[0011] Type II function: verify this function, output waveform to the outside, and verify whether the waveform is correct; for type II function regression verification, verify that the waveform is output after the program runs, and notify the interconnection system and control system through the notification signal pin to start outputting the waveform; the interconnection system samples the input waveform through the internal sampling FIFO and records the waveform data; the control system compares the waveform data in the internal sampling FIFO of the interconnection system with the waveform data stored in the eMMC storage chip. If they are the same, the verification is correct; if the waveform data are different, the verification is wrong. After saving the verification result to the information storage table, the regression test of the next function is carried out;

[0012] To verify the function of type III, external input stimulus is required. For the regression verification of type III function, after the verification program runs, the notification signal pin notifies the interconnected system and the control system to start capturing the waveform. The control system reads the waveform data from the eMMC storage chip and transmits it to the waveform output FIFO inside the interconnected system. The interconnected system generates the external stimulus signal required by the SOC system. The verification program captures the external input stimulus and determines whether it is correct. Then, the control system is notified of the reading operation result through the notification signal pin. After reading the notification signal, the control system reads the result feedback signal, saves the result to the information storage table, and then performs regression testing on the next function.

[0013] Preferably, the regression verification process also includes: the control system reads the verification program flow file (.bit file) from the eMMC storage chip according to the information storage table, and uses the general IO port to simulate the JTAG protocol to download the verification program flow file to the SOC system for execution.

[0014] Preferably, for all SOC functions, during the first verification process, an integrated development environment is used to write verification programs for corresponding functions, download them to the SOC system, and debug and run the programs; in addition to implementing specific functions, all verification programs also need to provide an additional pin as a notification signal and a pin as a result signal.

[0015] Preferably, for the type I function, after the first verification and confirmation of correctness, the control system saves the verification program stream file (.bit file) into the eMMC storage chip;

[0016] For the type II function, during the first verification, the verification program outputs a waveform after running, and the interconnection system samples the output waveform of the SOC system through the internal sampling FIFO and records the waveform data; at the same time, an external instrument such as an oscilloscope is used to observe whether the output waveform is correct. If the output waveform is correct, the control system saves the waveform data collected in the interconnection system and the verification program stream file (.bit file) to the eMMC storage chip; if the output waveform is wrong, it indicates that there is a problem with this SOC function, and it is necessary to modify the SOC chip design and repeat this operation;

[0017] For type III functions, during the first verification, an external instrument such as a signal generator is used to provide input waveform excitation. The interconnected system samples the input waveform through the internal sampling FIFO and records the waveform data. If the capture module in the SOC system captures the external input excitation correctly, the control system saves the waveform data collected in the interconnected system and the verification program flow file (.bit file) to the eMMC storage chip; if the capture function is wrong, it indicates that there is a problem with this SOC function, and it is necessary to modify the SOC chip design and repeat this operation;

[0018] Preferably, for the type I, type II and type III functional verification, each time the verification program and waveform data are saved in the eMMC storage chip, the information needs to be updated in the control system program according to the information storage table.

[0019] Preferably, the information storage table includes: function name, function code, type code, program address, data address and result; the function name uses ASCII code, the function code starts from the value 0 and increases by 1 in sequence, which is used to realize flexible connection between the SOC system pin and the FIFO signal pin in the interconnected system, the program address and data address are both storage addresses in the eMMC storage chip, and the result is 1 for success and 0 for failure.

[0020] The present invention also provides an FPGA-based SOC prototype automatic regression verification system, which adopts the FPGA-based SOC prototype automatic regression verification method as described above, including:

[0021] SOC system, used to run FPGA-based SOC chip netlist;

[0022] The interconnection system uses FPGA to realize the signal connection between the SOC system and the control system. In the first traditional verification process, it is responsible for the waveform data acquisition of the external input excitation waveform and the waveform data acquisition of the SOC system output waveform; in the regression verification process, it is responsible for outputting waveforms to the SOC system or collecting waveforms from the SOC system;

[0023] Control system, in the first traditional verification process, saves the verification program and correct waveform data to the eMMC storage chip; in the regression verification process, reads the verification program and waveform data from the eMMC storage chip, automatically downloads the verification program to the SOC system for operation, and uploads the results to the PC after all functions are completed;

[0024] eMMC storage chip, used to store verification programs and waveform data;

[0025] PC terminal, used to receive regression verification results.

[0026] Preferably, the interconnection system further includes:

[0027] A waveform acquisition FIFO is used to record the sampling information of the input waveform; in the interconnected system program, the external signal input pin is connected to the write pin of the waveform acquisition FIFO. When the waveform sampling is turned on, a timer counts up according to the set frequency. Whenever the external signal input and output pins change, the combined logic values ​​of all external waveform pin levels at this time and the value of the timer are saved in the waveform acquisition FIFO, and this operation is repeated until all waveform acquisitions are completed; after that, the control system reads the waveform data of the waveform acquisition FIFO according to demand; since there are multiple output modules of the SOC system, in order to realize that the waveform signals of all output modules can be connected to the write signal of the interconnected system acquisition FIFO without increasing the number of acquisition FIFOs and simplifying the interconnected system software design, the interconnected system software design uses a function code to switch the connection between the write signal of the waveform acquisition FIFO and the output signals of multiple output modules in the SOC system, and the function code is read by the control system from the information storage table and transmitted to the interconnected system through the pin;

[0028] A waveform output FIFO is used to receive waveform data sent by the control system, and then generate a waveform output to a pin. In the interconnected system program, the output pin of the waveform output FIFO is connected to the capture pin of the SOC system; a timer counts up according to a set frequency, and the output pin of the waveform output FIFO outputs a logic level according to the combinational logic value in the waveform data to generate a waveform signal; whenever the value of the timer is the same as the time value in the waveform data stored in the waveform output FIFO, the next set of waveform data is read, the time comparison value and the waveform output signal are updated, and this operation is repeated until all waveform outputs are completed; since there are multiple input modules of the SOC system, in order to realize that the capture signals of all input modules can be connected to the output signals of the waveform output FIFO without increasing the number of waveform output FIFOs and simplifying the interconnected system software design, a function code is used in the interconnected system software design to switch the connection between the output signal of the waveform output FIFO and the capture signals of multiple input modules in the SOC system, and the function code is read from the information storage table by the control system and transmitted to the interconnected system through the pin.

[0029] Preferably, when the interconnection system realizes the signal connection transparent transmission between the SOC system and the control system, it also includes: a verification program download signal pin, a notification signal pin, a result signal pin and a SOC system reset pin. The above pins are all transparently transmitted between the SOC system and the control system by the interconnection system. The advantage is that the flexible configuration of the signal pins can be realized by changing the program design in the interconnection system, avoiding the disadvantage that the hardware connection cannot be changed.

[0030] Preferably, in the program design of the control system, it is necessary to distinguish the functional body of the program according to the steps in the operation process. In step one of the operation process, the control system program mainly realizes reading the waveform data from the sampling FIFO inside the interconnected system, and then the program saves the verification program and the waveform data to the storage chip. In step two of the operation process, the control system program mainly realizes reading the verification program and waveform data from the storage chip eMMC, automatically downloading the verification program to the SOC system for operation, and deciding whether to download the waveform data to the internal FIFO of the interconnected system or read the waveform data from the internal FIFO of the interconnected system for comparison according to the type code. After all functions are run, the results are uploaded to the computer. Therefore, it is necessary to use macro definitions to distinguish the functional body of the program. That is, the control system also includes: using macro definitions to distinguish the functional body of the control system in the traditional verification and regression verification steps; designing a verification program flow array in the control system program for storing the verification program flow file; designing a waveform array for storing the waveform data read from the interconnected system waveform acquisition FIFO; designing an information storage table array for storing the relevant information of each SOC function.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The present invention saves the verified verification program and waveform data in the first verification process, and reuses them in the regression verification process, avoiding the need for an external oscilloscope to observe the correctness of the output waveform with naked eyes or an external signal generator to provide signal excitation to the waveform input module during the regression verification process, and realizes automatic downloading of the verification program. The repeated operation of the verified correct function in the regression verification process is avoided, the verification efficiency is improved, the verification time is reduced, and thus the chip listing cycle is shortened, which is conducive to seizing the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is the overall structural diagram of the system provided by the present invention.

[0034] Figure 2 This is a system signal pin connection diagram provided by the present invention.

[0035] Figure 3 The present invention provides a system operation flow chart.

[0036] Figure 4 This is a flow chart of the control system regression verification provided by the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0038] like Figure 1 As shown, the embodiment of the present invention provides a system structure of an automatic regression verification system for a SOC prototype based on FPGA. The structure includes an FPGA-based SOC system, an FPGA-based interconnection system, a control system, an eMMC storage chip, and a PC computer. The signal pins between the systems are connected as shown in FIG. Figure 2 The pin connections between the SOC system and the interconnection system are shown in Table 1. Among them, the SOC system waveform output pin is connected to the input pin of the interconnection system; the SOC system waveform capture input pin is connected to the output pin of the interconnection system.

[0039] Table 1:

[0040] Signal name of SOC system illustrate Notification signal NOTICE is used to notify the control system, read the result or indicate the current positive output waveform. The SOC system transmits it to the control system through the interconnection system. Result feedback signal RESULT is used to indicate the result of SOC function verification. The SOC system is transparently transmitted to the control system through the interconnection system. JTAG Signals Used for SOC system program download. Among them, TMS\TCK\TDI\TRST, the control system is transparently transmitted to the control system through the interconnection system. TDO, the SOC system is transparently transmitted to the control system through the interconnection system. Reset signal NRST is used to reset the SOC system. The control system is transparently transmitted to the control system through the interconnection system. Waveform output signal WAVE_OUT represents the output pin of a module. The output pins of all waveform output modules in the SOC system are connected to the input pins of the interconnection system. Waveform input signal WAVE_IN represents the input pin of a module. The input pins of all waveform capture modules of the SOC system are connected to the output pins of the interconnected system.

[0041] The pin connections between the interconnection system and the control system FPGA are shown in Table 2. Among them, the width n of the function code switching signal needs to be designed according to the total number N of SOC system verification functions, and needs to meet the condition: 2n ≥ N. The control system accesses the eMMC storage chip through the SDIO interface and communicates with the computer through the serial port to USB bus.

[0042] Table 2:

[0043] Control system signal name illustrate Notification signal NOTICE is used to notify the control system, read the result or indicate the current positive output waveform. The SOC system transmits it to the control system through the interconnection system. Result feedback signal RESULT is used to indicate the result of SOC function verification. The SOC system is transparently transmitted to the control system through the interconnection system. JTAG Signals Used for SOC system program download. Among them, TMS\TCK\TDI\TRST, the control system is transparently transmitted to the control system through the interconnection system. TDO, used for SOC system to transparently transmit to the control system through the interconnection system. Reset signal NRST is used to reset the SOC system. The control system is transparently transmitted to the control system through the interconnection system. FIFO write data signal FIFO_W is used to control the write port of the waveform output FIFO of the system to the interconnected system. Waveform output FIFO control signals WRESET is used to reset the FIFO, WEN is used to enable the FIFO write, WCLK is used to write the FIFO clock, WFULL indicates that the FIFO is full, and WEMPTY indicates that the FIFO is empty. FIFO read data signal FIFO_R is used to control the read port of the FIFO that samples the waveform from the interconnected system. Waveform acquisition FIFO control signal RRESET is used to reset the FIFO, REN is used to enable the FIFO write, RCLK is used for the FIFO write clock, RFULL indicates that the FIFO is full, and REMPTY indicates that the FIFO is empty. Function code switching signal SELECT, used for the control system to send function codes to the interconnected system.

[0044] The operation process of the present invention is as follows Figure 3 As shown, the first verification is performed using the traditional method. If the function verification is correct, the verification program and waveform are saved to the storage chip eMMC. If the function is wrong, the function design is modified and the traditional method verification is performed again. During the regression test, the verification program and waveform data are read from the storage chip eMMC, and the verification program is automatically downloaded to the SOC system for operation. After all functions are completed, the results are uploaded to the computer.

[0045] In order to utilize the verification program and waveform data saved during the first verification process and reuse them in the regression verification process, the following functional designs are required:

[0046] The present invention divides SOC prototype verification into three types of functions as shown in Table 3 below according to whether external input excitation or external output waveform is required:

[0047] Table 3:

[0048] Type I To verify this function, no external input stimulus is required, and no waveform is output. Type II To verify this function and output the waveform externally, you need to verify whether the waveform is correct. Type III To verify this function, external input stimulus is required.

[0049] Specifically, in the first traditional verification process, for all SOC functions, the integrated development environment IDE is used to write verification programs for the corresponding functions, download them to the SOC system, and debug and run the programs. In addition to implementing specific functions, all verification programs also need to provide an additional pin as a notification signal NOTICE and a pin as a result signal RESULT. During the compilation process, the verification program uses the IDE to generate a stream file (.bit file), and then uses a transcoding tool to convert it into an array in C language format.

[0050] For the type I function, after the first verification and confirmation, the verification personnel will transcode the verification program stream file (.bit file) and store it in the verification program stream array of the control system program, and then drive the SDIO port to save the verification program stream file array to the storage chip eMMC. Finally, the information storage table in the control system program is updated, where the data address of type I is invalid and the default value 0x00000000 is maintained, resulting in an initial value of 0.

[0051] For type II functions, during the first verification, the SOC program outputs a waveform after running, and the notification signal pin is pulled high. At the end of the output waveform, the notification signal pin is pulled low. After receiving the notification signal high, the interconnected system samples the output waveform of the SOC system through the internal sampling FIFO and records the waveform data. After the notification signal pin is pulled low, the sampling FIFO ends the acquisition of the waveform signal. During this process, the verifier also observes whether the output waveform is correct through external instruments such as oscilloscopes. If the waveform is correct, the control system reads the waveform data in the interconnected system and stores it in the waveform data array, transcodes the verification program stream file and stores it in the verification program stream array of the control system program, and then drives the SDIO port to save the verification program stream file and waveform data to the storage chip eMMC. Finally, update the information storage table in the control system program. If the waveform is wrong, it means that there is a problem with this SOC function, and the SOC design needs to be modified and the operation of this function needs to be repeated.

[0052] For type III functions, during the first verification, an external instrument such as a signal generator is used to provide input waveform excitation, and additional synchronization is required to pull the notification signal of the interconnected system high. At the end of the external input waveform excitation, the notification signal pin is pulled low. After receiving the notification signal high, the interconnected system samples the output waveform of the SOC system through the internal sampling FIFO and records the waveform data. After the notification signal pin is pulled low, the sampling FIFO ends the acquisition of the waveform signal. Through IDE debugging, the verification personnel check whether the capture function is correct. If this module function captures the external input excitation correctly, the control system reads the waveform data in the interconnected system and stores it in the waveform data array, transcodes the verification program stream file and stores it in the verification program stream array of the control system program, and then drives the SDIO port to save the verification program stream file and waveform data to the storage chip eMMC. Finally, update the information storage table in the control system program. If the capture function is wrong, it means that there is a problem with this SOC function, and it is necessary to modify the SOC design and repeat this operation.

[0053] For type I, II, and III functional verification, each time the verification program and waveform data need to be saved in the eMMC storage chip, the information is updated to the control system program according to the information storage table. The information storage table mainly includes the contents of Table 4 below.

[0054] Table 4:

[0055] Function Name Function Code Type Encoding Program address Data address result Use ASCII code. 0~N, each function increases by 1. Type I, Type II, Type III. Verify the save address of the program in eMMC. The storage address of waveform data in eMMC. Success: 1 Failure: 0

[0056] The function names in the information storage table use ASCII codes. The advantage is that when the regression verification is completed, the results uploaded by the control system to the PC can directly display the function names. The function code starts with the value 0 and increases in sequence. It is used to realize the flexible connection between the SOC system pins and the FIFO signal pins in the interconnected system. The advantage of using type coding is that it can be determined whether the data space needs to be saved in the storage chip eMMC according to the type coding. For example, for type I functions, only the verification program needs to be saved, and the waveform data does not need to be saved; for type II and III functions, the verification program and the data need to be saved at the same time. Distinguishing function types is conducive to saving storage space. The advantage of using program addresses and data addresses is that the location of the verification program and waveform data in the storage chip eMMC can be flexibly configured.

[0057] In order to avoid the need for an external oscilloscope to visually observe the correctness of the output waveform during the regression verification process, or to provide a signal excitation to the waveform input module with an external signal generator, and to realize the automatic download of the verification program, the following functional designs are required:

[0058] Specifically, during the regression verification process, the control system reads the verification program flow file from the storage chip eMMC according to the program address in the information storage table, and uses the general IO port to simulate the JTAG protocol to download the verification program flow file to the SOC system for execution.

[0059] For type I functions, after the SOC system program runs, the program determines whether the function is correct. After the judgment is completed, the notification signal NOTICE pin is pulled high to notify the control system to read the operation result. At the same time, if the operation result is correct, the result feedback signal RESULT pin is pulled high, otherwise the result feedback signal RESULT pin is pulled low. After reading the notification signal, the control system reads the result feedback signal, saves the result to the information storage table, and then performs the regression test of the next function.

[0060] For type II functions, the control system switches the connection between the waveform output pin of the module and the sampling FIFO write signal in the interconnected system according to the function code in the information storage table. After the SOC system program runs, the module outputs the waveform, and the notification signal NOTICE pin is pulled high. At the end of the output waveform, the notification signal NOTICE pin is pulled low. During the period when the notification signal NOTICE pin is pulled high, the interconnected system samples the input waveform through the internal sampling FIFO and records the corresponding time when the waveform changes. After the output waveform ends, the control system reads the corresponding waveform data from the internal sampling FIFO of the interconnected system and the storage chip eMMC for comparison. If they are the same, the result is correct. If the waveform data is inconsistent, the result is wrong. After saving the result to the information storage table, the regression test of the next function is performed. The beneficial effect is that the waveform output needs to be observed by naked eye with an external oscilloscope during the regression verification process.

[0061] For type III functions, the control system connects the waveform capture pin of the switching module to the waveform output FIFO output pin in the interconnected system according to the function code in the information storage table. After the SOC system program runs, the SOC system notifies the interconnected system and the control system by pulling the notification signal pin high to notify the SOC system to start capturing the input waveform. The control system reads the corresponding waveform data from the storage chip eMMC according to the information storage table and transmits it to the output waveform FIFO inside the interconnected system. The interconnected system generates the external excitation signal required by the SOC, and the SOC program captures the external input excitation to determine whether it is correct. After the judgment is completed, the control system is notified of the reading operation result by pulling the notification signal NOTICE pin low. At the same time, if the verification result is correct, the result feedback signal RESULT pin is pulled high, otherwise the result feedback signal RESULT pin is pulled low. After reading the notification signal, the control system reads the result feedback signal, saves the result to the information storage table, and then performs the regression test of the next function. Its beneficial effect is to avoid the need for an external signal generator to provide signal excitation to the waveform input module during the regression verification process.

[0062] In the functional design of the control system, macro definitions are used to distinguish the functional bodies of the control system in the traditional verification and regression verification steps. A verification program flow array is designed in the control system program to store the verification program flow file; a waveform array is designed to store the waveform data read from the interconnected system sampling FIFO; and an information storage table array is designed to store the relevant information of each SOC system function. In the traditional verification process, the verifier transcodes the flow file (.bit file) and copies it to the verification program flow array. If there is waveform data in the interconnected system sampling FIFO, the waveform data is read and saved in the waveform array. The SDIO port is driven to save the verification program flow file (.bit file) and waveform data to the storage chip eMMC. Then a set of data is added to the information storage table array, including the function name, the function code is incremented by one on the previous basis, the type code, program address and data address are updated, and the result is 0 by default.

[0063] The regression verification process is as follows Figure 4 As shown, during the regression verification process, the control system reads the verification program from the eMMC chip through the SDIO port into the verification program flow array according to the program address in the information storage table; and reads the waveform data into the waveform array according to the data address. Before downloading the program, the SOC system is reset through the reset signal NRST pin, and the number of the current function is output through the function code switching signal pin. The JTAG timing download program is simulated through the IO port, the waveform output FIFO in the interconnected system is reset through the WRESET pin, and the waveform input FIFO in the interconnected system is reset through the RRESET pin, and then the function regression verification process is executed according to the function type. After the program is downloaded, a system timeout detection is required. If the verification of this function is not completed within the set time, the verification error of this function is determined. After all functions are run, the results are uploaded to the computer through the serial port. Its beneficial effect is to realize the automatic download of the verification program and the result judgment during the regression verification process.

[0064] The functional design of the interconnected system mainly includes the following functions:

[0065] 1. Realize the signal connection between the SOC system and the control system. Among them, verify the program download signal JTAG pin, the control system uses the general IO port to simulate the JTAG protocol, and realizes the transparent transmission between the JTAG function pin on the SOC system side through the interconnection system. In addition, the notification signal pin NOTICE and the result signal pin RESULT are output by the SOC system and transparently transmitted to the control system through the interconnection system. The SOC system reset pin NRST is output by the control system and transparently transmitted to the SOC system through the interconnection system. The beneficial effect is that the flexible configuration of the signal pins can be achieved by changing the program design in the interconnection system, avoiding the disadvantage that the hardware connection cannot be changed.

[0066] 2. Realize the function of collecting waveforms in the interconnected system, and design a waveform collection FIFO in the interconnected system to realize this function. In this embodiment, each waveform output module pin WAVE_OUT of the SOC system is at most 32. The width of the FIFO write signal wFIFO_I is 64 bits. The upper 32 bits of the wFIFO_I signal are used to save the logical value formed by the waveform level combination, and the lower 32 bits of the wFIFO_I signal are used to save the time when the waveform level combination changes. The depth of the FIFO is designed to be 512, and the width of the FIFO read pin FIFO_R is 16. When the notification pin NOTICE is pulled high, waveform sampling is turned on. Design an internal clock CLK in the interconnected system with a frequency of 100MHz; design a 32-bit register TIM_CNT_O to save the time of collecting waveforms, and the initial value is 0. In the waveform acquisition stage, after the NOTICE pin is pulled high, TIM_CNT_O is incremented by one on the rising edge of the CLK clock. When there is any change in the waveform output of the SOC system, TIM_CNT_O is written to the lower 32 bits of the wFIFO_I signal, WAVE_OUT is written to the upper 32 bits of the wFIFO_I signal, and then wFIFO_I is written to the FIFO. This operation is performed until the notification pin NOTICE is pulled low. After the waveform acquisition is completed, the control system reads the time value and logic value of the waveform through the FIFO_R pin. In the interconnected system software design, the function code is used to switch the connection between the wFIFO_I signal written to the sampling FIFO and the output pin signals of multiple output modules in the SOC system. When the value of SELECT[n-1:0] is equal to the function code value, the upper 32 bits of the wFIFO_I signal are connected to the pins of this function module. If the waveform output module has less than 32 pins, the value of the remaining bits of the wFIFO_I signal remains 0. The beneficial effect is that the waveform signals of all output modules can be connected to the write signals of the acquisition FIFO of the interconnection system without increasing the number of acquisition FIFOs, thereby simplifying the software design of the interconnection system.

[0067] 3. Realize the function of waveform output of interconnected system, and design a waveform output FIFO in the interconnected system to realize this function. In this embodiment, each waveform capture module pin WAVE_IN of SOC system is at most 32. The width of FIFO read signal rFIFO_O is 64 bits, the upper 32 bits of rFIFO_O signal are used to save the logic value formed by the waveform level combination, the lower 32 bits of rFIFO_O signal are used to save the time when the waveform level combination changes, the depth of FIFO is designed to be 65536, and the width of FIFO write pin FIFO_W is 16. After downloading the program, the control system writes the time value and logic value of the waveform to FIFO through the FIFO_W pin. Design an internal clock CLK in the interconnected system with a frequency of 100MHz; design a 32-bit register TIM_CNT_I to save the time of collecting waveforms, and the initial value is 0. In the waveform capture stage, after the NOTICE pin is pulled high, a 64-bit rFIFO_O value is read, and the logic value formed by the waveform level combination saved by the upper 32 bits of rFIFO_O signal is assigned to the waveform capture module pin WAVE_IN. TIM_CNT_I increases by one on the rising edge of the CLK clock. When TIM_CNT_I is greater than the time value saved in the lower 32 bits of the rFIFO_O signal, a 64-bit rFIFO_O value is read again, and this operation is performed until the waveform output ends. In the interconnection system software design, the function code is used to switch the connection between the high 32 bits of the rFIFO_O signal, the read signal of the waveform output FIFO, and the input pin signals of multiple capture modules in the SOC system. When the value of SELECT[n-1:0] is equal to the function code value, the high 32 bits of the rFIFO_O signal are connected to the pins of this function module. If the waveform capture module has less than 32 pins, only the valid pins of this module are connected. Its beneficial effect is that all input module capture signals can be connected to the output signal of the waveform output FIFO without increasing the number of waveform output FIFOs, simplifying the interconnection system software design.

[0068] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A SOC prototype automatic regression verification method based on FPGA, characterized in that: The steps include: Step 1: Use the traditional method to perform the first verification, and save the verified program and waveform data to the eMMC storage chip; wherein the traditional method includes: for all SOC functions, in the first verification process, an integrated development environment is used to write a verification program for the corresponding function, download it to the SOC system, and debug and run the program; all verification programs also need to provide an additional pin as a notification signal and a pin as a result signal; Step 2: During the regression verification process, the verification program and waveform data are read from the eMMC storage chip, the verification program is automatically downloaded to the SOC system for operation, and the waveform data is used for functional verification. After all functions are run, the results are uploaded to the PC. Also includes: The functions of SOC prototype verification are divided into the following three categories according to whether external input stimulation or external output waveform is required: Type I function: To verify this function, no external input stimulus is required, and no waveform is output to the outside. For type I function regression verification, after the verification program is run, the verification program determines whether the function is correct by itself, and after the judgment is completed, it notifies the control system through the notification signal pin to read the verification result. After reading the notification signal, the control system obtains the verification result through the reading result feedback signal, saves the verification result to the information storage table, and then performs regression test on the next function. Type II function: verify this function, output waveform to the outside, and verify whether the waveform is correct; for type II function regression verification, verify that the waveform is output after the program runs, and notify the interconnection system and control system through the notification signal pin to start outputting the waveform; the interconnection system samples the input waveform through the internal sampling FIFO and records the waveform data; the control system compares the waveform data in the internal sampling FIFO of the interconnection system with the waveform data stored in the eMMC storage chip. If they are the same, the verification is correct; if the waveform data are different, the verification is wrong. After saving the verification result to the information storage table, the regression test of the next function is carried out; To verify the function of type III, external input stimulus is required. For the regression verification of type III function, after the verification program runs, the notification signal pin notifies the interconnected system and the control system to start capturing the waveform. The control system reads the waveform data from the eMMC storage chip and transmits it to the waveform output FIFO inside the interconnected system. The interconnected system generates the external stimulus signal required by the SOC system. The verification program captures the external input stimulus and determines whether it is correct. Then, the control system is notified of the reading operation result through the notification signal pin. After reading the notification signal, the control system reads the result feedback signal, saves the result to the information storage table, and then performs regression testing on the next function.

2. The FPGA-based SOC prototype automatic regression verification method according to claim 1, characterized in that: The regression verification process also includes: the control system reads the verification program flow file from the eMMC storage chip according to the information storage table, and uses the general IO port to simulate the JTAG protocol to download the verification program flow file to the SOC system for execution.

3. The FPGA-based SOC prototype automatic regression verification method according to claim 1, characterized in that: For the type I function, after the first verification and confirmation of correctness, the control system saves the verification program flow file to the eMMC storage chip; For the type II function, during the first verification, the verification program outputs a waveform after running, and the interconnection system samples the output waveform of the SOC system through the internal sampling FIFO and records the waveform data; at the same time, an oscilloscope is used to observe whether the output waveform is correct. If the output waveform is correct, the control system saves the verification program stream file and the waveform data collected in the interconnection system to the eMMC storage chip; If the output waveform is wrong, it means that there is a problem with the SOC function and you need to modify the SOC chip design and repeat this operation; For type III functions, during the first verification, a signal generator is used to provide input waveform excitation, and the interconnection system samples the input waveform through the internal sampling FIFO and records the waveform data. If the capture module in the SOC system captures the external input excitation correctly, the control system saves the verification program flow file and the waveform data collected in the interconnection system to the eMMC storage chip; If the capture function is wrong, it means that there is a problem with this SOC function and you need to modify the SOC chip design and repeat this operation.

4. The FPGA-based SOC prototype automatic regression verification method as claimed in claim 3, characterized in that: For the functional verification of type I, type II and type III, each time the verification program and waveform data are saved in the eMMC storage chip, the information needs to be updated in the control system program according to the information storage table.

5. The FPGA-based SOC prototype automatic regression verification method according to claim 1, characterized in that: The information storage table includes: function name, function code, type code, program address, data address and result; the function name uses ASCII code, the function code starts from the value 0 and increases by 1 in sequence, which is used to realize the flexible connection between the SOC system pin and the FIFO signal pin in the interconnection system, the program address and data address are both storage addresses in the eMMC storage chip, and the result is 1 if successful and 0 if failed.

6. An FPGA-based SOC prototype automatic regression verification system, using an FPGA-based SOC prototype automatic regression verification method as claimed in any one of claims 1 to 5, characterized in that: include: SOC system, used to run the FPGA-based SOC chip netlist; The interconnection system uses FPGA to realize the signal connection between the SOC system and the control system. In the first traditional verification process, it is responsible for the waveform data acquisition of the external input excitation waveform and the waveform data acquisition of the SOC system output waveform; in the regression verification process, it is responsible for outputting waveforms to the SOC system or collecting waveforms from the SOC system; Control system, in the first traditional verification process, saves the verification program and correct waveform data to the eMMC storage chip; in the regression verification process, reads the verification program and waveform data from the eMMC storage chip, automatically downloads the verification program to the SOC system for operation, and uploads the results to the PC after all functions are completed; eMMC storage chip, used to store verification programs and waveform data; PC terminal, used to receive regression verification results.

7. The FPGA-based SOC prototype automatic regression verification system as claimed in claim 6, characterized in that: The interconnection system also includes: A waveform acquisition FIFO is used to record the sampling information of the input waveform; in the interconnected system program, the external signal input pin is connected to the write pin of the waveform acquisition FIFO. When the waveform sampling is turned on, a timer counts up according to the set frequency. Whenever the external signal input and output pins change, the combined logic values ​​of all external waveform pin levels at this time and the value of the timer are saved in the waveform acquisition FIFO, and this operation is repeated until all waveform acquisitions are completed; thereafter, the control system reads the waveform acquisition FIFO waveform data according to demand; in the interconnected system software design, the function code is used to switch the connection between the write signal of the waveform acquisition FIFO and the output signals of multiple output modules in the SOC system, and the function code is read by the control system from the information storage table and transmitted to the interconnected system through the pin; A waveform output FIFO is used to receive waveform data sent by the control system, and then generate a waveform output to a pin. In the interconnected system program, the output pin of the waveform output FIFO is connected to the capture pin of the SOC system; a timer counts up according to a set frequency, and the output pin of the waveform output FIFO outputs a logic level according to the combinational logic value in the waveform data to generate a waveform signal; whenever the value of the timer is the same as the time value in the waveform data stored in the waveform output FIFO, the next set of waveform data is read, the time comparison value and the waveform output signal are updated, and this operation is repeated until all waveform outputs are completed; in the interconnected system software design, a function code is used to switch the connection between the output signal of the waveform output FIFO and the capture signals of multiple input modules in the SOC system, and the function code is read from the information storage table by the control system and transmitted to the interconnected system through the pin.

8. The FPGA-based SOC prototype automatic regression verification system as claimed in claim 6, characterized in that: When the interconnection system realizes the signal connection transparent transmission between the SOC system and the control system, it also includes: a verification program download signal pin, a notification signal pin, a result signal pin and a SOC system reset pin.

9. The FPGA-based SOC prototype automatic regression verification system as claimed in claim 6, characterized in that: The control system also includes: using macro definitions to distinguish the functional bodies of the control system in traditional verification and regression verification steps; designing a verification program flow array in the control system program to store verification program flow files; designing a waveform array to store waveform data read from the interconnected system waveform acquisition FIFO; and designing an information storage table array to store relevant information of each SOC function.

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