Method for simulation logic system design, electronic equipment and storage medium

Abstract

The invention provides a method for simulating a logic system design, electronic equipment and a storage medium, and the method comprises the steps: simulating a first logic system design through a first hardware simulation tool to obtain simulation waveform data of the first logic system design, and converting the simulation waveform data into a synthesizable waveform logic, the second logic system design generated based on the synthesizable waveform logic and the first logic system design is simulated through the first hardware simulation tool, so that simulation waveform data can be continuously operated, and the problem of low operation efficiency caused by waveform data playback in a discrete form is avoided.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a method, electronic device and storage medium for simulating logic system design. Background Art

[0002] A hardware simulation tool (e.g., a prototype verification board or a hardware simulator) can prototype and debug a logic system design including one or more modules. The logic system design can be, for example, an integrated circuit (Application Specific Integrated Circuit, referred to as ASIC) or a system-on-chip (System-On-Chip, referred to as SOC) for a specific application. Therefore, the logic system design tested in the simulation tool can also be called a design under test (Design Under Test, referred to as DUT). The simulation tool can simulate the design under test through one or more configurable components (e.g., Field Programmable Gate Array (Field Programmable Gate Array, referred to as FPGA)), including performing various operations of the design under test, thereby testing and verifying the functions of each module of the design under test before manufacturing. By connecting a variety of peripheral daughter cards to the simulation tool, the effect of the design under test and various peripherals running as a complete system can also be tested.

[0003] In the SA (Simulation Acceleration) mode of FPGA verification technology, after pre-storing the waveform data, discrete stimulus will provide FPGA clock in discrete form for replaying the waveform corresponding to the waveform data. In other words, the start and stop of each clock cycle has additional time overhead, so the application of discrete stimulus makes the overall operating frequency of the software simulator low and the test efficiency of DUT low. Summary of the invention

[0004] A first aspect of the present application provides a method for simulating a logic system design, wherein the logic system design includes a design to be tested, and the method includes: obtaining simulation waveform data of the first logic system design obtained by simulating the first logic system design via a first hardware simulation tool; converting the simulation waveform data into synthesizable waveform logic; generating a second logic system design based on the synthesizable waveform logic and the first logic system design; and simulating the second logic system design via the first hardware simulation tool to obtain a simulation result of the design to be tested.

[0005] A second aspect of the present application provides an electronic device, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device performs the method as described in the first aspect.

[0006] A third aspect of the present application provides a non-transitory computer-readable storage medium, which stores a set of instructions for a computer, and when the set of instructions is executed, causes the computer to perform the method as described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1 A schematic diagram of the structure of a host according to an embodiment of the present application is shown.

[0009] Figure 2 A schematic diagram of a simulation system according to an embodiment of the present application is shown.

[0010] Figure 3 A schematic diagram of an exemplary system for simulating logic system design according to an embodiment of the present application is shown.

[0011] Figure 4 A schematic diagram of an exemplary system for simulating logic system design according to an embodiment of the present application is shown.

[0012] Figure 5 A flowchart of an exemplary method for simulating logic system design according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0013] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0014] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0015] As mentioned above, in the SA (Simulation Acceleration) mode of FPGA verification technology, after pre-storing the waveform data, discrete stimulus will provide FPGA clock in discrete form for replaying the waveform corresponding to the waveform data. In other words, the start and stop of each clock cycle has additional time overhead, so the application of discrete stimulus makes the overall operating frequency of the software simulator low and the test efficiency of DUT low.

[0016] In view of this, the present application provides a method, electronic device and storage medium for simulating a logic system design, wherein a first logic system design is simulated by a first hardware simulation tool to obtain simulation waveform data of the first logic system design, the simulation waveform data is converted into synthesizable waveform logic, and a second logic system design generated based on the synthesizable waveform logic and the first logic system design is simulated by the first hardware simulation tool, so that the simulation waveform data can be run continuously, avoiding the problem of low operating efficiency caused by playing back the waveform data in a discrete form.

[0017] Figure 1 FIG. 1 shows a schematic diagram of the structure of a host 100 according to an embodiment of the present application. The host 100 may be an electronic device running a simulation system. Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other through the bus 110 in communication with each other inside the electronic device.

[0018] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0019] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). In some embodiments, the simulation test system for simulating the logic system design may be a computer program stored in the memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method for locating errors of the present application) and data to be processed (e.g., the memory may store temporary codes generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0020] The network interface 106 can be configured to provide communication with other external devices to the host 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC) etc.), a cellular network, the Internet or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0021] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0022] The bus 110 may be configured to transmit information between various components of the host 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0023] It should be noted that, although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the electronic device architecture may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above electronic device architecture may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0024] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of the present application is shown.

[0025] like Figure 2 As shown, the simulation system 200 may include a simulation tool 202 and a host 100 connected to the simulation tool 202 .

[0026] The simulation tool 202 is a hardware system for simulating a design under test (DUT). The simulation tool 202 can be a prototype verification board or a hardware simulator (emulator). A design under test can include multiple modules. The design under test can be a combinational logic circuit, a sequential logic circuit, or a combination of the two. The simulation tool 202 can include one or more configurable circuits (e.g., FPGA) for simulating the design under test. Wherein, the design under test can also be a logic system design.

[0027] Simulation tool 202 can include interface unit 2022, is used for coupling with main frame 100 communication ground, to carry out the communication between main frame 100 and simulation tool 202.In certain embodiments, interface unit 2022 can include one or more interfaces with electrical connection capability.For example, interface unit 2022 can include RS232 interface, USB interface, LAN port, optical fiber interface, IEEE1394 (firewire interface) etc.In certain embodiments, interface unit 2022 can be wireless network interface.For example, interface unit 2022 can be WIFI interface, bluetooth interface etc.

[0028] The host 100 may transmit the compiled DUT, debugging instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 may also transmit simulation data, etc. to the host 100 via the interface unit 2022.

[0029] The simulation tool 202 may also include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during the simulation process. In some embodiments, the signal values ​​generated by the design under test during the simulation process may be directly read by the host 100. It is understood that the memory 2024 may also be independent of the simulation tool 202, for example, using an external memory.

[0030] The simulation tool 202 may also include an FPGA 2026 for implementing the logic system design in hardware on the FPGA. It is understandable that the simulation tool 202 may include multiple FPGAs, which are only examples in the figure.

[0031] In addition to being connected to the host 100 , the emulation tool 202 may also be connected to one or more daughter cards 204 via an interface unit 2022 .

[0032] The daughter card is used to provide peripherals to the DUT to form a complete electronic system when using the simulation tool 202 for prototype verification. Prototype verification refers to a verification method that restores the actual use scenario of the chip as much as possible before the chip is taped out to verify whether the chip function is accurate and complete. The daughter card 204 can include a memory daughter card (for example, providing a DDR memory interface), a communication daughter card (for example, providing a variety of network interfaces or a wireless network card interface), etc.

[0033] The host 100 can be used to configure the simulation tool 202 to simulate a design to be tested. The design to be tested can be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, the host 100 can be a virtual host in a cloud computing system. The logic system design (e.g., ASIC or System-On-Chip) can be designed by a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog).

[0034] The host 100 may receive a request from a user to debug the design to be tested. As described above, the design to be tested may include one or more modules. The description of the design to be tested may be completed using a hardware description language. The host 100 may be synthesized based on the description of the design to be tested to generate, for example, a gate-level circuit netlist (not shown) of the design to be tested. The gate-level circuit netlist of the design to be tested may be loaded into the simulation tool 202 for operation, and then a circuit structure corresponding to the design to be tested may be formed in the simulation tool 202. Therefore, the circuit structure of the design to be tested may be obtained according to the description, and accordingly, the circuit structure of each block in the design to be tested may also be obtained similarly.

[0035] When performing verification tasks, the software simulator receives multiple stimuli from the testbench (usually described in System Verilog language), and sends the multiple stimuli to the DUT running on the software simulator, completes the simulation, obtains simulation data, and further obtains simulation results based on the simulation data.

[0036] In the SA (Simulation Acceleration) mode of FPGA, after pre-storing the waveform data, discrete stimulus will provide FPGA clock in discrete form for replaying the waveform corresponding to the waveform data. In other words, the start and stop of each clock cycle has additional time overhead, so the application of discrete stimulus makes the overall operating frequency of the software simulator low (about 10-100KHz scale), and the test efficiency of DUT is low.

[0037] At the same time, the common practice is to use a dedicated waveform playback device to play back waveform data. Since the waveform playback device needs to be connected to the FPGA that carries the DUT, it is highly rigid and lacks flexibility.

[0038] How to solve the above problems of slow playback speed and lack of flexibility is a technical problem that needs to be solved urgently.

[0039] Figure 3 FIG. 3 is a schematic diagram of an exemplary system 300 for simulating logic system design according to an embodiment of the present application.

[0040] like Figure 3 As shown, the system 300 may include a recording device 30 and a playback device 32 at different stages. The recording device 30 may include a compiler 304, a first hardware simulation tool 306, an external device 308 (e.g., a daughter card), and a waveform acquisition tool 310. It is understood that the compiler 304 may run on the host 100. In some embodiments, the external device 308 may be connected to the first hardware simulation tool 306 to provide at least part of the stimulus signal to the first logic system design 302 simulated in the first hardware simulation tool 306.

[0041] The recording device 30 can record the simulation waveform generated by simulating the first logic system design 302. The compiler 304 can compile the first logic system design 302 into an executable file and run it on the first hardware simulation tool 306 to generate simulation waveform data 330. Among them, the first logic system design 302 may include a design under test (DUT) and a test bench (testbench). The DUT may be a chip device or a part of a chip design. The test bench may be used to provide stimulus to the DUT. It is understood that in some embodiments, the external device 308 may also provide a part of the stimulus to the DUT.

[0042] The simulation waveform data 330 may include at least one of an input signal (e.g., stimulus), an output signal, or an internal signal of the first logic system design 302. The internal signal of the first logic system design 302 refers to a signal on an internal terminal, which can be used to observe the operation of the internal module of the first logic system design 302.

[0043] The recording device 30 may convert the simulation waveform data into a synthesizable waveform logic 312. The synthesizable waveform logic 312 may restore the above-mentioned simulation waveform data 330 when running. The synthesizable waveform logic 312 may be a code written in a hardware language, and the hardware description language includes at least one of Verilog, SystemVerilog or Very High Speed ​​Integrated Circuit Hardware Description Language (VHDL).

[0044] In some embodiments, the recording device 30 may describe the simulation waveform data 330 in the form of a state machine and a memory, and convert the state machine and the memory into a synthesizable waveform logic 312. For example, for waveform data with 30 waveform deformations (i.e., any bit in the waveform changes), S0, S1, ..., S29 may be used to represent 30 states. The memory may be used to record the value of each state and the duration.

[0045] In this way, by utilizing the combination of the state machine and the memory, the recording device 30 can use a hardware description language to describe the logic circuit corresponding to the simulation waveform data 330 , and then form a synthesizable waveform logic 312 .

[0046] It is understandable that the hardware language description of a logic circuit can be varied, and those skilled in the art can use other methods to describe the logic circuit corresponding to the simulation waveform data 330 without being limited to the above examples.

[0047] The playback device 32 can play back the simulation waveform data 330. By playing back the simulation waveform data 330, regression testing of the DUT can be implemented. The playback device 32 can include a compiler 304 and a first hardware simulation tool 306. It can be understood that the first hardware simulation tool 306 here does not mean that the hardware simulation tool of the playback device 32 and the hardware simulation tool of the recording device 30 are the same device, but can be different devices, but can provide compatible simulation capabilities.

[0048] The compiler 304 of the playback device 32 may compile the second logic system design 314 generated based on the synthesizable waveform logic 312 and the first logic system design 302 into an executable file. The synthesizable waveform logic 312 corresponding to the simulation waveform data 330 may be provided to the first logic system design 302. For example, the synthesizable waveform logic 312 may be connected to the first logic system design 302, so that the synthesizable waveform logic 312 may apply the restored simulation waveform data 330 to the first logic system design 302 at runtime, thereby allowing the user to perform regression testing on the first logic system design 302 under the same simulation waveform data 330. It is understood that the first logic system design 302 in the playback device 32 may be an unmodified first logic system design 302 or a modified first logic system design 302.

[0049] The first hardware simulation tool 306 may simulate the second logic system design 314 and output the simulation result (eg, simulation waveform graph) of the DUT to an output device (eg, displayed on a display).

[0050] Since the synthesizable waveform logic 312 and the first logic system design 302 are both written in hardware description language, they can be appropriately rewritten to achieve flexible connection, solving the problems of poor economy and low flexibility caused by fixed recording logic recording simulation waveform data, and can quickly switch the waveform replay required by different test cases. At the same time, since the synthesizable waveform logic 312 and the first logic system design 302 can be integrated into the hardware simulation tool for integrated operation, the efficiency of regression testing can be improved and continuous operation can be achieved.

[0051] In the regression test based on FPGA verification technology, the logic system design may be modified (for example, engineers fix defects or add functions to the first logic system design 302), and any changes in the hardware simulation environment (for example, changes in compiler parameters) may cause changes in the hardware simulation results. Since the simulation waveform data is converted into synthesizable waveform logic, in some embodiments, the modified first logic system design 302 can still generate the second logic system design 314 with the synthesizable waveform logic. Through the synthesizable waveform logic, the original stimulus is fully reproduced without adding additional development costs, ensuring the consistency of the stimulus before and after the modification of the logic system design, thereby improving the accuracy of the regression test.

[0052] like Figure 3As shown, when converting the simulation waveform data into synthesizable waveform logic, in some embodiments, the simulation waveform data 330 of the first logic system design 302 and the stimulus provided by the external device 308 can be collected by the waveform collection tool 310 connected to the first hardware simulation tool 306. The collected simulation waveform data 330 and the stimulus are converted into synthesizable waveform logic 312 by the waveform collection tool 310.

[0053] The waveform acquisition tool 310 may be a hardware device such as an FPGA. Figure 3 As shown, in some embodiments, the waveform acquisition tool 310 can provide a physical interface to the first hardware simulation tool 306, and the physical interface can be a device such as a GPIO (General Purpose Input Output) interface, and the waveform acquisition tool 310 can acquire simulation waveform data 330 through the physical interface.

[0054] The waveform acquisition tool 310 can run recording logic 3104 for acquiring simulation waveform data 330 and converting the simulation waveform data 330 into synthesizable waveform logic. In some embodiments, the recording logic 3104 can include a waveform acquisition port, a buffer, a processor, and a translation logic. The waveform acquisition port can be used to receive the simulation waveform data 330 from the physical port 3102. The buffer can be used to temporarily store the collected simulation waveform data. After the processor processes the simulation waveform data 330, it can convert the simulation waveform data 330 into synthesizable logic 312 equivalent to the simulation waveform through the translation logic.

[0055] In some embodiments, the playback device 32 may further include a memory 316. The memory 316 may store the synthesizable logic 312 and the first logic system design 302, so that the synthesizable logic 312 may be repeatedly used during the waveform playback process.

[0056] Figure 4 A schematic diagram of an exemplary system 400 for simulating logic system design according to an embodiment of the present application is shown.

[0057] like Figure 4As shown, the system 400 may include a recording device 40 and a playback device 32 at different stages. In some embodiments, a recording logic 402 corresponding to the first logic system design 302 may be generated, and the recording logic 402 may be provided to the first logic system design 302, for example, the recording logic 402 may be connected to the first logic system design 302. After being compiled by the compiler 304, the first logic system design 302 and the recording logic 402 may be run together on the first hardware simulation tool 306. In this way, the recording device 40 may record the simulation waveform data 330 while simulating. The simulation waveform data 330 may be output to the debugging tool 404, which may be a computer program running on the host 100.

[0058] In some embodiments, the recording logic 402 forms the synthesizable waveform logic while recording the simulation waveform data 330 during the simulation of the first logic system design 302. In other embodiments, the recording logic 402 forms part of the synthesizable waveform logic while recording the simulation waveform data 330 during the simulation of the first logic system design 302, and combines the part of the synthesizable waveform logic with the simulation waveform data 330 in the debugging tool 404 and converts them into the synthesizable waveform logic 312.

[0059] The generated synthesizable waveform logic 312 may be output by the recording device 40 .

[0060] The playback device 32 in the system 400 is the same as or similar to the playback device 32 in the system 300, and will not be described in detail here. Since the synthesizable waveform logic 312 and the first logic system design 302 are both written in the hardware description language, they can be appropriately rewritten to achieve flexible connection, solving the problems of poor economy and low flexibility caused by the fixed recording logic recording simulation waveform data, and can quickly switch the waveform player required by different test cases. At the same time, since the synthesizable waveform logic 312 and the first logic system design 302 can be integrated into the hardware simulation tool for integrated operation, the efficiency of regression testing can be improved and continuous operation can be achieved.

[0061] Figure 5 FIG. 5 is a flow chart of an exemplary method 500 for simulating logic system design according to an embodiment of the present application. The method 500 may be Figure 2 More specifically, the system 300 (e.g., Figure 3 300) or system 400 (e.g., Figure 4 The system 400 in FIG. Figure 5 As shown, method 500 may include the following steps.

[0062] In step 502, the host 100 may obtain a first hardware emulation tool (eg, Figure 3 or Figure 4 A first hardware simulation tool 306 in the embodiment of the present invention simulates a first logic system design (e.g., Figure 3 or Figure 4 The simulation waveform data of the first logic system design (eg, Figure 3 The simulation waveform data 330 of FIG. 4 can be stored in binary, XEDB, VCD or other formats.

[0063] In some embodiments, the simulation waveform data includes at least one of an input waveform (eg, a stimulus for the first logic system design) or an output waveform of the first logic system design.

[0064] In some embodiments, the host 100 may provide the first logic system design with recording logic corresponding to the first logic system design (eg, Figure 4 The recording logic 402 in the first logic system design); the simulation waveform data is recorded via the recording logic during the simulation process of the first logic system design. In this way, the simulation waveform data can be recorded while the simulation is being performed.

[0065] In step 504, the host 100 may convert the simulation waveform data into synthesizable waveform logic (e.g., Figure 3 or Figure 4 The synthesizable waveform logic 312 in FIG.

[0066] In some embodiments, the host 100 can be connected to the first hardware simulation tool via a waveform acquisition tool (eg, Figure 3 or Figure 4 The waveform acquisition tool 310 in the embodiment of the present invention acquires the simulation waveform data of the first logic system design.

[0067] In some embodiments, the host 100 can collect the stimulus of the first logic system design via the waveform acquisition tool; and convert the simulation waveform data and the stimulus into the synthesizable waveform logic. By converting the simulation waveform data into the synthesizable waveform logic, the problems of poor economy and low flexibility caused by recording simulation waveform data with fixed recording logic are solved, and the waveform replay required by different test cases can be quickly switched.

[0068] In some embodiments, the stimulus includes a signal from an external device (e.g., Figure 3 or Figure 4 The external device 308 in the apparatus transmits a signal to the first hardware simulation tool and the waveform acquisition tool.

[0069] In some embodiments, the waveform acquisition tool includes an FPGA, and the FPGA runs logic for acquiring the simulation waveform data. The waveform acquisition tool can convert the acquired simulation waveform data into synthesizable waveform logic.

[0070] In some embodiments, the synthesizable waveform logic is a code written in a hardware language, and the hardware description language includes at least one of Verilog, SystemVerilog, or a very high speed integrated circuit hardware description language (VHDL). Since the logic system design can usually be a synthesizable code written in a hardware description language such as Verilog, VHDL, etc., the simulation waveform data is converted into the synthesizable waveform logic and can be used as the input of the first hardware simulation tool together with the first logic system design (generating the second logic system design), so that the simulation results of the second logic system design are continuously output to the output device.

[0071] In some embodiments, the host 100 can convert the simulation waveform data into the synthesizable waveform logic via the recording logic. For example, converting the simulation waveform data into the synthesizable waveform logic via the recording logic further includes: describing the simulation waveform data in the form of a state machine and a memory; and converting the description of the state machine and the memory into the synthesizable waveform logic. The simulation waveform data is directly converted into the synthesizable waveform logic through the recording logic without the need for additional debugging tools for conversion.

[0072] In some embodiments, the host 100 may store the data via a memory (eg, Figure 3 or Figure 4 The synthesizable waveform logic is stored in the memory 316 in the waveform replay process.

[0073] In step 506, the host 100 may generate a second logic system design (eg, Figure 3 or Figure 4 The second logic system design 314 in.

[0074] In some embodiments, the host 100 can modify the first logic system design; generate the second logic system design based on the synthesizable waveform logic and the modified first logic system design. Through the synthesizable waveform logic, the original stimulus is fully reproduced without adding additional development costs, ensuring the consistency of the stimulus before and after the modification of the logic system design, thereby improving the accuracy of regression testing.

[0075] In step 508, the host 100 may simulate the second logic system design via the first hardware simulation tool to obtain a simulation result of the design under test.

[0076] The present application provides a method, electronic device and storage medium for simulating a logic system design. A first logic system design is simulated by a first hardware simulation tool to obtain simulation waveform data of the first logic system design, the simulation waveform data is converted into synthesizable waveform logic, and a second logic system design generated based on the synthesizable waveform logic and the first logic system design is simulated by the first hardware simulation tool, so that the simulation waveform data can be run continuously, avoiding the problem of low operating efficiency caused by playing back waveform data in a discrete form.

[0077] The present application also provides an electronic device. The electronic device may be Figure 1 The host 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device executes the method 500.

[0078] The embodiment of the present application further provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of instructions for a computer, and the set of instructions is used to make the computer perform the method 500 when executed.

[0079] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0080] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0081] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0082] This application is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A method for simulating a logic system design, wherein the logic system design includes a design to be tested, wherein the method include: Acquire simulation waveform data of the first logic system design obtained by simulating the first logic system design through a first hardware simulation tool; converting the simulation waveform data into synthesizable waveform logic; generating a second logic system design based on the synthesizable waveform logic and the first logic system design; The second logic system design is simulated via the first hardware simulation tool to obtain a simulation result of the design to be tested.

2. The method according to claim 1, in, The converting the simulation waveform data into synthesizable waveform logic further comprises: Simulation waveform data of the first logic system design is acquired via a waveform acquisition tool connected to the first hardware simulation tool.

3. The method according to claim 1, in, The simulating the first logic system design via the first hardware simulation tool to obtain simulation waveform data of the first logic system design further includes: providing the first logic system design with recording logic corresponding to the first logic system design; The simulation waveform data is recorded via the recording logic during the simulation process of the first logic system design.

4. The method according to claim 3, in, The converting the simulation waveform data into synthesizable waveform logic further comprises: The simulation waveform data is converted into the synthesizable waveform logic via the recording logic.

5. The method according to claim 1, in, The generating a second logic system design based on the synthesizable waveform logic and the first logic system design further comprises: modifying the first logic system design; The second logic system design is generated based on the synthesizable waveform logic and the modified first logic system design.

6. The method according to claim 1, in, The simulation waveform data includes at least one of an input waveform or an output waveform of the first logic system design.

7. The method according to claim 2, in, The waveform acquisition tool includes an FPGA, and logic for acquiring the simulation waveform data runs on the FPGA.

8. The method according to claim 1 or 4, in, The converting the simulation waveform data into synthesizable waveform logic further comprises: describing the simulation waveform data in the form of a state machine and a memory; and A description of the state machine and the memory is converted into the synthesizable waveform logic.

9. An electronic device, include: a memory for storing a set of instructions; as well as At least one processor is configured to execute the set of instructions so that the electronic device performs the method according to any one of claims 1 to 8. 10 . A non-transitory computer-readable storage medium storing a set of instructions for a computer, the set of instructions being used to cause the computer to perform the method according to claim 1 when executed.

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