Display device

Abstract

The invention discloses a display device, which comprises a display panel, a power management circuit and a display driving circuit, and is characterized in that the display panel comprises a display area and a non-display area at least partially surrounding the display area; the display area is provided with a plurality of pixels arranged in an array; each pixel at least comprises a reset module and a light-emitting element; the reset module is electrically connected with the first pole of the light-emitting element; the power management circuit is arranged in the non-display area; the power management circuit is at least used for providing a first power signal for the second pole of the light-emitting element; the display driving circuit is arranged in the non-display area; the display driving circuit is at least used for providing a reset signal for the reset module; wherein the working process of the display device at least comprises a power-on stage; in the power-on stage, the difference value between the voltage of the reset signal and the voltage of the first power supply signal is delta Vb; the turn-on voltage of the light-emitting element is V0; [delta] Vblt; v0. According to the technical scheme, the splash screen problem of the display device in the power-on stage can be solved, and the display effect of the display device is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device. Background Art

[0002] A display device generally includes a display panel and a driving circuit and a power supply circuit arranged on the display panel. The driving circuit provides a driving signal to the display panel, and the power supply circuit provides a power supply signal to the display panel, so that the display panel can display images under the joint control of the driving signal and the power supply signal.

[0003] During the power-on process of the display device, such as the startup process of the display device, the driving circuit usually provides the display panel with a driving signal corresponding to a 0 grayscale image, so that the display panel can present a black image. However, during the power-on process, the power signal output by the power circuit fluctuates and changes instantaneously, which causes the display device to flicker, affecting the display effect of the display device. Summary of the invention

[0004] The present invention provides a display device to solve the screen flickering problem of the display device during the power-on stage and improve the display effect of the display device.

[0005] The present invention provides a display device, comprising:

[0006] The display panel comprises a display area and a non-display area at least partially surrounding the display area; the display area is provided with a plurality of pixels arranged in an array; the pixels at least comprise a reset module and a light emitting element; the reset module is electrically connected to a first electrode of the light emitting element;

[0007] A power management circuit is arranged in the non-display area; the power management circuit is at least used to provide a first power signal to the second electrode of the light-emitting element;

[0008] A display driving circuit is arranged in the non-display area; the display driving circuit is at least used to provide a reset signal to the reset module;

[0009] The working process of the display device at least includes a power-on stage; in the power-on stage, the difference between the voltage of the reset signal and the voltage of the first power signal is ΔVb; the start voltage of the light-emitting element is V0; |ΔVb| <V0。

[0010] The technical solution provided by the present invention, in the power-on stage, controls the power management circuit to provide the voltage of the first power signal to the light-emitting element and the voltage of the reset signal provided by the display driving circuit to the reset module, so that the absolute value of the difference between the voltage of the reset signal provided to the first pole of the light-emitting element of the display panel and the first power signal provided to the second pole of the light-emitting element of the display panel is smaller than the start-up voltage of the light-emitting element, so that the light-emitting element cannot emit light in the power-on stage, ensuring that the display brightness of the light-emitting element is 0 gray scale, thereby avoiding the screen flickering problem that occurs in the display device in the power-on stage, and further facilitating improving the display effect of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a structural schematic diagram of a display device provided by an embodiment of the present invention;

[0012] Figure 2 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0013] Figure 3 It is a driving timing diagram of a display device in the related art;

[0014] Figure 4 is a schematic structural diagram of another display device provided by an embodiment of the present invention;

[0015] Figure 5 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0016] Figure 6 is a schematic diagram of a driving timing sequence of a pixel in a display device provided by an embodiment of the present invention;

[0017] Figure 7 is a driving timing diagram of a display device provided by an embodiment of the present invention;

[0018] Figure 8 is a driving timing diagram of another display device provided by an embodiment of the present invention;

[0019] Fig. 9 is a driving timing diagram of another display device provided by an embodiment of the present invention;

[0020] Fig.10 is a driving timing diagram of another display device provided by an embodiment of the present invention;

[0021] Fig.11 is a driving timing diagram of a display device provided by an embodiment of the present invention;

[0022] Fig.12 is a driving timing diagram of another display device provided by an embodiment of the present invention;

[0023] Fig.13 is a driving timing diagram of another display device provided by an embodiment of the present invention;

[0024] Fig.14 is a driving timing diagram of another display device provided by an embodiment of the present invention;

[0025] Fig.15 is a driving timing diagram of a display device provided by an embodiment of the present invention;

[0026] Fig.16 is a driving timing diagram of another display device provided by an embodiment of the present invention;

[0027] Fig.17 is a driving timing diagram of another display device provided by an embodiment of the present invention;

[0028] Fig.18 is a structural schematic diagram of another display device provided by an embodiment of the present invention;

[0029] Fig.19 is a driving timing diagram of another display device provided by an embodiment of the present invention;

[0030] Fig. 20 is a driving timing diagram of a display device provided by an embodiment of the present invention;

[0031] Fig.21 It is a schematic diagram of the structure of another display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0033] Figure 1 is a schematic structural diagram of a display device provided by an embodiment of the present invention, Figure 2 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention, with reference to Figure 1 and Figure 2The display device 200 includes a display panel 100, the display panel 100 includes a display area 101, and the display area 101 is provided with a plurality of pixels 110 arranged in an array; the pixel 110 includes a pixel circuit 111 and a light-emitting element 112; the pixel circuit 111 includes at least a reset module 15, and the reset module 15 is electrically connected to the first pole of the light-emitting element 112, so that the reset module 15 can reset the first pole of the light-emitting element 112 to clear the signal written to the first pole of the light-emitting element 112, so that when entering the light-emitting stage of the pixel 110, the light-emitting element 112 can accurately emit light.

[0034] The display device 200 may further include a power management circuit 104 and a display driving circuit 103. In this case, the display panel 100 may further include a non-display area 102 at least partially surrounding the display area 101, and the power management circuit 104 and the display driving circuit 103 may both be disposed in the non-display area 102. The power management circuit 104 is at least used to provide a first power signal to the second electrode of the light emitting element 112, and the display driving circuit 103 is at least used to provide a reset signal to the reset module 15.

[0035] Among them, the non-display area 102 at least partially surrounds the display area 101. It can be understood that the non-display area 102 is arranged around the display area 101, or the non-display area 102 is located on one side or multiple sides of the display area 101. It can be designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0036] It is understandable that when the display device 200 needs to start working, it will first enter the power-on stage of the display device 200, that is, the working process of the display device 200 at least includes the power-on stage. Since the display driving circuit 103, the power management circuit 104, and each node of each pixel 110 need to be charged or discharged during the power-on stage, the signals output by the display driving circuit 103 and the power management circuit 104 are unstable, and the signals provided to each pixel 110 are unstable, so that when the pixel 110 is controlled to display light during the power-on stage, it will cause the pixel 110 to be unable to accurately display light, affecting the display effect of the display device 200. Therefore, during the power-on stage, the display driving circuit 103 controls the display panel 100 to display a black screen, that is, the display light brightness of each pixel 110 is 0 grayscale.

[0037] Based on the above reasons, in the power-on stage, the display driving circuit 103 starts to provide the reset signal Vref2 to the reset module 15 of each pixel 110. At the same time, the display driving circuit 103 can also control the reset module 15 to transmit the reset signal Vref2 to the first pole of the light-emitting element 112 to reset the first pole of the light-emitting element 112, so that when the light-emitting element 112 displays light, it can ensure that the display driving signal can be accurately provided to the first pole of the light-emitting element 112. At this time, the signal of the first pole of the light-emitting element 112 is consistent with the reset signal Vref2; at the same time, the power management circuit 104 will provide the first power signal PVEE to the second pole of the light-emitting element 112 to charge or discharge the second pole of the light-emitting element 112 to prepare for subsequent display light emission. At this time, the signal of the second pole of the light-emitting element 112 can be consistent with the first power signal PVEE provided by the power management circuit 104. However, when entering the power-on stage, the first power signal output at the moment when the power management circuit 104 is powered on will produce instantaneous fluctuations, and the instantaneous fluctuations will affect the accuracy of the first power signal provided to the second pole of the light-emitting element 112.

[0038] For example, Figure 3 This is a driving timing diagram of a display device in the related technology. Figures 1 to 3 When the light-emitting element 112 includes a light-emitting diode, the first electrode may be the anode of the light-emitting diode, and the second electrode may be the cathode of the light-emitting diode. At the moment of power-on, if the first power signal is a relatively negative pulse signal due to the instantaneous fluctuation of the first power signal, the difference between the voltage of the first electrode signal and the voltage of the second electrode signal of the light-emitting element 112 will be greater than the start-up voltage of the light-emitting element 112, which will cause the light-emitting element 112 to display and emit light. In this way, during the power-on stage, due to the instantaneous display and emission of the light-emitting element 112, the display device 200 will display a non-black screen for an instant during the time period when the display device 200 needs to display a black screen, that is, the display brightness of the pixel 110 in the display panel 100 is greater than 0 grayscale, so that the display device 200 will have a flickering screen, affecting the display effect of the display device 200.

[0039] To solve the above technical problems, in an embodiment of the present invention, during the power-on phase of the display device 200, when the difference between the voltage of the reset signal Vref2 provided by the display driving circuit 103 and the voltage of the first power signal provided by the power management circuit 104 is ΔVb, and the start-up voltage of the light-emitting element 112 is V0, |ΔVb| <V0。

[0040] The start-up voltage V0 of the light-emitting element 112 is the minimum voltage difference between the anode and the cathode of the light-emitting element 112 when the light-emitting element 112 can emit light. The start-up voltage V0 is usually a positive value. At this time, the value range of ΔVb can be: -V0<ΔVb <V0。

[0041] like Figure 2 As shown, in the case where the first pole is the anode of the light emitting element 112 and the second pole is the cathode of the light emitting element 112 , the first power signal may be a negative power signal PVEE. Therefore, in the power-on stage, the reset signal Vref2 provided by the display driving circuit 103 can be controlled to be smaller than the first power signal PVEE provided by the power management circuit 104, so that the voltage difference ΔVb between the reset signal Vref2 of the first pole of the light-emitting element 112 and the first power signal PVEE of the second pole of the light-emitting element 112 is a negative value, that is, the voltage difference between the anode signal and the cathode signal of the light-emitting element 112 is a negative value, so that the voltage difference between the anode signal and the cathode signal of the light-emitting element 112 is smaller than the start-up voltage V0 of the light-emitting element 112, thereby ensuring that the light-emitting element 112 cannot display light; alternatively, the reset signal Vref2 provided by the display driving circuit 103 can also be greater than or equal to the first power signal PVEE provided by the power management circuit 104. At this time, as long as the difference between the reset signal Vref2 and the first power signal PVEE is ensured to be small enough, it can be ensured that the voltage difference between the reset signal Vref2 of the anode of the light-emitting element 112 and the first power signal PVEE of the cathode of the light-emitting element 112 is smaller than the start-up voltage V0 of the light-emitting element 112, which can also make the light-emitting element 112 unable to display light.

[0042] It should be noted that the above description only exemplarily illustrates the reset signal provided by the display driving circuit 103 and the first power supply signal provided by the power management circuit 104 during the power-on stage by taking the first electrode of the light-emitting element 112 as the anode of the light-emitting element 112 and the second electrode of the light-emitting element 112 as the cathode of the light-emitting element 112 as an example. In the embodiment of the present invention, Figure 4 As shown, the second electrode of the light emitting element 112 may also be the anode of the light emitting element 112 , and the first electrode of the light emitting element 112 may be the cathode of the light emitting element 112 .

[0043] Combined with reference Figure 4 and Figure 5For a case where the second electrode of the light emitting element 112 is the anode of the light emitting element and the first electrode of the light emitting element 112 is the cathode of the light emitting element 112 , the first power signal may be the positive power signal PVDD. At this time, in the power-on stage, the reset signal Vref2 provided by the display driving circuit 103 can be controlled to be greater than the first power signal PVDD provided by the power management circuit 104, so that the difference ΔVb between the first power signal PVDD of the second pole of the light-emitting element 112 and the reset signal Vref2 of the first pole of the light-emitting element 112 can be a negative value, that is, the voltage difference between the anode and the cathode of the light-emitting element 112 is a negative value, so that the voltage difference between the anode and the cathode of the light-emitting element 112 is less than its turn-on voltage V0, and the light-emitting element cannot emit light; or, the reset signal Vref2 provided by the display driving circuit 103 can also be less than the first power signal PVDD provided by the power management circuit 104. At this time, as long as the difference between the first power signal PVDD and the reset signal Vref2 is ensured to be small enough, it can be ensured that the voltage difference between the first power signal PVDD of the anode of the light-emitting element 112 and the reset signal Vref2 of the cathode of the light-emitting element 112 is less than the turn-on voltage V0 of the light-emitting element 112, which can also make the light-emitting element 112 unable to display light.

[0044] By adopting the above technical solution, during the power-on stage, the voltage of the first power signal provided by the power management circuit to the light-emitting element and the voltage of the reset signal provided by the display driving circuit to the reset module are controlled, so that the absolute value of the difference between the voltage of the reset signal provided to the first pole of the light-emitting element of the display panel and the first power signal provided to the second pole of the light-emitting element of the display panel is smaller than the start-up voltage of the light-emitting element, so that the light-emitting element cannot emit light during the power-on stage, ensuring that the display brightness of the light-emitting element is 0 grayscale, thereby avoiding the screen flickering problem that occurs in the display device during the power-on stage, and further facilitating improving the display effect of the display device.

[0045] Based on the above embodiment, optionally, continue to refer to Figure 1 , Figure 2 , Figure 4 and Figure 5, the operation process of the display device 200 further includes a display stage. In the display stage, the difference between the voltage of the reset signal Vref2 and the voltage of the first power supply signal (PVEE or PVDD) is ΔVa; |ΔVa| < V0. In this way, by making the absolute value of the difference ΔVa between the voltage of the reset signal Vref2 and the voltage of the first power supply signal in the display stage less than the turn-on voltage V0 of the light-emitting element 112, it is ensured that the light-emitting element 112 can be normally reset, preventing the signal provided to the first pole of the light-emitting element 112 in the previous display driving cycle from affecting the light-emitting accuracy of the light-emitting element 112 in the next light-emitting stage, improving the display reliability of the display device 200 in the display stage, and improving the display effect of the display device 200.

[0046] It can be understood that in the display stage, the absolute value of the difference |ΔVa| between the voltage of the reset signal Vref2 and the voltage of the first power supply signal (PVEE or PVDD) is less than the turn-on voltage V0 of the light-emitting element 112. In the power-on stage, the absolute value of the difference |ΔVb| between the voltage of the reset signal Vref2 and the voltage of the first power supply signal (PVEE or PVDD) is less than the turn-on voltage V0 of the light-emitting element 112. At this time, |ΔVa| and |ΔVb| can be the same or different, and the embodiments of the present invention do not make specific limitations on this.

[0047] In an optional embodiment, |ΔVb| ≤ |ΔVa|. In this way, by setting |ΔVb| in the power-on stage to be less than or equal to |ΔVa| in the display stage, the absolute value of the difference |ΔVa| between the voltage of the reset signal Vref2 and the voltage of the first power supply signal (PVEE or PVDD) is smaller in the power-on stage, ensuring that the light-emitting element 112 cannot emit light in the power-on stage, further preventing the display device 200 from flashing in the power-on stage, improving the display effect of the display device 200, and improving the user experience.

[0048] Optionally, referring to Figure 1 、 Figure 2 and Figure 4 , when the operation process of the display device 200 further includes a display stage, the display driving circuit 103 can also be used to provide the data signal Vdata of each pixel 110 respectively in the display stage. At this time, the pixel 110 further includes a driving module 11, and the driving module 11 is used to selectively provide a driving current to the light-emitting element 112 according to the data signal Vdata.

[0049] It can be understood that the light-emitting element 112 is usually a current-type driving element, that is, the light-emitting element 112 can only be driven to display light when the display driving signal provided to the light-emitting element 112 is a driving current; and the data signal Vdata provided by the display driving circuit 103 is usually a voltage signal. At this time, it is necessary to set a driving module 11 in the pixel circuit 111 of the pixel 110 so that the driving module 11 can convert the data signal Vdata into a driving current. When the driving current is provided to the light-emitting element 112, the light-emitting element 112 can display light according to the driving current, and generally, the greater the driving current, the higher the light-emitting brightness of the light-emitting element 112. In this way, by providing the data signal Vdata to each pixel 110 respectively, the display light brightness of each pixel 110 can be controlled respectively, so that the display panel 100 can display a colorful picture.

[0050] Among them, the driving module 11 can be connected in series with the light-emitting element 112 between the positive power signal PVDD and the negative power signal PVEE, so that when a conductive path is formed between the positive power signal PVDD and the negative power signal PVEE, the driving current generated by the driving module 11 can be transmitted to the light-emitting element 112 to drive the light-emitting element 112 to display light.

[0051] In addition, reference Figure 1 or Figure 4 , a plurality of first signal lines 21 and a plurality of second signal lines 22 may be provided in the display area 101 of the display panel 100, at least some of the pixels 110 in the same row may be electrically connected to the same first signal line 21, and at least some of the pixels 110 in the same column may be electrically connected to the same second signal line 22. The first signal line 21 may include a reset signal line 211 for transmitting a reset signal Vref2 and a first power signal line 212 for transmitting a first power signal, and the second signal line 22 may include a data signal line 221 for transmitting a data signal Vdata and a second power signal line 222 for transmitting a second power signal; in this way, the first power signal and the reset signal Vref2 may be provided to each pixel 110, and the second power signal and the data signal may be provided to each pixel 110, respectively. Wherein, when the first power signal is a positive power signal PVDD, the second power signal may be a negative power signal PVEE, and when the first power signal is a negative power signal PVEE, the second power signal may be a positive power signal PVDD.

[0052] It should be noted that Figure 1 and Figure 4It is only shown by way of example that the first signal line includes the first power signal line and the second signal line includes the second power signal line. In other optional embodiments, the first signal line may include the second power signal line and the second signal line may include the first power signal line. Alternatively, the first signal line may include both the first power signal line and the second power signal line. Alternatively, the second signal line may include both the first power signal line and the second power signal line.

[0053] In addition, since the first pole of the light-emitting element of each pixel receives the first power signal, the first pole of the light-emitting element of each pixel receives the same signal, and the first pole of the light-emitting element of each pixel can be an integrated structure. At this time, the first power signal line can be set in the non-display area of ​​the display panel, and is electrically connected to the first pole of the light-emitting element extending to the non-display area through a via hole in the non-display area, so that the light-emitting element of each pixel can receive the first power signal transmitted by the first power signal line located in the non-display area. The arrangement of each signal line in the display panel can be specifically arranged according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0054] Optional, continue to refer to Figure 1 , Figure 2 and Figure 4 The pixel 110 may further include a data writing module 12. In the same pixel 110, the data writing module 12 can control the data signal provided by the display driving circuit 103 to be written into the driving module 11. The data writing module 12 can be turned on or off under the control of the scanning signal SP, and when the data writing module 12 is turned on, the data signal Vdata can be transmitted to the driving module 11 through the data writing module 12, thereby realizing the writing of the data signal Vdata.

[0055] Optional, reference Figure 2 or Figure 4, the pixel 110 may further include a compensation module 13, an initialization module 14 and a light emitting control module 16. The driving module 11 may include a driving transistor M1. At this time, the data signal Vdata transmitted by the control data writing module 12 is written to the gate of the driving transistor M1, so that the driving transistor M1 can generate a corresponding driving current according to its gate signal, and selectively provide it to the light emitting element 112 to control the light emitting element 112 to emit light; the compensation module 13 compensates the threshold voltage of the driving transistor M1 to the gate of the driving transistor M1, so that the driving current generated by the driving transistor M1 according to its gate signal can be independent of the threshold voltage of the driving transistor M1, and prevents the accuracy of the driving current generated by the driving transistor M1 from being affected by the threshold voltage drift of the driving transistor M1; the initialization module 14 can initialize the gate of the driving transistor M1 to prepare for the writing of the data signal Vdata; the light emitting control module 16 can control the time of providing the driving current to the light emitting element 112 to control the light emitting time of the light emitting element 112.

[0056] Among them, the data writing module 12 may include a writing transistor M2, a first electrode of the writing transistor M2 is electrically connected to the first electrode of the driving transistor M1, a second electrode of the writing transistor M2 can receive a data signal Vdata, a gate of the writing transistor M2 can receive a scanning signal SP, and the scanning signal SP can control the writing transistor M2 to be turned on or off, so that the data signal Vdata can be written to the driving module 11 when the writing transistor M2 is in the on state.

[0057] The compensation module 13 may include a compensation transistor M3, a first electrode of the compensation transistor M3 may be electrically connected to the gate of the driving transistor M1, a second electrode of the compensation transistor M3 may be electrically connected to the second electrode of the driving transistor M1, and the gate of the compensation transistor M3 may receive a scanning signal S-N2, and the scanning signal S-N2 may control the on or off of the compensation transistor M3, so that when the compensation transistor M3 is in the on state, the data signal Vdata may be controlled to be transmitted to the gate of the driving transistor M1, and the threshold voltage of the driving transistor M1 may be compensated to the gate of the driving transistor M1.

[0058] The initialization module 14 may include an initialization transistor M4, a first electrode of the initialization transistor M4 is electrically connected to the gate of the driving transistor M1, a second electrode of the initialization transistor M4 receives an initialization signal Vref1, and the gate of the initialization transistor M4 receives a scanning signal S-N1. The scanning signal S-N1 can control the conduction or closing of the initialization transistor M4, so that the initialization signal Vref1 can be provided to the gate of the driving transistor M1 when the initialization transistor M4 is in the on state.

[0059] The light-emitting control module 16 may include a first light-emitting control transistor M6 and a second light-emitting control transistor M7, the gate of the first light-emitting control transistor M6 and the gate of the second light-emitting control transistor M7 both receive a light-emitting control signal Emit, a first electrode of the first light-emitting control transistor M6 receives a second power supply signal, and a second electrode of the first light-emitting control transistor M6 is electrically connected to a first electrode of the driving transistor M1. A first electrode of the second light-emitting control transistor M7 is electrically connected to a second electrode of the driving transistor M1, and a second electrode of the second light-emitting control transistor M7 is electrically connected to a first electrode of the light-emitting element 112. In this way, the light-emitting control signal Emit can control the first light-emitting control transistor M6 and the second light-emitting control transistor M7 to be turned on or off at the same time.

[0060] The reset module 15 may include a reset transistor M5, a first electrode of the reset transistor M5 may receive a reset signal Vref2, a second electrode of the reset transistor M5 is electrically connected to a first electrode of the light emitting element 112, and a gate of the reset transistor M5 may receive a scan signal SP. The reset transistor M5 may be turned on or off under the control of the scan signal SP, so that when the scan signal SP controls the reset transistor M5 to be turned on, the reset signal Vref2 may be transmitted to the first electrode of the light emitting element 112 to reset the first electrode of the light emitting element 112.

[0061] The pixel circuit 111 further includes a storage capacitor, which is electrically connected between the fixed power signal and the gate of the driving transistor M1, and is used to store the gate potential of the driving transistor M1, so as to ensure that the driving transistor M1 can continuously provide a driving current to the light-emitting element 112 during the light-emitting stage. The fixed power signal can reuse the first power signal or the second power signal, and can be designed according to actual needs, which is not specifically limited in the embodiment of the present invention.

[0062] It can be understood that each transistor in the pixel circuit 111 can be an NMOS transistor or a PMOS transistor, and can be specifically designed according to actual needs, and the embodiment of the present invention does not specifically limit this. For an NMOS transistor, it is turned on when the signal received by its gate is a high level, and is turned off when it is a low level; for an NMOS transistor, it is turned on when the signal received by its gate is a low level, and is turned off when it is a high level. For the convenience of description, without special limitations, the embodiments of the present invention take the driving transistor M1, the writing transistor M2, the reset transistor M5, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 as PMOS transistors, and the initialization transistor M4 and the compensation transistor M3 as NMOS transistors as an example to exemplify the technical solution of the embodiment of the present invention.

[0063] In an exemplary embodiment, taking the first power signal as a negative power signal PVEE and the second power signal as a positive power signal PVDD as an example, Figure 6 is a schematic diagram of a driving timing sequence of a pixel in a display device provided by an embodiment of the present invention, combined with reference Figure 2 and Figure 6 The power-on phase Tb of the pixel 110 may include a power-on non-luminous phase Tb1 and a power-on luminous phase Tb2, and the display phase Ta of the pixel 110 may include a display non-luminous phase Ta1 and a display luminous phase Ta2.

[0064] In the power-on stage Tb and the display stage Ta, the display driving circuit 103 can control the signals (scan signal SP, scan signal SN and light-emitting control signal Emit), the reset signal Vref2, the initialization signal Vref1, and the data signal Vdata received by the gate of each transistor in the pixel circuit 111, and the power management circuit 104 can provide the second power signal PVDD to the pixel circuit 111 and provide the first power signal PVEE to the light-emitting element 112.

[0065] When entering the first non-luminous stage Tb11 of the power-on non-luminous stage Tb1 in the power-on stage Tb, the display driving circuit 103 can control the first luminous control transistor M6 and the second luminous control transistor M7 in the pixel circuit 111 to receive the high-level luminous control signal Emit, the write transistor M2 and the reset transistor M5 to receive the high-level scan signal SP, the compensation transistor M3 to receive the low-level scan signal S-N1, and the initialization transistor M4 to receive the high-level scan signal S-N2, so that the write transistor M2, the reset transistor M5, the compensation transistor M3, and the first luminous control transistor M6 and the second luminous control transistor M7 are all in the off state, the initialization transistor M4 is in the on state, and the initialization signal Vref1 provided by the display driving circuit 103 can be written to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1; when entering the second non-luminous stage Tb12 of the power-on non-luminous stage Tb1 in the power-on stage Tb, the display driving circuit 103 can control the pixel circuit 111 to receive the high-level luminous control signal Emit, the write transistor M2 and the reset transistor M5 to receive the high-level scan signal SP, the compensation transistor M3 to receive the low-level scan signal S-N1, and the initialization transistor M4 to receive the high-level scan signal S-N2, so that the write transistor M2, the reset transistor M5, the compensation transistor M3, and the first luminous control transistor M6 and the second luminous control transistor M7 are all in the off state, and the initialization transistor M4 is in the on state, and the initialization signal Vref1 provided by the display driving circuit 103 can be written to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1; The first light-emitting control transistor M6 and the second light-emitting control transistor M7 in the circuit 111 continue to receive the high-level light-emitting control signal Emit, the write transistor M2 and the reset transistor M5 receive the low-level scan signal SP, the compensation transistor M3 receives the high-level scan signal S-N1, and the initialization transistor M4 receives the low-level scan signal S-N2, so that the write transistor M2, the reset transistor M5 and the compensation transistor M3 are in the on state, the initialization transistor M4, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are all in the off state, the data signal Vdata corresponding to the 0 gray scale can be written to the gate of the driving transistor M1, and the threshold voltage of the driving transistor M1 is compensated to the gate of the driving transistor M1, and at the same time, the reset signal Vref2 can be written to the first electrode of the light-emitting element 112. Since the absolute value of the difference between the reset signal Vref2 and the first power signal PVEE is less than the start-up voltage V0 of the light-emitting element 112 at this time, the light-emitting element 112 cannot emit light;When entering the power-on light-emitting stage Tb2 of the power-on stage Tb, the display driving circuit 103 can control the first light-emitting control transistor M6 and the second light-emitting control transistor M7 in the pixel circuit 111 to receive the low-level light-emitting control signal Emit, the write transistor M2 and the reset transistor M5 to receive the high-level scan signal SP, the compensation transistor M3 to receive the low-level scan signal S-N1, and the initialization transistor M4 to receive the low-level scan signal S-N2, so that the write transistor M2, the reset transistor M5, the compensation transistor M3, and the initialization transistor M4 are all in the off state, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are in the on state, and a current path is formed between the first power signal PVEE and the second power signal PVDD. The driving transistor M1 can provide a driving current corresponding to 0 grayscale to the light-emitting element 112, so that the light-emitting element 112 displays a light-emitting brightness of 0 grayscale, and the display panel 100 displays a black screen. ;

[0066] It can be understood that when the driving transistor M1 is a PMOS type transistor, the data signal Vdata corresponding to 0 gray scale has a higher voltage than the voltages of the data signal Vdata corresponding to other gray scales, so that during the power-on stage, the voltage of the data signal Vdata will remain at a continuously high level; conversely, when the driving transistor M1 is an NMOS type transistor, the data signal Vdata corresponding to 0 gray scale has a lower voltage than the voltages of the data signal Vdata corresponding to other gray scales, so that during the power-on stage, the voltage of the data signal Vdata will remain at a continuously low level.

[0067] Correspondingly, when entering the first non-luminous stage Ta11 of the non-luminous stage Ta1 in the display stage Ta, the display driving circuit 103 can control the first luminous control transistor M6 and the second luminous control transistor M7 in the pixel circuit 111 to receive the high-level luminous control signal Emit, the write transistor M2 and the reset transistor M5 to receive the high-level scan signal SP, the compensation transistor M3 to receive the low-level scan signal S-N2, and the initialization transistor M4 to receive the high-level scan signal S-N1, so that the write transistor M2, the reset transistor M5, the compensation transistor M3, and the first luminous control transistor M6 and the second luminous control transistor M7 are all in the off state, the initialization transistor M4 is in the on state, and the initialization signal Vref1 provided by the display driving circuit 103 can be written to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1; when entering the second non-luminous stage Ta12 of the non-luminous stage Ta1 in the display stage Ta, the display driving circuit 103 can control the pixel circuit 111 to receive the high-level luminous control signal Emit, the write transistor M2 and the reset transistor M5 to receive the high-level scan signal SP, the compensation transistor M3 to receive the low-level scan signal S-N2, and the initialization transistor M4 to receive the high-level scan signal S-N1, so that the write transistor M2, the reset transistor M5, the compensation transistor M3, and the first luminous control transistor M6 and the second luminous control transistor M7 are all in the off state, and the initialization transistor M4 is in the on state. The initialization signal Vref1 provided by the display driving circuit 103 can be written to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1; The first light-emitting control transistor M6 and the second light-emitting control transistor M7 in the circuit 111 continue to receive the high-level light-emitting control signal Emit, the write transistor M2 and the reset transistor M5 receive the low-level scanning signal SP, the compensation transistor M3 receives the high-level scanning signal S-N1, and the initialization transistor M4 receives the low-level scanning signal S-N2, so that the write transistor M2, the reset transistor M5 and the compensation transistor M3 are in the on state, the initialization transistor M4, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are all in the off state, and the data signal Vdata corresponding to the gray scale required to be presented by the pixel can be written to the gate of the driving transistor M1, and the threshold voltage of the driving transistor M1 is compensated to the gate of the driving transistor M1. At the same time, the reset signal Vref2 can be written to the first electrode of the light-emitting element 112. Since the absolute value of the difference between the reset signal Vref2 and the first power signal PVEE is less than the start-up voltage V0 of the light-emitting element 112 at this time, the light-emitting element 112 cannot emit light;When entering the display light-emitting stage Ta2 of the display stage Ta, the display driving circuit 103 can control the first light-emitting control transistor M6 and the second light-emitting control transistor M7 in the pixel circuit 111 to receive the low-level light-emitting control signal Emit, the write transistor M2 and the reset transistor M5 to receive the high-level scanning signal SP, the compensation transistor M3 to receive the low-level scanning signal S-N1, and the initialization transistor M4 to receive the low-level scanning signal S-N2, so that the write transistor M2, the reset transistor M5, the compensation transistor M3, and the initialization transistor M4 are all in the off state, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are in the on state, and a current path is formed between the first power signal PVEE and the second power signal PVDD. The driving transistor M1 can provide the driving current corresponding to the grayscale required to be displayed by the pixel 110 to the light-emitting element 112, so that the light-emitting element 112 displays the light-emitting brightness of 0 grayscale, and the display panel 100 can display the corresponding picture. ;

[0068] In this way, in the power-on stage Tb and the display stage Ta, the display driving circuit 103 can maintain the same order of turning on or off each transistor in the pixel circuit 111 of the pixel 110, so that the signal can be written into the pixel 110 accordingly to achieve power-on and display control of the pixel 110.

[0069] It should be noted that the reset transistor M5 can be turned on or off under the control of the scan signal SP, and when the scan signal SP controls the reset transistor M5 to be turned on, the reset transistor M5 can transmit the reset signal Vref2 to the first electrode of the light-emitting element 112 to reset the light-emitting element 112. At this time, the on-time of the reset transistor M5 can overlap with the on-time of the write transistor M2, so as to shorten the time length of the non-light-emitting stage between two adjacent light-emitting stages, so that the light-emitting stage has a sufficient time length, and the display luminous brightness of the display panel 100 is guaranteed. In another optional embodiment, when the reset transistor M5 is of the same type as the initialization transistor M4, the scan signal received by the reset transistor M5 can also be consistent with the scan signal received by the initialization transistor M4, so that the on-time of the reset transistor M5 overlaps with the on-time of the initialization transistor M4, so as to shorten the time length of the non-light-emitting stage between two adjacent light-emitting stages, so that the light-emitting stage has a sufficient time length, and the display luminous brightness of the display panel 100 is guaranteed. In another optional embodiment, when the reset transistor M5 is of the same type as the initialization transistor M4, the scan signal received by the reset transistor M5 can also be consistent with the scan signal received by the initialization transistor M4, so that the on-time of the reset transistor M5 overlaps with the on-time of the initialization transistor M4, so as to shorten the time length of the non-light-emitting stage between two adjacent light-emitting stages, so that the light-emitting stage has a sufficient time length, and the display luminous brightness of the display panel 100 is guaranteed.

[0070] It should also be noted that the above is only an exemplary description of the structure and working process of the pixel. On the premise of being able to realize the core invention of the embodiment of the present invention, the structure and working process of the pixel can be simply deformed on the basis of the above embodiment, and the structure and working process after simple deformation all belong to the protection scope of the embodiment of the present invention and will not be described one by one here.

[0071] It can be understood that the above is only an illustrative description of the technical solution of the embodiment of the present invention. Under the premise that the absolute value of the voltage difference between the reset signal provided by the display driving circuit and the first power signal provided by the power management circuit is ensured to be less than the start-up voltage of the light-emitting element, the embodiment of the present invention does not specifically limit the setting method of the first power signal provided by the power management circuit and the reset signal provided by the display driving circuit during the power-on phase.

[0072] Optional, Figure 7 is a driving timing diagram of a display device provided by an embodiment of the present invention, Figure 8 is a driving timing diagram of another display device provided by an embodiment of the present invention, referring to Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 7 and Figure 8 As shown, when the working process of the display device also includes the display stage Ta, the power-on stage Tb may include a reset adjustment time period Tf; in the reset adjustment time period Tf, the voltage of the reset signal Vref2 is V11; in the display stage Ta, the voltage of the reset signal Vref2 is V12; wherein V11≠V12.

[0073] It can be understood that the voltage V11 of the reset signal Vref2 in the reset adjustment period Tf is different from the voltage V12 of the reset signal Vref2 in the display stage Ta, that is, the voltage V11 of the reset signal Vref2 in the reset adjustment period Tf can be greater than the voltage V12 of the reset signal Vref2 in the display stage Ta, or the voltage V11 of the reset signal Vref2 in the reset adjustment period Tf is less than the voltage V12 of the reset signal Vref2 in the display stage Ta, which can be specifically designed according to actual needs. Under the premise that the voltage difference between the reset signal provided to the first pole of the light-emitting element 112 and the first power signal (PVEE or PVDD) provided to the second pole of the light-emitting element 112 in the power-on stage Tb cannot control the light-emitting element 112 to display and emit light, the embodiment of the present invention does not make specific limitations on this.

[0074] Specifically, when the voltage V11 of the reset signal Vref2 in the reset adjustment time period Tf is different from the voltage V12 of the reset signal Vref2 in the display stage Ta, after entering the reset adjustment time period Tf of the power-on stage Tb, the display driving circuit 103 can adjust the voltage of the reset signal Vref2 it outputs, so that the absolute value of the voltage difference between the reset signal Vref2 outputted in at least the reset adjustment time period Tf and the first power supply signal (PVEE or PVDD) is smaller than the start-up voltage V0 of the light-emitting element 112, thereby ensuring that the light-emitting element 112 cannot emit light, avoiding screen flickering of the display device 200, and improving the display effect of the display device 200.

[0075] The specific values ​​of the voltage V12 of the reset signal Vref2 in the display stage Ta and the voltage V11 of the reset signal Vref2 in the reset adjustment period Tf can be set according to actual needs. Figure 1 , Figure 2 and Figure 7 As shown, taking the first pole of the light-emitting element 112 as its anode and the second pole of the light-emitting element 112 as its cathode as an example, the voltage V12 of the reset signal Vref2 in the display stage Ta can be -0.9V, and the voltage V11 of the reset signal Vref2 in the reset adjustment time period Tf can be -2.3V. At this time, the reset signal Vref2 provided by the display driving circuit 103 in the reset adjustment time period Tf will have a smaller voltage value, so that the first pole of the light-emitting element 112 can be further reset, so that the signal of the first pole of the light-emitting element 112 can have a smaller voltage, so that when the first power signal PVEE is an instantaneous negative pulse signal, it can also ensure that the difference between the voltage of the reset signal Vref2 provided to the first pole of the light-emitting element 112 and the voltage of the first power signal PVEE is less than the start-up voltage of the light-emitting element 112, ensuring that the light-emitting element 112 cannot emit light, and the display device 200 will not have a power-on flash screen, thereby improving the display effect of the display device 200.

[0076] It should be noted that the duration of the reset adjustment period Tf may be equal to the duration of the power-on phase Tb. Figure 7 or Figure 8 As shown, the voltage V11 of the reset signal Vref2 in the entire power-on stage Tb is different from the voltage V12 of the reset signal Vref2 in the display stage Ta; or Fig. 9 and Fig.10As shown, the duration of the reset adjustment period Tf can be shorter than the duration of the power-on stage Tb. Under the premise that the absolute value of the voltage difference between the reset signal Vref2 and the first power signal in the power-on stage Tb can be ensured to be less than the start-up voltage V0 of the light-emitting element 112, the embodiment of the present invention does not make any specific limitation on this. For the convenience of description, under the premise that there is no special limitation, the embodiment of the present invention takes the case that the duration of the reset adjustment period Tf is shorter than the duration of the power-on stage Ta as an example to exemplarily illustrate the technical solution of the embodiment of the present invention.

[0077] Optional, continue to refer to Figure 1 , Figure 2 , Figure 4 , Figure 5 , Fig. 9 and Fig.10 As shown, the reset adjustment time period Tf includes a first time period T1; in the first time period T1, the voltage of the first power signal (PVEE or PVDD) is V21; in the display stage Ta, the voltage of the first power signal (PVEE or PVDD) is V22; wherein V21≠V22.

[0078] Among them, since in the power-on stage Tb, the display driving circuit 103 provides the reset signal Vref2 to the reset module 15, and the reset module 15 can transmit the reset signal Vref2 to the first pole of the light-emitting element 112, so as to reset the first pole of the light-emitting element 112 in the power-on stage Tb; at the same time, in the display stage Ta, the display driving circuit 103 will also provide the reset signal Vref2 to the reset module 15, so as to control the reset module 15 to transmit the reset signal Vref2 to the first pole of the light-emitting element 112 in the reset sub-stage of a display driving cycle, so as to clear the signal at the first pole of the light-emitting element 112, so as to prepare for the light-emitting element 112 to accurately emit light when entering the light-emitting sub-stage. Therefore, whether in the power-on stage Tb or in the reset sub-stage of the display stage Ta, the light-emitting element 112 does not need to emit light.

[0079] When the voltage V11 of the reset signal Vref2 provided by the display driving circuit 103 in the reset adjustment time period Tf of the power-on stage Tb is different from the voltage V12 of the reset signal Vref2 provided by the display driving circuit 103 in the display stage Ta, the power management circuit 104 can provide a first power signal with a voltage of V21 in at least the first time period T1 of the reset adjustment time period Tf, and provide a first power signal with a voltage of V22 in the display stage Ta, and V21 is different from V22, so that the absolute value of the difference between V21 and V11 is smaller than the start-up voltage V0 of the light-emitting element 112, and the absolute value of the difference between V22 and V12 is smaller than the start-up voltage V0 of the light-emitting element 112, ensuring that the light-emitting element 112 of the pixel 110 does not emit light in the reset sub-stage of the pixel 110 in the power-on stage Tb and the display stage Ta, thereby improving the display effect of the display device 200.

[0080] It can be understood that the first time period T1 can be any time period in which the voltage V21 of the first power signal output by the power management circuit 104 is different from the voltage V22 of the first power signal in the display stage Ta. In an exemplary embodiment, Fig. 9As shown, the first time period T1 can be a time period when the power management circuit 104 starts to output the first power signal and instantaneous fluctuations occur, such as the stage when the first power signal is a negative pulse or a positive pulse. Taking the first power signal as a negative power signal PVEE as an example, at the starting moment of the first time period T1, the power management circuit 104 starts to output the first power signal PVEE, but because the devices in the power management circuit 104 are unstable at this time or are interfered by external signals, etc., the first power signal PVEE output by the power management circuit 104 will have an instantaneous spike, for example, the first power signal PVEE will drop to -4.0V instantaneously; thereafter, the first power signal PVEE will gradually change from the instantaneous spike until the end moment of the first time period T1, and the first power signal PVEE can be restored to a normal voltage, which can be understood as the voltage V22 of the first power signal PVEE that needs to be provided in the display stage Ta. For example, V22 can be -1.6V. In this way, since the first power signal PVEE varies between an instantaneous peak and a normal voltage in the first time period T1, the voltage V21 of the first power signal PVEE provided by the power management circuit 104 in the first time period T1 is different from the voltage V22 of the first power signal PVEE provided in the display stage Ta. At this time, by adaptively adjusting the voltage V11 of the reset signal Vref2 provided by the display driving circuit 103 in the first time period T1, the voltage V11 of the reset signal Vref2 can be different from the voltage of the reset signal Vref2 provided in the display stage Ta, so as to ensure that the light-emitting element 112 does not emit light in the power-on stage Tb. Exemplarily, taking the case where the first pole of the light-emitting element 112 is an anode, the second pole is a cathode, and the start-up voltage V0 of the light-emitting element 112 is 2V, the voltage V11 of the reset signal Vref2 in the reset adjustment time period Tf may be -2.3V, and the voltage difference between the voltage V11 of the reset signal Vref2 and the minimum value (-4.0V) of the voltage V21 of the first power signal PVEE in the first time period T1 is 1.7V, which is less than the start-up voltage V0 (2V) of the light-emitting element 112, thereby making the light-emitting element 112 unable to emit light; in the display stage Ta, the voltage V12 of the reset signal Vref2 may be -0.9V, and the voltage V22 of the first power signal PVEE may be -1.6, and the difference between the two is 0.7V, which is still less than the start-up voltage V0 of the light-emitting element 112, so that when the reset module 15 is turned on and the reset signal Vref2 is provided to the first pole of the light-emitting element 112, the light-emitting element 112 still cannot emit light.

[0081] It should be noted that the above only exemplarily illustrates the relationship between the reset signal Vref2 and the first power supply signal PVEE when the first power supply signal is a negative power supply signal PVEE, that is, when V21 < V22, V11 < V12, so that the reset signal Vref2 can increase as the voltage of the first power supply signal PVEE increases, ensuring that the difference between the two is less than the turn-on voltage of the light-emitting element 112. In the embodiments of the present invention, as Fig.10 shown, the first power supply signal can also be a positive power supply signal PVDD. At this time, the instantaneous spike of the first power supply signal PVDD can be a relatively high positive voltage, and after the instantaneous spike, the first power supply signal PVDD can slowly drop to the normal voltage. At this time, in the reset adjustment stage Tf, the voltage V11 of the reset signal Vref2 can also be a relatively large voltage, and in the display stage Ta, the reset signal Vref2 can be a relatively small voltage V12, that is, when V21 > V22, V11 > V12, so that the voltage of the reset signal Vref2 decreases as the voltage of the first power supply signal PVDD decreases, ensuring that the difference between the two is less than the turn-on voltage of the light-emitting element 112. Or, in other alternative embodiments, the change trends of V11 and V12 can also be opposite to the change trends of V21 and V22. On the premise that the absolute value of the voltage difference between the reset signal Vref2 and the first power supply signal PVDD can be ensured to be less than the turn-on voltage of the light-emitting element 112, the embodiments of the present invention do not make specific limitations on this.

[0082] In addition, optionally, when V21 > V22 and V11 > V12, the voltage change trends of the first power supply signal in the first time period T1 and the first power supply signal in the display stage Ta are the same as the voltage change trends of the reset signal Vref2 in the reset adjustment stage Tf and the reset signal Vref2 in the display stage Ta. Thus, on the premise of ensuring that the light-emitting element 112 cannot emit light in the power-on stage Tb, it can be made that compared with the first time period T1, the voltages of the reset signal Vref2 and the first power supply signal in the display stage Ta are more inclined to 0V, which is beneficial to reducing the overall power consumption of the display device 200. Or, when V21 < V22 and V11 < V12, it can also be made that the voltages of the reset signal Vref2 and the first power supply signal in the display stage Ta are more inclined to 0V, which is beneficial to reducing the overall power consumption of the display device 200.

[0083] It should also be noted that since the reset adjustment time period Tf includes the first time period T1, the duration of the first time period T1 can be equal to the duration of the reset adjustment time period Tf, or the duration of the first time period T1 is less than the duration of the reset adjustment time period Tf, which can be set according to actual needs.

[0084] In an alternative embodiment, Fig.11is a driving timing diagram of a display device provided by an embodiment of the present invention, Fig.12 is a driving timing diagram of another display device provided by an embodiment of the present invention, referring to Fig.11 and Fig.12 As shown, the reset adjustment time period Tf also includes at least one second time period T2; in the second time period T2, the voltage of the first power supply signal is V23; wherein V21≠V23.

[0085] Specifically, Fig.11 As shown, when the first power signal is a negative power signal PVEE, there is an instantaneous peak negative voltage in the first power signal PVEE in the first time period T1, so that the voltage of the first power signal PVEE in the first time period T1 is smaller than the voltage of the first power signal PVEE in other time periods. For example, the voltage V23 of the first power signal PVEE in the second time period T2 can be greater than the voltage V21 of the first power signal PVEE in the first time period T1; at the same time, since the voltage of the reset signal Vref2 in the reset adjustment stage Tf is V11, and the reset adjustment stage Tf includes the first time period T1 and the second time period T2, so that the voltage of the reset signal Vref2 in the first time period T1 and the voltage of the reset signal Vref2 in the second time period T2 are both V11. Therefore, under the premise that the difference between the voltage V11 of the reset signal Vref2 and the voltage V21 of the first power signal PVEE in the first time period T1 is less than the start-up voltage V0 of the light-emitting element 112, in the second time period T2, the difference between the voltage V11 of the reset signal Vref2 and the voltage V23 of the first power signal PVEE is also less than the start-up voltage V0 of the light-emitting element 112, thereby preventing the light-emitting element 112 from emitting light in the power-on stage Tb. In this way, by ensuring that the light-emitting element 112 cannot emit light in the reset adjustment time period Tf, the screen flickering phenomenon of the display device 200 in the power-on stage is avoided, and the display effect of the display device 200 is improved.

[0086] In addition, when the reset adjustment time period Tf includes the second time period T2, the duration of the peak mutation of the first power signal PVEE is shorter than the duration of the reset adjustment time period Tf, so that the first time period T1 in which the first power signal PVEE undergoes a peak mutation and the second time period T2 before and / or after the mutation are both located within the reset adjustment time period Tf in which the reset signal Vref2 has a smaller voltage, so as to ensure that the voltage difference between the reset signal Vref2 and the first power signal PVEE can be smaller than the start-up voltage V0 of the light-emitting element 112, so that the light-emitting element 112 cannot emit light during the power-on stage, and the display device 200 will not flicker, thereby improving the display effect of the display device 200.

[0087] It should be noted that the above only exemplarily illustrates the technical solution of the embodiment of the present invention by taking the first power signal as a negative power signal PVEE as an example. In the embodiment of the present invention, when the first power signal is a positive power signal PVDD (such as Fig.12 As shown in the figure, the technical effect similar to that when the first power signal is a negative power signal can be achieved. The similarities can be referred to the above description and are not specifically limited here.

[0088] In addition, the reset adjustment phase Tf may include a second time period T2, and the second time period T2 is located after the first time period T1 (eg Fig.11 and Fig.12 Alternatively, the second time period T2 may be located before the first time period T1 (as shown in Fig.13 and Fig.14 Alternatively, the reset adjustment phase Tf may include two second time periods, wherein one second time period T2 may be located before the first time period T1, and the other second time period T2 may be located after the first time period T1 (as shown in FIG. Fig.15 and Fig.16 The number of second time periods T2 and the relative relationship between the second time period T2 and the first time period T1 can be set according to actual needs and are not specifically limited here.

[0089] In an optional embodiment, continue to refer to Fig.11 or Fig.12 , the second time period T2 can be located after the first time period T1. In this way, at the start time of the first time period T1, the power management circuit can provide the first power signal PVEE while the display driving circuit can provide the reset signal Vref2 with a voltage of V11; at the end time period of the first time period T1 and the start time period of the second time period T2, after the first power signal PVEE jumps from the voltage V21 to V23, the voltage of the reset signal Vref2 can still be maintained at V11, so as to ensure that in the entire reset adjustment time period Tf, the absolute value of the voltage difference between the reset signal Vref2 and the first power signal PVEE can be maintained at a state less than the start voltage V0 of the light-emitting element 112, thereby ensuring that the light-emitting element 112 does not emit light, thereby improving the display effect of the display device 200.

[0090] In an optional embodiment, if Fig.11 and Fig.12As shown, when the second time period T2 is after the first time period T1, V22 = V23. In this way, within the second time period T2, the voltage V23 of the first power signal can be the same as the voltage V22 of the first power signal during the display stage Ta, so that after the power management circuit provides the voltage V23 of the first power signal within the second time period T2, the power management circuit does not need to readjust the voltage of the first power signal after entering the display stage Ta, improving the signal stability of the first power signal from the power-on stage Tb to the display stage Ta, and saving the power consumption generated by charging or discharging the signal lines in the display panel 100 due to adjusting the voltage of the first power signal. While improving the display effect of the display device 200 during the display stage, the power consumption of the display device 200 can be reduced.

[0091] In another alternative embodiment, as Fig.13 and Fig.14 shown, the second time period T2 can also be before the first time period T1. In this way, within the second time period T2, the power management circuit has not started to output the first power signal PVEE, so that the terminal for outputting the first power signal PVEE in the power management circuit can be in a floating state, or output a voltage signal of 0V, and the voltage of the reset signal Vref2 output by the display driving circuit has been adjusted to V11, and within the entire reset adjustment time period Tf, the voltage of the reset signal Vref2 will continuously remain at V11. Thus, when the second time period T2 ends and enters the first time period T1, the power management circuit starts to provide the first power signal PVEE, and when an instantaneous spike appears in the first power signal PVEE, it can be ensured that the absolute value of the voltage difference between the reset signal Vref2 and the first power signal PVEE is less than the turn-on voltage V0 of the light-emitting element 112, thereby ensuring that the light-emitting element does not emit light and improving the display effect of the display device 200.

[0092] Optionally, continue to refer to Fig.13 and Fig.14 When the second time period T2 is before the first time period T1, the relationship between the voltage V23 of the first power signal within the second time period T2, the voltage V21 of the first power signal within the first time period T1, and the voltage V22 of the first power signal during the display stage Ta can be set as: V23 < V22 < V21, or V21 < V22 < V23.

[0093] Exemplarily, as Fig.13As shown, taking the first pole of the light emitting element 112 as an anode, the second pole of the light emitting element 112 as a cathode, and the first power signal provided by the power management circuit 104 as a negative power signal PVEE as an example, when the display device 200 is not started, for example, when the display device 200 is in a shutdown state, each signal terminal of the display driving circuit 103 and each signal terminal of the power management circuit 104 can be suspended or output a 0V voltage, so that the power consumption of the display device 200 is 0 or has a lower power consumption. When the display device 200 needs to be started, the display device 200 enters the power-on stage, and each signal terminal of the display driving circuit 103 and each signal terminal of the power management circuit 104 start to output signals or start to output signals with a voltage not equal to 0V. Among them, when entering the second time period T2 of the power-on stage Tb, the voltage at the signal end of the power management circuit 104 for outputting the first power signal PVEE can be the same as the voltage when the display device 200 is not started, that is, the voltage V23 of the first power signal PVEE output by the power management circuit 104 can be 0V. At this time, the signal at the signal end of the display driving circuit 103 for outputting the reset signal Vref2 has changed from 0V to a more negative voltage, that is, the display driving circuit 103 outputs the reset signal Vref2 with a voltage of V11, so as to prepare for entering the first time period T1; in the first time period T1, the power management circuit starts to output the negative first power signal PVEE. At this time, due to the instantaneous peak of the first power signal PVEE, the voltage V21 of the first power signal PVEE in the first time period T1 is is a smaller value, the voltage V21 of the first power signal PVEE is less than the voltage V22 of the first power signal PVEE in the display stage Ta. At this time, the display driving circuit 103 continues to output the reset signal Vref2 with a voltage of V11 to ensure that within this time period, the voltage V11 of the reset signal Vref2 is small enough to ensure that the light-emitting element 112 cannot emit light; and within the first time period T1, the instantaneous negative peak of the first power signal PVEE gradually rises to the voltage of a normal negative power signal to prepare for the display stage Ta; after entering the display stage Ta, the first power signal PVEE provided by the power management circuit 104 remains as a normal negative power signal, that is, the voltage V22 of the first power signal PVEE in the display stage Ta is less than the voltage V23 of the first power signal PVEE in the second time period T2. In this way, by adjusting the voltage of the reset signal Vref2 to V11 before the power management circuit 104 outputs the first power signal PVEE with a negative peak, it can ensure that the light-emitting element 112 cannot emit light during the entire power-on stage Tb, thereby improving the display effect of the display device 200 in the power-on stage Tb.

[0094] In another exemplary embodiment, Fig.14As shown, taking the first pole of the light emitting element 112 as the cathode, the second pole of the light emitting element 112 as the anode, and the first power signal provided by the power management circuit 104 as the positive power signal PVDD as an example, when the display device 200 is not started, for example, when the display device 200 is in the off state, each signal terminal of the display driving circuit 103 and each signal terminal of the power management circuit 104 can be suspended or output 0V voltage, so that the power consumption of the display device 200 is 0 or has a lower power consumption. When the display device 200 needs to be started, the display device 200 enters the power-on stage, and each signal terminal of the display driving circuit 103 and each signal terminal of the power management circuit 104 start to output signals or start to output signals with a voltage not equal to 0V. In the second time period T2 of the power-on phase Tb, the voltage at the signal end of the power management circuit 104 for outputting the first power signal PVDD may be the same as the voltage when the display device 200 is not started, that is, the voltage V23 of the first power signal PVDD output by the power management circuit 104 may be 0V. At this time, the signal at the signal end of the display driving circuit 103 for outputting the reset signal Vref2 has changed from 0V to a more positive voltage, that is, the display driving circuit 103 outputs the reset signal Vref2 with a voltage of V11, so as to prepare for entering the first time period T1. In the first time period T1, the power management circuit 104 starts to output the positive first power signal PVDD. At this time, due to the instantaneous peak of the first power signal PVDD, the voltage V 21 is a larger value, the voltage V21 of the first power signal PVDD is greater than the voltage V22 of the first power signal PVDD in the display stage Ta. At this time, the display driving circuit 103 continues to output the reset signal Vref2 with a voltage of V11 to ensure that the voltage V11 of the reset signal Vref2 is large enough in this time period to ensure that the light-emitting element 112 cannot emit light; and in the first time period T1, the instantaneous negative peak of the first power signal PVDD gradually decreases to the voltage of the normal positive power signal to prepare for the display stage Ta; after entering the display stage Ta, the first power signal PVDD provided by the power management circuit 104 remains as a normal positive power signal, that is, the voltage V22 of the first power signal PVDD in the display stage Ta is less than the voltage V23 of the first power signal PVDD in the second time period T2. In this way, by adjusting the voltage of the reset signal Vref2 to V11 before the power management circuit 104 outputs the first power signal PVDD with a positive peak, it can ensure that the light-emitting element 112 cannot emit light during the entire power-on stage Tb, thereby improving the display effect of the display device 200 in the power-on stage Tb.

[0095] In an alternative embodiment, reference Fig.15 and Fig.16, when at least one second time period T2 includes a first second time period T21 and a second second time period T22, the first second time period T21 may be located before the first time period T1, and the second second time period T22 may be located after the first time period T1. In this way, before and after the first time period T1 in which the first power signal has a spike mutation, the voltage of the reset signal Vref2 can be controlled to be V11, so that the absolute value of the difference between the voltage of the reset signal Vref2 and the voltage of the first power signal is less than the turn-on voltage V0 of the light-emitting element 112, ensuring that the light-emitting element 112 does not emit light during the reset adjustment time period Tf, and improving the display effect of the display device 200 during the power-on stage Tb.

[0096] Optionally, during the first second time period T21, the voltage of the first power signal is V231; during the second second time period T22, the voltage of the first power signal is V232. Wherein, V232 = V22, V21 < V232 < V231, or V231 < V232 < V21.

[0097] Exemplarily, referring to Fig.15, when the first electrode of the light-emitting element 112 is the anode and the second electrode of the light-emitting element 112 is the cathode, and the first power signal provided by the power management circuit 104 to the cathode of the light-emitting element 112 is the negative power signal PVEE, the voltage V21 of the first power signal PVEE in the first time period T1 can be less than the voltage V232 of the first power signal PVEE in the second second time period T22, and the voltage V232 of the first power signal PVEE in the second second time period T22 is less than the voltage V231 of the first power signal PVEE in the first second time period T21. On the premise that the absolute value of the voltage difference between the voltage V11 of the reset signal Vref2 and the voltage V21 in the first time period T1 is less than the turn-on voltage V0 of the light-emitting element 112, the voltage V231 of the first power signal PVEE in the first second time period T21 is greater than the voltage V21 of the first power signal PVEE in the first time T1, so as to ensure that the absolute value of the voltage difference between the voltage V11 of the reset signal Vref2 and the voltage V231 of the first power signal PVEE in the first second time period T2 is also less than the turn-on voltage V0 of the light-emitting element 112; the voltage V232 of the first power signal PVEE in the second second time period T22 is greater than the voltage V21 of the first power signal PVEE in the first time period T1, so as to ensure that the absolute value of the voltage difference between the voltage V11 of the reset signal Vref2 and the voltage V232 of the first power signal PVEE in the second second time period T22 is also less than the turn-on voltage V0 of the light-emitting element 112. Thus, by setting V21 < V232 < V231, it can be ensured that the light-emitting element 112 does not emit light during the entire reset adjustment time period Tf, so as to improve the display effect of the display device 200 in the power-on stage Tb. In addition, by setting the voltage V22 of the first power signal PVEE in the display stage Ta to be the same as the voltage V232 of the first power signal PVEE in the second second time period T22, during the process of entering the display stage Ta from the second second time period T22, the power management circuit 104 does not need to adjust the voltage of the first power signal, preventing the voltage adjustment from affecting the stability of the first power signal, and being able to avoid the additional power consumption caused by adjusting the voltage, thereby being beneficial to improving the signal stability of the first power signal from the power-on stage Tb to the display stage Ta, reducing the power consumption of the display device 200, and improving the display effect of the display device 200 in the display stage Ta.

[0098] In another exemplary embodiment, referring to Fig.16, when the first pole of the light-emitting element 112 is the cathode and the second pole of the light-emitting element 112 is the anode, and the first power supply signal provided by the power management circuit 104 to the anode of the light-emitting element 112 is the positive power supply signal PVDD, the voltage V231 of the first power supply signal PVDD in the first and second time periods T21 can be less than the voltage V232 of the first power supply signal PVDD in the second and second time periods T22, and the voltage V232 of the first power supply signal PVDD in the second and second time periods T22 is less than the voltage V21 of the first power supply signal PVDD in the first time period T1, so that on the premise that the absolute value of the voltage difference between the voltage V11 of the reset signal Vref2 and the voltage V21 in the first time period T1 is less than the turn-on voltage V0 of the light-emitting element 112, the voltage V232 of the first power supply signal PVDD in the second and second time periods T22 is less than the voltage V21 of the first power supply signal PVDD in the first time T1, so as to ensure that the absolute value of the voltage difference between the voltage V11 of the reset signal Vref2 and the voltage V232 of the first power supply signal PVDD in the second and second time periods T22 is also less than the turn-on voltage V0 of the light-emitting element 112; the voltage V231 of the first power supply signal PVDD in the first and second time periods T21 is less than the voltage V232 of the first power supply signal PVDD in the second and second time periods T21, so as to ensure that the absolute value of the voltage difference between the voltage V11 of the reset signal Vref2 and the voltage V232 of the first power supply signal PVDD in the first and second time periods T21 is also less than the turn-on voltage V0 of the light-emitting element 112. Thus, by setting V231 < V232 < V21, it can be ensured that the light-emitting element 112 does not emit light during the reset adjustment time period Tf, so as to improve the display effect of the display device 200 in the power-on stage Tb. In addition, by setting the voltage V22 of the first power supply signal PVDD in the display stage Ta to be the same as the voltage V232 of the first power supply signal PVDD in the second and second time periods T22, during the process of entering the display stage Ta from the second and second time periods T22, the power management circuit 104 does not need to adjust the voltage of the first power supply signal, preventing the voltage adjustment from affecting the stability of the first power supply signal, and being able to avoid the additional loss caused by the voltage adjustment, thereby being beneficial to improving the signal stability of the first power supply signal from the power-on stage Tb to the display stage Ta, reducing the power consumption of the display device 200, and improving the display effect of the display device 200 in the display stage Ta.

[0099] It should be noted that the above has respectively described the cases where the first power supply signal is the positive power supply signal PVDD and the negative power supply signal PVEE. In the embodiments of the present invention, the first power supply signal can be designed according to actual needs. For the convenience of description, without special limitation, the following takes the first power supply signal as the negative power supply signal PVEE as an example to exemplarily describe other technical solutions of the embodiments of the present invention.

[0100] Optional, Fig.17 is a driving timing diagram of another display device provided by an embodiment of the present invention, such as Fig.17 As shown, the display driving circuit 103 is further used to provide a display control signal DON, and control the start time and the end time of the reset adjustment period Tf according to the time when the display control signal DON is a valid pulse.

[0101] Among them, the display control signal DON is a sign that can control the display device 200 to display a signal, that is, it can be understood as a sign that controls the display device 200 to start entering the power-on stage Tb. In this way, when the display device 200 starts working, the display driving circuit 103 starts to output the valid pulse of the display control signal DON at the signal end for outputting the display control signal DON. At this time, the time of entering the power-on stage Tb can be determined according to the time when the display control signal DON jumps from a continuous invalid level to a valid pulse. After determining the time when the display device 200 enters the power-on stage Tb, the time when the power management circuit 104 starts to output the first power signal (PVDD or PVEE) can be estimated based on the time when the power management circuit 104 enters the power-on stage Tb. Based on this, when the power management circuit 104 starts to output the first power signal, or before outputting the first power signal, the display driving circuit 103 can output a reset signal Vref2 with a lower or higher voltage, so that the absolute value of the voltage difference between the reset signal Vref2 and the first power signal can be continuously smaller than the start-up voltage V0 of the light-emitting element 112. Thus, by making the display driving circuit 103 control the duration of the voltage of the reset signal Vref2 to be V11 according to the display control signal DON, the control reliability of the reset adjustment period Tf can be improved, thereby improving the display effect of the display device 200 in the reset adjustment period Tf.

[0102] Optional, Fig.18 is a schematic structural diagram of another display device provided by an embodiment of the present invention, Fig.19 is a driving timing diagram of another display device provided by an embodiment of the present invention, referring to Fig.18 and Fig.19 , the display driving circuit 103 is electrically connected to the power management circuit 104; the display driving circuit 103 is also used to provide a first control signal ES to the power management circuit 104, and control the start time and end time of the reset adjustment time period Tf according to the start time of the enable level of the first control signal ES; the power management circuit 104 is also used to control the output of the first power signal PVEE according to the first control signal ES.

[0103] When the display driving circuit 103 is electrically connected to the power management circuit 104, the display driving circuit 103 can provide the first control signal ES to the power management circuit 104. When the power management circuit 104 receives the enable level of the first control signal ES, it can start to output the first power signal PVE. Before receiving the enable level of the first control signal ES, the signal end of the power management circuit 104 outputting the first power signal PVEE can continuously output a 0V voltage. Therefore, based on the starting moment of the enable level of the first control signal ES, the time when the power management circuit 104 starts to output the first power signal PVEE can be determined. At this time, when the display driving circuit 103 provides the first control signal ES to the power management circuit 104, it can control the voltage at the signal end for outputting the reset signal Vref2 to change from 0V to V11, so that the absolute value of the voltage difference between the reset signal Vref2 output by the display driving circuit 103 and the first power signal PVEE output by the power management circuit 104 can be less than the start-up voltage V0 of the light-emitting element 112, ensuring that the light-emitting element 112 cannot emit light. In this way, the display driving circuit 103 controls the duration for the voltage of the reset signal Vref2 output by the display driving circuit 103 to become V11 according to the enable level time of the first control signal ES provided to the power management circuit 103, so as to accurately control the starting time when the voltage of the reset signal Vref2 becomes V11.

[0104] In an exemplary embodiment, the starting moment when the first control signal ES output by the display driving circuit 103 is at the enable level may be the moment when the power management circuit 104 starts to output the first power signal (PVEE or PVDD) of a non-0V voltage. At this time, the voltage of the reset signal Vref2 output by the display driving circuit 103 changes to V11 before the starting moment of the enable level of the first control signal ES, or, it may be the same moment as the starting moment of the enable level of the first control signal ES, that is, the starting moment of the reset adjustment time period Tf may be before the starting moment of the enable level of the first control signal ES, or, it may be the same moment as the starting moment of the enable level of the first control signal ES, so that the absolute value of the voltage difference between the voltage V11 of the reset signal Vref2 and the first power signal PVEE can be continuously smaller than the start-up voltage V0 of the light-emitting element 112, thereby ensuring that the light-emitting element 112 does not emit light during the power-on stage Tb, thereby improving the display effect of the display device 200.

[0105] It should be noted that the above description only exemplarily illustrates the starting moment when the display driving circuit 103 outputs the reset signal with a voltage of V11, and the starting moment when the power management circuit 104 starts to output the first power signal PVEE with a non-0V voltage, and the embodiments of the present invention are not limited to this. The moment when the voltage of the reset signal Vref2 output by the display driving circuit 103 becomes V11, and the starting moment when the power management circuit 104 outputs the first power signal PVE with a non-0V voltage can be designed according to actual needs, and the embodiments of the present invention do not make specific limitations on this.

[0106] It should also be noted that the above description is only illustrative of the reset signal Vref2 in which the display driving circuit 103 outputs a fixed voltage of V11 within the reset adjustment time period Tf. In the embodiment of the present invention, the voltage V11 of the reset signal Vref2 output by the display driving circuit 103 may also be a variable voltage, which may change with the change of the first power signal PVEE output by the power management circuit 104. The specific design may be based on actual needs, and the embodiment of the present invention does not specifically limit this.

[0107] Optional, reference Fig.18 and Fig. 20 When the display driving circuit 103 is electrically connected to the power management circuit 104, the display driving circuit 103 can also be used to receive the first power signal PVEE output by the power management circuit 104, and control the voltage of the reset signal Vref2 according to the first power signal PVEE. In this way, after entering the power-on stage Tb, the power management circuit 104 can normally provide the first power signal PVEE, and the display driving circuit 103 can adaptively adjust the voltage of the reset signal Vref2 outputted by it according to the first power signal PVEE received, thereby improving the control accuracy and reliability of the reset signal Vref2, and improving the display effect of the display device 200.

[0108] In an exemplary embodiment, after entering the power-on stage Tb, if the voltage of the first power signal provided by the power management circuit 104 is 0V, the display driving circuit 103 can output the reset signal Vref2 whose voltage is also 0V according to the first power signal, so as to ensure that the absolute value of the voltage difference between the first power signal and the reset signal during this period is less than the start-up voltage V0 of the light-emitting element 112. If the first power signal provided by the power management circuit 104 is a non-0V voltage that is more negative due to an instantaneous spike, the display driving circuit 103 can calculate the instantaneous spike voltage of the reset signal Vref2 corresponding to the start-up voltage V0 according to the negative voltage of the first power signal, and the display driving circuit 103 can output the reset signal Vref2 having the instantaneous spike voltage, so as to ensure that the light-emitting element 112 does not emit light during the spike jump phase of the first power signal. If the voltage of the first power signal provided by the power management circuit 104 is not 0V, the display driving circuit 103 can calculate the voltage setting voltage that makes the voltage difference between the first power signal and the reset signal Vref2 less than the start-up voltage V0 according to the voltage of the first power signal and the start-up voltage V0, and the display driving circuit 103 outputs the reset signal Vref2 with the set voltage to ensure that the light-emitting element 112 does not emit light. In this way, the display driving circuit 103 can adjust the voltage of the reset signal Vref2 in real time according to the voltage of the first power signal, so that the light-emitting element 112 does not emit light in the power-on stage Tb, so as to improve the display effect of the display device 200.

[0109] The display device provided by the embodiment of the present invention, in the power-on stage, controls the power management circuit to provide the voltage of the first power signal to the light-emitting element and the voltage of the reset signal provided by the display driving circuit to the reset module, so that the absolute value of the difference between the voltage of the reset signal provided to the first pole of the light-emitting element of the display panel and the first power signal provided to the second pole of the light-emitting element of the display panel is less than the start-up voltage of the light-emitting element, so that the light-emitting element cannot emit light in the power-on stage, ensuring that the display brightness of the light-emitting element is 0 grayscale, thereby avoiding the screen flickering problem that occurs in the display device in the power-on stage, and further facilitating improving the display effect of the display device.

[0110] For example, Fig.21 is a schematic diagram of the structure of another display device provided by an embodiment of the present invention, such as Fig.21 As shown, the display device 200 provided in the embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiment of the present invention does not make special limitations on this.

[0111] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display device, characterized in that: Comprising: A display panel, including a display area and at least partially a non-display area surrounding the display area; a plurality of pixels arranged in an array are provided in the display area; The pixel at least includes a reset module and a light-emitting element; the reset module is electrically connected to a first pole of the light-emitting element; A power management circuit, provided in the non-display area; The power management circuit is at least used to provide a first power signal to a second pole of the light-emitting element; A display driving circuit, provided in the non-display area; The display driving circuit is at least used to provide a reset signal to the reset module; Wherein, the working process of the display device at least includes a power-on stage; in the power-on stage, the difference between the voltage of the reset signal and the voltage of the first power signal is ΔVb; the turn-on voltage of the light-emitting element is V0; |ΔVb| < V0.

2. The display device according to claim 1, characterized in that The working process of the display device further includes a display stage; the power-on stage includes a reset adjustment time period; In the reset adjustment time period, the voltage of the reset signal is V11; In the display stage, the voltage of the reset signal is V12; Wherein, V11 ≠ V12.

3. The display device according to claim 2, characterized in that: The reset adjustment time period includes a first time period; In the first time period, the voltage of the first power signal is V21; In the display stage, the voltage of the first power signal is V22; Wherein, V21 ≠ V22.

4. The display device according to claim 3, characterized in that: The reset adjustment time period further includes at least one second time period; In the second time period, the voltage of the first power signal is V23; Wherein, V21 ≠ V23.

5. The display device according to claim 4, characterized in that: The second time period is located after the first time period.

6. The display device according to claim 5, characterized in that: V22 = V23.

7. The display device according to claim 4, characterized in that: The second time period is located before the first time period.

8. The display device according to claim 7, characterized in that: V23 < V22 < V21, or, V21 < V22 < V23.

9. The display device according to claim 4, characterized in that: At least one of the second time periods includes a first second time period and a second second time period; the first second time period is located before the first time period, and the second second time period is located after the first time period.

10. The display device according to claim 9, wherein In the first second time period, the voltage of the first power signal is V231; In the second second time period, the voltage of the first power signal is V232; Wherein, V232 = V22, V21 < V232 < V231, or, V231 < V232 < V21.

11. The display device according to claim 3, wherein When V21 > V22, V11 > V12; or, when V21 < V22, V11 < V12.

12. The display device according to claim 2, wherein The display driving circuit is further used to provide a display control signal, and control the start time and end time of the reset adjustment time period according to the time when the display control signal is an effective pulse.

13. The display device according to claim 2, characterized in that: The display driving circuit is electrically connected to the power management circuit; The display driving circuit is further used to provide a first control signal to the power management circuit, and control the start time and end time of the reset adjustment time period according to the start time of the enable level of the first control signal; The power management circuit is further configured to control the output of the first power signal according to the first control signal.

14. The display device according to claim 1, characterized in that The working process of the display device also includes a display stage; In the display stage, the difference between the voltage of the reset signal and the voltage of the first power supply signal is ΔVa; |ΔVa| <V0。 15. The display device according to claim 14, characterized in that: |ΔVb|≤|ΔVa|.

16. The display device according to claim 1, characterized in that: The display driving circuit is electrically connected to the power management circuit; The display driving circuit is further configured to receive a first power signal output by the power management circuit, and control the voltage of the reset signal according to the first power signal.

17. The display device according to claim 1, characterized in that: The working process of the display device also includes a display stage; The display driving circuit is also used to provide data signals for each pixel in the display stage; The pixel further includes a driving module; the driving module is used to selectively provide a driving current to the light emitting element according to the data signal.

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