Display device and driving method thereof

Abstract

The present disclosure relates to a display device and a driving method thereof, and belongs to the technical field of display. The display device comprises a display panel, a display driving chip and a power management integrated circuit. A first output end of the power management integrated circuit is electrically connected to a first voltage signal line in a frame area of the display panel through the display driving chip, and the first voltage signal line is electrically connected to a gate driving circuit. The power management integrated circuit comprises a comparison module and an adjusting module. A first comparison end of the comparison module is electrically connected to the first voltage signal line through a first connecting line, a second comparison end of the comparison module is electrically connected to the first output end of the power management integrated circuit, a feedback end of the comparison module is electrically connected to an input end of the adjusting module, and an output end of the adjusting module is electrically connected to the first output end of the power management integrated circuit. The driving method is used for driving the display device. The present disclosure can effectively improve the display problem of bright and dark horizontal lines of the display device under low gray scale display, and is beneficial to improve the display quality.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display device and its driving method. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are current-driven organic light-emitting devices. They are devices that emit light through carrier injection and recombination when organic semiconductor materials and light-emitting materials are driven by an electric field. Due to their excellent color saturation, contrast, and response speed, and because their materials are thinner, more transparent, and more flexible, enabling diverse designs, OLEDs have become a research hotspot in the display field.

[0003] As end-users increasingly demand higher display performance (such as refresh rate, resolution, and brightness), LTPO screen technology has emerged. LTPO (Low Temperature Polycrystalline Oxide) is a combination of the mainstream OLED screen technologies LTPS (Low Temperature Polycrystalline Silicon) and IGZO (Indium Gallium Zinc Oxide). LTPO screen technology can achieve a minimum refresh rate of 1Hz. Lower refresh rates result in lower power consumption, saving a significant amount of electricity.

[0004] However, in existing display devices using LTPO technology, regular bright and dark horizontal stripes are prone to appear when displaying at low brightness and low grayscale, which greatly affects the display quality.

[0005] Therefore, providing a display device and its driving method that can improve the display problem of horizontal stripes and enhance display quality is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] To address the aforementioned technical problems, this disclosure provides a display device and its driving method, which solves the problem that in existing display devices, regular bright and dark horizontal stripes easily appear when displaying at low brightness and low grayscale, resulting in the inability to effectively improve display quality.

[0007] This disclosure provides a display device, including a display panel, a display driver chip, and a power management integrated circuit; the display panel includes a bezel area, and the bezel area includes a gate driving circuit and a first voltage signal line;

[0008] The first output terminal of the power management integrated circuit is electrically connected to the input pin of the display driver chip, the output pin of the display driver chip is electrically connected to one end of the first voltage signal line, and the other end of the first voltage signal line is electrically connected to the first voltage signal terminal of the gate drive circuit.

[0009] The power management integrated circuit includes a comparator module and a regulator module; the first comparator terminal of the comparator module is electrically connected to the first voltage signal line via a first connection line, the second comparator terminal of the comparator module is electrically connected to the first output terminal of the power management integrated circuit, the feedback terminal of the comparator module is electrically connected to the input terminal of the regulator module, and the output terminal of the regulator module is electrically connected to the first output terminal of the power management integrated circuit.

[0010] Based on the same inventive concept, this disclosure also provides a driving method for a display device, which is used to drive the aforementioned display device; the driving method includes:

[0011] Within one frame display cycle of the display panel, the actual first voltage signal transmitted on the first voltage signal line is transmitted to the first comparison terminal of the comparison module of the power management integrated circuit through the first connection line. The second comparison terminal of the comparison module receives the preset first voltage signal output by the first output terminal of the power management integrated circuit. The comparison module compares the actual first voltage signal with the preset first voltage signal to obtain the error value.

[0012] The feedback terminal of the comparison module feeds back the error value to the input terminal of the adjustment module via electrical connection. The adjustment module then makes adjustments, and the output terminal of the adjustment module transmits the adjusted compensation first voltage signal to the first output terminal of the power management integrated circuit.

[0013] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0014] The display device disclosed herein electrically connects a first voltage signal line of the wiring in the bezel area of ​​the display panel to a first connecting line. A comparison module and an adjustment module are incorporated into the power management integrated circuit. The comparison module compares in real-time the real-time voltage on the first voltage signal line of the wiring in the bezel area of ​​the display panel with a preset voltage output from the first output terminal of the power management integrated circuit. In case of error, the adjustment module performs compensation, and the adjusted and compensated voltage is finally output to the display panel via the first output terminal of the power management integrated circuit. Even if the falling edge of the EM signal enters the porch area at different times and in different areas during the driving scanning display process, this disclosure ensures that the SPX signal coupling amount required by the pixel circuit of the display panel is a fixed voltage value. The display brightness of different areas of the display panel remains unaffected, effectively improving the display problem of bright and dark horizontal stripes in low grayscale displays and thus enhancing display quality. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of an electrical connection structure between the pixel circuit and the light-emitting element in a display device in the prior art;

[0018] Figure 2 yes Figure 1 Relevant timing diagrams;

[0019] Figure 3 yes Figure 1 and Figure 2 A diagram illustrating the horizontal stripe phenomenon on a display device;

[0020] Figure 4 This is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of another planar structure of the display device provided in an embodiment of the present invention;

[0022] Figure 6 This is a schematic diagram of another planar structure of the display device provided in an embodiment of the present invention;

[0023] Figure 7 This is a schematic diagram of another planar structure of the display device provided in an embodiment of the present invention;

[0024] Figure 8 This is a schematic diagram of another planar structure of the display device provided in an embodiment of the present invention;

[0025] Figure 9 yes Figure 8 A schematic diagram of an electrical connection structure between the pixel circuit and the light-emitting element;

[0026] Figure 10 yes Figure 8 A schematic diagram of another electrical connection structure between the middle pixel circuit and the light-emitting element;

[0027] Figure 11 This is a flowchart of the driving method for a display device provided in an embodiment of the present invention. Detailed Implementation

[0028] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0029] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0030] Please refer to the reference. Figures 1-3 , Figure 1 This is a schematic diagram of an electrical connection structure between the pixel circuit and the light-emitting element in a display device in the prior art. Figure 2 yes Figure 1 Relevant timing diagrams, Figure 3 yes Figure 1 and Figure 2 The diagram illustrates the horizontal stripe phenomenon on the display device. It is understandable that... Figure 1 The illustration shows a display device using LTPO technology in the prior art, including a display panel. The display panel typically includes pixel circuitry and an electrical connection structure between the pixel circuitry and the OLED light-emitting element. Figure 1 It is known that the pixel circuit includes 8 transistors (transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, and transistor T8) and 1 capacitor (capacitor Cst). Among them, transistors T4 and T5, which are electrically connected to the gate of transistor T3, are both N-type metal-oxide transistors, such as IGZO (indium gallium zinc oxide) transistors. The remaining transistors are P-type LTPS (low-temperature polycrystalline silicon) transistors. That is, transistors T4 and T5 conduct when their gate potential is high, while the gate potential of the remaining transistors is low. Figure 1 The potential of node N4 in the provided pixel circuit is the anode potential of the OLED light-emitting element, which determines the magnitude of the current flowing through the OLED light-emitting element. Figure 1 The transistor T8 in the provided pixel circuit is used to adjust the bias state of transistor T3. It should be noted that this disclosure does not elaborate on the connection structure and working principle of the pixel circuit described above; for details, please refer to the explanation of LTPO technology in related technologies for further understanding.

[0031] In this OLED display device employing LTPO technology, the gate control signals for transistors T4 and T5 are S2N and S1N, respectively. The switching level between S1N and S2N signals is VGH2 / VGL2 (VGH2 is the effective signal controlling the conduction of transistors T4 and T5). The gate control signals for the remaining transistors are EM, SP, and SPX, respectively. The switching level between EM, SP, and SPX signals is VGH1 / VGL1 (VGL1 is the effective signal controlling the conduction of transistors other than T4 and T5). The VGH1 and VGL1 levels, and VGH2 and VGL2 levels are generated and provided by the signal traces in the display panel bezel area via the gate on array (GOA). Since the EM, SP, and SPX signals required by the pixel circuits are all PMOS circuits, the gate on array is connected to the output pin of the driver chip, and the driver chip IC outputs a low-level VGL1 to the gate on array. The gate drive circuit signal is cascaded (since the gate drive circuit generally includes cascaded shift register circuits), so the signal input of each row of pixel circuits is fed in through the output of the previous stage. The signal input of the first stage is generated by the configuration of the driver chip IC. Therefore, it can be understood that the EM signal, SP signal and SPX signal required by the pixel circuit are also cascaded.

[0032] A display panel typically includes an active area and a porch area (this area is used for voltage conversion preparation; it can also be understood as a blanking area. In display technology, it refers to the area on the screen used for synchronization signal transmission, not the area used to display images. Generally, the active area is followed by the porch area. The porch area is a specific time period during which the display device does not display any valid image information but is used for the transmission and processing of synchronization signals to ensure the correct synchronization and stable operation of the display device). The porch area is fixed, so during display, different areas of the display panel will have corresponding EM signals falling on the porch area, resulting in the phenomenon of bright and dark horizontal stripes. Specifically, for example... Figure 2The timing diagram shown represents the porch region. EM(1) and EM(2) represent the timing of the EM signals in different regions as they are scanned sequentially. SPX(1) and SPX(2) represent the timing of the SPX signals in different regions as they are scanned sequentially. In region ②, the falling edge of the EM(2) signal is in the porch region. That is, the falling edge of the EM(2) signal in this region is inside the porch region. For the display area (active area) of the display panel, the VGL1 signal has one less low-level load, the overall load current of VGL1 is smaller, the VGL1 value is relatively lower than the original set value, and the difference between VGH1 and VGL1 is relatively larger. Since the EM signal and the SPX signal share the VGL1 voltage generated by the gate drive circuit, once the difference between VGH1 and VGL1 becomes relatively larger, the SPX signal high-level coupling increases, the N4 node potential is higher, and the brightness is brighter. In region ①, the falling edge of the EM(1) signal is not in the porch region. Therefore, for the active area of ​​the display panel, the VGL1 signal has an additional low-voltage load, increasing the overall load current of VGL1. The VGL1 value is relatively higher than the original set value, and the difference between VGH1 and VGL1 is relatively smaller. Since the EM signal and SPX signal share the VGL1 voltage generated by the gate drive circuit, once the difference between VGH1 and VGL1 becomes relatively smaller, the high-voltage coupling of the SPX signal decreases, the N4 node potential becomes lower, and the brightness becomes dimmer. The final display image is presented as follows: Figure 3 The prior art display device 111' shown is prone to exhibiting regular bright and dark horizontal stripes.

[0033] As can be seen from the above, in the prior art, when display devices using LTPO technology display low brightness and low grayscale, the state of the falling edge of the EM signal entering and exiting the porch area is different at different times. The VGL1 voltage shows potential fluctuations in units of the EM signal cycle. Since the EM signal, SP signal, and SPX signal all share the VGL1 voltage generated by the gate drive circuit, the coupling amount of the SPX signal also fluctuates periodically, resulting in bright and dark horizontal stripes appearing in the low grayscale image.

[0034] To address the aforementioned problems, this application proposes a display device and its driving method, which can improve the display of horizontal stripes and enhance display quality. Specific embodiments of the display device and its driving method proposed in this application are described in detail below.

[0035] Please refer to Figure 4 , Figure 4This is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. The display device 111 provided in this embodiment includes a display panel 10, a display driver chip 20 and a power management integrated circuit 30; the display panel 10 includes a bezel area NA, and the bezel area NA includes a gate driving circuit 101 and a first voltage signal line 102.

[0036] The first output terminal 30-out1 of the power management integrated circuit 30 is electrically connected to the input pin IN-pin of the display driver chip 20. The output pin OUT-pin of the display driver chip 20 is electrically connected to one end of the first voltage signal line 102. The other end of the first voltage signal line 102 is electrically connected to the first voltage signal terminal 1011 of the gate drive circuit 101.

[0037] The power management integrated circuit 30 includes a comparator module 301 and an adjustment module 302. The first comparator terminal 3011 of the comparator module 301 is electrically connected to the first voltage signal line 102 via the first connection line L1. The second comparator terminal 3012 of the comparator module 301 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30. The feedback terminal 3013 of the comparator module 301 is electrically connected to the input terminal 302-in of the adjustment module 302. The output terminal 302-out of the adjustment module 302 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30.

[0038] Specifically, the display device 111 provided in this embodiment can be an OLED display device, and the display device 111 includes a display panel 10, that is, the display panel 10 can be an OLED display panel. The display area AA of the display panel 10 can include pixel circuits and OLED light-emitting elements. Optionally, the pixel circuit designed for the display panel 10 in this embodiment can be a pixel circuit using LTPO technology (see reference). Figure 1 The display device 111 also includes a display driver chip 20 and a power management integrated circuit 30. The display driver chip 20 can be understood as a DDIC (Display Driver Integrated Circuit), which is mainly used to control the display panel 10, drive the display panel 10 through electrical signals, transmit display driving data, and work with the display panel 10 to achieve thinness, flexibility and foldability, and provide wide color gamut and high-fidelity display signals.

[0039] Optionally, the display driver chip 20 and the display panel 10 can be electrically connected via a flexible circuit board. It is understood that this embodiment does not limit the electrical connection method between the display driver chip 20 and the display panel 10; specific details can be found in related technologies regarding the bonding methods of the display driver chip 20 and the display panel 10. It is also understood that the final structure of the display device 111 can be such that the display driver chip 20 is located on the backlight side of the display panel 10 through bending of the flexible circuit board, thereby minimizing the overall size of the display device 111 and avoiding the display driver chip 20 occupying space in the device.

[0040] The power management integrated circuit 30 in this embodiment can be understood as a PMIC (Power Management IC), mainly used to power the display device, that is, the power supply for the display panel 10 to perform display operations, the power supply for the display driver chip 20 to control display drive signals, and the power supply requirements of other modules included in the display device 111 are all provided by the power management integrated circuit 30. Figure 1 The gate control potentials used to control the conduction of transistors in the pixel circuit of the display panel shown can all be provided to the display driver chip 20 by the power management integrated circuit 30, and then transmitted to the display panel 10 by the output pins of the display driver chip 20. Taking the first output terminal 30-out1 of the power management integrated circuit 30, which outputs the VGL1 signal required by the pixel circuit of the display panel 10, as an example, the VGL1 signal is a control... Figure 1 The effective signal for the conduction of transistors other than transistors T4 and T5.

[0041] The first output terminal 30-out1 of the power management integrated circuit 30 is electrically connected to the input pin IN-pin of the display driver chip 20. The output pin OUT-pin of the display driver chip 20 is electrically connected to one end of the first voltage signal line 102. The first voltage signal line 102 is routed in the bezel area NA of the display panel 10. The bezel area NA of the display panel 10 also includes a gate driving circuit 101. The other end of the first voltage signal line 102 is electrically connected to the first voltage signal terminal 1011 of the gate driving circuit 101. Thus, the first output terminal 30-out1 of the power management integrated circuit 30 outputs a low-level signal, which is introduced through the input pin IN-pin of the display driver chip 20, output through the output pin OUT-pin of the display driver chip 20 to the first voltage signal line 102 in the bezel area NA of the display panel 10, and then introduced into the gate driving circuit 101 through the first voltage signal terminal 1011 of the gate driving circuit 101. The gate driving circuit 101 generates the VGL1 signal required by the pixel circuit of the display area AA of the display panel 10 and outputs it to the pixel circuit to control... Figure 1 All transistors except transistors T4 and T5 are turned on.

[0042] It is understood that the VGL1 signal required by the pixel circuit of the display area AA of the display panel 10 in this embodiment is directly output by the first output terminal 30-out1 of the power management integrated circuit 30, without the need for signal adjustment by the internal circuit of the display driver chip 20, which helps to save the power consumption of the display driver chip 20.

[0043] It is understood that this embodiment is only used as an example to illustrate the power management integrated circuit 30, which includes the first output terminal 30-out1. In specific implementation, the output terminal of the power management integrated circuit 30 includes, but is not limited to, this first output terminal 30-out1.

[0044] Since the EM signal, SP signal, and SPX signal in the pixel circuit of the display device all share the VGL1 voltage generated by the gate drive circuit after being output from the first output terminal 30-out1 of the power management integrated circuit 30, and the state of the falling edge of the EM signal entering and leaving the porch area is different at different times during low brightness and low grayscale display, the VGL1 voltage will fluctuate in units of the EM signal period, which will cause the SPX signal coupling amount to fluctuate periodically, resulting in bright and dark horizontal stripes in the low grayscale image.

[0045] To solve the above problems, this embodiment sets the power management integrated circuit 30 to include a comparison module 301 and an adjustment module 302; wherein the comparison module 301 can be a comparator, the first comparison terminal 3011 and the second comparison terminal 3012 of the comparison module 301 can be understood as the two comparison signal input terminals of the comparator, and the feedback terminal 3013 of the comparison module 301 can be understood as the comparison signal output terminal. In this embodiment, the first comparison terminal 3011 of the comparison module 301 is electrically connected to the first voltage signal line 102 of the bezel area NA in the display panel 10 via the first connection line L1. It can be understood that the first comparison terminal 3011 of the comparison module 301 is electrically connected to the first voltage signal line 102 of the bezel area NA in the display panel 10 via the first connection line L1. This connection can be indirect, such as indirectly through the pins of the display driver chip 20. Alternatively, the first comparison terminal 3011 of the comparison module 301 of the power management integrated circuit 30 can be electrically connected to the first voltage signal line 102 of the bezel area NA in the display panel 10 via the first connection line L1. It can also be a direct electrical connection between the first connection line L1 and the first voltage signal line 102. This embodiment does not impose any limitations on this connection. The first comparison terminal 3011 of the comparison module 301 is electrically connected to the first voltage signal line 102 of the bezel area NA in the display panel 10 via the first connection line L1. Thus, the real-time voltage on the first voltage signal line 102 of the traces in the bezel area NA of the display panel 10 can be transmitted to the first comparison terminal 3011 of the comparison module 301 via the first connection line L1. The second comparison terminal 3012 of the comparison module 301 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30. That is, the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30 can be directly transmitted from the power management integrated circuit 30 to the second comparison terminal 3012 of the comparison module 301. The comparison module 301 can compare the real-time voltage on the first voltage signal line 102 of the traces in the bezel area NA of the display panel 10 with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30 in real time to obtain an error voltage.The feedback terminal 3013 of the comparison module 301 is electrically connected to the input terminal 302-in of the adjustment module 302, and the output terminal 302-out of the adjustment module 302 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30. If the feedback result obtained by the feedback terminal 3013 of the comparison module 301, i.e., the error voltage, exceeds the preset range, the adjustment module 302 can adjust the control parameters inside the power management integrated circuit 30 according to the magnitude of the error voltage, and adjust the output voltage of the first output terminal 30-out1 of the power management integrated circuit 30. After adjustment and compensation, the output voltage of the first output terminal 30-out1 of the power management integrated circuit 30 can ensure that the VGL1 level of the falling edge of the EM signal entering the porch area remains unchanged at different times. In this way, the coupling amount of the SPX signal is fixed, and the display brightness of different areas of the display panel 10 is not affected. This effectively improves the display problem of bright and dark horizontal stripes in low grayscale display and helps to improve display quality.

[0046] The display device 111 of this embodiment is electrically connected to the first connection line L1 via the first voltage signal line 102 of the NA trace in the bezel area of ​​the display panel 10. A comparison module 301 and an adjustment module 302 are provided in the power management integrated circuit 30. The comparison module 301 compares the real-time voltage on the first voltage signal line 102 of the trace in the NA bezel area of ​​the display panel 10 with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30. In case of error, the adjustment module 302 adjusts and compensates for the error. Finally, the adjusted and compensated voltage is output to the display panel via the first output terminal 30-out1 of the power management integrated circuit 30. Even if the falling edge of the EM signal enters the porch area at different times and in different areas during the driving scanning display process of the display panel 10, the SPX signal coupling amount required by the pixel circuit of the display panel 10 can be a fixed voltage value. The display brightness of different areas of the display panel 10 can be effectively guaranteed to be unaffected, thereby greatly improving the display problem of bright and dark horizontal stripes in low grayscale display and improving the display quality.

[0047] It should be noted that in this embodiment... Figure 4 The structure included in the display device 111 is only an example of the electrical connection relationship between them and does not represent the actual setting structure. In specific implementation, the structure can be based on the actual setting position, shape and other structures of the product. In specific implementation, the structure of the display device 111 includes but is not limited to this, and also includes other structures, such as the connector between the power management integrated circuit 30 and the display driver chip 20. The structure of the display panel 20 can be understood by referring to the structure of the OLED display panel in related technologies.

[0048] Optionally, the comparison module 301 in this embodiment can be a comparator structure. The comparator can be composed of a differential amplifier with two input terminals (positive input terminal and negative input terminal) and one output terminal. The two input terminals are the first comparison terminal 3011 and the second comparison terminal 3012 in this embodiment, and the output terminal is the feedback terminal 3013 in this embodiment. For example, if the first comparison terminal 3011 is the negative input terminal and the second comparison terminal 3012 is the positive input terminal, the output voltage is high when the voltage of the positive input terminal is higher than that of the negative input terminal, and low when the voltage of the negative input terminal is higher than that of the positive input terminal. Based on the feedback result of the feedback terminal 3013, the adjustment module 302 can perform voltage compensation adjustment. When the voltages at the two input terminals are equal, the output voltage depends on the characteristics of the comparator. There may be a certain bias voltage, or the output may be in an uncertain state. In this case, it means that the real-time voltage on the first voltage signal line 102 of the display panel 10 frame area NA that the comparator module 301 compares in real time is consistent with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30.

[0049] In some alternative embodiments, please refer to Figure 5 , Figure 5 This is another planar structural schematic diagram of the display device provided in the embodiment of the present invention. In this embodiment, one end of the first connecting line L1 is electrically connected to the first comparison terminal 3011 of the comparison module 301, and the other end of the first connecting line L1 is located at the connection node J of the first voltage signal line 102 in the frame area NA.

[0050] This embodiment explains that the first connecting line L1, which is electrically connected to the first voltage signal line 102 in the bezel area NA of the display panel 10, can be arranged in such a way that one end of the first connecting line L1 is electrically connected to the first comparison terminal 3011 of the comparison module 301, and the other end of the first connecting line L1 is located at the connection node J of the first voltage signal line 102 in the bezel area NA, that is, the other end of the first connecting line L1 is directly electrically connected to the first voltage signal line 102 in the bezel area NA of the display panel 10. In this embodiment, the first connecting line L1 is set to electrically connect the first voltage signal line 102 of the wiring in the bezel area NA of the display panel 10 to the first connecting line L1. A comparison module 301 and an adjustment module 302 are set in the power management integrated circuit 30. The comparison module 301 compares the real-time voltage on the first voltage signal line 102 of the wiring in the bezel area NA of the display panel 10 with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30. Therefore, the connection node J between the first connecting line L1 and the first voltage signal line 102 is set in the bezel area NA. The first connecting line L1 is directly led out from the first voltage signal line 102 in the bezel area NA of the display panel 10. This can accurately feed back the real-time VGL1 signal that needs to be compared transmitted on the first voltage signal line 102 of the display panel 10, thereby ensuring that the adjustment module 302 makes more accurate feedback compensation and can better guarantee the display quality.

[0051] In some alternative embodiments, please refer to Figure 6 , Figure 6 This is a schematic diagram of another planar structure of the display device provided in an embodiment of the present invention. In this embodiment, one end of the first connecting line L1 is electrically connected to the first comparison terminal 3011 of the comparison module 301, and the other end of the first connecting line L1 is connected to the first voltage signal line 102 at the connection node J on the input pin IN-pin of the display driver chip 20.

[0052] This embodiment explains that the first connecting line L1, which is electrically connected to the first voltage signal line 102 of the trace in the bezel area NA of the display panel 10, can be arranged as follows: one end of the first connecting line L1 is electrically connected to the first comparison terminal 3011 of the comparison module 301, and the other end of the first connecting line L1 and the connection node J of the first voltage signal line 102 are located on the input pin IN-pin of the display driver chip 20. That is, a VGL1 signal input pin IN-pin is found on the display driver chip 20, and the real-time voltage transmitted on the first voltage signal line 102 is introduced into the first connecting line L1 through the input pin IN-pin of the display driver chip 20. This enables the comparison module 301 to compare the real-time voltage on the first voltage signal line 102 of the trace in the bezel area NA of the display panel 10 with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30 in real time, so that the adjustment module 302 can adjust the VGL1 voltage output by the power management integrated circuit 30 to ensure display quality. Furthermore, the connection node J between the first connection line L1 and the first voltage signal line 102 is located on the input pin IN-pin of the display driver chip 20, which allows the layout of the first connection line L1 to not occupy the bezel space of the display panel 10, which is beneficial to reduce the bezel of the display device 000 and increase the screen ratio.

[0053] In some alternative embodiments, please refer to Figure 7 , Figure 7 This is another planar structural schematic diagram of the display device provided in the embodiment of the present invention. In this embodiment, the power management integrated circuit 30 includes a high-frequency crystal oscillator 303, and the frequency output terminal 3031 of the high-frequency crystal oscillator 303 is electrically connected to the first comparison terminal 3011 of the comparison module 301.

[0054] This embodiment explains that, since it is necessary to transmit and compare the voltage value on the first voltage signal line 102 of the traces within the NA bezel area of ​​the display panel 10 in real time, a high-frequency crystal oscillator 303 can be set in the power management integrated circuit 30. Based on the oscillation frequency provided by the high-frequency crystal oscillator 303, the first comparison terminal 3011 of the comparison module 301 responds to the voltage value on the first voltage signal line 102. Specifically, the high-frequency crystal oscillator 303 can be a quartz crystal-based oscillator, achieving oscillation through the resonant frequency of the quartz crystal. The vibration frequency of the high-frequency crystal oscillator 303 can be controlled within a fixed numerical range, typically reaching millions or even hundreds of millions of times per second. The frequency output terminal 3031 of the high-frequency crystal oscillator 303 is electrically connected to the first comparison terminal 3011 of the comparison module 301. The first comparison terminal 3011 of the comparison module 301 is also electrically connected to the first voltage signal line 102 in the display panel 10 through the first connection line L1. Therefore, by using the fixed high vibration frequency output by the frequency output terminal 3031 of the high-frequency crystal oscillator 303, the voltage of VGL1 scanned to each pixel circuit row of the display panel 10 can be monitored in real time. That is, the fixed high vibration frequency output by the frequency output terminal 3031 of the high-frequency crystal oscillator 303 controls the feedback frequency of the first connection line L1 to the first comparison terminal 3011 of the comparison module 301 for real-time monitoring. In actual implementation, the response can start when the scanning signal enters the porch area of ​​the display panel every few rows, and the real-time voltage value on the first voltage signal line 102 is compared and adjusted with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30. Optionally, in this embodiment, the selection of the high vibration frequency of the fixed value output by the frequency output terminal 3031 of the high-frequency crystal oscillator 303 can be greater than or equal to the frequency at which the display panel enters the porch area, so as to ensure that the voltage on the first voltage signal line 102 is compared and adjusted as much as possible in each porch area, or to more precisely compare and adjust the voltage on the first voltage signal line 102 when each pixel circuit is working, so as to effectively improve the horizontal stripe phenomenon of the display.

[0055] In some alternative embodiments, please refer to the references. Figures 4-7 , Figure 8 and Figure 9 , Figure 8 This is a schematic diagram of another planar structure of the display device provided in an embodiment of the present invention. Figure 9 yes Figure 8A schematic diagram of an electrical connection structure between a pixel circuit and a light-emitting element. In this embodiment, the display panel 10 includes a display area AA, which includes multiple pixel circuits 103 and light-emitting elements 104. The pixel circuit 103 includes an electrically connected driving module 1031, a first reset module 1032, a data writing module 1033, a bias voltage adjustment module 1034, and a light-emitting control module 1035.

[0056] The first terminal of the first reset module 1032 is electrically connected to the first reset signal line REF1, and the second terminal of the first reset module 1032 is electrically connected to the anode of the light-emitting element 104; the first terminal of the data writing module 1033 and the first terminal of the bias voltage adjustment module 1034 are both electrically connected to the first terminal of the drive module 1031, the second terminal of the data writing module 1033 is electrically connected to the data line DATA, and the second terminal of the bias voltage adjustment module 1034 is electrically connected to the bias voltage adjustment signal line DVH.

[0057] The light-emitting control module 1035 includes a first light-emitting control module 10351 and a second light-emitting control module 10352. The first end of the first light-emitting control module 10351 is electrically connected to the first power signal line PVDD, the second end of the first light-emitting control module 10351 is electrically connected to the first end of the driving module 1031, the first end of the second light-emitting control module 10352 is electrically connected to the second end of the driving module 1031, the second end of the second light-emitting control module 10352 is electrically connected to the anode of the light-emitting element 104, and the cathode of the light-emitting element 104 is electrically connected to the second power signal line PVEE.

[0058] The control terminals of the first reset module 1032 and the bias adjustment module 1034 are electrically connected to the first scan signal line SPX, the control terminal of the data writing module 1033 is electrically connected to the second scan signal line SP, and the control terminal of the light emission control module 1035 is electrically connected to the light emission control signal line EM.

[0059] The enable signal VGL1 for the first scan signal line SPX, the second scan signal line SP, and the light emission control signal line EM are all low-level signals.

[0060] The pixel circuit 103 also includes a threshold compensation module 1036 and a second reset module 1037;

[0061] The first end of the second reset module 1037 is electrically connected to the second reset signal line REF2, the second end of the second reset module 1037 is electrically connected to the control end of the drive module 1031, and the control end of the second reset module 1037 is electrically connected to the third scan signal line S1N.

[0062] The first end of the threshold compensation module 1036 is electrically connected to the control end of the drive module 1031, the second end of the threshold compensation module 1036 is electrically connected to the second end of the drive module 1031, and the control end of the threshold compensation module 1036 is electrically connected to the fourth scan signal line S2N.

[0063] The enable signals for the third scan signal line S1N and the fourth scan signal line S2N are both high-level signals.

[0064] Optionally, the first voltage signal terminal 1011 of the gate driving circuit 101 receives the voltage on the first voltage signal line 102 and generates an enable signal VGL1 for the first scan signal line SPX, the second scan signal line SP, and the light emission control signal line EM. The enable signal indicates that the first and second terminals of the module can be connected. If the transistor included in the module is a P-type transistor, the first scan signal line SPX, the second scan signal line SP, and the light emission control signal line EM are electrically connected to the control terminal of the module respectively. The provided low-level VGL1 signal can turn on the module; otherwise, the module is in the off state.

[0065] This embodiment explains the electrical connection relationships of the module structure that the pixel circuit 103 set in the display area AA of the display panel 000 can specifically include. In this embodiment, the driving transistor DT of the driving module 1031 is electrically connected to the data writing module 1033, the threshold compensation module 1036, and the bias adjustment module 1034. The first terminal of the driving transistor DT is electrically connected to the data writing module 1033 and the bias adjustment module 1034 respectively. The driving transistor DT is used to generate driving current. The first terminal of the driving transistor DT can be understood as the source of the driving transistor DT, and the second terminal of the driving transistor DT can be understood as the drain of the driving transistor DT. Alternatively, the first terminal of the driving transistor DT can be understood as the drain of the driving transistor DT, and the second terminal of the driving transistor DT can be understood as the source of the driving transistor DT. This embodiment does not limit this. The second terminal of the data writing module 1033 is electrically connected to the data line DATA. The data writing module 103 is turned on under the control of the second scan signal provided by the second scan signal SP, transmitting the data voltage to the second terminal of the data writing module 1033 via the data line DATA. The first terminal of the data writing module 1033 is electrically connected to the first electrode of the driving transistor DT. The data writing module 1033 is used to provide a data voltage value to the driving transistor DT. The threshold compensation module 1036 is connected between the gate and the second electrode of the driving transistor DT. The threshold compensation module 1036 is turned on under the control of the fourth scan signal provided by the fourth scan signal line S2N. The threshold compensation module 1036 is used to detect and compensate for the deviation of the threshold voltage of the driving transistor DT, and provides the compensated threshold voltage deviation and the data signal provided by the data line DATA itself to the driving transistor DT to achieve threshold compensation for the driving transistor DT. In this embodiment, the threshold compensation module 1036 can improve the display unevenness caused by the threshold voltage difference of the driving transistor DT due to the manufacturing process and the threshold voltage drift of the driving transistor DT due to transistor aging. The second reset module 1037 is turned on under the control of the third scan signal provided by the third scan signal line S1N. The second reset signal provided by the second reset signal line REF2 can reset the gate of the driving transistor DT and refresh the gate potential of the driving transistor DT in the previous frame.

[0066] When the light-emitting element 104 emits light, the first light-emitting control module 10351 and the second light-emitting control module 10352 are turned on by the light-emitting control signal provided by the light-emitting control signal line EM. A conductive path is formed between the first power signal line PVDD, the first light-emitting control module 10351, the driving transistor DT, the second light-emitting control module 10352, the light-emitting element 104, and the second power signal line PVEE. The driving current is provided to the light-emitting element 104 to control the light-emitting element 104 to emit light.

[0067] Optional, such as Figure 8 and Figure 10 As shown, Figure 10 yes Figure 8 A schematic diagram of another electrical connection structure between the pixel circuit and the light-emitting element is shown. The driving module 1031 includes a driving transistor DT, the first reset module 1032 includes a first transistor M1, the data writing module 1033 includes a second transistor M2, the bias adjustment module 1034 includes a third transistor M3, the first light-emitting control module 10351 includes a fourth transistor M4, the second light-emitting control module 10352 includes a fifth transistor M5, the threshold compensation module 1036 includes a sixth transistor M6, and the second reset module 1037 includes a seventh transistor M7. Optionally, the second reset module 1037 and the threshold compensation module 1036 include metal-oxide transistors, i.e., the sixth transistor M6 and the seventh transistor M7 are metal-oxide transistors, such as N-type metal-oxide transistors. The driving module 1031, the first reset module 1032, the data writing module 1033, the bias adjustment module 1034, the first light-emitting control module 10351, and the second light-emitting control module 10352 each include low-temperature polysilicon transistors, namely, the driving transistor DT, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are all low-temperature polysilicon transistors, such as P-type low-temperature polysilicon transistors. In this embodiment, the sixth transistor M6 and the seventh transistor M7, which are connected to the gate of the driving transistor DT at the control terminal of the driving module 1031, are N-type metal-oxide transistors (MOS transistors). The remaining transistors, namely the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the driving transistor DT, are all P-type low-temperature polysilicon transistors (LTPS). Since MOS transistors have low leakage current in the off-state, the influence of leakage current on the gate potential of the driving transistor DT can be reduced, thereby stabilizing the gate voltage of the driving transistor DT, improving the working stability of the driving transistor DT, and ensuring the stability of the driving current. This is beneficial for the display panel 10 in this embodiment to ensure the uniformity of the light emission brightness of the light-emitting element 104. Especially when the display panel 10 implements low-frequency driving display, the display time of one frame is relatively long, and the potential of the driving transistor DT needs to be maintained for a long time. If the transistor connected to the gate of the driving transistor DT is an LTPS, the large leakage current of the LTPS in the off-state can have a significant impact on the gate potential of the driving transistor DT, resulting in obvious flickering. Therefore, in this embodiment, by setting the sixth transistor M6 and the seventh transistor M7 as N-type metal-oxide transistors, and utilizing their characteristic of low leakage current in the off-state, the potential of the gate of the driving transistor DT can be maintained for a long time when the display panel 10 realizes low-frequency driving display, thereby improving the flickering phenomenon during low-frequency driving and enhancing the display effect.

[0068] Optionally, the pixel circuit 103 further includes a storage capacitor C, one end of which is connected to the first power signal line PVDD, and the other end of which is connected to the gate of the driving transistor DT. The storage capacitor C is used to stabilize the potential of the gate of the driving transistor DT, which helps the driving transistor DT to remain on.

[0069] It is understood that this embodiment does not elaborate on the operation process of the pixel circuit using LTPO screen technology, nor is it the main inventive point of this disclosure. Therefore, for specific understanding, please refer to the operating timing diagram of OLED display panels in related technologies.

[0070] In some alternative embodiments, please refer to the references. Figures 4-10 and Figure 11 , Figure 11 This is a flowchart of a driving method for a display device provided in an embodiment of the present invention. The driving method provided in this embodiment is used to drive the display device 111 in any of the above embodiments. The driving method provided in this embodiment includes:

[0071] S10: During one frame display cycle of the display panel 10, the actual first voltage signal VGL1-FB transmitted on the first voltage signal line 102 is transmitted to the first comparison terminal 3011 of the comparison module 301 of the power management integrated circuit 30 through the first connection line L1.

[0072] S20: The second comparison terminal 3012 of the comparison module 301 receives the preset first voltage signal VGL1-YS output by the first output terminal 30-out1 of the power management integrated circuit 30;

[0073] S30: Comparison module 301 compares the actual first voltage signal VGL1-FB with the preset first voltage signal VGL1-YS to obtain the error value;

[0074] S40: The feedback terminal 3013 of the comparison module 301 feeds back the error value to the input terminal 302-in of the adjustment module 302;

[0075] S50: Adjustment is performed by adjustment module 302. The output terminal 302-out of adjustment module 302 transmits the adjusted compensation first voltage signal ΔVGL1 to the first output terminal 30-out1 of power management integrated circuit 30.

[0076] The driving method provided in this embodiment is used to compensate the voltage on the first voltage signal line 102 of the bezel area NA in the display panel 10. The first voltage signal line 102 is mainly used to introduce the low-level VGL1 signal output by the first output terminal 30-out1 of the power management integrated circuit 30 into the gate driving circuit 101 of the bezel area NA after passing through the input pin IN-pin and output pin OUT-pin of the display driver chip 20. The cascading characteristics of the gate driving circuit 101 generate the control signals required by the pixel circuit of the display panel 10, such as the EM signal required for light emission control, the SP signal required for data writing, and the SPX signal required for bias adjustment.

[0077] Since the first comparison terminal 3011 of the comparison module 301 in the power management integrated circuit 30 is electrically connected to the first voltage signal line 102 of the bezel area NA in the display panel 10 through the first connection line L1, the real-time voltage on the first voltage signal line 102 of the traces in the bezel area NA of the display panel 10 can be transmitted to the first comparison terminal 3011 of the comparison module 301 through the first connection line L1. For example, during one frame display cycle of the display panel 10, when the falling edge of the EM signal enters the porch area during the scanning drive of the display panel 10, or when each pixel circuit line is scanned, the actual first voltage signal VGL1-FB transmitted on the first voltage signal line 102 is transmitted to the comparison module 301 of the power management integrated circuit 30 through the first connection line L1. The first comparison terminal 3011 of the comparison module 301 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30. That is, the preset first voltage signal VGL1-YS output by the first output terminal 30-out1 of the power management integrated circuit 30 can be directly transmitted from the power management integrated circuit 30 to the second comparison terminal 3012 of the comparison module 301. The comparison module 301 can compare the actual first voltage signal VGL1-FB on the first voltage signal line 102 of the wiring in the bezel area NA of the display panel 10 with the preset first voltage signal VGL1-YS output by the first output terminal 30-out1 of the power management integrated circuit 30 in real time to obtain an error value. The feedback terminal 3013 of the comparison module 301 is electrically connected to the input terminal 302-in of the adjustment module 302, and the output terminal 302-out of the adjustment module 302 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30. If the feedback result obtained by the feedback terminal 3013 of the comparison module 301, i.e., the error value, exceeds the preset range, the adjustment module 302 can adjust the control parameters inside the power management integrated circuit 30 according to the magnitude of the error voltage, and adjust the output voltage of the first output terminal 30-out1 of the power management integrated circuit 30. Finally, the output terminal 302-out of the adjustment module 302 transmits the adjusted compensation first voltage signal ΔVGL1 to the first output terminal 30-out1 of the power management integrated circuit 30. This embodiment provides a driving method that can ensure that the VGL1 level of the falling edge of the EM signal entering the porch area remains unchanged at different times, thereby making the coupling amount of the SPX signal fixed, and the display brightness of different areas of the display panel 10 unaffected. This effectively improves the display problem of bright and dark horizontal stripes in low grayscale display and is conducive to improving display quality.

[0078] Optionally, in this embodiment, the comparison module 301 compares the actual first voltage signal VGL1-FB with the preset first voltage signal VGL1-YS to obtain the error value. The comparison module 301 can be a comparator structure, which can be composed of a differential amplifier. The amplifier has two input terminals (positive input terminal and negative input terminal) and one output terminal. The two input terminals are the first comparison terminal 3011 and the second comparison terminal 3012, and the output terminal is the feedback terminal 3013. For example, if the first comparison terminal 3011 is the negative input terminal and the second comparison terminal 3012 is the positive input terminal, when the voltage of the positive input terminal is higher than that of the negative input terminal, the output voltage, i.e., the error value, is high level, and when the voltage of the negative input terminal is higher than that of the positive input terminal, the output voltage, i.e., the error value, is low level. According to the feedback result of the feedback terminal 3013, the adjustment module 302 can perform voltage compensation adjustment. When the voltages at the two input terminals are equal, the output voltage depends on the characteristics of the comparator. There may be a certain bias voltage, or the output may be in an uncertain state. In this case, it means that the real-time voltage on the first voltage signal line 102 of the display panel 10 frame area NA that the comparator module 301 compares in real time is consistent with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30. Therefore, no adjustment or compensation is required.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0080] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display device, characterized in that, It includes a display panel, a display driver chip, and a power management integrated circuit; the display panel includes a bezel area, and the bezel area includes a gate driving circuit and a first voltage signal line. The first output terminal of the power management integrated circuit is electrically connected to the input pin of the display driver chip, the output pin of the display driver chip is electrically connected to one end of the first voltage signal line, and the other end of the first voltage signal line is electrically connected to the first voltage signal terminal of the gate drive circuit. The power management integrated circuit includes a comparison module and an adjustment module; the first comparison terminal of the comparison module is electrically connected to the first voltage signal line through a first connection line, the second comparison terminal of the comparison module is electrically connected to the first output terminal of the power management integrated circuit, the feedback terminal of the comparison module is electrically connected to the input terminal of the adjustment module, and the output terminal of the adjustment module is electrically connected to the first output terminal of the power management integrated circuit. The power management integrated circuit includes a high-frequency crystal oscillator, and the frequency output terminal of the high-frequency crystal oscillator is electrically connected to the first comparison terminal of the comparison module. The output frequency of the high-frequency crystal oscillator is greater than or equal to the frequency at which the display panel enters the porch area during the scanning drive process.

2. The display device according to claim 1, characterized in that, One end of the first connecting line is electrically connected to the first comparison terminal of the comparison module, and the other end of the first connecting line is connected to the first voltage signal line at the border area.

3. The display device according to claim 1, characterized in that, One end of the first connection line is electrically connected to the first comparison terminal of the comparison module, and the connection node of the other end of the first connection line and the first voltage signal line is located on the input pin of the display driver chip.

4. The display device according to claim 1, characterized in that, The display panel includes a display area, which includes multiple pixel circuits and light-emitting elements; the pixel circuit includes an electrically connected driving module, a first reset module, a data writing module, a bias voltage adjustment module, and a light-emitting control module. The first terminal of the first reset module is electrically connected to the first reset signal line, and the second terminal of the first reset module is electrically connected to the anode of the light-emitting element; the first terminal of the data writing module and the first terminal of the bias voltage adjustment module are both electrically connected to the first terminal of the driving module, the second terminal of the data writing module is electrically connected to the data line, and the second terminal of the bias voltage adjustment module is electrically connected to the bias voltage adjustment signal line. The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first end of the first light-emitting control module is electrically connected to a first power signal line, the second end of the first light-emitting control module is electrically connected to a first end of the driving module, the first end of the second light-emitting control module is electrically connected to a second end of the driving module, the second end of the second light-emitting control module is electrically connected to the anode of the light-emitting element, and the cathode of the light-emitting element is electrically connected to a second power signal line. The control terminals of the first reset module and the bias adjustment module are electrically connected to the first scan signal line, the control terminal of the data writing module is electrically connected to the second scan signal line, and the control terminal of the light emission control module is electrically connected to the light emission control signal line. The enable signals for the first scan signal line, the second scan signal line, and the light emission control signal line are all low-level signals.

5. The display device according to claim 4, characterized in that, The first voltage signal terminal of the gate driving circuit receives the voltage on the first voltage signal line and generates enable signals for the first scan signal line, the second scan signal line, and the light emission control signal line through the gate driving circuit.

6. The display device according to claim 4, characterized in that, The pixel circuit also includes a threshold compensation module and a second reset module. The first end of the second reset module is electrically connected to the second reset signal line, the second end of the second reset module is electrically connected to the control end of the drive module, and the control end of the second reset module is electrically connected to the third scan signal line. The first end of the threshold compensation module is electrically connected to the control end of the drive module, the second end of the threshold compensation module is electrically connected to the second end of the drive module, and the control end of the threshold compensation module is electrically connected to the fourth scan signal line. The enable signals for both the third and fourth scan signal lines are high-level signals.

7. The display device according to claim 6, characterized in that, The second reset module and the threshold compensation module both include metal-oxide transistors.

8. The display device according to claim 6, characterized in that, The driving module, the first reset module, the data writing module, the bias adjustment module, and the light emission control module each include a low-temperature polysilicon transistor.

9. A driving method for a display device, characterized in that, The driving method is used to drive the display device according to any one of claims 1-8; the driving method includes: Within one frame display cycle of the display panel, the actual first voltage signal transmitted on the first voltage signal line is transmitted to the first comparison terminal of the comparison module of the power management integrated circuit through the first connection line. The second comparison terminal of the comparison module receives the preset first voltage signal output by the first output terminal of the power management integrated circuit. The comparison module compares the actual first voltage signal with the preset first voltage signal to obtain an error value. The feedback terminal of the comparison module feeds back the error value to the input terminal of the adjustment module, which is electrically connected for adjustment. The output terminal of the adjustment module transmits the adjusted compensation first voltage signal to the first output terminal of the power management integrated circuit. The comparison module compares the actual first voltage signal and the preset first voltage signal at a frequency controlled by a high-frequency crystal oscillator. The output frequency of the high-frequency crystal oscillator is greater than or equal to the frequency at which the display panel enters the porch area during the scanning drive process.

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