Charge pump circuit and operating method thereof

Abstract

An embodiment of the invention provides a circuit comprising first and second transistors coupled in series, their respective gate terminals are connected to a first node to receive a first signal through a first capacitor; third and fourth transistors coupled in series, their respective gate terminals are connected to the second node to receive a second signal through a second capacitor that is logically opposite to the first signal; a fifth transistor having a source / drain terminal coupled between the gate terminal of the first transistor and the first node; a sixth transistor having a source / drain terminal coupled between the first node and a gate terminal of the second transistor; a seventh transistor having a source / drain terminal coupled between the gate terminal of the third transistor and the second node; and an eighth transistor having a source / drain terminal coupled between the second node and a gate terminal of the fourth transistor. The embodiment of the invention also provides an operation method of the circuit.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to charge pump circuits and methods of operating the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. As integrated circuits continue to shrink, more and more devices are integrated into a single chip. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Summary of the invention

[0003] An embodiment of the present invention provides a circuit, comprising: a first transistor and a second transistor, which are coupled in series with each other between an input node and an output node, wherein corresponding gate terminals of the first transistor and the second transistor are connected to a first node, and the first node is configured to receive a first clock signal through a first charge capacitor; a third transistor and a fourth transistor, which are coupled in series with each other between the input node and the output node, wherein corresponding gate terminals of the third transistor and the fourth transistor are connected to a second node, and the second node is configured to receive a second clock signal that is logically opposite to the first clock signal through a second charge capacitor; a fifth transistor, wherein the source / drain terminal of the fifth transistor is coupled between the gate terminal of the first transistor and the first node; a sixth transistor, wherein the source / drain terminal of the sixth transistor is coupled between the first node and the gate terminal of the second transistor; a seventh transistor, wherein the source / drain terminal of the seventh transistor is coupled between the gate terminal of the third transistor and the second node; and an eighth transistor, wherein the source / drain terminal of the eighth transistor is coupled between the second node and the gate terminal of the fourth transistor.

[0004] Another embodiment of the present invention provides a circuit, comprising: a first charge capacitor, a first end and a second end of the first charge capacitor are respectively connected to a first clock signal and a first common node, wherein the first common node is coupled between a first transistor and a second transistor; a second charge capacitor, a first end and a second end of the second charge capacitor are respectively connected to a second clock signal and a second common node, wherein the second clock signal is logically opposite to the first clock signal, wherein the second common node is coupled between a third transistor and a fourth transistor; a fifth transistor, a gate terminal, a source terminal and a drain terminal of the fifth transistor are respectively connected to the first common node, the gate terminal of the second transistor and the second common node, wherein the fifth transistor and the second transistor both have a first conductivity type; and a sixth transistor, a gate terminal, a source terminal and a drain terminal of the sixth transistor are respectively connected to the second common node, the gate terminal of the fourth transistor and the first common node, wherein the sixth transistor and the fourth transistor both have the first conductivity type; wherein the second transistor and the third transistor are both configured to be activated alternately relative to the first transistor and the fourth transistor so as to boost the output voltage to a multiple of the input voltage.

[0005] Yet another embodiment of the present invention provides a method for operating a charge pump circuit, comprising: providing a charge pump circuit comprising a first transistor, a second transistor, a third transistor and a fourth transistor and a first charge capacitor and a second charge capacitor, wherein the first transistor and the third transistor are coupled in series with each other at a first node, the third transistor and the fourth transistor are coupled in series with each other at a second node, and the first node is connected to a first clock signal through a first charge capacitor, the second node is connected to a second clock signal through a second charge capacitor, and the second clock signal is logically opposite to the first clock signal; in a first stage, by activating the second transistor and the third transistor and deactivating the first transistor and the fourth transistor, the first node and the second node are charged to a first multiple of a power supply voltage and the power supply voltage, respectively; and in a second stage, by activating the first transistor and the fourth transistor and deactivating the second transistor and the third transistor, the first node and the second node are charged to the power supply voltage and a second multiple of the power supply voltage, respectively; wherein during the first stage, the first node is isolated from the gate terminal of the third transistor by deactivating at least the fifth transistor, and during the second stage, the first node is isolated from the gate terminal of the fourth transistor by deactivating at least the sixth transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an example memory device including a charge pump circuit is shown in accordance with some embodiments.

[0008] Figure 2 It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit in a memory device.

[0009] Figure 3A It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit in a memory device.

[0010] Figure 3B According to some embodiments, Figure 3A Example waveforms associated with a charge pump circuit.

[0011] Figure 4A It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit in a memory device.

[0012] Figure 4B According to some embodiments, Figure 4A Example waveforms associated with a charge pump circuit.

[0013] Figure 5 shows that according to some embodiments, Figure 1 Example voltage diagrams associated with an example charge pump circuit in a memory device.

[0014] Fig. 6A It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit in a memory device.

[0015] Figure 6B According to some embodiments, Fig. 6A Example waveforms associated with a charge pump circuit.

[0016] Fig. 7A and Figure 7B It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit in a memory device.

[0017] Figure 7C According to some embodiments, Fig. 7A and Figure 7B Example waveforms associated with a charge pump circuit.

[0018] Fig. 8A It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit in a memory device.

[0019] Figure 8B According to some embodiments, Fig. 8A Example waveforms associated with a charge pump circuit.

[0020] Fig. 9 It is shown that according to some embodiments, the operation may include Figure 1 A flow chart of an example method for an example charge pump circuit in a memory device. DETAILED DESCRIPTION

[0021] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0023] As technology nodes shrink, semiconductor memory devices become more and more integrated, and low operating power supply voltages are widely used. However, even memory devices that operate at low voltages may sometimes require high voltage power supplies for certain internal circuits and operations, such as driving bit lines and word lines. To this end, various voltage supply circuits (e.g., voltage or charge pump circuits) have been developed to generate high voltages. In general, a charge pump circuit consists of a capacitor and a switch. By controlling the on / off of these switches and the corresponding timing of alternating charging and discharging of the capacitor, the charge pump circuit can multiply the power supply voltage to boost or pump the output voltage to a relatively high level. In addition to memory devices (or systems), charge pump circuits have a wide range of applications, such as liquid crystal display (LCD) drivers, microelectromechanical systems (MEMS), power generation, etc.

[0024] The charge pump circuit can be operated by controlling capacitors and switches. The switch can sometimes be implemented as a clocked metal oxide semiconductor field effect transistor (MOSFET). By alternately charging and discharging the capacitor, the charge pump circuit can multiply the power supply voltage to boost or pump the output voltage to a relatively high level. However, the output voltage may suddenly drop under a large current load, such as when a coupled memory device requires a higher read or write voltage, requiring a large current for parallel reading or writing. Such a large current load can cause the gate-source voltage difference (Vgs=Vg-Vs) of the NMOS transistor (e.g., one of the switches) that should be activated and / or the source-gate voltage difference (Vsg=Vs-Vg) of the PMOS transistor (e.g., another switch") to be significantly reduced, which may cause these switches to be erroneously turned off. As a result, the output voltage will suddenly drop, resulting in the ineffectiveness of the charge pump operation. In this regard, the existing charge pump circuits are not completely satisfactory.

[0025] The present disclosure provides various embodiments of a charge pump circuit, which includes a switch, a capacitor (sometimes referred to as a charge transfer capacitor), an auxiliary switch, and an auxiliary capacitor (sometimes referred to as a gate capacitor). The switch and capacitor operably coupled to each other can receive an input voltage and provide an output voltage, which can be a pumped output of the input voltage. At least one of the auxiliary switch and the auxiliary capacitor can be operably connected to at least one of the switch and the capacitor to assist in providing the output voltage. The auxiliary switch connected to the switch and the capacitor and the connection to the auxiliary capacitor allow the charge pump circuit to maintain a larger current load. For example, when the switch is a PMOS transistor (and / or an NMOS transistor), the auxiliary switch connected to the device and the connection to the capacitor can maintain the gate-source voltage difference Vsg of the PMOS transistor (and / or the Vgs of the NMOS transistor) at a higher voltage, which can prevent Vsg (or Vgs) from falling below the threshold voltage of the device. This allows the charge pump circuit to maintain a larger current load and improve the driving capability.

[0026] Figure 1 A block diagram of an example memory device 100 including a charge pump circuit according to some embodiments is shown. In one aspect, the memory array 120 includes a plurality of memory circuits or memory cells. The memory array 120 also includes word lines WL0, WL1 ... WLJ and bit lines BL0, BL1 ... BLK, each word line extending in a first direction (e.g., X direction) and each bit line extending in a second direction (e.g., Y direction). The word line WL and the bit line BL can be a conductive metal or a conductive track, respectively. In some embodiments, each memory cell is connected to a corresponding word line WL and a corresponding bit line BL, and can be operated according to a voltage or current passing through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes a bit line BL / BLB connected to one or more memory cells arranged along a second direction (e.g., Y direction) and connected to a group of memory cells. The bit lines BL and BLB can receive and / or provide differential signals.

[0027] Each memory cell may include a volatile memory cell, a non-volatile memory cell, or a combination thereof. For example, each memory cell is embodied as a static random access memory (SRAM) cell. However, it should be understood that the memory cell may be implemented as any of a variety of other non-volatile memory cells, such as a resistive random access memory (RRAM) cell, a magnetoresistive random access memory (MRAM) cell, a phase change random access memory (PCRAM) cell, an electrical fuse, an anti-fuse, etc., while still within the scope of the present disclosure. In some embodiments, the memory array 120 includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0028] The memory controller 105 is a hardware component that controls the operation of the memory array 120. In some embodiments, the memory controller 105 includes a bit line (BL) controller 112, a word line (WL) controller 114, and a voltage supply circuit 110. The BL controller 112, the WL controller 114, and the voltage supply circuit 110 may be embodied as logic circuits, analog circuits, or a combination thereof. In one configuration, the WL controller 114 is a circuit that provides a voltage or current through one or more word lines WL of the memory array 120, and the BL controller 112 is a circuit that provides or senses a voltage or current through one or more bit lines BL of the memory array 120. In one configuration, the voltage supply circuit 110 is a circuit that provides a voltage signal to the BL controller 112 and / or the WL controller 114. The BL controller 112 may be connected to the bit lines BL of the memory array 120, and the WL controller 114 may be connected to the word lines WL of the memory array 120. In some embodiments, the memory controller 105 includes a logic circuit, an analog circuit, or a combination thereof. Figure 1More, fewer or different components may be shown.

[0029] In various embodiments, the voltage supply circuit 110 may include one or more charge pump circuits, each of which is configured to generate a boosted voltage signal to the BL controller 112 and / or the WL controller 114 to obtain the desired read / write performance. For example, in order to write data at a memory cell, the voltage supply circuit 110 may provide a boosted write voltage (or bias voltage) to the WL controller 114, so that the boosted write voltage is sent to the memory cell through the corresponding word line WL. This allows the bit line and / or complementary bit line of the memory cell 125 to discharge faster. Therefore, when the voltage on the word line is increased, the VCCmin (minimum operating voltage) required by the memory cell (and the entire memory array 120) at a specific write speed can be reduced. In another example, during a read operation of the memory cell, the voltage on the word line can be boosted to be greater than VCCmin, which allows the voltage present on the bit line to discharge faster. Therefore, the read speed of the memory cell (and the entire memory array 120) can be improved.

[0030] Figure 2 It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit 200 in a memory device. For example, the charge pump circuit 200 can be part of the voltage supply circuit 110. It should be understood that for the purpose of illustration, Figure 2 The schematic diagram is simplified, and therefore, the charge pump circuit 200 can be implemented in any of a variety of other configurations (as long as it can boost the input voltage to a higher voltage level through a capacitor) while remaining within the scope of the present disclosure.

[0031] As shown, the charge pump circuit 200 includes transistors Mn1, Mn2, Mp1, and Mp2, auxiliary transistors Mg1, Mg2, Mg3, and Mg4; charge transfer capacitors Cp1 and Cp2; and auxiliary capacitors Cg1, Cg2, Cg3, and Cg4. Transistor Mn2 and transistor Mp2 are connected in series with each other between an input node configured to receive VIN and an output node configured to provide VOUT, wherein the respective gate terminals of transistor Mn2 and transistor Mp2 are connected to node N1 configured to receive a clock signal CLK through charge capacitor Cp1. Transistor Mn1 and transistor Mp1 are connected in series with each other between the input node and the output node, wherein the respective gate terminals of transistor Mn1 and transistor Mp1 are connected to node N2, and node N2 is configured to receive a clock signal CLKB that is logically opposite to the clock signal CLK through charge capacitor Cp2.

[0032] Typically, the charge pump circuit 200 can receive VIN (e.g., VDD or VDDIO) at an input node and output a multiple of VIN as VOUT at an output node. As a brief overview, the charge pump circuit 200 can provide VOUT as a multiple of VIN during each of the first stage and the second stage. The first stage and the second stage can correspond to the asserted (e.g., pulled up) CLKB signal and CLK signal, respectively. For example, in the first stage, the CLKB signal is pulled up (e.g., to VDDIO), and the CLK signal is pulled down (e.g., pulled down to ground or 0V), which activates transistors Mn1 and Mp2 and disables transistors Mn2 and Mp1; in the second stage, the CLKB signal is pulled down (e.g., pulled down to ground or 0V), and the CLK signal is pulled up (e.g., pulled up to VDDIO), which activates transistors Mn2 and Mp1 and disables transistors Mn1 and Mp2. Therefore, in the first stage, the voltage at the node N2 can be pumped to a higher voltage (e.g., 2×VDDIO) by the charge capacitor Cp2, and the charge of the node N2 can be shared to the output node by the activated transistor Mp2, which makes VOUT equal to the pumping voltage. Similarly, in the second stage, the voltage at the node N1 can be pumped to a higher voltage (e.g., 2×VDDIO) by the charge capacitor Cp1, and the charge of the node N1 can be shared to the output node by the activated transistor Mp1, which makes VOUT equal to the pumping voltage. In addition, by including auxiliary transistors Mg1 to Mg4, each auxiliary transistor is connected to the gate terminal and source terminal of a corresponding one of the transistors Mn1, Mp1, Mn2 and Mp2, the nodes N2 and N1 can be isolated from the gate terminals of the activated transistors Mn1, Mp1, Mn2 and Mp2 at each stage. Therefore, even if a large load (causing a sudden drop in the voltage on the node N1 or N2) occurs in the charge pump circuit 200, these activated transistors are not easily deactivated. The detailed operation of the charge pump circuit will be provided below.

[0033] In some embodiments, the charge capacitor Cp1 includes a first terminal and a second terminal connected to the clock signal CLK and the node N1, respectively, and the node N1 is coupled between the transistor Mn1 and the transistor Mp1. Similarly, the charge capacitor Cp2 includes a first terminal and a second terminal connected to the clock signal CLKB and the node N2, respectively, and the node N2 is coupled between the transistor Mn2 and the transistor Mp2.

[0034] The source / drain terminal of the auxiliary transistor Mg3 is connected to the gate terminal of the transistor Mn2 and the node N1, respectively. The source / drain terminal of the auxiliary transistor Mg4 is connected to the node N1 and the gate terminal of the transistor Mp2, respectively. The source / drain terminal of the auxiliary transistor Mg1 is connected to the gate terminal of the transistor Mn1 and the node N2, respectively. The source / drain terminal of the transistor Mg2 is connected to the node N2 and the gate terminal of the transistor Mp1, respectively. More specifically, the auxiliary transistor Mg4 includes a gate terminal, a source terminal, and a drain terminal connected to the node N1, the gate terminal of the transistor Mp2, and the node N2, respectively. The auxiliary transistor Mg2 includes a gate terminal, a source terminal, and a drain terminal connected to the node N2, the gate terminal of the transistor Mp1, and the node N1, respectively.

[0035] The auxiliary transistor Mg3 includes a gate terminal, a source terminal, and a drain terminal connected to the node N2, the gate terminal of the transistor Mn2, and the node N1, respectively. The auxiliary transistor Mg1 includes a gate terminal, a source terminal, and a drain terminal connected to the node N1, the gate terminal of the transistor Mn1, and the node N2, respectively.

[0036] The input node connected to the source / drain terminal of transistors Mn2 and Mn1 is configured to receive an input voltage VIN (or a first reference voltage). The output node connected to the source / drain terminal of transistors Mp2 and Mp1 is configured to provide an output voltage VOUT. In some embodiments, the output node can be connected to a capacitor Cout. In some embodiments, the input node and the output node can be connected to ground through capacitors Cin and Cout, respectively.

[0037] As shown, the auxiliary capacitor Cg1 is configured to connect the clock signal CLK to the gate terminal of the transistor Mn2. The auxiliary capacitor Cg2 is configured to connect the clock signal CLK to the gate terminal of the transistor Mp2. The auxiliary capacitor Cg3 is configured to connect the clock signal CLKB to the gate terminal of the transistor Mn1. The auxiliary capacitor Cg4 is configured to connect the clock signal CLKB to the gate terminal of the transistor Mp1.

[0038] Auxiliary capacitors Cg1, Cg2, Cg3, and Cg4 have a first size, and charge capacitors Cp1 and Cp2 have a second size. In some embodiments, the first size is smaller than the second size. Auxiliary transistors Mg1, Mg2, Mg3, and Mg4 have a first size, and transistors Mn1, Mn2, Mp1, and Mp2 have a second size. In some embodiments, the first size is smaller than the second size.

[0039] In some embodiments, transistors Mn1, Mn2, Mg1, and Mg3 have a first conductivity type, and transistors Mp1, Mp2, Mg2, and Mg4 have a second conductivity type different from the first conductivity type. For example, the first conductivity type is n-type, and the second conductivity type is p-type. For example, the first conductivity type is p-type, and the second conductivity type is n-type.

[0040] Figure 3A It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit 200 in a memory device. More specifically, Figure 3A Shown in FIG. 2 may be a charge pump circuit 200 in a first stage. Figure 3B According to some embodiments, Figure 3A An example waveform 300 associated with the charge pump circuit 200 is shown.

[0041] In the first stage, transistors Mn2, Mp1, Mg4 and Mg1 are turned off, and transistors Mp2, Mn1, Mg3 and Mg2 are turned on, thereby isolating the gate terminal of transistor Mn1 from node N2. In the first stage, the clock signal CLK is provided in a first logic state. For example, Figure 3B As shown, the clock signal CLK in the first phase may be at a "logic low" (eg, 0V). In the first phase, the clock signal CLKB is provided at a second logic state. Figure 3B As shown, the clock signal CLKB in the first stage may be at a "logic high" (eg, VDDIO). The clock signal CLK and the clock signal CLKB may be logically opposite to each other. For example, Figure 3B As shown and described below, in the second phase, the clock signal CLK is provided at a second logic state (eg, "logic high", VDDIO, etc.), and the clock signal CLKB is provided at a first logic state (eg, "logic low", 0V, etc.).

[0042] In the first phase, the current 320 flowing through the transistor Mn1 and the current 325 flowing through the auxiliary transistor Mg3 can charge the charge transfer capacitor Cp1. Similarly, the charge transfer capacitor Cp2 can contain a charge (e.g., the charge transfer capacitor Cp2 has been charged in the previous second phase, as described with respect to Figure 4A and Figure 4BAs discussed). The charge pump circuit 200 with the charged charge transfer capacitor Cp2 can output a current 330 through the transistor Mp2 and the output node. Since the voltage across the capacitor cannot change immediately, the charge transfer capacitor Cp2 can be maintained at the voltage of the first stage (e.g., VDDIO). In order to maintain the voltage across it, the charge transfer capacitor Cp1 forces the voltage VOUT at the output node to be equal to 2×(the voltage of the first stage (e.g., VDDIO)), making the equivalent voltage across the capacitor Cp2 equal to the first stage (e.g., VDDIO) voltage. This allows a first voltage (e.g., VIN) at the input node to be pumped to a second voltage (e.g., VOUT) at the output node. For example, the second voltage (e.g., VOUT) can be a multiple of the first voltage (e.g., VIN). For example, VOUT=2×VIN.

[0043] In the first stage, the turned-off auxiliary transistor Mg1 can isolate the node NG1N from the node N2, so that the node NG1N is maintained at a higher voltage than the node N2. Figure 3B As shown, the voltage 310 of the node NG1N can be maintained at a higher voltage than the voltage 315 of the node N2. This allows the voltage difference between the gate terminal and the source terminal of the transistor Mn1 to remain greater than the threshold voltage of the transistor Mn1. The higher voltage difference between the gate terminal and the source terminal of the transistor Mn1 allows the charge pump circuit 200 to sustain a larger current load, such as Figure 5 shown.

[0044] Likewise, the turned-off auxiliary transistor Mg4 can isolate the node NG2P from the node N1, thereby maintaining the node NG2P at a higher voltage than the node N1. This allows the voltage difference between the gate terminal and the source terminal of the transistor Mp2 to remain greater than the threshold voltage of the transistor Mp2. The higher voltage difference between the gate terminal and the source terminal of the transistor Mp2 allows the charge pump circuit 200 to sustain a larger current load, such as Figure 5 shown.

[0045] Figure 4A It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit 200 in a memory device. More specifically, Figure 4A Shown in FIG. 2 may be the charge pump circuit 200 in the second stage. Figure 4B According to some embodiments, Figure 4A An example waveform 400 associated with the charge pump circuit 200 is shown.

[0046] In the second stage, transistors Mn2, Mp1, Mg4 and Mg1 are turned on, and transistors Mp2, Mn1, Mg3 and Mg2 are turned off, thereby isolating the gate terminal of transistor Mp1 from node N2. In the second stage, the clock signal CLKB is provided in the first logic state. For example, Figure 4B As shown, the clock signal CLKB in the second phase may be in a "logic low" state (eg, 0V). In the second phase, the clock signal CLK is provided in a second logic state. Figure 4B As shown, the clock signal CLK of the second phase may be at a "logic high" (eg, VDDIO). The clock signal CLKB and the clock signal CLK may be logically opposite to each other. For example, Figure 3B As shown, in the first phase, the clock signal CLKB is provided at a first logic state (eg, “logic high”, VDDIO, etc.), and the clock signal CLK is provided at a second logic state (eg, “logic low”, 0V, etc.).

[0047] In the second phase, the current 420 flowing through the transistor Mn2 and the current 425 flowing through the auxiliary transistor Mg1 can charge the charge transfer capacitor Cp2. Figure 3A and Figure 3B As discussed, the charge transfer capacitor Cp2 charged in the second phase can be used to pump the input voltage VIN to the output voltage VOUT in the first phase. Similarly, the charge pump circuit 200 having the charge transfer capacitor Cp1 charged in the first phase can output the current 430 through the transistor Mp1 and the output node. Since the voltage across the capacitor cannot change immediately, the charge transfer capacitor Cp1 can be maintained at the voltage (e.g., VDDIO) in the second phase. In order to maintain the voltage across it, the charge transfer capacitor Cp1 forces the voltage VOUT at the output node to be equal to 2×(the voltage (e.g., VDDIO) in the second phase), making the equivalent voltage across the capacitor Cp2 equal to the voltage (e.g., VDDIO) in the second phase. This allows the first voltage (e.g., VIN) at the input node to be pumped to the second voltage (e.g., VOUT) at the output node. For example, the second voltage (e.g., VOUT) can be a multiple of the first voltage (e.g., VIN). For example, VOUT=2×VIN.

[0048] In the second phase, the turned-off transistor Mg2 can isolate the node NG1P from the node N2, thereby maintaining the node NG1P at a voltage lower than the node N2. Figure 4B As shown, the voltage 410 of the node NG1P can be maintained at a voltage lower than the voltage 415 of the node N2. This allows the voltage difference between the gate terminal and the source terminal of the transistor Mp1 to remain greater than the threshold voltage of the transistor Mp1. The higher voltage difference between the gate terminal and the source terminal of the transistor Mp1 allows the charge pump circuit 200 to sustain a larger current load, such as Figure 5 shown.

[0049] Likewise, the turned-off auxiliary transistor Mg3 can isolate the node NG2N from the node N1, thereby maintaining the node NG2N at a voltage lower than the node N1. This allows the voltage difference between the gate terminal and the source terminal of the transistor Mn2 to remain greater than the threshold voltage of the transistor Mn2. The higher voltage difference between the gate terminal and the source terminal of the transistor Mn2 allows the charge pump circuit 200 to maintain a larger current load.

[0050] Transistors Mn2, Mp1, Mg4, and Mg1 may be configured to be activated alternately (e.g., alternately operate in the first phase and the second phase) relative to transistors Mn1, Mp2, Mg3, and Mg2 to boost the output voltage (e.g., VOUT) to a multiple of the input voltage (e.g., VIN). For example, alternating clock signals CLK and CLKB that are opposite to each other may be provided to configure the charge pump circuit 200 to operate in the first phase and the second phase.

[0051] In some embodiments, the voltage difference between the gate terminal and the source terminal of transistor Mn1 is greater than the voltage difference between the gate terminal and the source terminal of transistor Mp1. In some embodiments, the voltage difference between the gate terminal and the source terminal of transistor Mn1 is greater than the threshold voltage of transistor Mp1.

[0052] Figure 5 shows that according to some embodiments, Figure 1 An example voltage graph 500 is shown in connection with an example charge pump circuit in a memory device of the present invention. The voltage graph 500 shows the relationship between the voltage output (e.g., VOUT) at the output node and the current load at the output node. For example, the voltage graph 500 can be the voltage output (e.g., VOUT) at the output node of the charge pump circuit 200 relative to the current load.

[0053] As about Figure 2 As discussed in FIG. 4 , the operation of auxiliary transistors Mg1, Mg2, Mg3, and Mg4 and auxiliary capacitors Cg1, Cg2, Cg3, and Cg4 may be operably coupled to assist switches Mn1, Mn2, Mp1, Mp2, and capacitors Cp1 and Cp2. By operating the auxiliary switches and auxiliary capacitors, NMOS (e.g. Figure 2 The Vgs of transistor Mn1 in the PMOS (e.g. Figure 2 The Vsg of the transistor Mp1 can be maintained at a higher voltage (e.g., compared to the threshold voltage of the corresponding MOS device). The higher Vgs (or Vsg) enables the charge pump circuit to operate at lower current loads (e.g., Figure 5 The dashed line in the figure) does not need to turn off the MOS device. This allows the charge pump circuit to handle larger current loads (e.g. Figure 5 The dashed line in the figure) improves the driving capability of the charge pump circuit.

[0054] Fig. 6A It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit 600 in a memory device of FIG. 6A . For example, the charge pump circuit 600 may be part of the voltage supply circuit 110 . Figure 6B According to some embodiments, Fig. 6A Example waveforms associated with the charge pump circuit 600 .

[0055] The charge pump circuit 600 may be substantially similar to the charge pump circuit 200 and / or include features of the charge pump circuit without one or more auxiliary transistors (e.g., transistors Mg1 and Mg3) and one or more auxiliary capacitors (Cg1 and Cg3). That is, the charge pump circuit 600 may include auxiliary transistors Mg2 and Mg4, and auxiliary capacitors Cg2 and Cg4 on only one side thereof. For example, Fig. 6A As shown, the charge pump circuit 600 includes auxiliary transistors Mg2 and Mg4 and auxiliary capacitors Cg2 and Cg4 only on the p-type side, wherein the transistors Mp1, Mp2, Mg2 and Mg4 may be PMOS devices. In this case, in the first stage, the turned-off auxiliary transistor Mg2 may isolate the node NG1P from the node N2, thereby maintaining the node NG1P at a voltage lower than the node N2. For example, Figure 6B As shown, the voltage 610 of the node NG1P can be maintained at a voltage lower than the voltage 615 of the node N2. In the second stage, the turned-off auxiliary transistor Mg4 can isolate the node NG2P from the node N1. The transistors Mp1 and Mg4 can be configured to be alternately activated relative to the transistors Mp2 and Mg2 (e.g., alternately operate in the first stage and the second stage) so as to boost the output voltage (e.g., VOUT) to a multiple of the input voltage (e.g., VIN). For example, alternating clock signals CLK and CLKB that are opposite to each other can be provided to configure the charge pump circuit 600 to operate in the first stage and the second stage.

[0056] In some embodiments, although Fig. 6A and Figure 6B Although not shown, the charge pump circuit 600 may include auxiliary transistors Mg1 and Mg3 and auxiliary capacitors Cg1 and Cg3 only on the n-type side of the charge pump circuit 500 , where the transistors Mn1 , Mn2 , Mg1 , and Mg3 may be NMOS devices.

[0057] Fig. 7A and Figure 7B It is shown that according to some embodiments, it may be included in Figure 1Schematic diagram of an example charge pump circuit 700 in a memory device. For example, the charge pump circuit 700 can be part of the voltage supply circuit 110. More specifically, Fig. 7A An example charge pump circuit 700 is shown in the first stage, Figure 7B The same circuit in the second stage is shown. Figure 7C According to some embodiments, Fig. 7A and Figure 7B Example waveforms associated with the charge pump circuit 700.

[0058] The charge pump circuit 700 may be similar to and / or include Figure 2 . The charge pump circuit 700 may be a charge pump circuit 200 that outputs a negative voltage lower than an input voltage. Like the charge pump circuit 200, the charge pump circuit 700 includes transistors Mn1, Mn2, Mp1, and Mp2, auxiliary transistors Mg1, Mg2, Mg3, and Mg4; charge transfer capacitors Cp1 and Cp2; and auxiliary capacitors Cg1, Cg2, Cg3, and Cg4, as shown in FIG. Fig. 7A and Figure 7B shown.

[0059] refer to Fig. 7A In the first stage, transistors Mn2, Mp1, Mg4 and Mg1 are turned off, and transistors Mp2, Mn1, Mg3 and Mg2 are turned on, thereby isolating the gate terminal of transistor Mn1 from node N2. In the first stage, the clock signal CLK is provided in a first logic state. For example, Figure 7C As shown, the clock signal CLK in the first phase may be at a "logic low" (eg, 0V). In the first phase, the clock signal CLKB is provided at a second logic state. Figure 7C As shown, the clock signal CLKB in the first stage may be at a "logic high" (eg, VDDIO). The clock signal CLK and the clock signal CLKB may be logically opposite to each other. For example, Figure 7B As shown and described below, in the second phase, the clock signal CLK is provided at a second logic state (eg, "logic high", VDDIO, etc.) and the clock signal CLKB is provided at a first logic state (eg, "logic low", 0V, etc.).

[0060] In the first phase, the current 720 flowing through the transistor Mn1 and the current 725 flowing through the auxiliary transistor Mg3 can charge the charge transfer capacitor Cp1. Similarly, the charge transfer capacitor Cp2 may contain a charge (for example, the charge transfer capacitor Cp2 has been charged in the previous second phase, such as Figure 7BAs shown). The charge pump circuit 700 with the charged charge transfer capacitor Cp2 can output a current 730 (i.e., a negative voltage at the output node) through the transistor Mp2 and the input node. For example, the charge pump circuit 700 can pump a first voltage (e.g., VSS) at the input node to a second voltage (e.g., VOUT) at the output node, where the second voltage is a negative voltage lower than the first voltage. For example, the second voltage (e.g., VOUT<0) can be a multiple of the first voltage (e.g., VSS<0). For example, VOUT=2×VSS.

[0061] In the first stage, the turned-off auxiliary transistor Mg1 can isolate the node NG1N from the node N2, so that the node NG1N is maintained at a higher voltage than the node N2. Figure 7C As shown, the voltage 710 of the node NG1N can be maintained at a higher voltage than the voltage 712 of the node N2. This allows the voltage difference between the gate terminal and the source terminal of the transistor Mn1 to remain greater than the threshold voltage of the transistor Mn1. The higher voltage difference between the gate terminal and the source terminal of the transistor Mn1 allows the charge pump circuit 700 to sustain a larger current load.

[0062] refer to Figure 7B In the second stage, transistors Mn2, Mp1, Mg4 and Mg1 are turned on, and transistors Mp2, Mn1, Mg3 and Mg2 are turned off, thereby isolating the gate terminal of transistor Mp1 from node N2. In the second stage, the clock signal CLKB is provided in the first logic state. For example, Figure 7C As shown, the clock signal CLKB in the second phase may be in a "logic low" state (eg, 0V). In the second phase, the clock signal CLK is provided in a second logic state. Figure 7C As shown, the clock signal CLK of the second stage may be at a "logic high" (eg, VDDIO). The clock signal CLKB and the clock signal CLK may be logically opposite to each other. For example, Fig. 7A As shown, in the first phase, the clock signal CLKB is provided at a first logic state (eg, “logic high”, VDDIO, etc.), and the clock signal CLK is provided at a second logic state (eg, “logic low”, 0V, etc.).

[0063] In the second phase, the current 760 flowing through the transistor Mn2 and the current 765 flowing through the auxiliary transistor Mg1 can charge the charge transfer capacitor Cp2. Fig. 7AAs shown, the charge transfer capacitor Cp2 charged in the second stage can be used to pump the input voltage VSS to the output voltage VOUT in the first stage. Similarly, the charge pump circuit 700 having the charge transfer capacitor Cp1 charged in the first stage can output the current 770 (i.e., the negative voltage at the output node) through the transistor Mp1 and the input node. For example, the charge pump circuit 700 can pump the first voltage (e.g., VSS) at the input node to the second voltage (e.g., VOUT) at the output node, and the second voltage is a negative voltage lower than the first voltage. For example, the second voltage (e.g., VOUT < 0) can be a multiple of the first voltage (e.g., VSS < 0). For example, VOUT = 2 × VSS.

[0064] In the second stage, the turned-off auxiliary transistor Mg2 can isolate the node NG1P from the node N2, thereby maintaining the node NG1P at a voltage lower than the node N2. Figure 7C As shown, the voltage 715 of the node NG1P can be maintained at a voltage lower than the voltage 717 of the node N2. This allows the voltage difference between the gate terminal and the source terminal of the transistor Mp1 to remain greater than the threshold voltage of the transistor Mp1. The higher voltage difference between the gate terminal and the source terminal of the transistor Mp1 allows the charge pump circuit 700 to maintain a larger current load.

[0065] like Fig. 7A and Figure 7B As shown, transistors Mp1, Mn2, Mg4 and Mg1 can be configured to be alternately activated relative to transistors Mn1, Mp2, Mg3 and Mg2 (e.g., alternately operate in the first stage and the second stage) to increase the output voltage (e.g., VOUT) to a multiple of the input voltage (e.g., VSS). For example, alternating clock signals CLK and CLKB that are opposite to each other can be provided to configure the charge pump circuit 700 to operate in the first stage and the second stage.

[0066] Fig. 8A It is shown that according to some embodiments, it may be included in Figure 1 Schematic diagram of an example charge pump circuit 800 in a memory device of FIG. 8A . For example, the charge pump circuit 800 may be part of the voltage supply circuit 110 . Figure 8B According to some embodiments, Fig. 8A Example waveform 850 associated with a charge pump circuit.

[0067] The charge pump circuit 800 may be substantially similar to the charge pump circuit 700 and / or include components of the charge pump circuit without one or more auxiliary transistors (e.g., transistors Mg1 and Mg3) and one or more auxiliary capacitors (Cg1 and Cg3). That is, the charge pump circuit 800 that can output a negative voltage lower than the input voltage may include auxiliary transistors Mg2 and Mg4 and auxiliary capacitors Cg2 and Cg4 only on one side of the charge pump circuit 900. For example, Fig. 8A As shown, the charge pump circuit 800 includes auxiliary transistors Mg2 and Mg4 and auxiliary capacitors Cg2 and Cg4 only on its p-type side, wherein the transistors Mp1, Mp2, Mg2 and Mg4 may be PMOS devices. In this case, in the first stage, the turned-off auxiliary transistor Mg2 may isolate the node NG1P from the node N2, thereby maintaining the node NG1P at a voltage lower than the node N2. For example, Figure 8B As shown, the voltage 810 of the node NG1P can be maintained at a voltage lower than the voltage 815 of the node N2. In the second stage, the turned-off auxiliary transistor Mg4 can isolate the node NG2P from the node N1. The transistors Mp1 and Mg4 can be configured to be alternately activated relative to the transistors Mp2 and Mg2 (e.g., alternately operate in the first stage and the second stage) so as to boost the output voltage (e.g., VOUT) to a multiple of the input voltage (e.g., VSS). For example, alternating clock signals CLK and CLKB that are opposite to each other can be provided to configure the charge pump circuit 800 to operate in the first stage and the second stage.

[0068] In some embodiments, although Fig. 8A and Figure 8B Although not shown, the charge pump circuit 800 may include auxiliary transistors Mg1 and Mg3 and auxiliary capacitors Cg1 and Cg3 only on the n-type side of the charge pump circuit 800 , where the transistors Mn1 , Mn2 , Mg1 , and Mg3 may be NMOS devices.

[0069] Fig. 9 It is shown that according to some embodiments, the operation may include Figure 1 Flowchart of an example method 900 for an example charge pump circuit in a memory device. At least one operation of method 900 may be performed with a charge pump circuit disclosed herein (e.g., Figure 2 It should be noted that method 900 is only an example and is not intended to limit the present disclosure. Therefore, it can be understood that in Fig. 9 Additional operations may be provided before, during, and after method 900, and some other operations may only be briefly described herein.

[0070] Method 900 starts with operation 910 of providing a charge pump circuit (e.g., charge pump circuit 200, 600, 700, 800), the charge pump circuit including first, second, third and fourth transistors (e.g., transistors Mn2, Mp2, Mn1 and Mp1, etc.) and first and second charge capacitors (e.g., capacitors Cp1, Cp2, etc.). In operation 910, the corresponding gate terminals of the first transistor and the second transistor can be connected to a first node (e.g., N2), the first node is configured to receive a first clock signal through a first charge capacitor, and the corresponding gate terminals of the third transistor and the fourth transistor can be connected to a second node (e.g., N1), the second node is configured to receive a second clock signal that is logically opposite to the first clock signal through a second charge capacitor. In some embodiments, operation 910 may include providing a fifth transistor (e.g., auxiliary transistor Mg3). The source / drain terminals of the fifth transistor are respectively connected to the gate terminal and the first node of the first transistor. In some embodiments, operation 910 may include providing a sixth (e.g., auxiliary transistor Mg4) transistor. The source / drain terminals of the sixth transistor are respectively connected to the first node and the gate terminal of the second transistor. In some embodiments, operation 910 may include providing a seventh transistor (e.g., an auxiliary transistor Mg1). The source / drain terminal of the seventh transistor is connected to the gate terminal of the third transistor and the second node, respectively. In some embodiments, operation 910 may include providing an eighth transistor (e.g., an auxiliary transistor Mg2). The source / drain terminal of the eighth transistor is connected to the second node and the gate terminal of the fourth transistor, respectively. In some embodiments, the first, second, third, and fourth auxiliary capacitors have a first size, and the first and second charge capacitors have a second size, wherein the first size is less than the second size. In some embodiments, the fifth, sixth, seventh, and eighth transistors have a first size, and the first, second, third, and fourth transistors have a second size, wherein the first size is less than the second size. In some embodiments, the first, third, fifth, and seventh transistors have a first conductivity type, and the second, fourth, sixth, and eighth transistors have a second conductivity type different from the first conductivity type.

[0071] Method 900 can continue to operation 920, in the first stage, by activating the second and third transistors and disabling the first and fourth transistors, the first node and the second node are charged to the first multiple of the power supply voltage and the power supply voltage, respectively. In operation 920, by disabling at least the fifth transistor (e.g., auxiliary transistor Mg1), the first node is isolated from the gate terminal of the third transistor. The turned-off fifth transistor allows the voltage difference between the gate terminal and the source terminal of the corresponding transistor (e.g., transistor Mn1) to remain greater than the threshold voltage of the transistor. In some embodiments, the gate terminal, source terminal, and drain terminal of the fifth transistor are respectively connected to the second node, the first node, and the gate terminal of the third transistor.

[0072] Method 900 may continue with operation 930, in which, in a second stage, the first node and the second node are charged to the power supply voltage and the second multiple of the power supply voltage, respectively, by activating the first and fourth transistors and disabling the second and third transistors. In operation 930, the first node is isolated from the gate terminal of the fourth transistor by disabling at least the sixth transistor (e.g., the auxiliary transistor Mg2). The turned-off sixth transistor allows the voltage difference between the gate terminal and the source terminal of the corresponding transistor (e.g., transistor Mp1) to remain greater than the threshold voltage of the transistor. In some embodiments, the gate terminal, source terminal, and drain terminal of the sixth transistor are respectively connected to the second node, the first node, and the gate terminal of the fourth transistor. In some embodiments, the first, third, and fifth transistors all have n-type conductivity, and the second, fourth, and sixth transistors all have p-type conductivity.

[0073] In one aspect of the present disclosure, a circuit is disclosed. The circuit includes a first transistor and a second transistor coupled to each other in series between an input node and an output node, wherein the respective gate terminals of the first transistor and the second transistor are connected to a first node, the first node being configured to receive a first clock signal through a first charge capacitor; a third transistor and a fourth transistor coupled to each other in series between the input node and the output node, wherein the gate terminal of the third transistor and the gate terminal of the fourth transistor are respectively connected to a second node, the second node being configured to receive a second clock signal that is logically opposite to the first clock signal through a second charge capacitor; a fifth transistor, whose source / drain terminal is coupled between the gate terminal of the first transistor and the first node; a sixth transistor, whose source / drain terminal is coupled between the first node and the gate terminal of the second transistor; a seventh transistor, whose source / drain terminal is coupled between the gate terminal of the third transistor and the second node; and an eighth transistor, whose source / drain terminal is coupled between the second node and the gate terminal of the fourth transistor.

[0074] In some embodiments, the circuit also includes: a first gate capacitor configured to connect the first clock signal to the gate terminal of the first transistor; a second gate capacitor configured to connect the first clock signal to the gate terminal of the second transistor; a third gate capacitor configured to connect the second clock signal to the gate terminal of the third transistor; and a fourth gate capacitor configured to connect the second clock signal to the gate terminal of the fourth transistor.

[0075] In some embodiments, the first gate capacitor, the second gate capacitor, the third gate capacitor, and the fourth gate capacitor have a first size, the first charge capacitor and the second charge capacitor have a second size, and the first size is smaller than the second size.

[0076] In some embodiments, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have a first size, the first transistor, the second transistor, the third transistor, and the fourth transistor have a second size, and the first size is smaller than the second size.

[0077] In some embodiments, the first transistor, the third transistor, the fifth transistor, and the seventh transistor have a first conductivity type, and the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor have a second conductivity type different from the first conductivity type.

[0078] In some embodiments, in a first stage of providing the first clock signal in a first logic state, the first transistor, the fourth transistor, the sixth transistor, and the seventh transistor are turned off, and the second transistor, the third transistor, the fifth transistor, and the eighth transistor are turned on, thereby isolating at least the gate terminal of the third transistor from the second node.

[0079] In some embodiments, in the first phase, a voltage difference between a gate terminal and a source terminal of the third transistor is expanded to be maintained greater than a threshold voltage of the third transistor.

[0080] In some embodiments, in a second phase of providing the first clock signal in a second logic state, the first transistor, the fourth transistor, the sixth transistor, and the seventh transistor are turned on, while the second transistor, the third transistor, the fifth transistor, and the eighth transistor are turned off, thereby isolating at least the gate terminal of the fourth transistor from the second node.

[0081] In some embodiments, in the second phase, a voltage difference between a gate terminal and a source terminal of the fourth transistor is expanded to be maintained greater than a threshold voltage of the fourth transistor.

[0082] In some embodiments, a first voltage at the input node is configured to be pumped to a second voltage at the output node, the second voltage being a multiple of the first voltage.

[0083] In another aspect of the present disclosure, a circuit is disclosed. The circuit includes a first charge capacitor having a first end and a second end connected to a first clock signal and a first common node, respectively, wherein the first common node is coupled between a first transistor and a second transistor; a second charge capacitor having a first end and a second end connected to a second clock signal and a second common node, respectively, wherein the second clock signal is logically opposite to the first clock signal, wherein a third common node is coupled between a third transistor and a fourth transistor; a fifth transistor, whose gate end, source end, and drain end are connected to the first common node, the gate end of the second transistor, and the second common node, respectively, wherein the fifth transistor and the second transistor both have a first conductivity type; and a sixth transistor, whose gate end, source end, and drain end are connected to the second common node, the gate end of the fourth transistor, and the first common node, respectively, wherein the sixth transistor and the fourth transistor both have a first conductivity type; wherein the second and third transistors are configured to be activated alternately relative to the first and fourth transistors so as to boost the output voltage to a multiple of the input voltage.

[0084] In some embodiments, the circuit also includes: a seventh transistor, the gate terminal, the source terminal and the drain terminal of the seventh transistor are respectively connected to the second common node, the gate terminal of the first transistor and the first common node, wherein the seventh transistor and the first transistor both have a second conductivity type different from the first conductivity type; and an eighth transistor, the gate terminal, the source terminal and the drain terminal of the eighth transistor are respectively connected to the first common node, the gate terminal of the third transistor and the second common node, wherein the eighth transistor and the third transistor both have the second conductivity type.

[0085] In some embodiments, the fifth transistor and the sixth transistor have a first size, the first transistor, the second transistor, the third transistor, and the fourth transistor have a second size, and the first size is smaller than the second size.

[0086] In some embodiments, the circuit further includes: a first gate capacitor configured to connect the first clock signal to the gate terminal of the second transistor; and a second gate capacitor configured to connect the second clock signal to the gate terminal of the fourth transistor.

[0087] In some embodiments, the first gate capacitor and the second gate capacitor have a first size, the first charge capacitor and the second charge capacitor have a second size, and the first size is smaller than the second size.

[0088] In some embodiments, the first voltage difference is greater than the second voltage difference, and the first voltage difference is a voltage difference between a gate terminal and a source terminal of the third transistor, and the second voltage difference is a voltage difference between a gate terminal and a source terminal of the fourth transistor.

[0089] In some embodiments, the first voltage difference is greater than a threshold voltage of the fourth transistor.

[0090] In another aspect of the present disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes providing a charge pump circuit, the charge pump circuit including first, second, third and fourth transistors, and first and second charge capacitors, wherein the first and second transistors are coupled in series with each other at a first node, the third and fourth transistors are coupled in series with each other at a second node, and wherein the first node is connected to a first clock signal through the first charge capacitor, and the second node is connected to a second clock signal through the second charge capacitor, and the second clock signal is logically opposite to the first clock signal; in a first stage, by activating the second and third transistors and deactivating the first and fourth transistors, the first node and the second node are charged to a first multiple of a power supply voltage and a power supply voltage, respectively; in a second stage, by activating the first and fourth transistors and deactivating the second and third transistors, the first node and the second node are charged to a power supply voltage and a second multiple of the power supply voltage, respectively; wherein during the first stage, by deactivating at least the fifth transistor, the first node is isolated from the gate terminal of the third transistor, and wherein during the second stage, at least the sixth transistor is deactivated to isolate the first node from the gate terminal of the fourth transistor.

[0091] In some embodiments, the gate terminal, source terminal and drain terminal of the fifth transistor are respectively connected to the second node, the first node and the gate terminal of the third transistor, and the gate terminal, source terminal and drain terminal of the sixth transistor are respectively connected to the second node, the first node and the gate terminal of the fourth transistor.

[0092] In some embodiments, the first transistor, the third transistor, and the fifth transistor all have n-type conductivity, and the second transistor, the fourth transistor, and the sixth transistor all have p-type conductivity.

[0093] As used herein, the terms "approximately" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "approximately" may refer to a value of a given quantity that varies, for example, within a range of 10% to 30% of a value (e.g., +10%, ±20%, or ±30% of a value).

[0094] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A circuit, include: a first transistor and a second transistor coupled in series with each other between an input node and an output node, wherein corresponding gate terminals of the first transistor and the second transistor are connected to a first node configured to receive a first clock signal through a first charge capacitor; a third transistor and a fourth transistor coupled in series with each other between the input node and the output node, wherein corresponding gate terminals of the third transistor and the fourth transistor are connected to a second node, the second node being configured to receive a second clock signal having a logic opposite to the first clock signal through a second charge capacitor; a fifth transistor, a source / drain terminal of the fifth transistor being coupled between the gate terminal of the first transistor and the first node; a sixth transistor having a source / drain terminal coupled between the first node and the gate terminal of the second transistor; a seventh transistor having a source / drain terminal coupled between the gate terminal of the third transistor and the second node; and An eighth transistor, a source / drain terminal of the eighth transistor being coupled between the second node and the gate terminal of the fourth transistor.

2. The circuit according to claim 1, further comprising: include: a first gate capacitor configured to connect the first clock signal to a gate terminal of the first transistor; a second gate capacitor configured to connect the first clock signal to a gate terminal of the second transistor; a third gate capacitor configured to connect the second clock signal to a gate terminal of the third transistor; as well as A fourth gate capacitor is configured to connect the second clock signal to the gate terminal of the fourth transistor.

3. The circuit according to claim 2, in, The first gate capacitor, the second gate capacitor, the third gate capacitor, and the fourth gate capacitor have a first size, the first charge capacitor and the second charge capacitor have a second size, and the first size is smaller than the second size.

4. The circuit according to claim 1, in, The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have a first size, the first transistor, the second transistor, the third transistor, and the fourth transistor have a second size, and the first size is smaller than the second size.

5. The circuit according to claim 1, in, The first transistor, the third transistor, the fifth transistor, and the seventh transistor have a first conductivity type, and the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor have a second conductivity type different from the first conductivity type.

6. A circuit, include: a first charge capacitor, a first terminal and a second terminal of the first charge capacitor being connected to a first clock signal and a first common node, respectively, wherein the first common node is coupled between the first transistor and the second transistor; a second charge capacitor having a first terminal and a second terminal connected to a second clock signal and a second common node, respectively, wherein the second clock signal is logically opposite to the first clock signal, wherein the second common node is coupled between the third transistor and the fourth transistor; a fifth transistor, a gate terminal, a source terminal, and a drain terminal of the fifth transistor being respectively connected to the first common node, the gate terminal of the second transistor, and the second common node, wherein the fifth transistor and the second transistor both have a first conductivity type; and a sixth transistor, a gate terminal, a source terminal, and a drain terminal of the sixth transistor being connected to the second common node, the gate terminal of the fourth transistor, and the first common node, respectively, wherein the sixth transistor and the fourth transistor both have the first conductivity type; The second transistor and the third transistor are configured to be activated alternately relative to the first transistor and the fourth transistor so as to boost the output voltage to a multiple of the input voltage.

7. The circuit according to claim 6, further comprising: include: a seventh transistor having a gate terminal, a source terminal, and a drain terminal connected to the second common node, the gate terminal of the first transistor, and the first common node, respectively, wherein the seventh transistor and the first transistor both have a second conductivity type different from the first conductivity type; and An eighth transistor, a gate terminal, a source terminal and a drain terminal of the eighth transistor are respectively connected to the first common node, the gate terminal of the third transistor and the second common node, wherein the eighth transistor and the third transistor both have the second conductivity type.

8. A method for operating a charge pump circuit, include: providing a charge pump circuit including a first transistor, a second transistor, a third transistor and a fourth transistor and a first charge capacitor and a second charge capacitor, wherein the first transistor and the third transistor are coupled in series with each other at a first node, the third transistor and the fourth transistor are coupled in series with each other at a second node, and the first node is connected to a first clock signal through a first charge capacitor, the second node is connected to a second clock signal through a second charge capacitor, and the second clock signal is logically opposite to the first clock signal; In a first phase, the first node and the second node are charged to a first multiple of a power supply voltage and the power supply voltage, respectively, by activating the second transistor and the third transistor and deactivating the first transistor and the fourth transistor; and In a second phase, the first node and the second node are charged to the power supply voltage and a second multiple of the power supply voltage, respectively, by activating the first transistor and the fourth transistor and deactivating the second transistor and the third transistor; During the first phase, the first node is isolated from the gate terminal of the third transistor by disabling at least the fifth transistor, and during the second phase, the first node is isolated from the gate terminal of the fourth transistor by disabling at least the sixth transistor.

9. The method according to claim 8, in, The gate terminal, source terminal and drain terminal of the fifth transistor are respectively connected to the second node, the first node and the gate terminal of the third transistor, and the gate terminal, source terminal and drain terminal of the sixth transistor are respectively connected to the second node, the first node and the gate terminal of the fourth transistor.

10. The method according to claim 8, in, The first transistor, the third transistor, and the fifth transistor each have n-type conductivity, and the second transistor, the fourth transistor, and the sixth transistor each have p-type conductivity.

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