Memory device and operating method thereof

Abstract

A memory device and an operating method thereof are provided. The memory device includes: at least one swap circuit swapping a plurality of coded row addresses with a repair address using repair data; at least one register, wherein the at least one register is used for storing the repair data; a word line activation signal driver that receives the repair address and outputs a word line activation signal; and a sub word line driver that activates a corresponding sub word line in response to the word line activation signal.

Description

Technical Field

[0001] The inventive concept relates to a memory device, a memory system including the memory device, and an operating method of the memory device. Background Art

[0002] In general, as the miniaturization of dynamic random access memory (DRAM) manufacturing processes progresses, the incidence of memory cells with hard defects or soft defects (i.e., defective cells) increases. Here, a hard defective cell refers to a memory cell with a permanent defect, while a soft defective cell refers to a memory cell that is temporarily defective due to a slight defect. Summary of the invention

[0003] An aspect of the inventive concept is to provide a memory device that performs an address swap function during a repair operation, a memory system including the memory device, and an operating method of the memory device.

[0004] Another aspect of the inventive concept is to provide a memory device that efficiently uses repair resources during a repair operation, a memory system including the memory device, and an operating method of the memory device.

[0005] According to one aspect of the present invention, a memory device includes: at least one exchange circuit, which uses repair data to exchange multiple decoding row addresses with repair addresses; at least one register, which stores the repair data; a word line activation signal driver, which receives the repair address and outputs a word line activation signal; and a sub-word line driver, which activates a corresponding sub-word line in response to the word line activation signal.

[0006] According to another aspect of the inventive concept, a memory device includes: a plurality of sub-blocks implemented in a core-on-periphery (COP) structure; and a row decoder that controls the plurality of sub-blocks, wherein each of the plurality of sub-blocks includes a peripheral circuit located above a substrate, and the peripheral circuit includes a switching circuit that converts a plurality of decoded row addresses into one repair address using repair data.

[0007] According to another aspect of the inventive concept, a method for operating a memory device includes: receiving an address from an external device; determining whether the received address is a fault address; when the received address is a fault address, determining whether to use a swap circuit to swap the received address with a repair address; swapping the received address with the repair address; and performing access using the repair address, wherein the swap circuit swaps multiple addresses with the repair address using repair data.

[0008] According to another aspect of the inventive concept, a memory system includes multiple memory devices and a controller that controls the multiple memory devices, wherein each of the multiple memory devices includes: a swap circuit that uses repair data to swap multiple row addresses with one repair address; and a register that stores the repair data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram illustrating a memory device according to an embodiment of the inventive concept;

[0011] Figure 2 is a diagram illustrating a memory cell array according to an embodiment of the inventive concept;

[0012] Figure 3 is a diagram illustrating a row decoder according to an embodiment of the inventive concept;

[0013] Figure 4 is a diagram illustrating a word line driver according to an embodiment of the inventive concept;

[0014] Figure 5A is a diagram illustrating a repair operation using a swap circuit SWAP according to an embodiment of the inventive concept;

[0015] Figure 5B is a diagram illustrating a memory device having a COP structure according to an embodiment of the inventive concept;

[0016] Figure 6 is a flowchart illustrating a repair operation of a memory device according to an embodiment of the inventive concept;

[0017] Figure 7 is a diagram illustrating a memory device according to another embodiment of the present disclosure; and

[0018] Figure 8 is a diagram illustrating a memory system according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0019] The principles and embodiments of the present invention relate to a memory repair method related to an address-swapping function for implementing a redundant cell array.

[0020] In order to maximize the memory capacity of DRAM, a repair method of replacing a defective cell with a spare cell or a redundant cell provided separately from a normal cell is adopted as a method of repairing the defective cell. For example, a repair method of replacing a row including a defective cell with a spare row or a redundant row (referred to as row repair) or replacing a column including a defective cell with a spare column or a redundant column (referred to as column repair) is adopted.

[0021] The memory device according to the embodiment of the present invention, the memory system having the memory device and the operation method of the memory device can be implemented to provide the repair function of the row decoder and the address exchange function of each sub-word line driver component. The memory device can be configured as a core on the periphery (COP), and can include a circuit for exchanging addresses for each sub-block in the core and a register for storing exchange data. The memory device, the memory system and the operation method can use a repair data to perform multiple repair operations for each sub-block. For example, if a different number of faults occur in each sub-block, a repair operation can be performed in a sub-word line driver of the row decoder as frequently as the maximum number of sub-blocks (for example, once for each sub-block). Therefore, the memory device, the memory system and the operation method according to the embodiment can efficiently utilize the repair resources.

[0022] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0023] Figure 1 is a diagram illustrating a memory device 100 according to an embodiment of the inventive concept. Figure 1 , the memory device 100 may include a memory cell array 110 , a row decoder 120 , a column decoder 130 , and a repair control logic 140 .

[0024] In various embodiments, the memory cell array 110 may include a normal cell array NCA 112 in which a plurality of memory cells are arranged and a redundant cell array RCA 114 in which a plurality of redundant memory cells are arranged. In an embodiment, the normal cell array 112 may include a plurality of memory cells arranged at intersections of a plurality of word lines WL and a plurality of bit lines BL, respectively. Each of the plurality of memory cells may include a volatile memory cell or a nonvolatile memory cell.

[0025] In an embodiment, the redundant cell array 114 may be adjacent to the normal cell array 112 in the extension direction of the word lines WL. For example, the redundant cell array 114 may include a plurality of redundant memory cells respectively arranged at intersections of a plurality of redundant bit lines RBL and a plurality of word lines WL, wherein the word lines WL extend from the normal cell array 112. In an embodiment, the redundant cell array 114 may be adjacent to the normal cell array 112 in the extension direction of the bit lines BL. For example, the redundant cell array 114 may include a plurality of redundant memory cells respectively arranged at intersections of a plurality of redundant word lines RWL and a plurality of bit lines BL, wherein the bit lines BL extend from the normal cell array 112.

[0026] A defect may occur in at least one memory cell arranged in the normal cell array 112, wherein the defective cell may be a single bit, a weak cell, or a defective cell. The defective cell occurring in the normal cell array 112 may be replaced with a redundant memory cell included in the redundant cell array 114. This replacement operation is referred to as a "repair operation". Following the repair operation, read data may be stored in or read from the redundant memory cell.

[0027] In various embodiments, in response to a row address (RA), the row decoder 120 may select at least one word line from a plurality of word lines WL and activate the selected word line. In addition, in response to a row address match signal, the row decoder 120 may select at least one redundant word line from a plurality of redundant word lines RWL and activate the selected redundant word line. For example, the row decoder 120 may activate the corresponding redundant word line RWL in response to the row address match signal.

[0028] In various embodiments, the row decoder 120 may include at least one switching circuit SWAP configured to exchange a plurality of row addresses with a repair address, wherein one or more of the plurality of repair addresses may be utilized. At least one switching circuit SWAP may convert repair data (i.e., physically different addresses) into logically identical repair addresses for each sub-block. In addition, at least one switching circuit SWAP may interchange the decoded row address with the repair data. The repair data may be set according to power-on of the memory device 100 or may be provided by an external device. At least one switching circuit SWAP may be located in each of a plurality of memory blocks, wherein at least one switching circuit SWAP may be included in each of a plurality of sub-blocks. The row decoder 120 may be disposed on the left or right side of a plurality of memory blocks.

[0029] In various embodiments, in response to the column address CA, the column decoder 130 may select at least one bit line from among the plurality of bit lines BL and activate the selected bit line. In addition, in response to the column address match signal, the column decoder 130 may select at least one redundant bit line from among the plurality of redundant bit lines RBL and activate the selected redundant bit line. For example, in response to the column address match signal, the column decoder 130 may deactivate the column address CA and activate the redundant column bit line.

[0030] In various embodiments, the repair control logic 140 may be implemented to perform a repair operation on a defective cell among a plurality of storage cells. For example, when the input row address RA corresponds to a defective cell, the repair control logic 140 may generate a row address matching signal. In addition, when the input column address CA corresponds to a defective cell, the repair control logic 140 may generate a column address matching signal. In addition, the repair control logic 140 may change the scope of the repair area according to the type of fault. Here, the repair area is an area corresponding to a redundant address. For example, the repair control logic 140 may change the type or number of address bits corresponding to the defective cell. The repair control logic 140 may store repair mapping data about the type of address bits or the number of address bits in a non-volatile memory (e.g., a fuse).

[0031] Figure 2 is a diagram illustrating a memory cell array according to an embodiment of the inventive concept. Figure 2, the memory cell array may include a normal cell array NCA and a redundant cell array RCA. The normal cell array NCA 112 may include a plurality of memory cells arranged at the intersection between word lines WL1 to WLm (where m is a natural number greater than or equal to 2) and bit lines BL1 to BLn (where n is a natural number greater than or equal to 2). The redundant cell array RCA 114 may include a plurality of redundant memory cells arranged at the intersection between redundant word lines RWL1 to RWLi (where i is a natural number greater than or equal to 2) and redundant bit lines RBL1 to RBLj (where j is a natural number greater than or equal to 2). The memory cell array may include a plurality of memory cells, wherein the memory cells can be arranged at the intersection of word lines and bit lines. Here, each memory cell MC may include a selection transistor and a storage capacitor (e.g., a 1T1C cell). Each of the plurality of memory cells may include a vertical channel transistor (VCT) as a selection transistor. The selection transistor may be connected between the storage capacitor and the corresponding bit line, and operate in response to the voltage of the corresponding word line. The storage capacitor may be connected between the selection transistor and the first node, and may store data according to the operation of the selection transistor and the level of the bit line. In an embodiment, the selection transistor may be implemented as a vertical channel transistor VCT. Each of the plurality of memory cells may include a vertical channel transistor (VCT) oriented in a direction perpendicular to the substrate.

[0032] In various embodiments, Figure 2 The redundant word lines RWL1 to RWLi illustrated in FIG are arranged above the word lines WL1 to WLm. However, the positions of the redundant word lines RWL1 to RWLi are not limited thereto. The redundant word lines RWL1 to RWLi may be arranged below the word lines WL1 to WLm, or may be arranged as a group inserted between the word lines WL1 to WLm, or may be arranged as a plurality of groups located between the word lines WL1 to WLm.

[0033] In various embodiments, a memory device may include: a substrate including a cell region and a peripheral circuit region disposed on at least one side of the cell region; a plurality of cell transistors disposed in the cell region of the substrate; a peripheral circuit disposed in the peripheral circuit region of the substrate; an etch stop layer disposed in the cell region and the peripheral circuit region of the substrate and including a first portion disposed in the cell region and a second portion disposed in the peripheral circuit region; a capacitor structure disposed in the cell region of the substrate and including a plurality of lower electrodes connected to the plurality of cell transistors through a first portion of the etch stop layer and arranged at a first pitch along a first direction parallel to an upper surface of the substrate. The second portion of the etch stop layer may include a plurality of recesses arranged at a second pitch that is the same as the first pitch along the first direction.

[0034] at the same time, Figure 2 The redundant bit lines RBL1 to RBLj illustrated in FIG. 1 are arranged on the right side of the bit lines BL1 to BLn. However, the positions of the redundant bit lines RBL1 to RBLj are not limited thereto. The redundant bit lines RBL1 to RBLj may be arranged on the left side of the bit lines BL1 to BLn, or may be arranged as a group between the bit lines BL1 to BLn, or may be arranged as a plurality of groups between the bit lines BL1 to BLn.

[0035] In various embodiments, a sub-word line control signal generator that generates a sub-word line control signal PXI is disposed in the row decoder region. A normal word line driver NWD is disposed adjacent to the sub-word line control signal generator. Figure 4 As shown, a sub-word line control driver (PXI driver) that amplifies a sub-word line control signal PXI generated by a sub-word line control signal generator and supplies the amplified sub-word line control signal to a sub-word line driver SWD can be set in a junction area of ​​a memory core area. The sub-word line control driver can use a high voltage as a power supply voltage, and the output signal can be arranged at a high voltage. The sub-word line driver SWD drives the sub-word line in response to a main word line signal generated by a normal word line driver NWD and an output signal PXID from the sub-word line control driver. Here, since the sub-word line control signal PXI and the output signal PXID from the sub-word line control driver have the same voltage level and the output signal PXID from the sub-word line control driver is a signal amplified from the sub-word line control signal PXI, the signal will be collectively referred to as the sub-word line control signal PXI.

[0036] Figure 3 1 is a diagram illustrating a row decoder 120 according to an embodiment of the inventive concept. Figure 3 , the row decoder 120 may include a pre-decoder 121 and a word line driver 122. The plurality of word lines WL may include a plurality of sub-word lines. The plurality of sub-word lines may be grouped into a plurality of sub-word line groups. One sub-word line group may be connected to one main word line.

[0037] In various embodiments, the predecoder 121 may be configured to decode the input row address RA and generate a decoded row address DRA, wherein the decoded row address DRA can be provided to the word line driver 122. The predecoder 121 may be configured to receive a row address and decode the received row address to generate a decoded row address DRA. The decoded row address DRA may include a first decoded row address and a second decoded row address having predetermined bits. For a plurality of decoded row addresses, the number of the plurality of decoded row addresses may be 2. In an embodiment, the length of the first decoded row address may be 2 bits; however, it should be understood that the length of the first decoded row address is not limited thereto.

[0038] In various embodiments, the word line driver 122 may receive the decoded row address DRA and activate the corresponding word line WL. The word line driver 122 may include a sub-word line driver and a normal word line driver. The sub-word line driver may be configured to generate a sub-word line activation signal that controls activation or deactivation of a selected sub-word line, the selected sub-word line being selected in response to the first decoded row address. The normal word line driver may be configured to decode the second decoded row address and generate a word line activation signal to activate the selected normal word line.

[0039] In various embodiments, the word line driver 122 may be configured to activate a selected sub-word line in response to a sub-word line activation signal and a main word line activation signal. One of the plurality of sub-blocks may be configured to activate a sub-word line corresponding to a repair address according to a first decoded row address. Another sub-block of the plurality of sub-blocks may activate the sub-word line for activating the repair address according to a second decoded row address. Here, the word lines corresponding to the sub-word lines may share word line activation signals in units of 4 or 8.

[0040] Figure 4 1 is a diagram illustrating a word line driver 122 according to an embodiment of the inventive concept. Figure 4 , the word line driver 122 may include at least one switching circuit (SWAP) 122 - 1 , at least one register 122 - 2 , a normal word line driver (NWE driver) 122 - 3 , and a sub word line driver (SWD) 122 - 4 .

[0041] In various embodiments, the exchange circuit 122-1 may be configured to convert the repair data representing physically different addresses into logically identical addresses for each sub-word line driver block. For example, the exchange circuit 122-1 may convert the first decoded row address DRA345 based on the repair data. <0> and the second decoded row address DRA345 <1> Converted to the same row address, wherein the swap circuit 122-1 can swap the data received as input to the NWE driver with other input data.

[0042] In various embodiments, register 122-2 may be implemented to store repair data (or swap data). In an embodiment, the repair data may be set in a register setting operation of memory device 100. In another embodiment, the repair data may be sent from an external device (e.g., to a controller) on demand. The peripheral circuit may include a register configured to store repair data.

[0043] In various embodiments, a general memory device maintains a repair unit in a row decoder of an NWE (normal word line) driver (or a PXI driver) as it is, and changes a failed address to a repair address for each sub-block of an array.

[0044] In various embodiments, according to an embodiment of the present invention, the memory device 100 can use the repair resource more efficiently by performing repair in units of sub-word line drivers using one repair resource. The memory device 100 of the present invention can facilitate redundancy margin control by using a repair unit of a row decoder, where there is no change in core control such as a sensing operation. Since the memory device 100 of the present invention can be repaired for each sub-block, the memory device 100 has the effect of including as many repair resources as the number of sub-blocks.

[0045] In various embodiments, the memory device 100 of the present invention may receive segmented data from the column decoder 130, and enable repair resources to function according to different addresses for each position. In preparation for the concept of column decoder repair, the memory device 100 of the present invention may include an exchange circuit 122-1 instead of a comparison circuit. In an embodiment, the exchange circuit 122-1 may be set to a COP. For example, the circuit (NWE driver 122-3) in the row decoder 120 may be set at the bottom of the cell. Therefore, the area of ​​the memory device 100 may be expected to be reduced. By using the exchange circuit 121-1 and exchanging the DRA encoding applied to the NWE driver 122-3, multiple decoded row addresses may be replaced with one fault address. If the row decoder 120 performs a repair operation, multiple faults may be physically displayed as one fault logically. This makes it possible to repair multiple faults without using repair resources equal to the number of faults.

[0046] Figure 5A is a diagram illustrating a repair operation using a swap circuit SWAP according to an embodiment of the inventive concept. Figure 5A As illustrated, when multiple faults occur in one sub-block, the multiple faults can be repaired with one resource. For example, assume that a fault occurs at address 100 in a sub-block (sub_blk1) and a fault occurs at address 001 in a sub-block (sub_blk2). Address 100 and address 001 of the sub-block (sub_blk1) can be swapped, and address 001 can be repaired in the row decoder 120.

[0047] A general memory device may use two repair resources, but in the memory device 100 according to the inventive concept, two failures may be repaired using only one repair resource.

[0048] Because the memory device 100 of the present invention is based on a mixed address method, it is determined that it is impossible to repair multiple failures in one sub-block by using a combination of all addresses, and the circuit configuration can be arranged by exchanging only specific addresses. For example, the failure address can be the same as DRA345 <0> or <1> alignment.

[0049] In general, a memory device may include multiple blocks in a first direction. Here, each of the multiple blocks may include multiple sub-blocks arranged along a second direction different from the first direction. Each of the multiple memory blocks may be implemented as a core-on-periphery (COP) structure. Each of the multiple memory blocks may include multiple sub-blocks. Multiple sub-blocks may be implemented in a core-on-periphery (COP) structure. In an embodiment, the second direction may be a direction perpendicular to the first direction.

[0050] Figure 5B is a diagram illustrating a memory device having a COP structure according to an embodiment of the inventive concept. Figure 5B , the row decoder R / D may control a plurality of sub-blocks, such as sub_blk0, sub_blk1, and sub_blk2. Each of the plurality of sub-blocks sub_blk0, sub_blk1, and sub_blk2 may include a peripheral circuit located above a substrate and a cell array located above the peripheral circuit. At least one switching circuit SWAP may be included in each of the plurality of sub-blocks. Figure 5B As shown, the peripheral circuit may include the above reference Figures 1 to 5A Describe the switching circuit SWAP.

[0051] Figure 6 is a flowchart illustrating a repair operation of a memory device according to an embodiment of the inventive concept. Figures 1 to 6 , the memory device 100 may perform a repair operation as follows.

[0052] In various embodiments, the memory device 100 may receive an address from an external source (S110). The memory device 100 may determine whether the received address is a failure address (S120). When the address is a failure address, the memory device 100 may determine to swap the failure address with a repair address (S130). Subsequently, the memory device 100 may perform a repair operation using the repair address in response to determining to swap the failure address with the repair address (S140).

[0053] In various embodiments, a memory device may include a plurality of banks.

[0054] An operating method of a memory device may include: receiving an address from an external device; determining whether the received address is a fault address; when the received address is a fault address, determining whether to use a swap circuit to swap the received address with a repair address; swapping the received address with the repair address; and then performing access using the repair address, wherein the swap circuit swaps a plurality of addresses with the repair address using repair data. The repair data may be stored according to a request of the external device.

[0055] Figure 7 is a diagram illustrating a memory device according to another embodiment of the present disclosure. Figure 7 , the memory device 200 may include a memory cell array 210, a row decoder 220, a column decoder 230, a sense amplifier circuit 240, an address register 250, a memory body control logic 252, a refresh counter 254, a row address multiplexer (RA MUX) 256, a column address latch 258, a control logic circuit 260, a repair control circuit 266, a timing control circuit 264, an input / output (I / O) gating circuit 270, an error correction circuit 280 and a data I / O buffer 282.

[0056] In various embodiments, the memory cell array 210 may include first to eighth memory bank arrays 211 to 218 , but it should be understood that the number of memory bank arrays constituting the memory cell array 210 is not limited thereto.

[0057] In various embodiments, the first memory bank array 211 to the eighth memory bank array 218, the first memory bank row decoder 221 to the eighth memory bank row decoder 228, the first memory bank column decoder 231 to the eighth memory bank column decoder 238, and the first memory bank sense amplifier 241 to the eighth memory bank sense amplifier 248 may constitute the first memory bank to the eighth memory bank, respectively. The first memory bank array 211 to the eighth memory bank array 218 may each include a plurality of memory cells MC formed at intersections of word lines WL and bit lines BL. In an embodiment, as Figure 1 As illustrated, the first to eighth memory bank arrays 211 to 218 may each include the normal cell array 112 and the redundant cell array 114 of the memory cell array 110 .

[0058] In various embodiments, the row decoder 220 may include first to eighth bank row decoders 221 to 228 connected to the first to eighth bank arrays 211 to 218, respectively. In an embodiment, the first to eighth bank row decoders 221 to 228 may be implemented using the above reference code. Figures 1 to 6 The repair operation is performed by using the address swapping function described in the embodiment. In an embodiment, the memory row decoder activated by the memory control logic 252 among the first memory row decoder 221 to the eighth memory row decoder 228 can decode the row address RA output from the row address multiplexer 256 to activate the word line corresponding to the row address. For example, the activated memory row decoder can apply a word line drive voltage to the word line corresponding to the row address. In addition, the activated memory row decoder can activate the redundant word line corresponding to the spare row address (SRA) (or "redundant row address") output from the repair control circuit 266 while activating the word line corresponding to the row address.

[0059] In various embodiments, the column decoder 230 may include first bank column decoders 231 to eighth bank column decoders 238 connected to the first bank array 211 to the eighth bank array 218, respectively. In an embodiment, a bank column decoder activated by the bank control logic 252 among the first bank column decoder 231 to the eighth bank column decoder 238 may activate a sense amplifier circuit corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit 270. The activated bank column decoder may perform a column repair operation in response to a column repair signal CRP output from the repair control circuit 266.

[0060] In various embodiments, the sense amplifier circuit 240 may include first to eighth bank sense amplifiers 241 to 248 connected to the first to eighth bank arrays 211 to 218 , respectively.

[0061] In various embodiments, the address register 250 may receive an address ADDR having a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from an external memory controller and store the address ADDR. The address register 250 may provide the received bank address BANK_ADDR to the bank control logic 252, the received row address ROW_ADDR to the row address multiplexer 256, and the received column address COL_ADDR to the column address latch 258.

[0062] In various embodiments, the bank control logic 252 may generate a bank control signal in response to the bank address BANK_ADDR. A bank row decoder corresponding to the bank address BANK_ADDR among the first bank row decoder 221 to the eighth bank row decoder 228 may be activated in response to the bank control signal. A bank column decoder corresponding to the bank address BANK_ADDR among the first bank column decoder 231 to the eighth bank column decoder 238 may be activated in response to the bank control signal.

[0063] In various embodiments, the row address multiplexer 256 may receive the row address ROW_ADDR from the address register 250 and the refresh row address REF_ADDR from the refresh counter 254. The row address multiplexer 256 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 256 may be applied to each of the first to eighth bank row decoders 221 to 228.

[0064] In various embodiments, the column address latch 258 may receive the column address COL_ADDR from the address register 250 and temporarily store the received column address COL_ADDR. The column address latch 258 may incrementally increase the received column address COL_ADDR in a burst mode. The column address latch 258 may apply the temporarily stored or incrementally increased column address COL_ADDR to each of the first to eighth bank column decoders 231 to 238.

[0065] In various embodiments, the control logic circuit 260 may be implemented to control the operation of the semiconductor memory device 200. For example, the control logic circuit 260 may generate a control signal to enable the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 260 may include a command decoder 261 and a mode register 262, the command decoder 261 being configured to decode the command CMD received from the memory controller, and the mode register 262 being configured to set the operation mode of the memory device 200. For example, the command decoder 261 may decode the write activation signal / WE, the row address strobe signal / RAS, the column address strobe signal / CAS, the chip selection signal / CS, etc. to generate operation control signals ACT, PCH, WR, and RD corresponding to the command CMD. The control logic circuit 260 may provide the operation control signals ACT, PCH, WR, and RD to the timing control circuit 264. The control signals ACT, PCH, WR, and RD may include an activation signal ACT, a precharge signal PCH, a write signal WR, and / or a read signal RD. The timing control circuit 264 may generate a first control signal CTL1 for controlling a voltage level of a word line WL and a second control signal CTL2 for controlling a voltage level of a bit line BL in response to the operation control signals ACT, PCH, WR, and RD, and provide the first control signal CTL1 and the second control signal CTL2 to the memory cell array 210 .

[0066] Based on the row address ROW_ADDR and the column address COL_ADDR in the address ADDR (or the access address) and the fuse data of each word line, the repair control circuit 266 can generate the repair control signals CRP, SEL, EN and SRA for controlling the repair operation of the first cell area and the second cell area of ​​at least one memory cell array in the memory cell array. The repair control circuit 266 can provide the spare row address (SRA) (or the redundant row address) to the corresponding memory cell row decoder 221 to 228, provide the column repair signal (CRP) to the corresponding memory cell column decoder 231 to 238, and provide the selection signal (SEL) and the activation signal EN to the block control circuit associated with the corresponding spare array block (or redundant array block). The repair control circuit 266 can change the repair unit based on the address ADDR and the fuse data. For example, the repair control circuit 266 can change the type and number of the repair address bits based on the address ADDR and the fuse data.

[0067] Each of the I / O gating circuits 270 may include input data masking logic, a read data latch for storing data output from the first memory array 211 to the eighth memory array 218, a write driver for writing data to the first memory array 211 to the eighth memory array 218, and a circuit for gating I / O data.

[0068] During a write operation, the error correction circuit 280 may generate a parity bit based on the data bit of the data DQ provided to the error correction circuit 280 from the data I / O buffer 282, and provide a codeword CW including the data DQ and the parity bit to the I / O gating circuit 270. The I / O gating circuit 270 may write the codeword CW in the first memory bank array 211 to the eighth memory bank array 218. In addition, during a read operation, the error correction circuit 280 may receive a codeword CW read from one memory bank array from the I / O gating circuit 270. The error correction circuit 280 may perform ECC decoding on the data DQ using the parity bit included in the read codeword CW, correct at least one error bit included in the data DQ, and provide corresponding data to the data I / O buffer 282.

[0069] In various embodiments, the codeword CW to be read from one of the first to eighth memory arrays 211 to 218 may be sensed by a sense amplifier circuit corresponding to the one memory array and stored in a read data latch. The codeword CW stored in the read data latch may undergo ECC decoding and may then be provided to a memory controller through a data I / O buffer 282. The write data DQ may undergo ECC encoding in an error correction circuit 280 and may then be written to one of the first to eighth memory arrays 211 to 218 through a write driver.

[0070] In various embodiments, during a write operation, the data I / O buffer 282 may provide data DQ to the error correction circuit 280 based on a clock signal CLK provided from the memory controller, and during a read operation, the data DQ provided from the error correction circuit 280 may be provided to the memory controller.

[0071] In various embodiments, a memory system can include: a plurality of memory devices; and a controller configured to control the plurality of memory devices, wherein each of the plurality of memory devices includes: a swap circuit configured to swap a plurality of row addresses with a repair address using repair data; and a register configured to store the repair data. Each of the plurality of memory devices can be implemented as a COP structure, wherein each of the plurality of memory devices includes a plurality of sub-blocks having a plurality of memory cells arranged at intersections of word lines and bit lines, and each of the plurality of memory cells includes a vertical channel transistor (VCT).

[0072] In various embodiments, each of the plurality of sub-blocks may include: a peripheral circuit disposed on a substrate; and a memory cell array disposed above the peripheral circuit, wherein the peripheral circuit includes a switching circuit and a register. The switching circuit is capable of receiving one of a first decoding row address and a second decoding row address and outputting a repair address according to repair data. The controller is capable of sending repair data to the register.

[0073] Figure 8 1 is a diagram illustrating a memory system 1000 according to an embodiment of the inventive concept. Figure 8 , the memory system 1000 may include a plurality of memory modules 1300 - 1 , 1300 - 2 , 1300 - 3 , and 1300 - 4 and a controller (CTRL) 1400 . In an embodiment, an interposer 1200 may be disposed on the package substrate 1100 .

[0074] In various embodiments, the memory system 1000 may be configured to be included in a personal computer (PC) or a mobile electronic device. The mobile electronic device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an IoE (Internet of Everything) device, or a drone.

[0075] The memory modules 1300-1, 1300-2, 1300-3, and 1300-4 may each be configured to be mounted on a package substrate 1100 such as a printed circuit board. In addition, the memory modules 1300-1 to 1300-4 may each be connected to the controller 1400 through channels CH1 to CH4 and may be configured as a stacked chip (chip-on-chip, CoC).

[0076] In addition, each of the memory modules 1300-1 to 1300-4 may include a buffer chip 1310 and at least one memory chip (MEM) 1320. Here, the buffer chip 1310 and the at least one memory chip 1320 may be connected to each other through through silicon vias (TSVs).

[0077] In various embodiments, the buffer chip 1310 may be configured to perform a buffering function on data in the memory chip 1320. In addition, the buffer chip 1310 may be implemented to perform a training operation on the memory chip 1320.

[0078] In various embodiments, the memory chip (MEM) 1320 may be implemented as a volatile memory device or a non-volatile memory device. In an embodiment, the volatile memory device may be implemented as a random access memory (RAM), a dynamic RAM (DRAM), a static RAM (SRAM), or a low power double data rate (LPDDR) DRAM. In an embodiment, the non-volatile memory device may be implemented as an electrically erasable programmable read-only memory (EPROM), a NOR flash memory, a NAND flash memory, a magnetoresistive random access memory (MRAM), a spin-transfer torque (STT)-MRAM, a ferroelectric memory (FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulated resistance change memory. As described above with reference to Figures 1 to 7 As described, the memory chip 1320 may be implemented to exchange a plurality of addresses with one repair address.

[0079] In an embodiment, the memory modules 1300-1, 1300-2, 1300-3 and 1300-4 may all be high bandwidth memories (HBM). At the same time, it should be understood that Figure 8 The number of the memory modules 1300 - 1 , 1300 - 2 , 1300 - 3 , and 1300 - 4 illustrated in FIG. 1 is not limited.

[0080] Controller (CTRL) 1400 may be configured to control memory modules 1300-1, 1300-2, 1300-3, and 1300-4 connected to channels, respectively. In an embodiment, controller 1400 may be implemented as a system on chip (SoC), an application processor (AP), a mobile AP, a chipset, or a chipset. Controller 1400 may include a random access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), or a modem. In an embodiment, controller 1400 may perform the functions of a modem and an AP. Controller 1400 may determine the need for a repair operation of a memory chip and send repair data required for the repair operation to the memory chip.

[0081] In addition, the controller 1400 may be configured to control the memory chip 1320 to read data stored in the memory chip 1320 or write data to the memory chip 1320. The controller 1400 may control a write operation or a read operation on the memory chip 1320 by providing a command and an address to the memory chip 1320 in synchronization with a clock signal. In addition, data may be sent and received between the controller 1400 and the memory chip 1320 in synchronization with a data transmission clock.

[0082] In various embodiments, the controller 1400 may control the memory modules 1300-1, 1300-2, 1300-3, and 1300-4 to provide a data mirroring function, wherein at least two of the memory modules 1300-1, 1300-2, 1300-3, and 1300-4 may store the same data during a write operation. For example, the controller 1400 may control the memory module 1300-1 connected to the first channel CH1 and the memory module 1300-2 connected to the second channel CH2 to simultaneously write the same data to each memory module 1300-1 and 1300-2 in response to one write command. In addition, during a write operation, the controller 1400 may support a mirroring mode that provides a data mirroring function and a normal mode that provides normal operation. The memory system 1000 may write the same data to a plurality of memory channels CH1 to CH4 in a mirroring mode, and when data in some channels is damaged, data integrity may be maintained by using data in undamaged channels.

[0083] In a memory device and an operating method thereof according to an embodiment of the inventive concept, repair improvements in VCT using DRA data exchange may be expected.

[0084] A memory device, a memory system including the same, and an operating method of the memory device according to an embodiment of the inventive concept may efficiently use repair resources by including a component for electrically interchanging a plurality of addresses with each other.

[0085] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A storage device, the storage device include: at least one swap circuit configured to swap a plurality of decoded row addresses with a repair address using the repair data; at least one register configured to store the repair data; a word line activation signal driver configured to receive the repair address and output a word line activation signal; as well as A sub-word line driver is configured to activate a corresponding sub-word line in response to the word line activation signal.

2. The memory device according to claim 1, further comprising: include: A pre-decoder is configured to receive a row address and decode the received row address.

3. The memory device according to claim 1, in, The number of the plurality of decoded row addresses is two.

4. The memory device according to claim 1, further comprising: include: A memory cell array, the memory cell array comprising a plurality of memory cells arranged at intersections of word lines and bit lines, the memory cell array comprising a plurality of memory blocks, Each of the plurality of storage blocks includes a plurality of sub-blocks, and The at least one switching circuit is located in each of the plurality of storage blocks.

5. The memory device according to claim 4, in, Each of the plurality of memory blocks is implemented as a core-on-periphery structure.

6. The memory device according to claim 4, in, Each memory cell of the plurality of memory cells includes a vertical channel transistor.

7. The memory device according to claim 4, further comprising: include: a row decoder configured to select one of the word lines, The row decoder is arranged on the left side or the right side of the plurality of storage blocks.

8. The memory device according to claim 7, in, The at least one switching circuit is included in each of the plurality of sub-blocks.

9. The memory device according to claim 1, in, The at least one exchange circuit converts the repair data into logically identical repair addresses for each sub-block, the repair data being physically different addresses.

10. The memory device according to claim 1, in, The at least one swap circuit swaps the plurality of decoded row addresses with the repair data.

11. A storage device, the storage device include: A plurality of sub-blocks, the plurality of sub-blocks being implemented in a peripheral upper core structure; as well as a row decoder configured to control the plurality of sub-blocks, Each of the plurality of sub-blocks includes a peripheral circuit located above the substrate, and The peripheral circuit includes a switching circuit that converts a plurality of decoded row addresses into a repair address using the repair data.

12. The memory device according to claim 11, in, The peripheral circuit further includes a register storing the repair data.

13. The memory device according to claim 11, in, The plurality of decoded row addresses include a first decoded row address and a second decoded row address.

14. The memory device according to claim 13, in, One of the plurality of sub-blocks activates a sub-word line corresponding to the repair address according to the first decoded row address, and Another sub-block of the plurality of sub-blocks activates the sub-word line for activating the repair address according to the second decoded row address.

15. The memory device according to claim 11, in, Each of the plurality of sub-blocks includes a plurality of storage units, and Each of the plurality of memory cells includes a vertical channel transistor oriented in a direction perpendicular to the substrate.

16. A method for operating a storage device, the method comprising: include: receiving an address from an external device; determining whether the received address is a faulty address; When the received address is a faulty address, determining whether to use a swap circuit to swap the received address with a repair address; exchanging the received address with the repair address; as well as performing an access using the repair address, The exchange circuit uses the repair data to exchange a plurality of addresses with the repair address.

17. The operating method according to claim 16, further comprising: include: The received address is decoded.

18. The operating method according to claim 16, in, The switching circuit is provided in each sub-block included in the memory device.

19. The operating method according to claim 18, in, Each of the sub-blocks is implemented as a peripheral-on-core structure.

20. The operating method according to claim 16, further comprising: include: The repair data is stored according to a request of the external device.

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