Method for preparing flip-chip stacked transistor, transistor, device and equipment

Abstract

The present application provides a method for preparing a flip-chip stacked transistor, a transistor, a device and an apparatus, the method comprising: forming an active structure on a substrate, the active structure having a first part and a second part, the first part being closer to the substrate than the second part; etching the active structure in the source-drain region, and filling the first source-drain region with an insulating material to form a filling structure, the source-drain region comprising a first source-drain region and a second source-drain region, the first source-drain region corresponding to the first part, and the second source-drain region corresponding to the second part; based on the second source-drain region, forming a first source-drain structure and a first source-drain metal of a first transistor; flipping the first transistor and removing the substrate; filling the structure by selectively etching the material to expose the first source-drain region; based on the first source-drain region, forming a second source-drain structure and a second source-drain metal of a second transistor. The present application can achieve complete self-alignment of front and back transistors.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a flip-chip stacked transistor, a transistor, a device and equipment. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] Related Technology In the process of preparing flip-chip stacked transistors, after the front transistor is prepared, the source / drain region and the gate region are usually opened by photolithography to prepare the back transistor aligned with the front transistor. This method relies on the photolithography accuracy, which increases the process difficulty and equipment requirements, and the front and back transistors may not be completely self-aligned. Summary of the invention

[0004] The present application provides a method for preparing a flip-chip stacked transistor, a transistor, a device and an apparatus, which can reduce the requirements for photolithography and achieve complete self-alignment of the front and back transistors of the flip-chip stacked transistor.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a flip-chip stacked transistor, the method comprising: forming an active structure on a substrate, the active structure having a first part and a second part, the first part being closer to the substrate than the second part; etching the active structure in a source-drain region, and filling the first source-drain region with an insulating material to form a filling structure, the source-drain region comprising a first source-drain region and a second source-drain region, the first source-drain region corresponding to the first part, and the second source-drain region corresponding to the second part; based on the second source-drain region, forming a first source-drain structure and a first source-drain metal of a first transistor; flipping the first transistor and removing the substrate; filling the structure by selectively etching the material to expose the first source-drain region; based on the first source-drain region, forming a second source-drain structure and a second source-drain metal of a second transistor.

[0006] In one possible embodiment, an active structure is formed on a substrate, including: providing a substrate; sequentially forming a sacrificial layer and a first material layer on the substrate; etching the sacrificial layer and the first material layer to form an active structure, the active structure being the first material layer after etching; after flipping the first transistor and removing the substrate, the method further includes: filling a semiconductor material in a gate region so that the upper surface of the formed dummy gate structure is flush with the upper surface of the sacrificial layer; and removing the sacrificial layer.

[0007] In one possible embodiment, the method also includes: before forming a first source-drain structure and a first source-drain metal of the first transistor based on the second source-drain region, depositing a semiconductor material on the active structure to form a dummy gate structure; after forming the first source-drain structure of the first transistor, removing the third part of the dummy gate structure to form a first gate structure of the first transistor, and after forming the second source-drain structure of the second transistor, removing the fourth part of the dummy gate structure to form a second gate structure of the second transistor, the third part corresponds to the second part, and the fourth part corresponds to the first part; or, after forming the second source-drain structure of the second transistor, removing the dummy gate structure to form the first gate structure of the first transistor and the second gate structure of the second transistor, respectively.

[0008] In one possible embodiment, after forming a first gate structure of the first transistor and / or forming a second gate structure of the second transistor, the method further includes: forming a gate cut-off structure on both sides of the first gate structure and the second gate structure, the gate cut-off structure being used to isolate the gate region of the flip-chip stacked transistor from the gate region of an adjacent flip-chip stacked transistor.

[0009] In one possible embodiment, the method also includes: before forming the first source-drain structure and the first source-drain metal of the first transistor, forming a source-drain isolation dielectric layer on the filling structure, wherein the source-drain isolation dielectric layer is used to isolate the first source-drain structure from the second source-drain structure; or, after forming the first source-drain structure and the first source-drain metal of the first transistor, and before forming the second source-drain structure and the second source-drain metal of the second transistor, forming a source-drain isolation dielectric layer on the second source-drain region.

[0010] In a possible implementation, etching the filling structure includes: etching the filling structure to a preset height, using the etched filling structure as a source-drain isolation dielectric layer, wherein the source-drain isolation dielectric layer is used to isolate the first source-drain structure from the second source-drain structure.

[0011] In a possible implementation, the method further includes: forming a gate isolation dielectric layer on the first gate structure of the first transistor, wherein the gate isolation dielectric layer is used to isolate the first gate structure from the second gate structure of the second transistor.

[0012] In a second aspect, an embodiment of the present application provides a flip-chip stacked transistor, which is manufactured using the preparation method described in the first aspect and any one of its embodiments, and includes: a first transistor; a second transistor, the first transistor and the second transistor are arranged back to back; wherein the first source-drain structure of the first transistor and the second source-drain structure of the second transistor are self-aligned in the vertical direction.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a flip-chip stacked transistor as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, an active structure including a first part and a second part is formed on a substrate, the active structure in the source-drain region is etched, and a filling structure is formed in the first source-drain region corresponding to the first part, so that the filling structure covers the source-drain region of the back transistor. Afterwards, based on the second source-drain region corresponding to the second part, a first transistor (front transistor) is formed, the first transistor is flipped and the substrate is removed, and then the filling structure is selectively removed by the material to expose the first source-drain region, and based on the first source-drain region, a second transistor (back transistor) is formed. After the transistor is flipped, the filling structure is used to locate the source-drain region where the back transistor is located, so that when preparing the back transistor, it is not necessary to select the region through photolithography, and the source-drain region can be directly opened through the selectivity of the material, so that a back transistor that is completely self-aligned with the front transistor can be prepared. In this way, the requirements for photolithography can be reduced, and the source-drain region of the front transistor of the flip-chip stacked transistor can be completely self-aligned with the source-drain region of the back transistor.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an implementation process of a method for preparing a flip-chip stacked transistor in an embodiment of the present application;

[0019] Figure 2 A schematic top view of a flip-chip stacked transistor in an embodiment of the present application;

[0020] FIG. 3A to FIG. 3K This is a schematic diagram of the structure of the flip-chip stack transistor in the first preparation process in an embodiment of the present application;

[0021] Figure 3L This is a schematic diagram of a first structure of a flip-chip stacked transistor in an embodiment of the present application;

[0022] Figures 4A to 4K This is a schematic structural diagram of a flip-chip stack transistor in a second preparation process according to an embodiment of the present application;

[0023] Figure 4L A second structural schematic diagram of a flip-chip stack transistor according to an embodiment of the present application;

[0024] Figure 5A A schematic diagram of the structure of a flip-chip stack transistor in a third preparation process according to an embodiment of the present application;

[0025] Figure 5B A third structural schematic diagram of the flip-chip stack transistor according to an embodiment of the present application;

[0026] FIG. 6A to FIG. 6E It is a schematic structural diagram of a flip-chip stack transistor in a fourth preparation process according to an embodiment of the present application;

[0027] Fig. 6F A fourth structural schematic diagram of the flip-chip stack transistor according to an embodiment of the present application;

[0028] 7A to 7E A schematic diagram of the structure of a flip-chip stack transistor in a fifth preparation process according to an embodiment of the present application;

[0029] Figure 7F This is a fifth structural schematic diagram of the flip-chip stacked transistor according to an embodiment of the present application.

[0030] The above pictures:

[0031] 10. Flip-chip stack transistor; 11. First transistor (front transistor); 111. Second nanosheet structure; 112. First source-drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 1141. First gate dielectric layer; 1142. First gate electrode layer; 115. First source-drain metal; 116. First metal interconnect layer; 12. Second transistor; 121. Second nanosheet structure; 122. Second source-drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 1241. Second gate dielectric layer; 1242. Second gate electrode layer; 125. Second source-drain metal; 126. Second metal interconnect layer; 13. Insulation layer; 14. Carrier wafer; 20. Substrate; 21. First Sacrificial layer; 22, bottom stacking layer; 23, second sacrificial layer; 24, top stacking layer; 25, active structure; 251, first active structure; 252, second active structure; 253, second intermediate sacrificial layer; 254, first intermediate sacrificial layer; 26, isolation structure; 27, pseudo-gate structure; 28, side wall; 29, first groove; 30, MDI layer; 31, first inner side wall; 32, filling structure; 33, source-drain isolation dielectric layer; 34, first gate cut-off structure; 35, first isolation layer; 36, second inner side wall; 37, gate isolation dielectric layer; 38, second gate cut-off structure; 39, second isolation layer; 40, gate structure; 401, gate dielectric layer; 402, gate electrode layer; 41, gate cut-off structure. DETAILED DESCRIPTION

[0032] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0033] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0034] In one embodiment, there are two schemes for the preparation process of stacked transistors, the first is a monolithic stacking scheme, and the second is a sequential scheme, but both schemes have certain technical problems. In order to solve the technical problems, a flip-chip stacked transistor is proposed, which forms the active areas of the upper and lower layers of the same source transistors by etching, and realizes the manufacture of flip-chip stacked transistors on the front and back sides of the wafer by flipping the wafer, so as to overcome the shortcomings of the above two schemes.

[0035] In the method of preparing flip-chip stacked transistors, after the front transistor is prepared, the source, drain and gate regions are usually opened by photolithography to prepare the back transistor aligned with the front transistor. This method relies on the accuracy of photolithography, which increases the process difficulty and equipment requirements, and the front and back transistors may not be completely self-aligned.

[0036] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a flip-chip stacked transistor, which can reduce the requirements for photolithography and achieve complete self-alignment of the front and back transistors of the flip-chip stacked transistor.

[0037] In the embodiments of the present application, the flip-chip stacked transistor can be applied to semiconductor devices such as memory and processor.

[0038] In some embodiments, the flip-chip stacked transistor may include at least two transistors. Taking the first transistor and the second transistor as an example, the first transistor and the second transistor are arranged back to back, and the first source and drain structure of the first transistor is self-aligned with the second source and drain structure of the second transistor in the vertical direction, so the first transistor and the second transistor are completely self-aligned.

[0039] In an embodiment of the present application, the first transistor and the second transistor in the flip-chip stacked transistor are transistors of the same type, such as any one of the following: a fin field effect transistor (FinFET), a gate-all-around field effect transistor (GAAFET) and a planar transistor.

[0040] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a flip-chip stacked transistor in an embodiment of the present application. Figure 1 As shown, the method for preparing the flip-chip stacked transistor in the embodiment of the present application may include:

[0041] Step S110: forming an active structure on a substrate.

[0042] In some embodiments, the implementation process of step S110 can be divided into the following three steps: providing a substrate; sequentially forming a sacrificial layer and a first material layer on the substrate; etching the sacrificial layer and the first material layer to form an active structure, wherein the active structure is the etched first material layer.

[0043] By way of example, the substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate.

[0044] After providing the substrate, semiconductor materials can be stacked on the substrate in sequence to form a sacrificial layer and a first material layer, and certain areas of the sacrificial layer and the first material layer can be etched to form a number of active structures standing on the substrate, and the active structure is the first material layer after etching. Among them, the material forming the sacrificial layer is different from the material forming the first material layer, so that the sacrificial layer can be removed later by material selectivity, and the role of the sacrificial layer will be described later. The etching process can be exemplified by at least one of dry etching, wet etching, reactive ion etching, etc.

[0045] Here, each active structure includes a first part (first active structure) and a second part (second active structure), and the first part is closer to the substrate than the second part, that is, the first material layer after etching is divided into two parts, the lower part close to the substrate serves as the first active structure, and the upper part away from the substrate serves as the second active structure.

[0046] In some embodiments, the first material layer may include a first semiconductor material, or the first material layer may include at least a first semiconductor material and a second semiconductor material alternately stacked in sequence along the arrangement direction of the active structure. For example, the first semiconductor material may be silicon, and the second semiconductor material may be silicon germanium.

[0047] It can be understood that the first material layer can be a single layer formed by depositing one material, or can be a stacked layer formed by alternately depositing two different materials.

[0048] In one example, when the flip-chip stacked transistor is a FinFET, the substrate may be formed of silicon, the sacrificial layer may be formed of silicon germanium, and the first material layer forming the active structure may be formed of silicon. When the flip-chip stacked transistor is a GAAFET, the substrate may be formed of silicon, the sacrificial layer may be formed of silicon germanium, and the first material layer forming the active structure may be formed of alternately deposited silicon germanium and silicon, wherein the germanium content in the silicon germanium material forming the sacrificial layer is different from the germanium content in the silicon germanium material forming the active structure (i.e., SiGe 1 is used to prepare the sacrificial layer, and SiGe 2 is used to prepare the active structure).

[0049] In some other embodiments, the present application can also prepare an isolation structure between a front transistor and a back transistor in a flip-chip stacked transistor. In this case, the aforementioned sacrificial layer can be referred to as a first sacrificial layer.

[0050] Based on this, in the case where the first material layer includes the first semiconductor material, the first semiconductor material can be deposited on the first sacrificial layer to form a bottom layer, an isolation material can be deposited on the bottom layer to form a second sacrificial layer, and the first semiconductor material can be deposited again on the second sacrificial layer to form a top layer. In the case where the first material layer includes the first semiconductor material and the second semiconductor material alternately stacked in sequence, the first semiconductor and the second semiconductor can be alternately deposited on the first sacrificial layer to form a bottom stacking layer, an isolation material can be deposited on the bottom stacking layer to form a second sacrificial layer, and the first semiconductor material and the second semiconductor material can be alternately deposited again on the second sacrificial layer to form a top stacking layer. After etching to form an active structure, the etched second sacrificial layer (second intermediate sacrificial layer) is located between the first active structure and the first active structure. By way of example, the isolation material forming the second sacrificial layer can be the same as the material forming the first sacrificial layer.

[0051] In some embodiments, after forming the active structure, an oxide material may be deposited on the substrate to form an isolation structure.

[0052] It is understandable that after the active structure is formed, an oxide material may be deposited on the substrate and thinned so that the upper surface of the formed isolation structure is flush with the upper surface of the sacrificial layer to expose the active structure.

[0053] In one example, the isolation structure may be formed using shallow trench isolation (STI).

[0054] For example, the oxide material forming the isolation structure may be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc. The thinning process may be a process such as chemical-mechanical planarization (CMP).

[0055] In some embodiments, after forming the active structure, a semiconductor material may be deposited on the active structure to form a dummy gate structure.

[0056] To distinguish the semiconductor material from the first semiconductor material and the second semiconductor material, the semiconductor material here is referred to as a third semiconductor material, where the third semiconductor material may be, for example, polysilicon (poly Si), amorphous silicon, or the like.

[0057] It can be understood that after the active structure and the STI structure are formed, the gate region can be opened by photolithography, and a third semiconductor material such as polysilicon can be deposited in the gate region as a pseudo-gate structure. That is, the present application defines the gate regions of the front transistor and the back transistor in the flip-chip stacked transistor by a pseudo-gate structure. Therefore, the pseudo-gate structure here includes a first pseudo-gate structure for defining the gate region of the front transistor, and a second pseudo-gate structure for defining the gate region of the back transistor, so that self-alignment of the upper and lower transistors in the flip-chip stacked transistor can be achieved in the gate region. Among them, the height of the pseudo-gate structure is greater than the height of the active structure.

[0058] In some embodiments, after forming the dummy gate structure, a spacer may be formed on both sides of the dummy gate structure. Accordingly, the spacer also includes a first spacer located on both sides of the first dummy gate structure and a second spacer located on both sides of the second dummy gate structure. For example, the spacer may have a single-layer structure, and the entire structure may be made of the same material, such as porous carbon silicon oxyhydride (SICOH).

[0059] Step S120: etching the active structure in the source-drain region, and filling the first source-drain region with an insulating material to form a filling structure.

[0060] The source-drain region includes a first source-drain region and a second source-drain region, the first source-drain region corresponds to a first portion of the first active structure, and the second source-drain region corresponds to a second portion of the second active structure.

[0061] It can be understood that by etching the active structure in the source and drain area, both the first active structure and the second active structure in the source and drain area can be removed. Since there is a first sacrificial layer after etching and an isolation structure located on both sides of the first sacrificial layer above the substrate below the active structure, the first sacrificial layer after etching and the isolation structure located in the source and drain area can also be removed here to completely expose the entire source and drain area. The source and drain area may include a first source and drain area corresponding to the first part and a second source and drain area corresponding to the second part. After the source and drain area is exposed, an insulating material may be filled in the first source and drain area corresponding to the first part to form a filling structure, so that the source and drain area of ​​the back transistor can be defined by the filling structure to achieve self-alignment of the upper and lower transistors in the source and drain area of ​​the flip-chip stacked transistor.

[0062] By way of example, the insulating material may be silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or the like.

[0063] In addition, in some embodiments, before etching the active structure in the source and drain region, the second intermediate sacrificial layer between the first active structure and the second active structure can be selectively removed to form a groove, and an insulating material is filled in the groove to form a middle dielectric isolation (MDI) layer. The MDI layer can serve as isolation between the front transistor and the back transistor.

[0064] In some embodiments, when the MDI layer is present, the filling structure may cover a portion of the MDI layer when the filling structure is formed.

[0065] In some embodiments, after forming the filling structure, a source-drain isolation dielectric layer may be formed on the filling structure, and the source-drain isolation dielectric layer is used to isolate the first source-drain structure of the first transistor from the second source-drain structure of the second transistor.

[0066] It can be understood that after forming the filling structure, an insulating material may be deposited on the filling structure and thinned so that the upper surface of the formed source-drain isolation dielectric layer is flush with the upper surface of the MDI layer.

[0067] Step S130: Based on the second source-drain region, a first source-drain structure and a first source-drain metal of the first transistor are formed.

[0068] It can be understood that after etching the active structure in the source-drain region in step S120, a source-drain groove will be formed, so source-drain epitaxial growth can be performed in the source-drain groove to form a first source-drain structure.

[0069] Exemplarily, strained materials such as silicon germanium or silicon carbide can be formed in the source and drain grooves by selective epitaxial growth to fill the source and drain grooves of the front transistor (first transistor), and then a first source and drain structure is formed on the strained material by a heavy doping process.

[0070] In some embodiments, after forming the first source-drain structure, an interlayer dielectric may be deposited on the first source-drain structure and thinned to the upper surface of the first source-drain structure to form a first interlayer dielectric layer, wherein the interlayer dielectric may be SiO2, for example.

[0071] When forming the first interlayer dielectric layer, a portion of the first interlayer dielectric layer may be etched to expose the first source-drain structure, and then a metal material is deposited on the first source-drain structure to form a first source-drain metal.

[0072] For ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the first source-drain metal, the second source-drain structure, the second source-drain metal, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0073] In the embodiment of the present application, gate structures can be prepared separately on the front and back sides, that is, a first gate structure of a front transistor (first transistor) is prepared on the front side, and a second gate structure of a back transistor (second transistor) is prepared on the back side. The first gate structure of the front transistor and the second gate structure of the back transistor can also be formed at the back side at one time. The scheme of forming gate structures separately on the front and back sides is called the first scheme, and the scheme of forming gate structures at the back side at one time is called the second scheme. The method of forming the first gate structure on the front side in the first scheme is described below.

[0074] In some embodiments, after forming the first source-drain structure, the third portion of the dummy gate (ie, the first dummy gate structure) may be removed to form the first gate structure of the first transistor, and the third portion corresponds to the second portion of the active structure.

[0075] It is understandable that the pseudo gate structure of the first transistor formed above can be removed by an etching process to obtain a first gate groove, an insulating material can be deposited at the first gate groove to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute a first gate structure.

[0076] For example, the first gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0077] By way of example, the first gate electrode layer may be composed of multiple layers of electrode materials, the electrode materials of each layer including but not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0078] It should be noted that the first source-drain structure, the first interlayer dielectric layer, the first gate structure, and the first source-drain metal can all be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0079] In some embodiments, after forming the first transistor, a back-end process may be performed on the first transistor to form a first metal interconnection layer.

[0080] It can be understood that the back-end process may be, for example, a process such as dielectric deposition between interconnect lines, metal line formation, and lead pad formation.

[0081] Furthermore, in some embodiments, before forming the first source-drain metal, a first isolation layer may be formed on the first gate structure and the first interlayer dielectric layer, and the first isolation layer is used to isolate the first transistor from the first metal interconnection layer.

[0082] It is understandable that an insulating material can be deposited on the first gate structure and the first interlayer dielectric layer to form a first isolation layer, which can also be called a pre-metal dielectric (PMD) layer. The PMD layer has the following two functions: (1) electrical isolation. The PMD layer electrically isolates the transistor device and the metal interconnect layer to prevent current from flowing in unnecessary paths and ensure the normal operation of the circuit; (2) physical protection. The PMD layer can block impurity sources such as movable particles (such as sodium ions) to prevent impurity sources from affecting the performance of transistor devices and protect the devices from the influence of the external environment. Among them, the insulating material forming the PMD layer can be SiO2, SiN and other materials.

[0083] Step S140: flipping the first transistor and removing the substrate.

[0084] It can be understood that after forming the first transistor, the first transistor can be bonded to the carrier wafer, and then the first transistor can be flipped over to prepare the back-side transistor later.

[0085] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the first metal interconnect layer to form a first insulating layer, and the first insulating layer may be bonded to a carrier wafer, after which the first transistor may be flipped over and the substrate may be removed.

[0086] In some embodiments, after removing the substrate, a semiconductor material may be filled in the gate region so that the upper surface of the formed dummy gate structure is flush with the upper surface of the sacrificial layer (first sacrificial layer).

[0087] It is understandable that, since the first sacrificial layer and the isolation structures on both sides of the first sacrificial layer still exist in the gate region of the back transistor, the isolation structure in the gate region can be removed after removing the substrate to expose the first sacrificial layer. Then, the etched gate region can be filled with materials such as polysilicon so that the formed dummy gate structure can completely define the gate region of the back transistor.

[0088] Step S150: filling the structure by selectively etching the material to expose the first source and drain region.

[0089] It can be understood that the filling structure covers the first source and drain region of the back transistor, so when preparing the back transistor, the filling structure can be etched through the selectivity of the material to expose the first source and drain region. Since the filling structure is used to locate the source and drain region where the back transistor is located, when preparing the back transistor later, there is no need to select the region through photolithography, and the source and drain region can be directly opened through the selectivity of the material to prepare a back transistor that is completely self-aligned with the front transistor.

[0090] Step S160: Based on the first source-drain region, a second source-drain structure and a second source-drain metal of the second transistor are formed.

[0091] It can be understood that after etching the filling structure in the first source-drain region in step S150, a source-drain groove will be formed, so source-drain epitaxial growth can be performed in the source-drain groove to form a second source-drain structure.

[0092] In some embodiments, after the second source-drain structure is formed, an interlayer dielectric may be deposited on the second source-drain structure, and the interlayer dielectric may be thinned to an upper surface of the second source-drain structure to form a second interlayer dielectric layer.

[0093] When forming the second interlayer dielectric layer, a portion of the second interlayer dielectric layer may be etched to expose the second source-drain structure, and then a metal material is deposited on the second source-drain structure to form a second source-drain metal.

[0094] The following describes a method for forming the second gate structure on the back side in the first solution.

[0095] In some embodiments, after forming the second source-drain structure, the fourth portion of the dummy gate (ie, the second dummy gate structure) may be removed to form a second gate structure of the second transistor, and the fourth portion corresponds to the first portion of the active structure.

[0096] It is understandable that the pseudo gate structure of the second transistor formed above can be removed by an etching process to obtain a second gate groove, an insulating material can be deposited at the second gate groove to form a second gate dielectric layer, and a metal material can be deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute a second gate structure.

[0097] The second solution is introduced below, which is a solution for forming the first gate structure and the second gate structure at the back side at the same time.

[0098] In some embodiments, after the second source-drain structure is formed, the dummy gate structure may be removed to form a first gate structure and a second gate structure, respectively.

[0099] It is understandable that the pseudo gate structure formed above can be removed by an etching process to obtain a gate groove, and a gate structure shared by the front and back sides can be formed at the gate groove. Then, the gate structure can be etched back to the bottom of the back transistor, and the retained gate structure is used as the first gate structure of the front transistor, and the second gate structure of the back transistor is formed in the exposed gate region of the back transistor.

[0100] In some embodiments, after forming the second transistor, a back-end process may be performed on the second transistor to form a second metal interconnection layer.

[0101] Among them, the preparation method of the second source-drain structure, the second interlayer dielectric layer, the second gate structure, the second source-drain metal, and the second metal interconnection layer of the second transistor can refer to the preparation method of the first source-drain structure, the first interlayer dielectric layer, the first gate structure, the first source-drain metal, and the first metal interconnection layer of the first transistor formed in the above-mentioned step S130, and will not be repeated here.

[0102] In addition, the embodiment of the present application can also achieve isolation between flip-chip stacked transistors through a gate cut structure, that is, perform gate cut processing on the flip-chip stacked transistors.

[0103] In some embodiments, after forming a first gate structure of a first transistor and / or forming a second gate structure of a second transistor, a gate cut-off structure can be formed on both sides of the first gate structure and the second gate structure, and the gate cut-off structure is used to isolate the gate region of the flip-chip stacked transistor from the gate region of an adjacent flip-chip stacked transistor.

[0104] It can be understood that the gate cut-off structure can be formed on the back transistor at one time, that is, after forming the gate structure of the back transistor, the first gate structure and the second gate structure are gate-cut to form the gate cut-off structure (first case). It can also be formed on the front transistor at one time, that is, after forming the gate structure of the front transistor, the first gate structure and the filling structure under the first gate structure are gate-cut to form the gate cut-off structure (second case). It is also possible to gate-cut the gate structure of the front transistor and the gate structure of the back transistor after they are formed, respectively, to form the first gate cut-off structure and the second gate cut-off structure (third case), and the first gate cut-off structure and the second gate cut-off structure constitute the gate cut-off structure.

[0105] In some embodiments, after forming the second gate structure of the second transistor, the first gate structure and the second gate structure may be gate-cut to form a gate-cut groove, and an insulating material may be filled in the gate-cut groove to form a gate-cut structure.

[0106] It is understandable that a photoresist may be coated on the second gate structure, and after exposure and development (i.e., forming a photoresist layer), a notch at a preset position is formed, wherein the notch corresponds to the gate cut-off region of the second transistor. Next, the second gate structure and a portion of the first gate structure are etched using the photoresist layer as a mask to form a gate cut-off groove.

[0107] It should be noted that the width of the gate cut-off groove (ie, the size of the gap in the photoresist layer) can be designed according to actual conditions, but cannot be engraved on the active structure, and the embodiments of the present application do not specifically limit this.

[0108] After forming the gate cut-off groove, an insulating material may be used to fill the gate cut-off groove to form a gate cut-off structure located at both sides of the first gate structure and the second gate structure.

[0109] Next, the second case is introduced. In some embodiments, after forming the first gate structure of the first transistor, the first gate structure and the isolation structure located below the first gate structure can be gate cut to form a gate cut groove, the bottom of the gate cut groove is in contact with the substrate; and the gate cut groove is filled with an insulating material to form a gate cut structure.

[0110] It is understandable that the bottom of the gate cut-off structure formed by one etching on the front side contacts the substrate. The process of forming the gate cut-off structure on the front side can refer to the above-mentioned contents of forming the gate cut-off structure on the back side, which will not be described in detail here.

[0111] Next, the third case is introduced. In some embodiments, after forming the first gate structure of the first transistor, the first gate structure can be gate-cut to form a first gate cut-off groove; and the first gate cut-off groove is filled with insulating material to form a first gate cut-off structure. After forming the second gate structure of the second transistor, the second gate structure can be gate-cut to form a second gate cut-off groove; and the second gate cut-off groove is filled with insulating material to form a second gate cut-off structure. Among them, the implementation process of forming the first gate cut-off structure and the second gate cut-off structure can refer to the relevant content of forming the gate cut-off structure mentioned above, which will not be repeated here.

[0112] In addition, the embodiment of the present application can also prepare an isolation structure between the front transistor and the back transistor in the gate region.

[0113] Based on this, before forming the second gate structure of the second transistor, a gate isolation dielectric layer can be formed on the first gate structure, and then the second gate structure is formed on the gate isolation dielectric layer, and the gate isolation dielectric layer is used to isolate the first gate structure from the second gate structure.

[0114] It is understandable that an oxide material may be deposited on the first gate structure, then anisotropically etched to the bottom of the second portion of the active structure, and then isotropically etched to form a gate isolation dielectric layer.

[0115] In addition, the embodiment of the present application can also prepare an isolation structure between the front transistor and the back transistor in the source and drain region.

[0116] Based on this, in some embodiments, the process of etching the filling structure in the above step S150 can be: etching the filling structure to a preset height, using the etched filling structure as a source-drain isolation dielectric layer, and the source-drain isolation dielectric layer is used to isolate the first source-drain structure from the second source-drain structure of the second transistor. The preset height can be set in advance, and the embodiment of the present application does not limit this.

[0117] It can be understood that a portion of the filling structure can be etched away, and the remaining portion of the filling structure can be used as a source-drain isolation dielectric layer in the source-drain region of the front transistor and the back transistor.

[0118] In some other embodiments, before forming the first source-drain structure and the first source-drain metal of the first transistor, a source-drain isolation dielectric layer may be formed on the filling structure. The material forming the source-drain isolation dielectric layer may be SiO2 or other materials. In this case, step S150 may completely etch away the filling structure.

[0119] In some other embodiments, after forming the first source-drain structure and the first source-drain metal of the first transistor, and before forming the second source-drain structure and the second source-drain metal of the second transistor, a source-drain isolation dielectric layer may be formed on the second source-drain region. The material forming the source-drain isolation dielectric layer may be SiO2 or other materials, for example. In this case, step S150 may also completely etch away the filling structure.

[0120] In the present application, an active structure including a first part and a second part is formed on a substrate, a pseudo-gate structure is formed on the active structure, the active structure in the source-drain region is etched, and a filling structure is formed in the first source-drain region corresponding to the first part, so that the filling structure covers the source-drain region of the back transistor. Then, based on the second source-drain region corresponding to the second part, a first transistor is formed, the first transistor is flipped and the substrate is removed, and then the filling structure is removed to expose the first source-drain region, and a second transistor is formed based on the first source-drain region. After the transistor is flipped, the filling structure and the pseudo-gate structure are used to define the source-drain region and the gate region where the back transistor is located, so that when preparing the back transistor, it is not necessary to select the region through photolithography, and the source-drain region and the gate region can be directly opened through the selectivity of the material to prepare a back transistor that is completely self-aligned with the front transistor. In this way, the requirements for photolithography can be reduced, and the source-drain region of the front transistor of the flip-chip stacked transistor can be completely self-aligned with the source-drain region of the back transistor.

[0121] Furthermore, the solution of the present application can greatly improve the integration density of transistors, and also take into account the consistency, defect density and alignment of the active areas of the front and back transistors. Moreover, the solution of the present application is also a further optimization of the current flip-chip stacked transistor solution. In the solution of the present application, when preparing flip-chip stacked transistors, fewer high aspect ratio processes can be used, and fully self-aligned flip-chip stacking of transistors of various forms can be more compatible. In addition, the preparation scheme of flip-chip stacked transistors is compatible with existing mainstream device architectures, and can realize flip-chip stacking of planar transistors, FinFETs, GAA Nanosheets and even vertical transistors on the front and back without the need for special process development for specific device architectures, and has strong flexibility. From the perspective of semiconductor process node iteration, it has strong extensibility. Flip-chip stacked transistors are very advanced in concept, have important industrial value, and are highly practical and have broad prospects for development.

[0122] The following describes the method for preparing the flip-chip stacked transistor provided in the embodiment of the present application by taking the active structure in the flip-chip stacked transistor as a nanosheet structure as an example. Figure 2 This is a top view schematic diagram of the flip-chip stacked transistor in the embodiment of the present application. It should be noted that, for ease of understanding, only the nanosheet structure, gate structure, and source-drain structure are shown in the top view. The AA' direction is the cross-sectional direction of the flip-chip stacked transistor along the gate structure; the BB' direction is the cross-sectional direction of the flip-chip stacked transistor along the source-drain structure; and the CC' direction is the cross-sectional direction of the flip-chip stacked transistor along the nanosheet structure.

[0123] The first preparation process is first introduced below, that is, forming a gate structure and a gate cut-off structure separately on the front and back sides, and forming an isolation layer in the source and drain area between the front transistor and the back transistor on the front side, and there is an isolation layer between the gate structure of the front transistor and the gate structure of the back transistor. FIG. 3A to FIG. 3K This is a schematic diagram of the structure of the flip-chip stack transistor in the first preparation process according to an embodiment of the present application. Figure 3L This is a schematic diagram of a first structure of a flip-chip stacked transistor according to an embodiment of the present application.

[0124] Step 1: forming a first sacrificial layer 21 on the original substrate 20, forming a bottom stacking layer 22 on the first sacrificial layer 21, forming a second sacrificial layer 23 on the bottom stacking layer 22, and forming a top stacking layer 24 on the second sacrificial layer 23 (see Figure 3A (a) in the figure.

[0125] For example, a Si layer 20 may be provided, and SiGe 1 material may be deposited on the Si layer 20 to form a first sacrificial layer 21; then SiGe 2 material and Si material may be alternately deposited on the first sacrificial layer 21 to form a stacked layer of a preset thickness, which is a bottom stacked layer 22; then SiGe 1 material may be deposited on the bottom stacked layer 22 to form a second sacrificial layer 23; finally, SiGe 2 material and Si material may be alternately deposited on the second sacrificial layer 23 to form a stacked layer of a preset thickness, which is a top stacked layer 24. It should be noted that the SiGe 1 material and SiGe 2 material here are only exemplary, and other materials may actually be used.

[0126] Step 2: Etch the top stack layer 24, the second sacrificial layer 23, the bottom stack layer 22, and the first sacrificial layer 21 sequentially until the substrate 20 to form an active structure 25 (see Figure 3A (b) in the figure.

[0127] A first active structure 251 close to the substrate, a second active structure 252 far from the substrate, a second intermediate sacrificial layer 253 and a first intermediate sacrificial layer 254 may be formed by etching.

[0128] Step 3: Deposit an oxide material on the substrate 20 to form an isolation structure 26, and perform CMP and etching to the upper surface of the first intermediate sacrificial layer 254 (see Figure 3A (c) in the figure.

[0129] Step 4: The gate region is opened by photolithography, and polysilicon and other materials are deposited in the gate region to form a pseudo gate structure 27 shared by the front and back sides, and a sidewall (spacer) 28 is formed on both sides of the pseudo gate structure and the active structure (see Figure 3B(a) in FIG. 1 ). By defining the gate regions of the front transistor and the back transistor in the flip-stack transistor through a pseudo-gate structure, self-alignment of the upper and lower transistors in the flip-stack transistor at the gate region can be achieved.

[0130] Step 5: Etch the sidewall 28 until the second intermediate sacrificial layer 253 to expose the active structure of the front transistor (see Figure 3B (b) in the figure.

[0131] Step 6: Etch the active structure in the source and drain area of ​​the front transistor (see Figure 3B (c) in the figure.

[0132] Step 7: Selectively etch the second intermediate sacrificial layer 253 between the active structures of the front and back transistors to form a first groove 29 (see Figure 3C (a) in the figure.

[0133] Step 8: Fill the insulating material and etch it until it is flush with the upper surface of the dummy gate structure 27 (see Figure 3C (b) in the figure.

[0134] Step 9: Anisotropically remove excess insulating material to form an MDI layer 30 in the first groove (see Figure 3C (c) in the figure.

[0135] Step 10: Laterally etch a portion of the SiGe2 material of the front transistor, fill with insulating material and etch again to form a first inner spacer 31 located on both sides of the SiGe2 of the front transistor (see Figure 3D (a) in the figure.

[0136] In some embodiments, the tenth step of forming the first inner sidewall may be performed simultaneously with the ninth step of forming the MDI layer.

[0137] Step 11: Anisotropic etching removes the spacers and active structures of the back transistor in the source and drain regions (see Figure 3D (b) in the figure.

[0138] Step 12: Anisotropically etch the first intermediate sacrificial layer 254 and the isolation structure 26 in the source and drain regions (see Figure 3D (c) in the figure.

[0139] Step 13: Fill the source and drain regions with insulating material to form a filling structure 32 covering the source and drain regions of the back transistor (see Figure 3E (a) in the figure.

[0140] Step 14: Form a source-drain isolation dielectric layer 33 on the filling structure 32 (see Figure 3E(b) in the figure.

[0141] It should be noted that the source-drain isolation dielectric layer is formed on the filling structure here, and the embodiment of the present application can also etch the filling structure after flipping the wafer to form the source-drain isolation dielectric layer. Or after flipping the wafer, part of the filling structure is etched and the remaining filling structure is used as the source-drain isolation dielectric layer.

[0142] Step 15: Form the first source-drain structure 112 of the front transistor (see Figure 3E (c) in the figure.

[0143] Step 16: Deposit an interlayer dielectric in the source and drain regions to form a first interlayer dielectric layer 113 (see Figure 3F (a) in the figure.

[0144] Step 17: Anisotropically etch the pseudo-gate structure of the front transistor (see Figure 3F (b) in the figure.

[0145] Step 18: Remove the SiGe2 material in the second active structure to form a second nanosheet structure 111, and deposit an insulating material on the surface of the second nanosheet structure 111 to form a first gate dielectric layer 1141, and deposit a metal material on the first gate dielectric layer 1141 in the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute a first gate structure 114 (see Figure 3F (c) in the figure.

[0146] Step 19: Form a first gate cut-off structure 34 on both sides of the first gate structure 114 (see Figure 3G (a) in the figure.

[0147] Step 20: Form a first isolation layer 35 on the first gate structure 114 and the first interlayer dielectric layer 113, and form a first source-drain metal 115 on the first source-drain structure 112 (see Figure 3G (b) in the figure.

[0148] Step 21: Forming a first metal interconnection layer 116 (see Figure 3G (c) in the figure.

[0149] Step 22: Deposit insulating material on the first metal interconnect layer 116 to form an insulating layer 13, bond the carrier wafer 14 to the insulating layer 13, and then flip the first transistor (see Figure 3H (a) in the figure.

[0150] Step 23: Thinning and CMP removal of substrate 20 (see Figure 3H (b) in the figure.

[0151] Step 24: Selectively etch the isolation structure 26 in the gate region (see Figure 3H (c) in the figure.

[0152] Step 25: Fill the etched area with polysilicon or other materials to supplement the pseudo gate structure formed above (see Fig. 3I (a) in the figure.

[0153] Step 26: Remove the filling structure 32 (see Fig. 3I (b) in the figure.

[0154] Step 27: Laterally etch a portion of the SiGe2 material of the back transistor, fill it with insulating material and etch it to form a second inner sidewall 36 located on both sides of the SiGe2 of the back transistor (see Fig. 3I (c) in the figure.

[0155] Step 28: Form the second source-drain structure 122 and the second interlayer dielectric layer 123 of the back transistor (see Figure 3J (a) in the figure.

[0156] Step 29: Etch and remove the pseudo gate structure of the back transistor (see Figure 3J (b) in the figure.

[0157] Step 30: Deposit an insulating dielectric in the gate region, and then perform CMP and etching to the upper surface of the MDI layer 30 to form a gate insulating dielectric layer 37 (see Figure 3J (c) in the figure.

[0158] Step 31: Remove the SiGe2 material in the first active structure to form a first nanosheet structure 121, and deposit an insulating material on the surface of the first nanosheet structure 121 to form a second gate dielectric layer 1241, and deposit a metal material on the second gate dielectric layer 1241 in the gate region to form a second gate electrode layer 1242. The second gate dielectric layer 1241 and the second gate electrode layer 1242 constitute a second gate structure 124 (see Figure 3K (a) in the figure.

[0159] Step 32: Form a second gate cut-off structure 38 on both sides of the second gate structure 124 (see Figure 3K (b) in the figure.

[0160] Step 33: Form a second isolation layer 39 on the second gate structure 124 and the second interlayer dielectric layer 123, and form a second source-drain metal 125 on the second source-drain structure 122 (see Figure 3K (c) in the figure.

[0161] Step 34: Forming a second metal interconnection layer 126 (see Figure 3L ).

[0162] The second preparation process is introduced below, that is, forming a gate structure and a gate cut-off structure on the back side at the same time, and an isolation layer is provided between the gate structure of the front transistor and the gate structure of the back transistor. Figures 4A to 4K This is a schematic diagram of the structure of the flip-chip stack transistor in the second preparation process according to an embodiment of the present application. Figure 4L This is a schematic diagram of the second structure of the flip-chip stacked transistor of the embodiment of the present application. It should be noted that the method of forming the gate cut-off structure on the back side during the second preparation process is only an example, and in fact, the gate cut-off structure can also be formed on the front side at once, or on the front side and the back side respectively.

[0163] Step 1: forming a first sacrificial layer 21 on the original substrate 20, forming a bottom stacking layer 22 on the first sacrificial layer 21, forming a second sacrificial layer 23 on the bottom stacking layer 22, and forming a top stacking layer 24 on the second sacrificial layer 23 (see Figure 4A (a) in the figure.

[0164] For example, a Si layer 20 may be provided, and SiGe1 material may be deposited on the Si layer 20 to form a first sacrificial layer 21; then SiGe2 material and Si material may be alternately deposited on the first sacrificial layer 21 to form a stacked layer of a preset thickness, which is a bottom stacked layer 22; then SiGe1 material may be deposited on the bottom stacked layer 22 to form a second sacrificial layer 23; finally, SiGe2 material and Si material may be alternately deposited on the second sacrificial layer 23 to form a stacked layer of a preset thickness, which is a top stacked layer 24. It should be noted that the SiGe1 material here is only an exemplary description, and other materials may actually be used.

[0165] Step 2: Etch the top stack layer 24, the second sacrificial layer 23, the bottom stack layer 22, and the first sacrificial layer 21 sequentially until the substrate 20 to form an active structure 25 (see Figure 4A (b) in the figure.

[0166] A first active structure 251 close to the substrate, a second active structure 252 far from the substrate, a second intermediate sacrificial layer 253 and a first intermediate sacrificial layer 254 may be formed by etching.

[0167] Step 3: Deposit an oxide material on the substrate 20 to form an isolation structure 26, and perform CMP and etching to the upper surface of the first intermediate sacrificial layer 254 (see Figure 4A (c) in the figure.

[0168] Step 4: The gate region is opened by photolithography, and polysilicon and other materials are deposited in the gate region to form a pseudo gate structure 27 shared by the front and back sides, and a sidewall (spacer) 28 is formed on both sides of the pseudo gate structure and the active structure (see Figure 4B (a) in the figure.

[0169] Step 5: Etch the sidewall 28 until the second intermediate sacrificial layer 253 to expose the active structure of the front transistor (see Figure 4B (b) in the figure.

[0170] Step 6: Etch the active structure in the source and drain area of ​​the front transistor (see Figure 4B (c) in the figure.

[0171] Step 7: Selectively etch the second intermediate sacrificial layer 253 between the active structures of the front and back transistors to form a first groove 29 (see Figure 4C (a) in the figure.

[0172] Step 8: Fill with insulating material and perform CMP until the surface is flush with the upper surface of the dummy gate structure 27 (see Figure 4C (b) in the figure.

[0173] Step 9: Anisotropically remove excess insulating material to form an MDI layer 30 in the first groove (see Figure 4C (c) in the figure.

[0174] It should be noted that the embodiment of the present application may not form an MDI layer. In the case where the MDI layer is not formed, the second intermediate sacrificial layer 253 may be made of Si material. Moreover, the fifth step may etch the sidewall 28 to the position above the second intermediate sacrificial layer 253 and around the bottom of the second active structure 252. At this time, the sidewall 28 may play a role in limiting the growth of the source-drain structure of the first transistor.

[0175] Step 10: Laterally etch a portion of the SiGe2 material of the front transistor, fill with insulating material and etch again to form a first inner spacer 31 located on both sides of the SiGe2 of the front transistor (see Figure 4D (a) in the figure.

[0176] Step 11: Anisotropic etching removes the spacer and active structure of the back transistor in the source and drain area (see Figure 4D (b) in the figure.

[0177] Step 12: Anisotropically etch the first intermediate sacrificial layer 254 and the isolation structure 26 in the source and drain regions (see Figure 4D (c) in the figure.

[0178] Step 13: Fill the source and drain regions with insulating material to form a filling structure 32 covering the source and drain regions of the back transistor (see Figure 4E (a) in the figure.

[0179] Step 14: Form a source-drain isolation dielectric layer 33 on the filling structure 32 (see Figure 4E (b) in the figure.

[0180] It should be noted that the source-drain isolation dielectric layer is formed on the filling structure here, and the embodiment of the present application can also etch the filling structure after flipping the wafer to form the source-drain isolation dielectric layer. Or after flipping the wafer, part of the filling structure is etched and the remaining filling structure is used as the source-drain isolation dielectric layer.

[0181] Step 15: Form the first source-drain structure 112 of the front transistor (see Figure 4E (c) in the figure.

[0182] Step 16: Deposit an interlayer dielectric in the source and drain regions to form a first interlayer dielectric layer 113 (see Figure 4F (a) in the figure.

[0183] Step 17: Form a first isolation layer 35 on the dummy gate structure 27 and the first interlayer dielectric layer 113, and form a first source-drain metal 115 on the first source-drain structure 112 (see Figure 4F (b) in the figure.

[0184] Step 18: Forming a first metal interconnection layer 116 (see Figure 4F (c) in the figure.

[0185] Step 19: Deposit insulating material on the first metal interconnect layer 116 to form an insulating layer 13, bond the carrier wafer 14 to the insulating layer 13, and then flip the first transistor (see Figure 4G (a) in the figure.

[0186] Step 20: Remove the substrate 20 (see Figure 4G (b) in the figure.

[0187] Step 21: Selectively etch the isolation structure 26 in the gate region (see Figure 4G (c) in the figure.

[0188] Step 22: Fill the etched area with polysilicon or other materials to form a pseudo gate structure (see Figure 4H (a) in the figure.

[0189] Step 23: Remove the filling structure 32 (see Figure 4H (b) in the figure.

[0190] Step 24: Laterally etch a portion of the SiGe2 material of the back transistor, fill it with insulating material and etch it to form a second inner sidewall 36 located on both sides of the SiGe2 of the back transistor (see Figure 4H (c) in the figure.

[0191] Step 25: Form the second source-drain structure 122 and the second interlayer dielectric layer 123 of the back transistor (see Fig. 4I (a) in the figure.

[0192] Step 26: Etch and remove the dummy gate structure 27 (see Fig. 4I (b) in the figure.

[0193] Step 27: Remove the SiGe2 material in the active structure to form the first nanosheet structure 121 and the second nanosheet 111, and deposit an insulating material on the surface of the first nanosheet structure 121 and the second nanosheet 111 to form a gate dielectric layer 401, and deposit a metal material on the gate dielectric layer 401 in the gate region to form a gate electrode layer 402. The gate dielectric layer 401 and the gate electrode layer 402 constitute the gate structure 40 (see Fig. 4I (c) in the figure.

[0194] like Fig. 4I As shown in AA' in (c), the gate structure 40 formed here surrounds the nanosheet structure of the front transistor and the nanosheet structure of the back transistor.

[0195] Step 28: Etch back the gate electrode layer 402 to the front transistor position to form the first gate structure 114 of the front transistor (see Figure 4J (a) in the figure.

[0196] The first gate structure includes a first gate dielectric layer 1141 and a first gate electrode layer 1142 .

[0197] Step 29: Deposit an insulating dielectric on the first gate structure 114, and then CMP to the upper surface of the MDI layer 30 to form a gate isolation dielectric layer 37 (see Figure 4J (b) in the figure.

[0198] Step 30: Form the second gate structure 124 of the back transistor (see Figure 4J (c) in the figure.

[0199] The second gate structure includes a second gate dielectric layer 1241 and a second gate electrode layer 1242 .

[0200] Step 31: Form a gate cut-off structure 41 on both sides of the first gate structure 114 and the second gate structure 124 (see Figure 4K (a) in the figure.

[0201] Step 32: Form a second isolation layer 39 on the second gate structure 124 and the second interlayer dielectric layer 123, and form a second source-drain metal 125 on the second source-drain structure 122 (see Figure 4K (b) in the figure.

[0202] Step 33: Form a second metal interconnection layer 126 (see Figure 4L ).

[0203] The third preparation process is described below, that is, forming the gate structure on the back side at one time, and there is no isolation layer between the gate structure of the front transistor and the gate structure of the back transistor. Figure 5A is a schematic diagram of the structure of the flip-chip stack transistor in the third preparation process according to an embodiment of the present application, Figure 5B This is a third structural schematic diagram of the flip-chip stack transistor according to an embodiment of the present application.

[0204] Step 1: Form a gate structure 40 shared by the front and back transistors on the back side (see Figure 5A (a) in the figure.

[0205] Reference may be made here to the first to twenty-seventh steps of the preparation method of the second structure described above.

[0206] The gate structure may include a first gate structure corresponding to the second nanosheet structure, and a second gate structure corresponding to the first nanosheet structure.

[0207] Step 2: Form gate cut-off structures 41 on both sides of the gate structure 40 (see Figure 5A (b) in the figure.

[0208] Step 3: Form a second isolation layer 39 on the gate structure 40 and the second interlayer dielectric layer 123, and form a second source-drain metal 125 on the second source-drain structure 122 (see Figure 5A (c) in the figure.

[0209] Step 33: Form a second metal interconnection layer 126 (see Figure 5B ).

[0210] The fourth preparation process is introduced below. The difference from the preparation process of the first structure is that here an isolation layer between the front transistor and the back transistor in the source and drain region is formed on the back side. FIG. 6A to FIG. 6E is a schematic structural diagram of a flip-chip stack transistor in a fourth preparation process according to an embodiment of the present application, Fig. 6F This is a fourth structural schematic diagram of the flip-chip stacked transistor according to an embodiment of the present application.

[0211] Step 1: Form a filling structure 32 covering the source and drain regions of the back transistor (see Fig. 6A (a) in the figure.

[0212] Reference may be made here to the first to thirteenth steps of the preparation method of the first structure described above.

[0213] Step 2: Form the first source-drain structure 112 of the front transistor (see Fig. 6A (b) in the figure.

[0214] Step 3: Deposit an interlayer dielectric in the source / drain region to form a first interlayer dielectric layer 113 (see Fig. 6A (c) in the figure.

[0215] Step 4: Anisotropically etch the pseudo-gate structure of the front transistor (see Figure 6B (a) in the figure.

[0216] Step 5: Remove the SiGe2 material in the second active structure to form a second nanosheet structure 111, and deposit an insulating material on the surface of the second nanosheet structure 111 to form a first gate dielectric layer 1141, and deposit a metal material on the first gate dielectric layer 1141 in the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute a first gate structure 114 (see Figure 6B (b) in the figure.

[0217] Step 6: Form a first gate cut-off structure 34 on both sides of the first gate structure 114 (see Figure 6B (c) in the figure.

[0218] Step 7: Form a first isolation layer 35 on the first gate structure 114 and the first interlayer dielectric layer 113, and form a first source-drain metal 115 on the first source-drain structure 112 (see Figure 6C (a) in the figure.

[0219] Step 8: Forming a first metal interconnection layer 116 (see Figure 6C (b) in the figure.

[0220] Step 9: Deposit insulating material on the first metal interconnect layer 116 to form an insulating layer 13, bond the carrier wafer 14 to the insulating layer 13, and then flip the first transistor (see Figure 6C (c) in the figure.

[0221] Step 10: Remove the substrate 20 (see Fig.6D (a) in the figure.

[0222] Step 11: Selectively etch the isolation structure 26 in the gate region (see Fig.6D (b) in the figure.

[0223] Step 12: Fill the etched area with polysilicon or other materials to form a pseudo gate structure (see Fig.6D (c) in the figure.

[0224] Step 13: Remove the filling structure 32 (see Fig. 6E (a) in the figure.

[0225] Step 14: Deposit an insulating dielectric in the etched area and perform CMP to the active structure of the back transistor to form a source-drain isolation dielectric layer 33 (see Fig. 6E (b) in the figure.

[0226] Step 15: Formation of the second metal interconnect layer 126 of the backside transistor according to the standard process flow (see Fig. 6F ).

[0227] Reference may be made here to steps 27 to 34 of the preparation method of the first structure described above.

[0228] The fifth preparation process is introduced below. Different from the preparation process of the first structure, here part of the filling structure is etched, and the remaining filling structure is used as an isolation layer between the front transistor and the back transistor in the source and drain region. 7A to 7E is a schematic diagram of the structure of the flip-chip stack transistor in the fifth preparation process according to an embodiment of the present application, Figure 7F This is a fifth structural schematic diagram of the flip-chip stacked transistor according to an embodiment of the present application.

[0229] Step 1: Form a filling structure 32 covering the source and drain regions of the back transistor (see Fig. 7A (a) in the figure.

[0230] Reference may be made here to the first to thirteenth steps of the preparation method of the first structure described above.

[0231] Step 2: Form the first source-drain structure 112 of the front transistor (see Fig. 7A (b) in the figure.

[0232] Step 3: Deposit an interlayer dielectric in the source / drain region to form a first interlayer dielectric layer 113 (see Fig. 7A (c) in the figure.

[0233] Step 4: Anisotropically etch the pseudo-gate structure of the front transistor (see Figure 7B (a) in the figure.

[0234] Step 5: Remove the SiGe2 material in the second active structure to form a second nanosheet structure 111, and deposit an insulating material on the surface of the second nanosheet structure 111 to form a first gate dielectric layer 1141, and deposit a metal material on the first gate dielectric layer 1141 in the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute a first gate structure 114 (see Figure 7B (b) in the figure.

[0235] Step 6: Form a first gate cut-off structure 34 on both sides of the first gate structure 114 (see Figure 7B (c) in the figure.

[0236] Step 7: Form a first isolation layer 35 on the first gate structure 114 and the first interlayer dielectric layer 113, and form a first source-drain metal 115 on the first source-drain structure 112 (see Figure 7C (a) in the figure.

[0237] Step 8: Forming a first metal interconnection layer 116 (see Figure 7C (b) in the figure.

[0238] Step 9: Deposit insulating material on the first metal interconnect layer 116 to form an insulating layer 13, bond the carrier wafer 14 to the insulating layer 13, and then flip the first transistor (see Figure 7C (c) in the figure.

[0239] Step 10: Remove the substrate 20 (see Fig.7D (a) in the figure.

[0240] Step 11: Selectively etch the isolation structure 26 in the gate region (see Fig.7D (b) in the figure.

[0241] Step 12: Fill the etched area with polysilicon or other materials to form a pseudo gate structure (see Fig.7D (c) in the figure.

[0242] Step 13: Etch part of the filling structure 32 and use the remaining filling structure as the source-drain isolation dielectric layer 33 (see Fig. 7E ).

[0243] Step 14: Formation of the second metal interconnect layer 126 of the backside transistor according to the standard process flow (see Figure 7F ).

[0244] Reference may be made here to steps 27 to 34 of the preparation method of the first structure described above.

[0245] In the embodiment of the present application, the gate structure of the flip-chip stacked transistor can be formed at one time on the back side, or it can be formed separately on the front and back sides. There may be an isolation structure (i.e., a gate isolation dielectric layer) between the gate structure of the front transistor and the gate structure of the back transistor, or there may be no isolation structure. A gate cut-off structure may be formed on both sides of the gate structure, or there may be no gate cut-off structure. In the case of forming a gate cut-off structure, the gate cut-off structure may be formed at one time on the back side, or it may be formed at one time on the front side, or it may be formed separately on the front and back sides. There may be an isolation structure (i.e., a source-drain isolation dielectric layer) between the source-drain structure of the front transistor and the source-drain structure of the back transistor, or there may be no isolation structure. In the case of a source-drain isolation dielectric layer, the source-drain isolation dielectric layer may be formed on the front side or on the back side, and an isolation material may be deposited separately to form a source-drain isolation dielectric layer, or the filling structure retained after the etching part is used as a source-drain isolation dielectric layer. In the embodiment of the present application, the method for forming the gate structure is completely independent of the method for forming the source-drain region, and the various formation methods of the two may be arranged and combined, and the embodiment of the present application does not specifically limit this. In addition, the embodiment of the present application may form an MDI layer or may not form an MDI layer. When the MDI layer is not formed, in the first step of the above-mentioned various preparation processes, after forming the bottom stacking layer 22, the second sacrificial layer 23 is not formed, and the top stacking layer 24 can be directly formed on the bottom stacking layer 22.

[0246] In the present application, an active structure including a first part and a second part is formed on a substrate, a pseudo-gate structure is formed on the active structure, the active structure in the source-drain region is etched, and a filling structure is formed in the first source-drain region corresponding to the first part, so that the filling structure covers the source-drain region of the back transistor. Then, based on the second source-drain region corresponding to the second part, a first transistor is formed, the first transistor is flipped and the substrate is removed, and then the filling structure is removed to expose the first source-drain region, and a second transistor is formed based on the first source-drain region. After the transistor is flipped, the filling structure and the pseudo-gate structure are used to define the source-drain region and the gate region where the back transistor is located, so that when preparing the back transistor, it is not necessary to select the region through photolithography, and the source-drain region and the gate region can be directly opened through the selectivity of the material to prepare a back transistor that is completely self-aligned with the front transistor. In this way, the requirements for photolithography can be reduced, and the source-drain region of the front transistor of the flip-chip stacked transistor can be completely self-aligned with the source-drain region of the back transistor.

[0247] Furthermore, the flip-chip stacked transistor provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the structure of the flip-chip stacked transistor.

[0248] The present application provides a semiconductor device, including: a flip-chip stacked transistor as in the above embodiment. The specific definition of the flip-chip stacked transistor can be found in the above flip-chip stacked transistor, which will not be described in detail here.

[0249] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device being arranged on the circuit board. The semiconductor device includes the above flip-chip stacked transistor. The specific definition of the flip-chip stacked transistor can be referred to the above flip-chip stacked transistor, which will not be described in detail here.

[0250] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0251] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a flip-chip stacked transistor, characterized in that: The method comprises: forming an active structure on a substrate, the active structure having a first portion and a second portion, the first portion being closer to the substrate than the second portion; Etching the active structure in the source-drain region, and filling the first source-drain region corresponding to the first part on the substrate with an insulating material to form a filling structure; On the filling structure, based on the second source-drain region, forming a first source-drain structure and a first source-drain metal of the first transistor, wherein the second source-drain region corresponds to the second portion; Flipping the first transistor and removing the substrate; Selectively etching the filling structure to expose the first source and drain region; Based on the first source-drain region, a second source-drain structure and a second source-drain metal of the second transistor are formed.

2. The method according to claim 1, characterized in that The forming of an active structure on a substrate comprises: providing a substrate; forming a sacrificial layer and a first material layer in sequence on the substrate; Etching the sacrificial layer and the first material layer to form the active structure, wherein the active structure is the etched first material layer; After flipping the first transistor and removing the substrate, the method further includes: Filling a semiconductor material in the gate region so that the upper surface of the formed dummy gate structure is flush with the upper surface of the sacrificial layer; The sacrificial layer is removed.

3. The method according to claim 1, characterized in that The method further comprises: Before forming a first source-drain structure and a first source-drain metal of the first transistor based on the second source-drain region, depositing a semiconductor material on the active structure to form a dummy gate structure; After forming a first source-drain structure of the first transistor, removing a third portion of the dummy gate structure to form a first gate structure of the first transistor, and after forming a second source-drain structure of the second transistor, removing a fourth portion of the dummy gate structure to form a second gate structure of the second transistor, the third portion corresponding to the second portion, and the fourth portion corresponding to the first portion; Alternatively, after forming the second source-drain structure of the second transistor, the dummy gate structure is removed to form a first gate structure of the first transistor and a second gate structure of the second transistor respectively.

4. The method according to claim 1, characterized in that: After forming the first gate structure of the first transistor and / or forming the second gate structure of the second transistor, the method further includes: A gate cut-off structure is formed on both sides of the first gate structure and the second gate structure, and the gate cut-off structure is used to isolate the gate region of the flip-chip stacked transistor from the gate region of an adjacent flip-chip stacked transistor.

5. The method according to claim 1, characterized in that The method further comprises: Before forming the first source-drain structure and the first source-drain metal of the first transistor, forming a source-drain isolation dielectric layer on the filling structure, wherein the source-drain isolation dielectric layer is used to isolate the first source-drain structure from the second source-drain structure; Alternatively, after forming the first source-drain structure and the first source-drain metal of the first transistor and before forming the second source-drain structure and the second source-drain metal of the second transistor, the source-drain isolation dielectric layer is formed on the second source-drain region.

6. The method according to claim 1, characterized in that The method of selectively etching the filling structure through the material comprises: The filling structure is selectively etched to a preset height, and the remaining filling structure is used as a source-drain isolation dielectric layer, wherein the source-drain isolation dielectric layer is used to isolate the first source-drain structure from the second source-drain structure.

7. The method according to claim 1, characterized in that The method further comprises: A gate isolation dielectric layer is formed on the first gate structure of the first transistor, and the gate isolation dielectric layer is used to isolate the first gate structure from the second gate structure of the second transistor.

8. A flip-chip stack transistor, prepared using the preparation method according to any one of claims 1 to 7, characterized in that: include: a first transistor; a second transistor, wherein the first transistor and the second transistor are arranged opposite to each other; The first source-drain structure of the first transistor and the second source-drain structure of the second transistor are self-aligned in a vertical direction.

9. A semiconductor device, characterized in that: include: The flip-chip stack transistor as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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