Method for forming contact hole of semiconductor device and semiconductor device structure

Abstract

The present application discloses a method for forming a contact hole of a semiconductor device and a semiconductor device structure. The method includes: providing a substrate formed with a first contact hole etch stop layer, and a plurality of gate structures are also formed on the substrate; forming an original sacrificial layer on the first contact hole etch stop layer, and partially modifying the original sacrificial layer so that the original sacrificial layer located above the top of each gate structure is modified into a modified sacrificial layer; etching the modified sacrificial layer and the first contact hole etch stop layer so that the first contact hole etch stop layer located between the modified sacrificial layer and the top of each gate structure is retained and a compensation etch stop layer is formed; forming a target structure including a second contact hole etch stop layer and an interlayer dielectric layer on the substrate; and forming a contact hole on the target structure. Through the scheme of the present application, problems such as gate damage and interlayer dielectric layer gaps and holes that are prone to occur during the contact hole manufacturing process are improved.

Description

Technical Field

[0001] The present application generally relates to the field of semiconductor manufacturing processes and more specifically to a method for forming a contact hole of a semiconductor device and a semiconductor device structure. Background Art

[0002] In the preparation process of semiconductor devices, the interlayer dielectric (ILD) process refers to the dielectric material formed between the device and the metal layer 1 to form electrical isolation. The contact hole process refers to the formation of many small vertical through holes on the ILD dielectric layer, which is the connection channel between the transistor and the metal layer 1. In the existing contact hole processing process, due to the large height difference between the gate and the source and drain, a contact hole etch stop layer is often required to eliminate the etching load. Among them, the contact hole etch stop layer must have a certain thickness to prevent the gate polysilicon from being over-etched. However, as the size of semiconductor devices decreases, the spacing between gates is further reduced, and the thickness occupied by the contact hole etch stop layer will make it more and more difficult to fill the oxide layer in the ILD, and defects such as gaps and holes will often occur, causing electrical offsets and other problems.

[0003] Figure 1 A schematic diagram of the structure of a semiconductor device in the related art is shown. As shown in the figure, the semiconductor device 100 includes a substrate 101. A plurality of gates 102, a contact hole etch stop layer 103 and an interlayer dielectric layer 104 are formed on the substrate 101. It can be seen that the contact hole etch stop layer 103 has a certain thickness, and as the spacing between adjacent gates 102 decreases, the thicker contact hole etch stop layer 103 will increase the depth-to-width ratio of the oxide layer when filling the interlayer dielectric layer 104, thereby causing the filling of the oxide layer to become increasingly difficult, and the aforementioned problems such as gaps and holes often occur. At the same time, during the etching process of the contact hole 105, due to the presence of the above-mentioned etching height load, and the thickness of the contact hole etch stop layer 103 at the gate 102 and other regions is the same, when the contact hole 105 is etched to the contact hole etch stop layer between adjacent gates 102, the contact hole etch stop layer at the top of the gate 102 is often over-etched (such as Figure 1 ), thereby causing the gate 102 to be damaged.

[0004] In view of this, there is an urgent need to provide a solution for forming contact holes of semiconductor devices, so as to improve the problems of gate damage, gaps and holes that are prone to occur during the contact hole formation process. Summary of the invention

[0005] In order to at least solve one or more of the technical problems mentioned above, the present application proposes a solution for forming a contact hole of a semiconductor device in multiple aspects.

[0006] In a first aspect, the present application provides a method for forming a contact hole of a semiconductor device, comprising: providing a substrate having a first contact hole etch stop layer formed thereon, wherein a plurality of gate structures are also formed on the substrate, and the first contact hole etch stop layer is located above the gate structures; forming an original sacrificial layer on the first contact hole etch stop layer, and partially modifying the original sacrificial layer so that the original sacrificial layer located above the top of each of the gate structures is modified into a modified sacrificial layer; etching the modified sacrificial layer and the first contact hole etch stop layer so that the first contact hole etch stop layer located between the modified sacrificial layer and the top of each of the gate structures is retained, and a compensation etch stop layer is formed, wherein a critical dimension of the compensation etch stop layer is smaller than a critical dimension of the gate structure; forming a target structure including a second contact hole etch stop layer and an interlayer dielectric layer on the substrate, wherein a film thickness of the second contact hole etch stop layer is smaller than a film thickness of the first contact hole etch stop layer; and forming a contact hole on the target structure.

[0007] In some embodiments, forming an original sacrificial layer on the first contact hole etch stop layer includes: forming the original sacrificial layer having a film thickness not less than that of the first contact hole etch stop layer on the first contact hole etch stop layer using a chemical vapor deposition process.

[0008] In some embodiments, partially modifying the original sacrificial layer includes: coating the original sacrificial layer with photoresist; etching back the photoresist to expose the top of the original sacrificial layer, wherein the height of the photoresist is not lower than the height of the gate structure; and modifying the portion of the original sacrificial layer not covered by the photoresist.

[0009] In some embodiments, modifying the portion of the original sacrificial layer not covered by the photoresist includes: injecting modifying ions into the portion of the original sacrificial layer not covered by the photoresist; and removing the photoresist and the portion of the original sacrificial layer covered by the photoresist, wherein the wet etching rate of the modified sacrificial layer is lower than that of the unmodified original sacrificial layer.

[0010] In some embodiments, wherein the first contact hole etch stop layer comprises a silicon nitride layer, and the original sacrificial layer comprises a silicon oxide layer, modifying the portion of the original sacrificial layer not covered by the photoresist comprises: injecting nitrogen ions into the portion of the silicon oxide layer not covered by the photoresist; removing the photoresist; and removing the portion of the original sacrificial layer covered by the photoresist using a wet etching process.

[0011] In some embodiments, etching the modified sacrificial layer and the first contact hole etch stop layer includes: using a diluted hydrofluoric acid wet etching process to push back the side wall of the modified sacrificial layer, so that the critical dimension of the modified sacrificial layer after the push back is not larger than the critical dimension of the gate structure and larger than the critical dimension of the contact hole, and the film thickness of the modified sacrificial layer after the push back is not larger than the film thickness of the first contact hole etch stop layer; and etching the modified sacrificial layer and the first contact hole etch stop layer after the push back.

[0012] In some embodiments, etching the pushed-back modified sacrificial layer and the first contact hole etch stop layer includes: etching the pushed-back modified sacrificial layer and the first contact hole etch stop layer using a hot phosphoric acid etching process; or thinning the pushed-back modified sacrificial layer and the first contact hole etch stop layer that are not covered by the pushed-back modified sacrificial layer using a dry etching process; and etching the thinned modified sacrificial layer and the first contact hole etch stop layer using a hot phosphoric acid etching process.

[0013] In some embodiments, forming a target structure including a second contact hole etch stop layer and an interlayer dielectric layer on the substrate includes: forming the second contact hole etch stop layer on the substrate using chemical vapor deposition technology, wherein the thickness of the contact hole etch stop layer corresponding to the area on the top of each gate structure covered by the compensation etch stop layer is the sum of the thicknesses of the compensation etch stop layer and the second contact hole etch stop layer, and the thickness of the contact hole etch stop layer corresponding to other areas on the substrate is the thickness of the second contact hole etch stop layer; and forming the interlayer dielectric layer on the second contact hole etch stop layer using a high aspect ratio process.

[0014] In a second aspect, the present application provides a semiconductor device structure, comprising: a substrate; a target structure and a plurality of gate structures formed on the substrate; and a contact hole formed on the target structure, wherein the contact hole is made using the formation method described in the first aspect.

[0015] In some embodiments, the compensating etch stop layer is formed by a first contact hole etch stop layer located between the modified sacrificial layer and the top of each of the gate structures, and the film thickness of the contact hole etch stop layer corresponding to the area covered by the compensating etch stop layer on the top of each gate structure is greater than the film thickness of the contact hole etch stop layer corresponding to other areas on the substrate, and the critical dimension of the compensating etch stop layer is smaller than the critical dimension of the gate structure.

[0016] The unexpected beneficial technical effect of the present application is: through the method for forming a contact hole of a semiconductor device and the semiconductor device structure provided above, the embodiment of the present application forms an original sacrificial layer on the initial first contact hole etch stop layer during the contact hole formation process of the semiconductor device, and modifies the original sacrificial layer to obtain a modified sacrificial layer. In the subsequent etching process, the modified sacrificial layer is used to protect the first contact hole etch stop layer covered by it, so that the first contact hole etch stop layer located between the modified sacrificial layer and the top of each gate structure is retained and forms a compensation etch stop layer. At the same time, a second contact hole etch stop layer with a film thickness less than the first contact hole etch stop layer is formed on the substrate. As a result, the contact hole etch stop layer (i.e., the second contact hole etch stop layer) at the position between adjacent gate structures is thinned, and at the same time, the contact hole etch stop layer at the top part of the gate structure is thickened due to the effect of the compensation etch stop layer, and the critical dimension of the compensation etch stop layer is smaller than the critical dimension of the gate, which will form a "step" at the hole filling opening of the interlayer dielectric layer, so that the hole filling opening is enlarged when the oxide layer in the interlayer dielectric layer is filled, effectively reducing the hole filling aspect ratio. That is, the solution of the present application can achieve the gate structure without damage during the contact hole etching process through the compensation etch stop layer on the top of the gate structure on the basis of thinning the contact hole etch stop layer, and at the same time, the hole filling opening is enlarged and the aspect ratio is reduced, thereby filling a seamless and hole-free structure, thereby improving the overall performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become easy to understand. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0018] Figure 1 A cross-sectional schematic diagram of a semiconductor device structure with contact holes formed therein in the related art is shown;

[0019] Figure 2 A cross-sectional schematic diagram showing a semiconductor device structure according to an embodiment of the present application;

[0020] Figure 3 A schematic flow chart showing a method for forming a contact hole of a semiconductor device according to some embodiments of the present application;

[0021] Figure 4 A schematic flowchart showing a method for forming a contact hole of a semiconductor device according to other embodiments of the present application; and

[0022] Figure 5a-5jA cross-sectional schematic diagram of a semiconductor device during a contact hole formation process using some embodiments of the present application is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0024] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present application indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0025] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in this application specification and claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms. It should also be further understood that the term "and / or" used in this application specification and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0026] The specific implementation of the present application is described in detail below with reference to the accompanying drawings.

[0027] Figure 2 A cross-sectional schematic diagram of a semiconductor device structure 200 according to an embodiment of the present application is shown.

[0028] The semiconductor device structure in the solution of the present application may include a Metal Oxide Semiconductor Field Effect Transistor (MOS), a Complementary Metal Oxide Semiconductor (CMOS), and the like.

[0029] like Figure 2 As shown, the semiconductor device structure 200 may include a substrate 201, a target structure formed on the substrate 201, and a plurality of gate structures. The substrate 201 may be a silicon substrate, a silicon germanium substrate, or other semiconductor material substrates known to those skilled in the art. For example, MOS transistors, CMOS transistors, etc. generally use silicon substrates, etc.

[0030] The gate structure may specifically include a gate polysilicon 202 and a contact layer (such as metal silicide such as NiSi) located on the top of the gate polysilicon 202. The film thickness of the contact layer is usually thin and is used to reduce the contact resistance. In some embodiments, a sidewall structure (for example, a sidewall of an ONO structure may be used) is also formed on the side of the gate polysilicon 202. In addition, a gate oxide layer may also be formed between the substrate 201 and the gate polysilicon 202. It should be noted that the gate polysilicon, contact layer, sidewall, gate oxide layer, etc. in this embodiment can be formed using traditional or known processes, and the specific details of these structures will not be repeated in the solution of the present application. In addition, a source and a drain are also formed on the substrate 201. The source and the drain can be prepared using known techniques, and the solution of the present application does not provide too much explanation on the source and the drain.

[0031] In this embodiment, the contact hole 206 of the semiconductor device 200 is mainly formed by the following process:

[0032] First, a substrate 201 is provided on which a first contact hole etching stop layer (not shown in the figure) is formed. A plurality of gate structures (such as Figure 2 The first contact hole etch stop layer is located above the gate structure and other areas of the substrate 201. Next, an original sacrificial layer (not shown in the figure) is formed on the first contact hole etch stop layer, and the original sacrificial layer is partially modified so that the original sacrificial layer located above the top of each gate structure is modified into a modified sacrificial layer (not shown in the figure). Then, the modified sacrificial layer and the first contact hole etch stop layer are etched so that the first contact hole etch stop layer located between the modified sacrificial layer and the top of each gate structure is retained and a compensation etch stop layer (not shown in the figure) is formed. The critical dimension of the compensation etch stop layer is smaller than the critical dimension of the gate structure.

[0033] Next, a target structure including a second contact hole etch stop layer 203 and an interlayer dielectric layer 205 is formed on the substrate 201. The thickness of the second contact hole etch stop layer 203 is less than the thickness of the first contact hole etch stop layer. Then, a contact hole 206 is formed on the target structure. The specific preparation process of the above-mentioned various parts of the semiconductor device can refer to the relevant description below.

[0034] Furthermore, the aforementioned compensating etch stop layer is formed by a first contact hole etch stop layer located between the modified sacrificial layer and the top of each gate structure, and the film thickness of the contact hole etch stop layer 204 corresponding to the area on the top of each gate structure covered by the compensating etch stop layer is greater than the film thickness of the contact hole etch stop layer (i.e., the second contact hole etch stop layer 203) corresponding to other areas on the substrate 201 (e.g., the area on the top of the gate structure not covered by the compensating etch stop layer, the sidewall area of ​​the gate structure, the recessed area between adjacent gate structures, etc.), and the critical dimension of the compensating etch stop layer is smaller than the critical dimension of the gate structure.

[0035] During the formation of the contact hole 206 of the semiconductor device 200 in the present application, an original sacrificial layer is additionally formed on the initial first contact hole etch stop layer, and the original sacrificial layer is modified to obtain a modified sacrificial layer. In the subsequent etching process, the modified sacrificial layer is used to protect the first contact hole etch stop layer covered by it, so that the first contact hole etch stop layer located between the modified sacrificial layer and the top of each gate structure is retained and forms a compensation etch stop layer. At the same time, a second contact hole etch stop layer 203 with a film thickness less than the first contact hole etch stop layer is formed on the substrate 201 (for example, the film thickness of the second contact hole etch stop layer 203 can be about one tenth of the film thickness of the first contact hole etch stop layer). In addition, the critical dimension of the compensation etch stop layer is smaller than the critical dimension of the gate structure, which can expand the hole filling opening when the oxide layer in the interlayer dielectric layer 205 is filled, and reduce the hole filling aspect ratio.

[0036] The unexpected beneficial technical effect of the present application is that the contact hole etch stop layer (i.e., the second contact hole etch stop layer 201) at the position between the adjacent gate structures on the substrate 201 of the semiconductor device 200 is thinned, and at the same time, the contact hole etch stop layer 204 at the top part of the gate structure increases in thickness due to the effect of the compensation etch stop layer, and the critical dimension of the compensation etch stop layer is smaller than the critical dimension of the gate, which will form a "step" at the hole filling opening of the interlayer dielectric layer, so that the hole filling opening in the oxide layer of the interlayer dielectric layer 104 is enlarged when filling, and the hole filling depth-to-width ratio is effectively reduced. That is, the scheme of the present application can achieve the gate structure without damage during the contact hole etching process through the compensation etch stop layer on the top of the gate structure on the basis of thinning the contact hole etch stop layer, and at the same time, the hole filling opening is enlarged and the depth-to-width ratio is reduced, thereby filling a seamless and hole-free structure, thereby improving the overall performance of the semiconductor device.

[0037] Figure 3 A schematic flow chart of a method 300 for forming a contact hole of a semiconductor device in some embodiments of the present application is shown. It should be noted that: Figure 3 It can be understood that Figure 2 An exemplary process for preparing a contact hole in a semiconductor device, Figure 2 The relevant instructions in also apply to the following.

[0038] like Figure 3 As shown, at step S301, a substrate having a first contact hole etch stop layer formed thereon may be provided. A plurality of gate structures are also formed on the substrate, and the first contact hole etch stop layer is located above the gate structure and other areas of the substrate. The gate structure may include gate polysilicon and a contact layer located on top of the gate polysilicon. In addition, as described above, sidewalls, gate oxide layers, drains, sources, etc. may also be formed on the substrate. It should be noted that the gate polysilicon, contact layers, sidewalls, gate oxide layers, drains, sources, etc. in this embodiment may be formed using conventional or known processes, and the relevant details are not repeated here. In addition, in some embodiments, the first contact hole etch stop layer may be generated using a chemical vapor deposition (CVD) process, and its film thickness may be set and adjusted according to the performance requirements of the semiconductor device being prepared.

[0039] At step S302, an original sacrificial layer is formed on the first contact hole etch stop layer, and a part of the original sacrificial layer is modified so that the original sacrificial layer located above the top of each gate structure is modified into a modified sacrificial layer. In some embodiments, the original sacrificial layer can be formed by a chemical vapor deposition process, and the above-mentioned modification process can be performed by an ion implantation process.

[0040] In practical applications, if the first contact hole etch stop layer is modified directly, on the one hand, it is impossible to accurately control only part of the contact hole etch stop layer to be modified, and on the other hand, during the ion implantation process, ions may penetrate the first contact hole etch stop layer to the gate structure, thereby damaging the gate structure. Therefore, in this embodiment, the original sacrificial layer is formed on the first contact hole etch stop layer to perform the modification process using the original sacrificial layer, which can effectively avoid the above problems.

[0041] At step S303, the modified sacrificial layer and the first contact hole etch stop layer are etched so that the first contact hole etch stop layer between the modified sacrificial layer and the top of each gate structure is retained and a compensation etch stop layer is formed. Wherein, the critical dimension of the compensation etch stop layer is smaller than the critical dimension of the gate structure. In some embodiments, the modified sacrificial layer and the first contact hole etch stop layer can be etched in combination with a wet etching process, etc., to remove the modified sacrificial layer and the first contact hole etch layer. The area not covered by the modified sacrificial layer is removed, so that the first contact hole etch stop layer between the modified sacrificial layer and the top of each gate structure is retained and a compensation etch stop layer is formed. That is, the area covered by the modified sacrificial layer in the first contact hole etch layer is retained and exists as a compensation etch stop layer. Wherein, the thickness of the compensation etch stop layer is the film thickness of the first contact hole etch stop layer in an ideal state. Of course, in the actual preparation process, the first contact hole etch stop layer may be slightly worn, and at this time, the film thickness of the compensation etch stop layer is close to, approximately equal to, or similar to the film thickness of the first contact hole etch stop layer.

[0042] At step S304, a target structure including a second contact hole etch stop layer and an interlayer dielectric layer is formed on the substrate. The thickness of the second contact hole etch stop layer is less than the thickness of the first contact hole etch stop layer. The aforementioned compensating etch stop layer exists at the top position of each gate structure, and the thickness of the compensating etch stop layer is equal to or approximate to the thickness of the first contact hole etch stop layer. At this time, a second contact hole etch stop layer with a thickness less than that of the first contact hole etch stop layer can be re-formed on the substrate to meet the process requirements. After the preparation of the second contact hole etch stop layer is completed, an interlayer dielectric layer can be formed on the second contact hole etch stop layer by conventional or known processes, thereby obtaining a target structure.

[0043] At step S305, a contact hole is formed on the target structure. In this embodiment, a contact hole can be formed on the target structure by using a conventional or known process (such as a photolithography process, a contact hole etching process, a chemical vapor deposition process, a chemical mechanical planarization process, and a physical vapor deposition process). Thus, the preparation of the contact hole is completed.

[0044] The unexpected beneficial technical effect of the present application is that the modified sacrificial layer can be used to protect the first contact hole etch stop layer covered by it, so that the area covered by the modified sacrificial layer in the first contact hole etch layer can be retained and used as a compensating etch stop layer. At the same time, a second contact hole etch stop layer with a film thickness less than the first contact hole etch stop layer is formed on the substrate. In addition, the critical dimension of the compensating etch stop layer is less than the critical dimension of the gate structure, which can expand the hole filling opening when the oxide layer in the interlayer dielectric layer is filled, and reduce the hole filling aspect ratio. Therefore, on the basis of thinning the contact hole etch stop layer, the gate structure can be made damage-free during the contact hole etching process through the compensating etch stop layer on the top of the gate structure, and at the same time, the hole filling opening is enlarged and the aspect ratio is reduced, so that a seamless and hole structure is filled, thereby improving the overall performance of the semiconductor device.

[0045] Figure 4 FIG. 4 is a schematic flow chart of a method 400 for forming a contact hole of a semiconductor device according to another embodiment of the present application. It should be noted that: Figure 4 It can be understood that Figure 3 Therefore, the above combined with Figure 3 The relevant description also applies to the following.

[0046] like Figure 4 As shown, at step S401, a substrate having a first contact hole etch stop layer formed thereon may be provided. As described above, a plurality of gate structures, source electrodes, drain electrodes, sidewall structures, gate oxide layers, shallow trench isolation regions, etc. may be grown on the substrate using conventional or known processes. The gate structure includes gate polysilicon and a contact layer (e.g., a NiSi layer) located on top of the gate polysilicon. In some embodiments, a first contact hole etch stop layer is grown on the substrate using a CVD process, and the film thickness of the first contact hole etch stop layer may be specifically set and adjusted according to the processing and performance requirements of the semiconductor device.

[0047] refer to Figure 5a , the semiconductor device 500 includes a substrate 501. A gate polysilicon 502, a contact layer 503, a sidewall structure 504, a gate oxide layer 505, and a first contact hole etch stop layer 506 are grown on the substrate 501. In some embodiments, the first contact hole etch stop layer 506 may be made of a silicon nitride (SiN) layer, or may be made of other materials with properties close to or similar to SiN.

[0048] return Figure 4At step S402, an original sacrificial layer having a film thickness not less than that of the first contact hole etch stop layer may be formed on the aforementioned first contact hole etch stop layer. In some embodiments, a chemical vapor deposition process may be used to generate the original sacrificial layer. For example, when the first contact hole etch stop layer adopts a SiN layer, the original sacrificial layer may adopt a silicon oxide layer. At this time, a tetraethoxysilane (TEOS) process or a high aspect ratio (HARP) process may be used to prepare the original sacrificial layer. Among them, TEOS is a common silicon source in a chemical vapor deposition process and can be used to generate a SiO2 film. Silicon dioxide accumulates as a deposit on the surface of the first contact hole etch stop layer to form a silicon dioxide film (i.e., the original sacrificial layer). The HARP process is specifically a non-plasma CVD thermal oxidation process, which forms a silicon oxide film (i.e., the original sacrificial layer) on the surface of the first contact hole etch stop layer by inducing deposition strain.

[0049] refer to Figure 5b In the semiconductor device 500, a first contact hole etch stop layer 506 is formed on the substrate 501, and an original sacrificial layer 507 can be formed on the first contact hole etch stop layer 506. The film thickness of the original sacrificial layer 507 is not less than that of the first contact hole etch stop layer 506. In some embodiments, the first contact hole etch stop layer 506 can be a SiN layer with a thickness of 500A to 600A, and the original sacrificial layer 507 can be a silicon oxide layer with a film thickness greater than or equal to that of the SiN layer. It should be noted that the detailed description of the film thickness of the first contact hole etch stop layer 506 and the original sacrificial layer 507 is only an exemplary description, and the solution of the present application is not limited thereto.

[0050] After the original sacrificial layer is formed, a partial modification process may be performed on the original sacrificial layer so that the original sacrificial layer located above the top of each gate structure is modified into a modified sacrificial layer.

[0051] Specific return Figure 4, at step S403, the original sacrificial layer may be coated with photoresist, and the photoresist may be back-etched to expose the top of the original sacrificial layer. The height of the photoresist is not less than the height of the gate structure. In practical applications, photoresist (PR for short) may be applied first so that the photoresist completely covers the original sacrificial layer. Then, the photoresist is etched to expose the top of the original sacrificial layer from the photoresist. Since the exposed original sacrificial layer needs to be modified and etched later, the exposed original sacrificial layer here needs to be precisely controlled. Excessive exposure will affect the subsequent etching speed and the film thickness of the modified sacrificial layer, and too little exposure may affect the film thickness of the subsequent compensation etch stop layer, that is, too much or too little exposure cannot meet the subsequent process requirements. Therefore, in this embodiment, the height of the photoresist can be controlled to be not less than the height of the gate structure after the photoresist is back-etched, that is, slightly higher than or equal to the height of the gate structure.

[0052] refer to Figure 5c A first contact hole etching stop layer 506 and an original sacrificial layer 507 are formed on a substrate 501 of a semiconductor device 500, a photoresist 508 is applied to the original sacrificial layer 507, and the photoresist 508 is etched back to expose the top of the original sacrificial layer. In this embodiment, the photoresist can be applied and etched back using conventional or known processes, which will not be described in detail here.

[0053] return Figure 4 , at step S404, the portion of the original sacrificial layer not covered by the photoresist can be modified. In some embodiments, modified ions can be injected into the portion of the original sacrificial layer not covered by the photoresist, and the photoresist and the portion or region covered by the photoresist in the original sacrificial layer can be removed. Among them, the wet etching rate of the modified sacrificial layer is less than that of the unmodified original sacrificial layer. So far, the preparation of the modified sacrificial layer is completed. In this embodiment, only the portion or region of the original sacrificial layer not covered by the photoresist is injected with modified ions, and the other portions are protected by the photoresist and will not be injected with modified ions. In addition, ion implantation is performed on the original sacrificial layer, and the first contact hole etch stop layer will not be penetrated by the modified ions, that is, the first contact hole etch stop layer can better block ion implantation, thereby effectively avoiding damage to the gate structure.

[0054] As an example, the modified ions used need to be adjusted according to the specific material properties of the original sacrificial layer and the first contact hole etch stop. Figure 5d , the first contact hole etching stop layer 506 (see Figure 5c ) using a silicon nitride layer, the original sacrificial layer 507 (see Figure 5c) A silicon oxide layer is used, then the modified ions can be N ions. At this time, nitrogen ions are injected into the portion of the silicon oxide layer not covered by the photoresist, and the portion injected with nitrogen ions can be called a modified sacrificial layer 509.

[0055] After the nitrogen ion implantation is completed, the photoresist can be removed, and the portion of the original sacrificial layer covered by the photoresist can be removed by a wet etching process to obtain a modified sacrificial layer. Figure 5e , all the remaining photoresist on the substrate 501 can be cleaned and removed by conventional or known processes such as dry or wet etching processes. The unmodified original sacrificial layer (that is, the original sacrificial layer into which the modified ions are not injected) is etched and removed by, for example, a DHF wet etching process. In this process, the wet etching rate of the modified original sacrificial layer is about 1 / 4 to 1 / 2 of the unmodified original sacrificial layer (the specific etching selectivity depends on the amount of modified ions doped, and the wet etching rate of the modified sacrificial layer is usually less than that of the unmodified original sacrificial layer), so the unmodified original sacrificial layer will be completely removed, while the modified original sacrificial layer will be retained. That is, the modified sacrificial layer has a lower wet etching rate, and the modified sacrificial layer is still retained after the unmodified original sacrificial layer is completely removed. In the actual process, the modified original sacrificial layer (that is, the modified sacrificial layer 509) may be consumed in a small amount.

[0056] After forming the modified sacrificial layer, the modified sacrificial layer and the first contact hole etch stop layer can be etched so that the first contact hole etch stop layer between the modified sacrificial layer and the top of each gate structure is retained and a compensation etch stop layer is formed, wherein the critical dimension of the compensation etch stop layer is smaller than the critical dimension of the gate structure. Figure 4 In step S405, a diluted hydrofluoric acid wet etching process can be used to push back the sidewalls of the modified sacrificial layer so that the critical dimension of the modified sacrificial layer after the push back is not larger than the critical dimension of the gate structure and larger than the critical dimension of the contact hole, and the film thickness of the modified sacrificial layer after the push back is not larger than the film thickness of the first contact hole etching stop layer.

[0057] refer to Figure 5f, the DHF wet etching process can be continued to be used to etch and push back the sidewalls of the modified sacrificial layer 509. In the actual process, the sidewalls of the modified sacrificial layer 509 are etched in multiple directions, while the top of the modified sacrificial layer 509 is only etched in the vertical direction, so the etching rate of the sidewalls is faster than that of the top, so as to form the modified sacrificial layer 509 after being pushed back. At this time, the critical dimension (abbreviated as CD) of the modified sacrificial layer 509 after being pushed back should be less than or equal to the critical dimension of the gate structure to ensure that the critical dimension of the final compensation etching stop layer is less than the critical dimension of the gate structure. At the same time, the critical dimension of the modified sacrificial layer 509 after being pushed back needs to be greater than the critical dimension of the contact hole. In addition, the film thickness of the modified sacrificial layer 509 after being pushed back should be less than or equal to the film thickness of the first contact hole etching stop layer, preferably close to or approximate to the film thickness of the first contact hole etching stop layer, so as to ensure the final remaining amount of the first contact hole etching stop layer at the top of the gate structure. Of course, if the film thickness and critical dimensions of the modified sacrificial layer 509 obtained in step 404 already meet the above requirements, there is no need to perform step S405.

[0058] Next, at step S406 , the pushed-back modified sacrificial layer and the first contact hole etch stop layer may be etched.

[0059] refer to Figure 5g For example, a hot phosphoric acid etching process can be used to Figure 5f The modified sacrificial layer 509 and the first contact hole etch stop layer after being pushed back are etched, so that the first contact hole etch stop layer between the modified sacrificial layer 509 and the top of each gate structure (specifically, the top of the contact layer 503 in the gate structure) is retained, and a compensation etch stop layer 510 is formed. For another example, a dry etching process can also be used to thin the portions of the modified sacrificial layer 509 and the first contact hole etch stop layer that are not covered by the modified sacrificial layer after being pushed back (such as the side and bottom areas), and a hot phosphoric acid etching process is used to etch the thinned modified sacrificial layer and the first contact hole etch stop layer, so that the first contact hole etch stop layer 506 between the modified sacrificial layer 509 and the top of each gate structure (specifically, the top of the contact layer 503 in the gate structure) is retained, and a compensation etch stop layer 510 is formed. Wherein, hot phosphoric acid has a similar wet etching rate to the modified sacrificial layer and the first contact hole etch stop layer.

[0060] After forming the compensation etch stop layer, return Figure 4In step S407, a second contact hole etch stop layer is formed on the substrate by chemical vapor deposition technology. The thickness of the contact hole etch stop layer corresponding to the area covered by the compensation etch stop layer on the top of each gate structure is the sum of the thickness of the compensation etch stop layer and the second contact hole etch stop layer, and the thickness of the contact hole etch stop layer corresponding to other areas on the substrate is the thickness of the second contact hole etch stop layer.

[0061] refer to Figure 5h Since a compensating etch stop layer of sufficient thickness already exists on the top of the gate structure to eliminate the load of the subsequent contact hole etching height, it is only necessary to form a second contact hole etch stop layer 511 with a film thickness less than the first contact hole etch stop layer on the substrate 501. At the same time, since a compensating etch stop layer exists in some areas of the top of the gate structure, some areas are not covered by the compensating etch stop layer. After the thinner second contact hole etch stop layer 511 is re-formed, a "small step" 512 will be formed at the top edge of the gate structure. Due to the existence of the "small step" 512 and the thinning of the contact hole etch stop layer between the gate structures, the hole filling opening when the oxide layer in the subsequent interlayer dielectric layer is filled is enlarged, which effectively reduces the hole filling aspect ratio and improves the subsequent hole filling aspect ratio process window.

[0062] return Figure 4 In step S408, a high aspect ratio process may be used to form an interlayer dielectric layer on the second contact hole etch stop layer.

[0063] refer to Figure 5i , an oxide layer of an interlayer dielectric layer (abbreviated as ILD) 513 can be formed on the second contact hole etch stop layer by using a HARP process, and then the oxide layer is processed by a CMP process. In the process of forming the oxide layer of the ILD by using the HARP process, due to the thinning of the contact hole etch stop layer between the gate structures, the hole filling width of the HARP process is increased, and the top opening becomes larger, thereby reducing the depth-to-width ratio of the filled hole, which is conducive to filling the ILD oxide layer without gaps. At this point, a target structure including a second contact hole etch stop layer and an interlayer dielectric layer is formed.

[0064] After the target structure is formed, at step S409 , a contact hole may be formed on the target structure.

[0065] refer to Figure 5j , the contact hole 514 can be processed by using a known contact hole forming process. Figure 5jIn the embodiment, a target structure is formed on a substrate 501 of a semiconductor device 500, and the target structure includes a second contact hole etch stop layer 511 and an interlayer dielectric layer 513. A contact hole etching process can be used to etch the target structure. In this process, the film thickness of the contact hole etch stop layer 515 corresponding to the area covered by the compensation etch stop layer on the top of the gate structure is the compensation etch stop layer (i.e. Figure 5g The thickness of the contact hole etch stop layer corresponding to other areas on the substrate 501 is the thickness of the second contact hole etch stop layer 511, so that the contact hole etch stop layer 515 has sufficient thickness to offset the etching height load, ensuring that the gate structure is not damaged during the contact hole etching process.

[0066] The unexpected beneficial technical effect of the present application is that: on the basis of thinning the contact hole etch stop layer, the gate structure can be made damage-free during the contact hole etching process by means of the compensation etch stop layer on the top of the gate structure. In addition, the thickness of the contact hole etch stop layer formed for the second time (i.e., the second contact hole etch stop layer) is very thin (e.g., about 50-100 Å), and the top compensation etch stop layer of the hole filling is pushed back after completion, thereby expanding the opening and reducing the hole filling aspect ratio, which is beneficial for ILD HARP to fill a seamless and hole structure.

[0067] It should be noted that although the operations of the method of the present application are described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. On the contrary, the steps depicted in the flow chart can be performed in a different order. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be decomposed into multiple steps.

[0068] Although multiple embodiments of the present application have been shown and described herein, it is obvious to those skilled in the art that such embodiments are provided only by way of example. Those skilled in the art can think of many changes, modifications and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The attached claims are intended to limit the scope of protection of the present application, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for forming a contact hole of a semiconductor device, characterized in that: include: Providing a substrate having a first contact hole etch stop layer formed thereon, wherein a plurality of gate structures are also formed on the substrate, and the first contact hole etch stop layer is located above the gate structures; forming an original sacrificial layer on the first contact hole etching stop layer, and performing a partial modification process on the original sacrificial layer so that the original sacrificial layer located above the top of each gate structure is modified into a modified sacrificial layer; Etching the modified sacrificial layer and the first contact hole etch stop layer so that the first contact hole etch stop layer between the modified sacrificial layer and the top of each gate structure is retained and a compensation etch stop layer is formed, wherein the critical dimension of the compensation etch stop layer is smaller than the critical dimension of the gate structure; forming a target structure including a second contact hole etch stop layer and an interlayer dielectric layer on the substrate, wherein the film thickness of the second contact hole etch stop layer is smaller than the film thickness of the first contact hole etch stop layer; as well as A contact hole is formed on the target structure.

2. The forming method according to claim 1, characterized in that: Forming an original sacrificial layer on the first contact hole etch stop layer comprises: The original sacrificial layer having a film thickness not less than that of the first contact hole etch stop layer is formed on the first contact hole etch stop layer by using a chemical vapor deposition process.

3. The forming method according to claim 1, characterized in that: The partial modification of the original sacrificial layer comprises: Applying photoresist to the original sacrificial layer; Performing an etching back process on the photoresist to expose the top of the original sacrificial layer, wherein the height of the photoresist is not less than the height of the gate structure; and The portion of the original sacrificial layer not covered by the photoresist is modified.

4. The forming method according to claim 3, characterized in that: The modification process of the portion of the original sacrificial layer not covered by the photoresist comprises: Implanting modified ions into the portion of the original sacrificial layer not covered by the photoresist; and The photoresist and the portion of the original sacrificial layer covered by the photoresist are removed, wherein the wet etching rate of the modified sacrificial layer is lower than that of the unmodified original sacrificial layer.

5. The forming method according to claim 4, characterized in that: The first contact hole etching stop layer includes a silicon nitride layer, and the original sacrificial layer includes a silicon oxide layer, and modifying the portion of the original sacrificial layer not covered by the photoresist includes: Implanting nitrogen ions into a portion of the silicon oxide layer not covered by the photoresist; removing the photoresist; and A wet etching process is used to remove the portion of the original sacrificial layer covered by the photoresist.

6. The forming method according to claim 1, characterized in that: Etching the modified sacrificial layer and the first contact hole etch stop layer comprises: Pushing back the sidewall of the modified sacrificial layer by a diluted hydrofluoric acid wet etching process, so that the critical dimension of the modified sacrificial layer after the push-back is not larger than the critical dimension of the gate structure and larger than the critical dimension of the contact hole, and the film thickness of the modified sacrificial layer after the push-back is not larger than the film thickness of the first contact hole etching stop layer; and The pushed-back modified sacrificial layer and the first contact hole etch stop layer are etched.

7. The forming method according to claim 6, characterized in that: Etching the pushed-back modified sacrificial layer and the first contact hole etch stop layer comprises: Etching the pushed-back modified sacrificial layer and the first contact hole etching stop layer using a hot phosphoric acid etching process; or Using a dry etching process to perform a thinning process on the portion of the pushed-back modified sacrificial layer and the first contact hole etch stop layer that is not covered by the pushed-back modified sacrificial layer; and The thinned modified sacrificial layer and the first contact hole etching stop layer are etched using a hot phosphoric acid etching process.

8. The forming method according to any one of claims 1 to 7, characterized in that: Forming a target structure including a second contact hole etch stop layer and an interlayer dielectric layer on the substrate comprises: forming the second contact hole etch stop layer on the substrate by chemical vapor deposition technology, wherein the thickness of the contact hole etch stop layer corresponding to the area on the top of each gate structure covered by the compensation etch stop layer is the sum of the thicknesses of the compensation etch stop layer and the second contact hole etch stop layer, and the thickness of the contact hole etch stop layer corresponding to other areas on the substrate is the thickness of the second contact hole etch stop layer; and The interlayer dielectric layer is formed on the second contact hole etch stop layer by using a high aspect ratio process.

9. A semiconductor device structure, characterized in that: include: substrate; a target structure and a plurality of gate structures formed on the substrate; as well as A contact hole is formed on the target structure, wherein the contact hole is made by the forming method according to any one of claims 1 to 8.

10. The semiconductor device structure according to claim 9, characterized in that: The compensating etch stop layer is formed by a first contact hole etch stop layer located between the modified sacrificial layer and the top of each gate structure, and the film thickness of the contact hole etch stop layer corresponding to the area covered by the compensating etch stop layer on the top of each gate structure is greater than the film thickness of the contact hole etch stop layer corresponding to other areas on the substrate, and the critical dimension of the compensating etch stop layer is smaller than the critical dimension of the gate structure.

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