Semiconductor structure and its forming method and operating method

Abstract

The present invention discloses a semiconductor structure and a method for forming and operating the structure. The semiconductor structure comprises: multiple active structures, each of which includes an active region, a gate structure located above the active region, and a conductive connection structure located above and electrically connected to the active region; the active regions in the multiple active structures have the same width along a first direction, and the active regions in any two active structures have different lengths along a second direction, where the first direction intersects the second direction. The present invention improves the accuracy and reliability of active region resistance testing, providing a reference for improving semiconductor device performance.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a forming method and an operating method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to a capacitor. The word line voltage on the word line can control the on and off of the transistor, thereby allowing data stored in the capacitor to be read or written through the bit line.

[0003] In semiconductor structures such as DRAM, it is usually necessary to test the resistance value of the active region of the transistor in order to improve the performance of the semiconductor structure such as DRAM. However, for transistors with a MOS structure, the gate layer blocks the dopant ion injection into the source and drain regions, so that the dopant ions are only injected into the source and drain regions. However, the presence of a concentration gradient causes the dopant ions to diffuse below the gate layer, thereby causing a change in the resistance value of the active region. Currently, when testing the resistance of the active region, the effect of the gate layer setting on the resistance value of the active region is not taken into account, resulting in low accuracy and reliability of the test results, which affects the improvement of the performance of the semiconductor structure.

[0004] Therefore, how to improve the accuracy and reliability of active area resistance detection, so as to provide a reference for improving semiconductor structure performance, is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a formation method and an operation method thereof, which are used to improve the accuracy and reliability of active area resistance testing in a semiconductor structure, thereby providing a reference for improving and enhancing the performance of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure comprising:

[0007] a plurality of active structures, each of the active structures comprising an active region, a gate structure located above the active region, and a conductive connection structure located above the active region and electrically connected to the active region;

[0008] The active regions in the plurality of active structures have the same width along a first direction, and the active regions in any two active structures have different lengths along a second direction, and the first direction intersects the second direction.

[0009] In some embodiments, the gate structure in the active structure includes a main body, and a plurality of branches connected to the main body and arranged at intervals along the first direction;

[0010] The spacing distance between two adjacent branches in any two active structures along the first direction is equal.

[0011] In some embodiments, the conductive connection structure includes:

[0012] a first conductive connection structure, located above the active area and electrically connected to the active area;

[0013] a second conductive connection structure located above the active area and electrically connected to the active area; the first conductive connection structure and the second conductive connection structure are spaced apart and distributed on opposite sides of the active area along the second direction, and both the first conductive connection structure and the second conductive connection structure partially overlap with the active area.

[0014] In some embodiments, the first conductive connection structure includes a first main portion extending along the first direction, and a plurality of first extension portions connected to the first main portion and extending along the second direction, wherein the plurality of first extension portions are arranged at intervals along the first direction, and the first extension portions are at least partially located above the active area and electrically connected to the active area;

[0015] The second conductive connection structure includes a second main body extending along the first direction, and a plurality of second extension portions connected to the second main body and extending along the second direction, and the plurality of second extension portions are arranged at intervals along the first direction, and the second extension portions are at least partially located above the active area and electrically connected to the active area.

[0016] In some embodiments, the trunk portion is distributed outside the active area along the second direction, and the plurality of branches are located above the active area;

[0017] The first main body portion is distributed outside the main body portion along the second direction, and the plurality of first extension portions are distributed on opposite sides of the main body portion along the first direction;

[0018] The second main body portion and the first main body portion are distributed on two opposite outer sides of the active region along the second direction, and the second extension portion and the first extension portion are distributed opposite to each other along the second direction.

[0019] In some embodiments, the second extension portion and the first extension portion in any two of the active structures are spaced apart by different distances along the second direction.

[0020] In some embodiments, the conductive connection structure includes:

[0021] a third conductive connection structure, located above the active area and electrically connected to the active area;

[0022] a fourth conductive connection structure located above the active area and electrically connected to the active area, the third conductive connection structure and the fourth conductive connection structure are distributed on opposite sides of the active area along the second direction, and the orthographic projection of the third conductive connection structure on the top surface of the active area and the orthographic projection of the fourth conductive connection structure on the top surface of the active area are both located inside the active area.

[0023] In some embodiments, the trunk portion is distributed outside the active area along the second direction, and the plurality of branches are located above the active area;

[0024] The projection of the third conductive connection structure on the active area is located in the area between the projections of the two branches on the active area;

[0025] The projection of the fourth conductive connection structure on the active region is located in a region between projections of the two branches on the active region.

[0026] In some embodiments, the active structure further comprises:

[0027] An external gate structure is located outside the active area along the first direction, and the external gate structure is arranged in the same layer as the gate structure.

[0028] According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure, comprising the following steps:

[0029] providing a substrate;

[0030] forming a plurality of active regions arranged at intervals in the substrate, wherein the widths of the plurality of active regions along a first direction are the same, and the lengths of any two of the active regions along a second direction are different, and the first direction intersects the second direction;

[0031] A gate structure and a conductive connection structure electrically connected to the active region are formed above each active region to form a plurality of active structures, each of the active structures including the active region and the gate structure and the conductive connection structure corresponding to the active region.

[0032] According to some further embodiments, the present disclosure further provides a method for operating a semiconductor structure, comprising the following steps:

[0033] Providing a semiconductor structure as described above;

[0034] selecting one of the plurality of active structures as a first active structure, and selecting another of the plurality of active structures as a second active structure;

[0035] transmitting a first test signal to the conductive connection structure in the first active structure, and obtaining a resistance of the active area in the first active structure as a first resistance;

[0036] transmitting the first test signal to the conductive connection structure in the second active structure, and obtaining the resistance of the active area in the second active structure as a second resistance;

[0037] A unit resistance of the active area is obtained according to the first resistance and the second resistance.

[0038] In some embodiments, while transmitting the first test signal to the conductive connection structure in the first active structure, the following steps are also included: applying a 0V voltage to the gate structure in the first active structure;

[0039] While transmitting the first test signal to the conductive connection structure in the second active structure, the method further includes the following step: applying a 0V voltage to the gate structure in the second active structure.

[0040] In some embodiments, the conductive connection structure includes a first conductive connection structure and a second conductive connection structure, both located above the active area and spaced apart along the second direction, the first conductive connection structure and the second conductive connection structure are both electrically connected to the active area, and the first conductive connection structure and the second conductive connection structure partially overlap with the active area. The specific steps of transmitting a first test signal to the conductive connection structure in the first active structure and obtaining the resistance of the active area in the first active structure as the first resistance include:

[0041] transmitting a first voltage signal to the first conductive connection structure and simultaneously transmitting a second voltage signal to the second conductive connection structure, wherein the first voltage signal is higher than the second voltage signal;

[0042] obtaining a current in the active area between the first conductive connection structure and the second conductive connection structure as a first current;

[0043] The first resistance is calculated according to a difference between the first voltage signal and the second voltage signal, and the first current.

[0044] In some embodiments, the specific steps of obtaining the unit resistance of the active area according to the first resistor and the second resistor include:

[0045] acquiring a distance between the first conductive connection structure and the second conductive connection structure in the first active structure as a first distance;

[0046] acquiring a distance between the first conductive connection structure and the second conductive connection structure in the second active structure as a second distance;

[0047] A unit resistance of the active area is calculated according to the first resistance, the second resistance, the first distance, and the second distance.

[0048] In some embodiments, the specific steps of calculating the unit resistance of the active area according to the first resistance, the second resistance, the first distance, and the second distance include:

[0049] The unit resistance R of the active area is calculated using the following formula: s :

[0050] R s =(R2–R1) / [2(L2-L1)]

[0051] Here, R2 represents the second resistor, R1 represents the first resistor, L2 represents the second distance, and L1 represents the first distance.

[0052] Some embodiments of the present disclosure provide semiconductor structures, formation methods, and operating methods thereof. By forming an active region, a gate structure located above the active region, and a conductive connection structure located above the active region and electrically connected to the active region within the active structure, the influence of the gate structure is taken into account during the calculation of the active region resistance, thereby improving the accuracy and reliability of the active region resistance test and providing a reference for improving semiconductor device performance. Furthermore, in some embodiments of the present disclosure, the active regions of any two of the multiple active structures provided have unequal lengths, thereby reducing or even eliminating the influence of the conductive connection structure on the active region resistance test by measuring the multiple active structures, further improving the accuracy and reliability of the active region resistance test. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Attachment Figure 1 is a schematic top view of an active structure in a specific embodiment of the present disclosure;

[0054] Attachment Figure 2 is a top view schematic diagram of another active structure in a specific embodiment of the present disclosure;

[0055] Attachment Figure 3 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

[0056] Attachment Figure 4 is a flow chart of an operating method of a semiconductor structure in a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] The specific implementation methods of the semiconductor structure and its formation method and operation method provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0058] This embodiment provides a semiconductor structure. Figure 1 is a top view of an active structure in a specific embodiment of the present disclosure, Figure 2 FIG. 1 is a top view of another active structure in a specific embodiment of the present disclosure. Figure 1 and Figure 2 As shown, the semiconductor structure includes:

[0059] A plurality of active structures 20 , each of the active structures 20 including an active region 10 , a gate structure 11 located above the active region 10 , and a conductive connection structure 21 located above the active region 10 and electrically connected to the active region 10 ;

[0060] The active regions 10 in the plurality of active structures 20 have the same width along the first direction D1 , and the active regions 10 in any two active structures 20 have different lengths along the second direction D2 , where the first direction D1 intersects the second direction D2 .

[0061] Specifically, the active structure 20 is used to simulate the structure of a semiconductor device to be tested. By testing the resistance of the active region 10 in the active structure 20, the resistance of the active region in the semiconductor device is indirectly obtained, thereby facilitating subsequent improvements to the performance, structure, or manufacturing process of the semiconductor device. The semiconductor device may be, but is not limited to, a DRAM.

[0062] The active structure 20 may include the active area 10, and the active area 10 includes a channel area, and a source area and a drain area distributed on opposite sides of the channel area along the first direction D1. The source area and the drain area both include dopant ions (for example, including N-type dopant ions), and the dopant ions in the source area and the drain area are formed after the gate structure 11 is formed. In one example, the gate structure 11 is located above the channel area in the active area 10, and the gate structure 11 may include a gate dielectric layer covering the top surface of the active area 10, and a gate conductive layer covering the top surface of the gate dielectric layer. The conductive connection structure 21 may be located above the source area and / or the drain area. The multiple mentioned in this specific embodiment refers to more than two. Figure 1 The length of the active area 10 along the second direction D2 shown in FIG is Figure 2 The lengths of the active regions 10 along the second direction D2 are different, for example Figure 1 The length of the active area 10 along the second direction D2 is less than Figure 2 The length of the active region 10 along the second direction D2 is shown. In one example, the first direction D1 and the second direction D2 are parallel to the top surface of the active region 10 .

[0063] During the process of testing the resistance of the active area 10 using the active structure 20, a test electrical signal is transmitted to the active area 10 via the conductive connection structure 21, and a feedback signal (e.g., a physical quantity such as current) of the active area 10 under the test electrical signal is measured to obtain the resistance of the active area 10. Because the gate structure 11 is provided in the active structure 20, the resistance of the active area 10 obtained through testing takes into account the influence of the gate structure 11. This makes the resistance of the active area 10 obtained through testing closer to the actual resistance of the active area 10, improving the accuracy and reliability of the resistance test of the active area 10 and providing a reference for improving the performance of semiconductor devices. At the same time, this specific embodiment includes a plurality of active structures 20, and the widths of the active areas 10 in the plurality of active structures 20 along the first direction D1 are the same, and the lengths of the active areas 10 in any two active structures 20 along the second direction D2 are different. By testing the resistance of the active areas 10 in the plurality of active structures 20, on the one hand, the influence of the conductive connection structure itself on the resistance test of the active area 10 can be eliminated, thereby further improving the accuracy and reliability of the resistance test of the active area 10; on the other hand, the resistance of the active area 10 per unit size (for example, per unit length) can also be obtained, so that the resistance of the active areas 10 of different sizes can be calculated more quickly and conveniently, thereby further simplifying the operation of obtaining the resistance of the active area in semiconductor devices such as DRAM.

[0064] In some embodiments, the active structure 20 further includes:

[0065] The external gate structure 16 is located outside the active area 10 along the first direction D1 . The external gate structure 16 and the gate structure 11 are disposed in the same layer.

[0066] Specifically, since an actual semiconductor device includes multiple active areas arranged in an array, in order to make the active structure 20 closer to an actual semiconductor device, the active structure 20 also includes an external gate structure 16 located along the first direction D1 of the active area 10, thereby better simulating a real semiconductor device and further improving the reliability of the resistance test results of the active area 10. In one example, the external gate structure 16 is provided on both opposite outer sides of the active area 10 along the first direction D1. The external gate structure 16 is provided on the same layer as the gate structure 11, and the length of the external gate structure 16 along the second direction D2 is also equal to the length of the gate structure 11 along the second direction D2, thereby improving the accuracy of the resistance test results of the active area 10 while simplifying the manufacturing process of the semiconductor structure.

[0067] In some embodiments, the gate structure 11 in the active structure 20 includes a main body 111 and a plurality of branches 112 connected to the main body 111 and arranged at intervals along the first direction D1;

[0068] The spacing distance between two adjacent branches 112 in any two active structures along the first direction D1 is equal.

[0069] Specifically, if Figure 1 and Figure 2 As shown, the gate structure 11 is comb-shaped and includes a main portion 111 extending along the first direction D1, and branches 112 connected to the main portion 111 and extending along the second direction D2. The branches 112 are arranged at intervals along the first direction D1. Accordingly, the active area 10 includes a plurality of channel regions arranged at intervals along the first direction D1, and a source region and a drain region located on opposite sides of each channel region along the first direction D1. The branches 112 are positioned one by one above the plurality of channel regions. This makes the specific structure of the active area 10 and the gate structure 11 in the active structure 20 more similar to the structure of the semiconductor device to be tested, thereby further improving the accuracy and reliability of the resistance test of the active area 10. The spacing between two adjacent branches 112 in any two active structures 20 along the first direction D1 is equal, thereby avoiding the problem of inaccurate active area resistance measurement caused by different spacing between branches, thereby further improving the accuracy of active area resistance testing.

[0070] In order to reduce the influence of process deviation on the resistance test result of the active area 10 during the process of forming the plurality of active structures 20, in some embodiments, the conductive connection structure 21 includes:

[0071] a first conductive connection structure 12 , located above the active area 10 and electrically connected to the active area 10 ;

[0072] The second conductive connection structure 13 is located above the active area 10 and is electrically connected to the active area 10. The first conductive connection structure 12 and the second conductive connection structure 13 are spaced apart and distributed on opposite sides of the active area 10 along the second direction D2, and the first conductive connection structure 12 and the second conductive connection structure 13 both partially overlap with the active area 10.

[0073] In some embodiments, the first conductive connection structure 12 includes a first main portion 121 extending along the first direction D1, and a plurality of first extension portions 122 connected to the first main portion 121 and extending along the second direction D2. The plurality of first extension portions 122 are arranged at intervals along the first direction D1. The first extension portions 122 are at least partially located above the active area 10 and electrically connected to the active area 10.

[0074] The second conductive connection structure 13 includes a second main body 131 extending along the first direction D1, and a plurality of second extension portions 132 connected to the second main body 131 and extending along the second direction D2, and the plurality of second extension portions 132 are arranged at intervals along the first direction D1, and the second extension portions 132 are at least partially located above the active area 10 and electrically connected to the active area 10.

[0075] In some embodiments, the trunk portion 111 is distributed outside the active area 10 along the second direction D2, and the plurality of branches 112 are located above the active area 10;

[0076] The first main portion 121 is distributed outside the main body 111 along the second direction D2, and the plurality of first extension portions 122 are distributed on opposite sides of the main body 111 along the first direction D1;

[0077] The second main portion 131 and the first main portion 121 are distributed on two opposite outer sides of the active area 10 along the second direction D2 , and the second extension portion 132 and the first extension portion 122 are distributed opposite to each other along the second direction D2 .

[0078] For example, if Figure 1 and Figure 2As shown, the first conductive connection structure 12 and the second conductive connection structure 13 only partially overlap with the active area 10 (i.e., the orthographic projection of the first conductive connection structure 12 on the top surface of the active area 10 and the orthographic projection of the second conductive connection structure 13 on the top surface of the active area 10 both only partially overlap with the active area 10). The first conductive connection structure 12 includes a first main portion 121, a plurality of first extensions 122 connected to the first main portion 121 and extending along the second direction D2, and a first contact plug 123 located at an end of the first extension 122 away from the first main portion 121. The first contact plug 123 extends along a third direction (the third direction is perpendicular to the top surface of the active area 10 and intersects the first direction D1 and the second direction D2). One end of the first contact plug 123 is in electrical contact with the active area 10 (e.g., a source region or a drain region in the active area 10), and the other end is in electrical contact with the first extension 122. In one example, the first conductive connection structure 12 includes two first extensions 122 distributed along the first direction D1 at opposite ends of the first main portion 121. Both first extensions 122 extend from outside the active area 10 to above the source region and / or the drain region in the active area 10. A test electrical signal from the outside is transmitted to the source region and / or the drain region in the active area 10 through the first main portion 121, the first extensions 122, and the first contact plugs 123. The second conductive connection structure 13 includes a second main portion 131, a plurality of second extensions 132 connected to the second main portion 131 and extending along the second direction D2, and second contact plugs 133 located at ends of the second extensions 132. The second contact plugs 133 extend along the third direction, with one end of the second contact plugs 133 electrically connected to the active area 10 (e.g., the source region or the drain region in the active area 10) and the other end of the second extensions 132 electrically connected.

[0079] In some embodiments, the distances between the second extensions 132 and the first extensions 122 in any two of the active structures along the second direction are different. Figure 1 The distance between the first contact plug 123 and the second contact plug 133 along the second direction D2 is a first distance L1. Figure 2 A distance between the first contact plug 123 and the second contact plug 133 along the second direction D2 is a second distance L2, and the second distance L2 is greater than the first distance L1.

[0080] The first main portion 121 of the first conductive connection structure 12 and the second main portion 131 of the second conductive connection structure 13 are distributed along the second direction D2 on two opposite outer sides of the active area 10, and the first extension portion 122 of the first conductive connection structure 12 and the second extension portion 132 of the second conductive connection structure 13 are distributed opposite to each other. When the active structure 20 is used to test the resistance of the active area 10, a high voltage is transmitted to the first conductive connection structure 12 and a low voltage is transmitted to the second conductive connection structure 13, thereby forming a potential difference U between the first conductive connection structure 12 and the second conductive connection structure 13. 12 By detecting the current I in the active region 10 between the first contact plug 123 and the second contact plug 133 12 , according to the formula R 12 =U 12 / I 12 , the resistance of the active area 10 between the first contact plug 123 and the second contact plug 133 is obtained. For example, by testing Figure 1 The resistance of the active region 10 between the first contact plug 123 and the second contact plug 133 is Figure 2 The resistance of the active area 10 located between the first contact plug 123 and the second contact plug 133 can offset the influence of the first contact plug 123 and the second contact plug 133 on the resistance of the active area 10, and the unit length resistance of the active area 10 can be obtained according to the first distance L1 and the second distance L2.

[0081] In order to improve the application scope and flexibility of the active structure 20, in some embodiments, the conductive connection structure includes:

[0082] a third conductive connection structure 14 , located above the active area 10 and electrically connected to the active area 10 ;

[0083] The fourth conductive connection structure 15 is located above the active area 10 and is electrically connected to the active area 10. The third conductive connection structure 14 and the fourth conductive connection structure 15 are distributed on opposite sides of the active area 10 along the second direction D2, and the orthographic projection of the third conductive connection structure 14 on the top surface of the active area 10 and the orthographic projection of the fourth conductive connection structure 15 on the top surface of the active area 10 are both located inside the active area 10.

[0084] In some embodiments, the trunk portion 111 is distributed outside the active area 10 along the second direction D2, and the plurality of branches 112 are located above the active area 10;

[0085] The projection of the third conductive connection structure 14 on the active area 10 is located in the area between the projections of the two branches 112 on the active area 10 ;

[0086] The projection of the fourth conductive connection structure 15 on the active region 10 is located in a region between the projections of the two branches 112 on the active region 10 .

[0087] For example, if Figure 1 and Figure 2 As shown, the active structure further includes a third conductive connection structure 14 and a fourth conductive connection structure 15 distributed along the second direction D2 at opposite ends of the active region 10. The third conductive connection structure 14 includes a first connection portion 141 and a third contact plug 142. The third contact plug 142 extends along the third direction, with one end of the third contact plug 142 in contact and electrical connection with the first connection portion 141 and the other end in contact and electrical connection with the active region 10 (e.g., the source region or the drain region in the active region 10). The fourth conductive connection structure 15 includes a second connection portion 151 and a fourth contact plug 152. The fourth contact plug 152 extends along the third direction, with one end of the fourth contact plug 152 in contact and electrical connection with the second connection portion 151 and the other end in contact and electrical connection with the active region 10 (e.g., the source region or the drain region in the active region 10). In some embodiments, the spacing between the first connection portion 141 and the second connection portion 151 in any two of the active structures along the second direction D2 is different. Figure 1 The distance between the first connecting portion 141 and the second connecting portion 151 along the second direction D2 is smaller than that in Figure 2 The distance between the first connection portion 141 and the second connection portion 151 along the second direction D2.

[0088] When the active structure is used to test the resistance of the active area 10, a high voltage is transmitted to the third conductive connection structure 14 and a low voltage is transmitted to the fourth conductive connection structure 15, thereby forming a potential difference U between the third conductive connection structure 14 and the fourth conductive connection structure 15. 34 By detecting the current I in the active region 10 between the third contact plug 142 and the fourth contact plug 152 34 , according to the formula R 34 =U 34 / I 34 , the resistance of the active region 10 between the third contact plug 142 and the fourth contact plug 152 is obtained.

[0089] In one example, the active structure may include only the first conductive connection structure 12 and the second conductive connection structure 13. In another example, the active structure may include only the third conductive connection structure 14 and the fourth conductive connection structure 15. In yet another example, the active structure may include both the first conductive connection structure 12 and the second conductive connection structure 13, as well as the third conductive connection structure 14 and the fourth conductive connection structure 15.

[0090] This embodiment also provides a method for forming a semiconductor structure. Figure 3 This is a flow chart of the method for forming a semiconductor structure in a specific embodiment of the present disclosure. The schematic diagram of the semiconductor structure formed in this specific embodiment can be found in Figure 1 and Figure 2 .like Figure 1-Figure 3 As shown, the method for forming the semiconductor structure includes the following steps:

[0091] Step S31, providing a substrate;

[0092] Step S32, forming a plurality of active regions 10 arranged at intervals in the substrate, wherein the widths of the plurality of active regions 10 along a first direction D1 are the same, and the lengths of any two active regions 10 along a second direction D2 are different, and the first direction D1 intersects the second direction D2;

[0093] In step S33 , a gate structure 11 and a conductive connection structure electrically connected to the active area 10 are formed above each active area 10 to form a plurality of active structures 20 , wherein each active structure 20 includes the active area 10 and the gate structure 11 and the conductive connection structure 21 corresponding to the active area 10 .

[0094] In some embodiments, the specific steps of forming the gate structure 11 above each active area 10 and the conductive connection structure 21 electrically connected to the active area 10 include:

[0095] forming a gate material layer above the active area 10;

[0096] The gate material layer is patterned to form the gate structure 11 including a main body 111 and a plurality of branches 112 connected to the main body 111 and arranged at intervals along the first direction D1. The spacing between any two adjacent branches 112 above any two active areas 10 is equal.

[0097] In some embodiments, the specific steps of forming the gate structure 11 above each active area 10 and the conductive connection structure 21 electrically connected to the active area 10 include:

[0098] forming a first conductive connection material layer above the active area 10;

[0099] The first conductive connection material layer is patterned to form a first conductive connection structure 12 and a second conductive connection structure 13 spaced apart on opposite sides of the active area 10 along the second direction D2. The first conductive connection structure 12 and the second conductive connection structure 13 are both electrically connected to the active area 10, and the first conductive connection structure 12 and the second conductive connection structure 13 partially overlap with the active area 10. The spacing distance between the first conductive connection structure 12 and the second conductive connection structure 13 above any two active areas 10 along the second direction D2 is different.

[0100] In some embodiments, the specific steps of forming the gate structure 11 above each active area 10 and the conductive connection structure electrically connected to the active area 10 include:

[0101] forming a second conductive connection material layer above the active area 10;

[0102] The second conductive connection material layer is patterned to form a third conductive connection structure 14 and a fourth conductive connection structure 15 that are spaced apart and distributed on opposite sides of the active area 10 along the second direction D2. The third conductive connection structure 14 and the fourth conductive connection structure 15 are both electrically connected to the active area 10, and the orthographic projection of the third conductive connection structure 14 on the top surface of the active area 10 and the orthographic projection of the fourth conductive connection structure 15 on the top surface of the active area 10 are both located inside the active area 10. The spacing distance between the third conductive connection structure 14 and the fourth conductive connection structure 15 above any two active areas 10 along the second direction D2 is different.

[0103] This embodiment also provides a method for operating a semiconductor structure. Figure 4 This is a flow chart of the method for operating a semiconductor structure in a specific embodiment of the present disclosure. Figure 4 As shown, the operating method of the semiconductor structure includes the following steps:

[0104] Step S41, providing Figure 1 and Figure 2 The semiconductor structure;

[0105] Step S42, selecting one of the active structures 20 as a first active structure, and selecting another of the active structures 20 as a second active structure.

[0106] Step S43 , transmitting a first test signal to the conductive connection structure 21 in the first active structure, and obtaining the resistance of the active area 10 in the first active structure as a first resistor R1 ;

[0107] Step S44 , transmitting the first test signal to the conductive connection structure 21 in the second active structure, and obtaining the resistance of the active area 10 in the second active structure as a second resistor R2 ;

[0108] Step S45 : obtaining a unit resistance of the active area 10 according to the first resistor R1 and the second resistor R2 .

[0109] In order to avoid the formation of an inversion layer resistance under the gate structure 11 and interference with the test result of the active area resistance, in some embodiments, while transmitting the first test signal to the conductive connection structure 21 in the first active structure, the following steps are also included: applying a 0V voltage to the gate structure 11 in the first active structure;

[0110] While transmitting the first test signal to the conductive connection structure 21 in the second active structure, the method further includes the following step: applying a voltage of 0 V to the gate structure 11 in the second active structure.

[0111] In some embodiments, the conductive connection structure 21 includes a first conductive connection structure 12 and a second conductive connection structure 13, both located above the active area 10 and spaced apart along the second direction D2. The first conductive connection structure 12 and the second conductive connection structure 13 are both electrically connected to the active area 10, and the first conductive connection structure 12 and the second conductive connection structure 13 partially overlap with the active area 10. The specific steps of transmitting a first test signal to the conductive connection structure in the first active structure and obtaining the resistance of the active area 10 in the first active structure as the first resistor R1 include:

[0112] Transmitting a first voltage signal U1 to the first conductive connection structure 12 and simultaneously transmitting a second voltage signal U2 to the second conductive connection structure 13 , wherein the first voltage signal U1 is higher than the second voltage signal U2 ;

[0113] Obtaining a current in the active area 10 between the first conductive connection structure 12 and the second conductive connection structure 13 as a first current I1;

[0114] The first resistor R1 is calculated according to the difference between the first voltage signal U1 and the second voltage signal U2 , and the first current I1 .

[0115] In some embodiments, the specific steps of obtaining the unit resistance of the active area 10 according to the first resistor R1 and the second resistor R2 include:

[0116] Obtaining a distance between the first conductive connection structure 12 and the second conductive connection structure 13 in the first active structure as a first distance L1;

[0117] Obtaining a distance between the first conductive connection structure 12 and the second conductive connection structure 13 in the second active structure as a second distance L2;

[0118] The unit resistance R of the active area is calculated based on the first resistance R1, the second resistance R2, the first distance L1 and the second distance L2. s .

[0119] In some embodiments, the unit resistance R of the active area 10 is calculated based on the first resistance R1, the second resistance R2, the first distance L1, and the second distance L2. s The specific steps include:

[0120] The unit resistance R of the active area is calculated using the following formula: s :

[0121] R s =(R2–R1) / [2(L2-L1)]

[0122] Here, R2 represents the second resistor, R1 represents the first resistor, L2 represents the second distance, and L1 represents the first distance.

[0123] For example, Figure 1 The active structure 20 shown in FIG is used as the first active structure, and the active structure 20 is used as the first active structure. Figure 2The active structure 20 shown in the figure serves as the second active structure. The first voltage signal U1 is transmitted to the first conductive connection structure 12 in the first active structure, the second voltage signal U2 is transmitted to the second conductive connection structure 13, and a 0V signal is transmitted to the fifth plug 143 electrically connected to the gate structure 11, and the remaining conductive structures are floating. According to the difference between the first voltage signal U1 and the second voltage signal U2, and the first current I1, the first resistance R1 is calculated according to the formula R1=(U1-U2) / I1. The first voltage signal U1 is transmitted to the first conductive connection structure 12 in the second active structure, the second voltage signal U2 is transmitted to the second conductive connection structure 13, and a 0V signal is transmitted to the fifth plug 143 electrically connected to the gate structure 11, and the remaining conductive structures are floating. According to the difference between the first voltage signal U1 and the second voltage signal U2, and the second current I2 (i.e. Figure 2 The second resistance R2 is calculated according to the formula R2=(U1-U2) / I2. s =(R2–R1) / [2(L2-L1)] to calculate the unit resistance R of the active area s .

[0124] In other specific embodiments, Figure 1 and Figure 2 A voltage signal is applied to the third conductive connection structure 14 and the fourth conductive connection structure 15 in the active region, and the unit resistance of the active region is obtained in the same way.

[0125] The semiconductor structures and their formation and operation methods provided in some embodiments of this specific embodiment include an active region, a gate structure located above the active region, and a conductive connection structure located above and electrically connected to the active region, within the active structure. This allows the influence of the gate structure to be taken into account when calculating the active region resistance, thereby improving the accuracy and reliability of the active region resistance test and providing a reference for improving semiconductor device performance. Furthermore, in some embodiments of this specific embodiment, the active regions of any two of the multiple active structures provided have unequal lengths, thereby reducing or even eliminating the influence of the conductive connection structure on the active region resistance test through measurement of the multiple active structures, further improving the accuracy and reliability of the active region resistance test.

[0126] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a plurality of active structures, each of the active structures comprising an active region, a gate structure located above the active region, and a conductive connection structure located above the active region and electrically connected to the active region; The active regions of the plurality of active structures have the same width along a first direction, and the active regions of any two active structures have different lengths along a second direction, and the first direction intersects the second direction; Wherein, the conductive connection structure includes: a first conductive connection structure, located above the active area and electrically connected to the active area; a second conductive connection structure, located above the active area and electrically connected to the active area, the first conductive connection structure and the second conductive connection structure being spaced apart and distributed on opposite sides of the active area along the second direction, and both the first conductive connection structure and the second conductive connection structure partially overlapping the active area; The first conductive connection structure includes a first main body extending along the first direction, and a plurality of first extensions connected to the first main body and extending along the second direction, wherein the plurality of first extensions are arranged at intervals along the first direction, and the first extensions are at least partially located above the active area and electrically connected to the active area; The second conductive connection structure includes a second main body extending along the first direction, and a plurality of second extension portions connected to the second main body and extending along the second direction, and the plurality of second extension portions are arranged at intervals along the first direction, and the second extension portions are at least partially located above the active area and electrically connected to the active area.

2. The semiconductor structure according to claim 1, wherein: The gate structure in the active structure includes a main body and a plurality of branches connected to the main body and arranged at intervals along the first direction; The spacing distance between two adjacent branches in any two active structures along the first direction is equal.

3. The semiconductor structure according to claim 2, wherein: The main body is distributed outside the active area along the second direction, and the plurality of branches are located above the active area; The first main body portion is distributed outside the main body portion along the second direction, and the plurality of first extension portions are distributed on opposite sides of the main body portion along the first direction; The second main body portion and the first main body portion are distributed on two opposite outer sides of the active region along the second direction, and the second extension portion and the first extension portion are distributed opposite to each other along the second direction.

4. The semiconductor structure according to claim 3, wherein: The second extension portion and the first extension portion in any two of the active structures are spaced apart from each other by different distances along the second direction.

5. The semiconductor structure according to claim 2, wherein: The conductive connection structure includes: a third conductive connection structure, located above the active area and electrically connected to the active area; a fourth conductive connection structure located above the active area and electrically connected to the active area, the third conductive connection structure and the fourth conductive connection structure are distributed on opposite sides of the active area along the second direction, and the orthographic projection of the third conductive connection structure on the top surface of the active area and the orthographic projection of the fourth conductive connection structure on the top surface of the active area are both located inside the active area.

6. The semiconductor structure according to claim 5, wherein: The main body is distributed outside the active area along the second direction, and the plurality of branches are located above the active area; The projection of the third conductive connection structure on the active area is located in the area between the projections of the two branches on the active area; The projection of the fourth conductive connection structure on the active region is located in a region between projections of the two branches on the active region.

7. The semiconductor structure according to claim 1, wherein: The active structure further comprises: An external gate structure is located outside the active area along the first direction, and the external gate structure is arranged in the same layer as the gate structure.

8. A method for operating a semiconductor structure, characterized in that: The steps include: Providing the semiconductor structure according to claim 1; selecting one of the plurality of active structures as a first active structure, and selecting another of the plurality of active structures as a second active structure; transmitting a first test signal to the conductive connection structure in the first active structure, and obtaining a resistance of the active area in the first active structure as a first resistance; transmitting the first test signal to the conductive connection structure in the second active structure, and obtaining the resistance of the active area in the second active structure as a second resistance; A unit resistance of the active area is obtained according to the first resistance and the second resistance.

9. The method for operating a semiconductor structure according to claim 8, wherein: While transmitting the first test signal to the conductive connection structure in the first active structure, the method further includes the following steps: applying a 0V voltage to the gate structure in the first active structure; While transmitting the first test signal to the conductive connection structure in the second active structure, the method further includes the following step: applying a 0V voltage to the gate structure in the second active structure.

10. The method for operating a semiconductor structure according to claim 8, wherein: The conductive connection structure includes a first conductive connection structure and a second conductive connection structure, both of which are located above the active area and spaced apart along the second direction, the first conductive connection structure and the second conductive connection structure are both electrically connected to the active area, and the first conductive connection structure and the second conductive connection structure partially overlap with the active area. The specific steps of transmitting a first test signal to the conductive connection structure in the first active structure and obtaining the resistance of the active area in the first active structure as the first resistance include: transmitting a first voltage signal to the first conductive connection structure and simultaneously transmitting a second voltage signal to the second conductive connection structure, wherein the first voltage signal is higher than the second voltage signal; obtaining a current in the active area between the first conductive connection structure and the second conductive connection structure as a first current; The first resistance is calculated according to a difference between the first voltage signal and the second voltage signal, and the first current.

11. The method for operating a semiconductor structure according to claim 10, wherein: The specific steps of obtaining the unit resistance of the active area according to the first resistor and the second resistor include: acquiring a distance between the first conductive connection structure and the second conductive connection structure in the first active structure as a first distance; acquiring a distance between the first conductive connection structure and the second conductive connection structure in the second active structure as a second distance; A unit resistance of the active area is calculated according to the first resistance, the second resistance, the first distance, and the second distance.

12. The method for operating a semiconductor structure according to claim 11, wherein: The specific steps of calculating the unit resistance of the active area according to the first resistance, the second resistance, the first distance, and the second distance include: The unit resistance R of the active area is calculated using the following formula: s : R s = (R2 – R1) / [2(L2-L1)] Here, R2 represents the second resistor, R1 represents the first resistor, L2 represents the second distance, and L1 represents the first distance.

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