Pixel structure and display device thereof

Abstract

The invention discloses a pixel structure and a display device thereof, and the pixel structure comprises a first light-emitting diode which is used for emitting a first light ray, the first light-emitting diode is provided with a first semiconductor lamination layer, a first light-emitting surface and a first electrode which is located below the first semiconductor lamination layer and is far away from the first light-emitting surface; the second light-emitting diode is used for emitting a second light ray and is provided with a second semiconductor laminated layer, a second light-emitting surface and a second electrode which is positioned below the second semiconductor laminated layer and is far away from the second light-emitting surface; the dielectric layer surrounds and is in contact with the first light emitting diode and the second light emitting diode, and exposes the first light emitting surface, the first electrode, the second light emitting surface and the second electrode; the common electrode structure is provided with a semiconductor layer and a metal layer; and the light-transmitting conductive layer covers and is electrically connected with the first light-emitting diode, the second light-emitting diode and the common electrode structure.

Description

Technical Field

[0001] The invention relates to a pixel structure, and in particular to a pixel structure using vertical red, blue and green light emitting diodes and a display device thereof. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor element that emits monochromatic light. When used in pixels in display devices, each pixel contains at least one set of red, blue, and green light-emitting diodes. LEDs have three structures: vertical, horizontal, and flip-chip. The p and n electrodes of horizontal and flip-chip LEDs must be set on the same side of the light-emitting layer, while the p and n electrodes of vertical LEDs are located on opposite sides of the light-emitting layer. Compared with horizontal and flip-chip LEDs, vertical LEDs can produce similar luminous intensity with a smaller size, and are more suitable for display devices with high pixel density. Summary of the invention

[0003] A pixel structure includes a first light emitting diode, a second light emitting diode, a dielectric layer, a common electrode structure and a light-transmitting conductive layer. The first light emitting diode is used to emit a first light, and has a first semiconductor stack, a first light-emitting surface and a first electrode, wherein the first light-emitting surface and the first electrode are located on opposite sides of the first semiconductor stack. The second light emitting diode is used to emit a second light, and has a second semiconductor stack, a second light-emitting surface and a second electrode, wherein the second light-emitting surface and the second electrode are located on opposite sides of the second semiconductor stack. The dielectric layer surrounds and contacts the first light emitting diode and the second light emitting diode, and exposes the first light-emitting surface, the first electrode, the second light-emitting surface and the second electrode. The common electrode structure has a semiconductor layer and a metal layer. The light-transmitting conductive layer covers and electrically connects the first light emitting diode, the second light emitting diode and the common electrode structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a cross-sectional view of a pixel structure of an embodiment;

[0005] Figure 2 is a schematic structural diagram of a display device according to an embodiment;

[0006] Figure 3A is a top view of a pixel structure of an embodiment;

[0007] Figure 3B is a top view of a pixel structure of an embodiment;

[0008] Figure 4A schematic diagram of the structure of a first chip, a second chip and a third chip according to an embodiment;

[0009] Figure 5A A schematic diagram of the structure of a first chip, a second chip and a third chip according to an embodiment;

[0010] Figure 5B A top view of a common conductive structure, a first chip, a second chip, and a third chip according to an embodiment;

[0011] Figure 6 is a cross-sectional view of a pixel structure of an embodiment;

[0012] Figures 7 to 11 is a manufacturing flow chart of a pixel structure according to an embodiment;

[0013] Fig.12 is a cross-sectional view of a pixel structure of an embodiment;

[0014] Fig.13 is a top view of a pixel structure of an embodiment;

[0015] Fig.14 A bottom view of a pixel structure according to an embodiment;

[0016] Figures 15 to 18 is a manufacturing flow chart of a pixel structure according to an embodiment;

[0017] Figures 19 to 21 is a manufacturing flow chart of a pixel structure according to another embodiment;

[0018] Fig.22A is a cross-sectional view of a chip according to an embodiment;

[0019] Fig. 22B for Fig.22A Enlarged view of the middle G region;

[0020] Fig.23 is a cross-sectional view of a chip according to an embodiment;

[0021] Fig.24 is a cross-sectional view of an arrangement structure of an embodiment;

[0022] Fig.25 is a cross-sectional view of an arrangement structure of another embodiment;

[0023] Figure 26 to Figure 29 A manufacturing flow chart of an arrangement structure according to an embodiment;

[0024] Fig.30 is a cross-sectional view of an arrangement structure of an embodiment;

[0025] Fig.31A schematic diagram of steps S200 to S208 of forming an arrangement structure C according to an embodiment;

[0026] Fig.32A is a cross-sectional view of a chip according to an embodiment;

[0027] Fig.32B is a cross-sectional view of a chip according to an embodiment;

[0028] FIG. 33A to FIG. 33H A manufacturing flow chart of a chip according to an embodiment;

[0029] Figure 34A to Figure 34C is a schematic structural diagram of a display device according to an embodiment;

[0030] Fig.35 A cross-sectional view of a chip temporarily fixed on a temporary carrier by an adhesive layer according to an embodiment;

[0031] Fig.36 is a cross-sectional view of a display device according to an embodiment;

[0032] Fig.37 is a structural schematic diagram of a light emitting array device according to an embodiment;

[0033] Fig.38A is a cross-sectional view of a light emitting array device according to an embodiment;

[0034] Fig.38B is a cross-sectional view of a light emitting array device according to an embodiment;

[0035] Fig.38C is a top view of a light emitting array device according to an embodiment;

[0036] FIG. 39A to FIG. 39E is a manufacturing flow chart of a light emitting array device according to an embodiment; and FIG. 40A to FIG. 40E FIG. 4 is a manufacturing flow chart of a light emitting array device according to an embodiment of the present invention.

[0037] Description of symbols 1, 1' light-transmitting carrier plate;

[0038] 10, 10' light emitting element;

[0039] 100, 100' pixel structure;

[0040] 1000 support substrates;

[0041] 1000G adhesive layer

[0042] 102 lower electrode;

[0043] 103 semiconductor stack;

[0044] 1031 upper semiconductor layer;

[0045] 1031A epitaxial layer;

[0046] 1031S surface;

[0047] 1032 lower semiconductor layer;

[0048] 1032S surface;

[0049] 1033 luminous layer;

[0050] 103M platform structure;

[0051] 103S side wall;

[0052] 104G growth substrate;

[0053] 106 insulating protective layer;

[0054] 106S surface;

[0055] 11 surface;

[0056] 1A temporary carrier board;

[0057] 1B, 1C, 1D, 1C', 1D', 1E, 1E', 1F, 1G, 1H adhesive layer;

[0058] 1CD double adhesive layer structure;

[0059] 2, 2' light-transmitting conductive layer;

[0060] 20, 20A, 20B common conductive layer;

[0061] 200 pixel structure;

[0062] 20A1 first epitaxial layer;

[0063] 20A2 second epitaxial layer;

[0064] 20C metal grid;

[0065] 3, 3', 3A dielectric layer;

[0066] 31 first common surface;

[0067] 32 second common surface;

[0068] 3S1 lower surface;

[0069] 3S2 upper surface;

[0070] 4, 4', 4" common conductive structure;

[0071] 400 Temporary board;

[0072] 41 upper electrode;

[0073] 42 lower electrode;

[0074] 43Semiconductor structure;

[0075] 431 upper semiconductor layer;

[0076] 432 lower semiconductor layer;

[0077] 433Multilayer quantum well structure;

[0078] 43S1 first side wall;

[0079] 43S2 second side wall;

[0080] 44, 44' conductive part;

[0081] 5, 5', 5" first chip;

[0082] 500 temporary carrier board;

[0083] 51, 51' upper electrode;

[0084] 511 light-transmitting conductive layer;

[0085] 512 current channel layer;

[0086] 52, 52A, 52B lower electrode;

[0087] 521 reflective metal layer;

[0088] 522 barrier metal layer;

[0089] 523 metal connection layer;

[0090] 53 a first semiconductor stack;

[0091] 531, 531' first upper semiconductor layer;

[0092] 532, 532A, 532B a first lower semiconductor layer;

[0093] 533, 533A first light emitting layer;

[0094] 533B multi-layer quantum well structure;

[0095] 53A luminous stacking area;

[0096] 53B conductive stacking region;

[0097] 54 insulation layer;

[0098] 55 through holes;

[0099] 5A, 5C luminous areas;

[0100] 5B, 5D conductive areas;

[0101] 6 second chip;

[0102] 600 temporary carrier board;

[0103] 61 upper electrode;

[0104] 611 light-transmitting conductive layer;

[0105] 612 current channel layer;

[0106] 62 lower electrode;

[0107] 621 reflective metal layer;

[0108] 622 barrier metal layer;

[0109] 623 metal connection layer;

[0110] 63 second semiconductor stack;

[0111] 631 second upper semiconductor layer;

[0112] 632 second lower semiconductor layer;

[0113] 633 second light emitting layer;

[0114] 7 third chip;

[0115] 700 temporary carrier board;

[0116] 71 upper electrode;

[0117] 711 light-transmitting conductive layer;

[0118] 712 current channel layer;

[0119] 72 lower electrode;

[0120] 721 reflective metal layer;

[0121] 722 barrier metal layer;

[0122] 723 metal connection layer;

[0123] 73 a third semiconductor stack;

[0124] 731 a third upper semiconductor layer;

[0125] 732 third lower semiconductor layer;

[0126] 733 third light emitting layer;

[0127] 8 circuit redistribution layers;

[0128] 800, 800', 800A, 800B temporary carrier;

[0129] 800S, 800AS surface;

[0130] 81 shared pad;

[0131] 82 first welding pad;

[0132] 83 second welding pad;

[0133] 84 third welding pad;

[0134] 8A lower surface;

[0135] 8B upper surface;

[0136] 90 circuit boards;

[0137] 90B circuit device;

[0138] 90B1 common electrode;

[0139] 90B2 lower electrode;

[0140] 900A, 900B, 900C display devices;

[0141] 900D, 900E, 900E' light array device;

[0142] 91, 91' pixels;

[0143] 92, 92' lower electrode;

[0144] 921 ohm contact layer;

[0145] 92T recessed part;

[0146] 93 semiconductor stacking;

[0147] 930 growth substrate;

[0148] 930A, 930B temporary carrier boards;

[0149] 930S graphic surface;

[0150] 931 upper semiconductor layer;

[0151] 9311 a first upper semiconductor layer;

[0152] 9311S1 mid-side surface;

[0153] 9311S2 upper surface;

[0154] 9312 second upper semiconductor layer;

[0155] Platforms 931B and 931C;

[0156] 932 lower semiconductor layer;

[0157] 932S lower surface;

[0158] 933Multilayer quantum well structure;

[0159] Platforms 93B and 93C;

[0160] 93S side surface;

[0161] 93S1 upper surface;

[0162] 93S2 lower surface;

[0163] 93T through hole;

[0164] 93V groove;

[0165] 95 electrical connection portion;

[0166] 95-1 first electrical connection portion;

[0167] 95-2 second electrical connection portion;

[0168] 96 insulation protection layer;

[0169] 97 upper electrode;

[0170] 97B metal electrode;

[0171] 98 conductive part;

[0172] 99 dashed line;

[0173] 9A, 9B, 9B', 9C, 9C', 9D chips; 9Aa, 9Da front side;

[0174] 9Ab, 9Db back;

[0175] 9DA luminous area;

[0176] 9DB conductive area;

[0177] A, B, C arrangement structure;

[0178] D Temporary structure;

[0179] G spacing;

[0180] H1, H4, H5, H6, H7 height;

[0181] T1 first temperature;

[0182] Tg glass transition temperature;

[0183] W1 side length;

[0184] Width of W1C, W9A, W9D;

[0185] AA', BB', XX' dotted lines;

[0186] Angle between θ1 and θ2 DETAILED DESCRIPTION

[0187] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. The present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself represent the relationship between the various embodiments and / or configurations discussed.

[0188] Figure 1 A cross-sectional view of a pixel structure 100 according to an embodiment is shown. The pixel structure 100 can emit red, blue and green light and serve as a pixel of a display device. Figure 2 The structure diagram of a display device 900A is shown. The display device 900A has a circuit board 90 and a plurality of pixels 91. The plurality of pixels 91 are arranged in an array on the circuit board 90, wherein the circuit board 90 may be a printed circuit board (PCB) or a glass circuit board, and the pixels 91 may be Figure 1 The pixel structure 100 is shown.

[0189] like Figure 1As shown, the pixel structure 100 has a transparent substrate 1, a transparent conductive layer 2, a common conductive structure 4, a dielectric layer 3, a first chip 5, a second chip 6, a third chip 7, a common pad 81, a first pad 82, a second pad 83 and a third pad 84. The transparent conductive layer 2 is located below the transparent substrate 1 and covers the surface 11 of the transparent substrate 1. The common pad 81, the first pad 82, the second pad 83 and the third pad 84 are used to connect to an external circuit (not shown). The common conductive structure 4 is located between the transparent substrate 1 and the common pad 81 and is connected to the transparent conductive layer 2 and the common pad 81 to conduct current between the transparent conductive layer 2 and the common pad 81. The first chip 5 is located between the transparent substrate 1 and the first pad 82 and is electrically connected to the transparent conductive layer 2 and the first pad 82. The second chip 6 is located between the transparent substrate 1 and the second pad 83 and is electrically connected to the transparent conductive layer 2 and the second pad 83. The third chip 7 is located between the transparent substrate 1 and the third pad 84 and is electrically connected to the transparent conductive layer 2 and the third pad 84. The first chip 5 can be driven to emit a first light, the second chip 6 can be driven to emit a second light, and the third chip 7 can be driven to emit a third light, wherein the first light, the second light and the third light can be visible light of the same or different wavelength ranges, or invisible light of the same or different wavelength ranges. In order to isolate mechanical impact from the outside to improve the reliability of the pixel structure 100, the dielectric layer 3 surrounds the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 from the side and is in direct or indirect contact with the transparent conductive layer 2 (not shown). In one embodiment, the dielectric layer 3, the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 together form a first common surface 31 and a second common surface 32 opposite to each other. The first common surface 31 is in direct contact with the light-transmitting conductive layer 2, wherein the first common surface 31 and / or the second common surface 32 may be a flat surface or an uneven surface. The common pad 81 is below the second common surface 32 and electrically connected to the common conductive structure 4. The first pad 82 is below the second common surface 32 and electrically connected to the first chip 5, the second pad 83 is below the second common surface 32 and electrically connected to the second chip 6, and the third pad 84 is below the second common surface 32 and electrically connected to the third chip 7. The pixel structure 100 is connected to an external circuit (not shown) through the common pad 81, the first pad 82, the second pad 83 and the third pad 84 to receive power and be controlled to emit a first light, a second light and a third light of a specific brightness.

[0190] like Figure 3A The top view of the pixel structure 100 is shown, where the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 are arranged in a straight line. Figure 3BA top view of the pixel structure 100 is shown, wherein the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 are arranged in an array. In other embodiments, the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 can be arranged in a different order or position according to design requirements, such as in a triangle, a rhombus, a parallelogram, etc.

[0191] like Figure 1 As shown, the common conductive structure 4 has a semiconductor structure 43, an upper electrode 41, a lower electrode 42 and a conductive portion 44. The upper electrode 41 is located above the semiconductor structure 43, and the lower electrode 42 is located below the semiconductor structure 43. In one embodiment, Figure 1 and Figure 3AAs shown, the semiconductor structure 43 has a first sidewall 43S1 and a plurality of second sidewalls 43S2 located between the upper electrode 41 and the lower electrode 42, the conductive portion 44 covers and contacts the first sidewall 43S1 of the semiconductor structure 43 and is located between the upper electrode 41 and the lower electrode 42 and directly contacts the upper electrode 41 and the lower electrode 42, and the plurality of second sidewalls 43S2 are not covered by the conductive portion 44. The semiconductor structure 43 has an upper semiconductor layer 431, a lower semiconductor layer 432, and a multi-layer quantum well structure (Multiple Quantum Well; MQW) 433 located between the upper semiconductor layer 431 and the lower semiconductor layer 432. The upper semiconductor layer 431 is electrically connected to the upper electrode 41, and the lower semiconductor layer 432 is electrically connected to the lower electrode 42. In one embodiment, the entire surface of the upper semiconductor layer 431, the multi-layer quantum well structure 433 and the lower semiconductor layer 432 (i.e., the first sidewall 43S1) are in contact with the conductive portion 44, and the material of the conductive portion 44 is a material with a lower resistance than the semiconductor structure 43, such as a metal material, including copper, tin, aluminum, silver, palladium, gold, alloys of the above materials, or stacks of the above materials. The current will flow through the conductive portion 44 but not through the multi-layer quantum well structure 433, so the common conductive structure 4 will not emit light. In one embodiment, on the first sidewall 43S1 of the semiconductor structure 43, the conductive portion 44 covers and contacts the entire surface of the lower semiconductor layer 432 and the multi-layer quantum well structure 433 and a portion of the surface of the upper semiconductor layer 431 (not shown), and the conductive portion 44 is in direct contact with the lower electrode 42 but not with the upper electrode 41. In one embodiment, the path of the current flowing between the upper electrode 41 and the lower electrode 42 is to flow from the upper electrode 41, pass through a portion of the upper semiconductor layer 431, pass through the conductive portion 44, and finally enter the lower electrode 42. In one embodiment, on the first sidewall 43S1 of the semiconductor structure 43, the conductive portion 44 covers and contacts the entire surface of the upper semiconductor layer 431 and the multi-layer quantum well structure 433 and a portion of the surface of the lower semiconductor layer 432 (not shown), and the conductive portion 44 directly contacts the upper electrode 41 but does not contact the lower electrode 42. In one embodiment, the path for the current to flow between the upper electrode 41 and the lower electrode 42 is to flow from the upper electrode 41, pass through the conductive portion 44, pass through a portion of the lower semiconductor layer 432, and finally enter the lower electrode 42. In one embodiment, on the first side wall 43S1 of the semiconductor structure 43, the conductive portion 44 covers and contacts the entire surface of the multi-layer quantum well structure 433 and the surfaces of portions of the upper semiconductor layer 431 and the lower semiconductor layer 432 (not shown), and the conductive portion 44 is not in direct contact with the upper electrode 41 and the lower electrode 42. The path for current to flow between the upper electrode 41 and the lower electrode 42 is to flow in from the upper electrode 41, pass through portions of the upper semiconductor layer 431, pass through the conductive portion 44, and then pass through portions of the lower semiconductor layer 432, and finally enter the lower electrode 42.In one embodiment, the conductive portion 44 covers the first sidewall 43S1 of the semiconductor structure 43 and part or all of the second sidewalls 43S2 , ie, reference . Figure 3A , the conductive portion 44 may cover all or part of the sidewalls of the semiconductor structure 43 (not shown).

[0192] like Figure 1As shown, the first chip 5 has a first semiconductor stack 53, an upper electrode 51 and a lower electrode 52, wherein the upper electrode 51 is located on the first semiconductor stack 53, the lower electrode 52 is located below the first semiconductor stack 53, the first semiconductor stack 53 has a first upper semiconductor layer 531 electrically connected to the upper electrode 51, a first lower semiconductor layer 532 electrically connected to the lower electrode 52, and a first light emitting layer 533 located between the first upper semiconductor layer 531 and the first lower semiconductor layer 532. When current is introduced into the first semiconductor stack 53 through the upper electrode 51 or the lower electrode 52, the first light emitting layer 533 emits a first light. The second chip 6 has a second semiconductor stack 63, an upper electrode 61 and a lower electrode 62, wherein the upper electrode 61 is located on the second semiconductor stack 63, the lower electrode 62 is located below the second semiconductor stack 63, the second semiconductor stack 63 has a second upper semiconductor layer 631 electrically connected to the upper electrode 61, a second lower semiconductor layer 632 electrically connected to the lower electrode 62, and a second light emitting layer 633 located between the second upper semiconductor layer 631 and the second lower semiconductor layer 632. When current is introduced into the second semiconductor stack 63 through the upper electrode 61 or the lower electrode 62, the second light emitting layer 633 emits a second light. The third chip 7 has a third semiconductor stack 73, an upper electrode 71 and a lower electrode 72, wherein the upper electrode 71 is located on the third semiconductor stack 73, the lower electrode 72 is located below the third semiconductor stack 73, the third semiconductor stack 73 has a third upper semiconductor layer 731 electrically connected to the upper electrode 71, a third lower semiconductor layer 732 electrically connected to the lower electrode 72, and a third light emitting layer 733 located between the third upper semiconductor layer 731 and the third lower semiconductor layer 732. When current is introduced into the third semiconductor stack 73 through the upper electrode 71 or the lower electrode 72, the third light emitting layer 733 emits a third light. In one embodiment, the first chip 5 is a blue light emitting diode die, which can emit blue light (first light) with a dominant wavelength (Dominant Wavelength) or a peak wavelength between 440nm and 480nm; the second chip 6 is a green light emitting diode die, which can emit green light (second light) with a dominant wavelength (Dominant Wavelength) or a peak wavelength between 500nm and 540nm; the third chip 7 is a red light emitting diode die, which can emit red light (third light) with a dominant wavelength (Dominant Wavelength) or a peak wavelength between 600nm and 660nm, wherein the semiconductor stacks of the blue light emitting diode die and the green light emitting diode die include materials of the gallium nitride (GaN) series, and the semiconductor stacks of the red light emitting diode die include quaternary materials of the aluminum gallium indium phosphide (AlGaInP) series. In one embodiment, the first chip 5 is a green light emitting diode die, the second chip 6 can be a red light emitting diode die, and the third chip 7 can be a blue light emitting diode die.Or in one embodiment, the first chip 5 is a red light emitting diode die, the second chip 6 is a blue light emitting diode die, and the third chip 7 is a green light emitting diode die.

[0193] In one embodiment, the semiconductor structure 43 has the same or similar structure as one of the first semiconductor stack 53, the second semiconductor stack 63 and the third semiconductor stack 73; the upper electrode 41 has the same or similar structure as one of the upper electrode 51, the upper electrode 61 and the upper electrode 71; the lower electrode 42 has the same or similar structure as one of the lower electrode 52, the lower electrode 62 and the lower electrode 72. The difference between the common conductive structure 4 and the first chip 5, the second chip 6 and the third chip 7 is that the common conductive structure 4 has a conductive portion 44 covering the first side wall 43S1 and / or the second side wall 43S2 of the semiconductor structure 43, so that the common conductive structure 4 serves as a current conduction path between the common pad 81 and the light-transmitting conductive layer 2 and does not emit light. In the existing packaging technology, a conductive column is usually set between different conductive layers to conduct current, wherein the material of the conductive column is metal, such as copper or gold. The manufacturing method of the conductive column is usually an electroplating process, but the cost of the electroplating process is high and the manufacturing process time is long. In one embodiment, the common conductive structure 4 is disposed between the transparent conductive layer 2 and the common pad 81 to conduct current. The structure and manufacturing process of the common conductive structure 4 are similar to those of the first chip 5, the second chip 6 or the third chip 7. Therefore, the common conductive structure 4 can be mass-produced together with the first chip 5, the second chip 6 and the third chip 7. Figure 1 In the manufacturing process of the pixel structure 100, the manufacturing process of the conductive pillar can be omitted to reduce the cost and shorten the manufacturing process.

[0194] like Figure 1 As shown, the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 have the same height H1. In one embodiment, the height H1 is less than 100 μm, or between 1 μm and 10 μm. Figure 3A and Figure 3B A top view of the pixel structure 100 is shown. Figure 3A and Figure 3B As shown, the outer contours of the common conductive structure 4 , the first chip 5 , the second chip 6 and the third chip 7 are all rectangular, with a side length W1 . In one embodiment, the side length W1 is between 1 μm and 100 μm.

[0195] like Figure 1As shown, in one embodiment, the first upper semiconductor layer 531, the second upper semiconductor layer 631 and the third upper semiconductor layer 731 include p-type semiconductor layers, the first lower semiconductor layer 532, the second lower semiconductor layer 632 and the third lower semiconductor layer 732 include n-type semiconductor layers, the upper electrode 51, the upper electrode 61 and the upper electrode 71 all include light-transmitting conductive materials and the contact resistance between them and the p-type semiconductor layers is less than 10 -2 Ω·cm. The light-transmitting conductive material includes indium tin oxide (ITO), and the transmittance of visible light with a main wavelength or peak wavelength between 440nm and 660nm exceeds 80%. The lower electrode 52, the lower electrode 62 and the lower electrode 72 have the same or similar metal stacked structure. Figure 4 The schematic diagram of the structure of the first chip 5, the second chip 6 and the third chip 7 is shown. Figure 4 As shown, the lower electrode 52, the lower electrode 62 and the lower electrode 72 all include a reflective metal layer 521, 621, 721 connected to the lower semiconductor layer 532, 632, 732 to reflect the first light, the second light and the third light. A barrier metal layer 522, 622, 722 covers the reflective metal layer 521, 621, 721 to prevent the migration of metal elements in the reflective metal layer 521, 621, 721 during the conduction process, resulting in electrical abnormalities of the first chip 5, the second chip 6 and the third chip 7. A metal connection layer 523, 623, 723 covers the barrier metal layer 522, 622, 722 to connect to the first pad 82, the second pad 83 and the third pad 84. The reflective metal layers 521, 621, 721 include a metal having a reflectivity greater than 80% for the first light, the second light, and the third light, such as aluminum (Al) or silver (Ag). The barrier metal layers 522, 622, 722 include titanium (Ti), platinum (Pt), titanium (Ti), platinum (Pt) or a stack thereof. The metal connection layers 523, 623, 723 include gold (Au).

[0196] In one embodiment, Figure 5AThe schematic diagram of the structure of the first chip 5, the second chip 6 and the third chip 7 is shown. The first upper semiconductor layer 531, the second upper semiconductor layer 631 and the third upper semiconductor layer 731 include n-type semiconductor layers, the first lower semiconductor layer 532, the second lower semiconductor layer 632 and the third lower semiconductor layer 732 include p-type semiconductor layers, the upper electrode 51, the upper electrode 61 and the upper electrode 71 include a light-transmitting conductive layer 511, 611, 711 covering the upper semiconductor layer 531, 631, 731 including the n-type semiconductor layer, and a current channel layer 512, 612, 712 is located between the upper semiconductor layer 531, 631, 731 and the light-transmitting conductive layer 511, 611, 711. In one embodiment, the light-transmitting conductive layer 511, 611, 711 includes indium tin oxide (ITO). The high resistance between indium tin oxide (ITO) and the n-type semiconductor layer is not conducive to the flow of current. The current channel layer 512, 612, 712 can guide the current from the light-transmitting conductive layer 511, 611, 711 to the upper semiconductor layer 531, 631, 731 including the n-type semiconductor layer. If the upper semiconductor layer 531, 631, 731 includes an n-type semiconductor layer of the gallium nitride (GaN) series, the material of the current channel layer 512, 612, 712 includes titanium nitride (TiN x ); if the upper semiconductor layer 531, 631, 731 comprises an n-type semiconductor layer of aluminum gallium indium phosphide (AlGaInP) series, the material of the current channel layer 512, 612, 712 comprises germanium gold (GeAu). Figure 5B A top view showing the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7. In one embodiment, the current channel layer 512, 612, 712 is dot-shaped and is substantially located at the center of the surface of the upper semiconductor layer 531, 631, 731. Figure 5A As shown, the dotted lines illustrate the current tracks in the first chip 5, the second chip 6 and the third chip 7. The current channel layers 512, 612, 712 are used to drive the current to flow into the center of the upper semiconductor layer 531, 631, 731, so as to reduce the current flowing through the outer side walls of the first semiconductor stack 53, the second semiconductor stack 63 and the third semiconductor stack 73 and generate excessive non-radiative recombination, thereby reducing the luminous efficiency of the first chip 5, the second chip 6 and the third chip 7.

[0197] like Figure 1As shown, the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 have the same or similar height H1, the dielectric layer 3 surrounds the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 respectively and forms a first common surface 31 with the upper electrode 41 of the common conductive structure 4, the upper electrode 51 of the first chip 5, the upper electrode 61 of the second chip 6 and the upper electrode 71 of the third chip 7, and the dielectric layer 3 forms a second common surface 32 with the lower electrode 42 of the common conductive structure 4, the lower electrode 52 of the first chip 5, the lower electrode 62 of the second chip 6 and the lower electrode 72 of the third chip 7. The transparent carrier 1 covers the first common surface 31, and the surface 11 of the transparent carrier 1 and the first common surface 31 are bonded by the transparent conductive layer 2. The transparent carrier 1 is used to support the structure formed by the dielectric layer 3, the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7.

[0198] The material of the dielectric layer 3 includes epoxy, silicone or photo-imageable dielectric (PID), wherein the photo-imageable dielectric can be formed into a thin film by spin coating, and then processed into different shapes by a patterning process of photomask plus UV light irradiation. The photo-imageable dielectric can be cured at low temperature and has excellent metal adhesion and electrical insulation. In one embodiment, the dielectric layer 3 includes a dark material, such as carbon black, so that the transmittance of the dielectric layer 3 for the first light, the second light and the third light is less than 50%, avoiding optical crosstalk between the first chip 5, the second chip 6 and the third chip 7, and shielding the common pad 81, the first pad 82, the second pad 83 and the third pad 84, so as to increase the contrast of the display device 900A.

[0199] The transparent substrate 1 comprises epoxy, silicone, glass, sapphire substrate or ceramic substrate, and has a thickness between 10 μm and 1000 μm, and has a transmittance of more than 80% for visible light with a dominant wavelength or a peak wavelength between 440 nm and 660 nm. The material of the transparent conductive layer 2 comprises indium tin oxide (ITO), and has a transmittance of more than 80% for visible light with a dominant wavelength or a peak wavelength between 440 nm and 660 nm. The transparent conductive layer 2 is in direct contact with the upper electrode 41, the upper electrode 51, the upper electrode 61 and the upper electrode 71, and electrically connects the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 together. The common pad 81, the first pad 82, the second pad 83 and the third pad 84 are respectively connected to the lower electrode 42, the lower electrode 52, the lower electrode 62 and the lower electrode 72 to receive current to drive the first chip 5, the second chip 6 and the third chip 7 to emit light. The material of the common pad 81, the first pad 82, the second pad 83 and the third pad 84 includes metal, such as copper, tin, aluminum, silver, palladium, gold or a stack thereof.

[0200] Figure 6 A cross-sectional view of a pixel structure 200 according to an embodiment is shown. The pixel structure 200 may be Figure 2 The pixel 91 of the display device 900A is shown. The pixel structure 200 has a first chip 5', the first chip 5' has a light-emitting area 5A connected to the first pad 82, a conductive area 5B connected to the common pad 81, and an insulating layer 54 partially isolates the light-emitting area 5A and the conductive area 5B from each other, wherein the insulating layer 54 can be formed in the process of manufacturing the first chip 5'. In another embodiment, the insulating layer 54 can be formed in the process of forming the dielectric layer 3. The light-emitting area 5A acts as the first chip 5 of the pixel structure 100 to emit the first light, and the conductive area 5B acts as the common conductive structure 4 of the pixel structure 100 to conduct current between the light-transmitting conductive layer 2 and the common pad 81 without emitting light. In one embodiment, the light-emitting area 5A and the conductive area 5B share an upper electrode 51', and the light-emitting area 5A has a lower electrode 52A and a light-emitting stacked area 53A located between the upper electrode 51' and the lower electrode 52A. The light emitting stacked region 53A has a first upper semiconductor layer 531 ′ connected to the upper electrode 51 ′, a first lower semiconductor layer 532A connected to the lower electrode 52A, and a first light emitting layer 533A located between the first upper semiconductor layer 531 ′ and the first lower semiconductor layer 532A.

[0201] like Figure 6As shown, the conductive region 5B has a lower electrode 52B, a conductive stack region 53B located between the upper electrode 51' and the lower electrode 52B, and a conductive portion 44' located in the conductive stack region 53B and penetrating the conductive stack region 53B and connected to the upper electrode 51' and the lower electrode 52B. The conductive stack region 53B and the light-emitting stack region 53A share a first upper semiconductor layer 531'. The conductive stack region 53B also has a first lower semiconductor layer 532B connected to the lower electrode 52B, and a multi-layer quantum well structure 533B located between the first upper semiconductor layer 531' and the first lower semiconductor layer 532B. The insulating layer 54 separates the light-emitting stack region 53A from the conductive stack region 53B and separates the lower electrode 52A from the lower electrode 52B. When current flows from the common pad 81 into the conductive stack region 53B, the current flows into the light-transmitting conductive layer 2 through the lower electrode 52B, the conductive portion 44' and the upper electrode 51'. The current then flows through the transparent conductive layer 2 into the light-emitting stack area 53A, the second chip 6 and the third chip 7 to emit the first light, the second light and the third light, wherein the intensity of the first light, the second light and the third light is determined by the current size input into the light-emitting stack area 53A, the second chip 6 and the third chip 7 from the first pad 82, the second pad 83 and the third pad 84 of the external circuit (not shown).

[0202] like Figure 6 As shown, the material and structure of the upper electrode 51' of the pixel structure 200 can refer to the aforementioned paragraphs and drawings related to the upper electrode 51 of the pixel structure 100. The material and structure of the light-emitting stack region 53A and the conductive stack region 53B can refer to the aforementioned paragraphs and drawings related to the first semiconductor stack 53 of the pixel structure 100. In the pixel structure 200, the material and structure of the first light-emitting layer 533A and the multi-layer quantum well structure 533B can refer to the aforementioned paragraphs and drawings related to the first light-emitting layer 533 of the pixel structure 100. The material and structure of the first lower semiconductor layer 532A and the first lower semiconductor layer 532B can refer to the aforementioned paragraphs and drawings related to the first lower semiconductor layer 532 of the pixel structure 100. The material and structure of the lower electrode 52A and the lower electrode 52B can refer to the aforementioned paragraphs and drawings related to the lower electrode 52 of the pixel structure 100. In one embodiment, the conductive region 5B has a through hole 55 penetrating the conductive stacking region 53B, and the conductive portion 44' is disposed in the through hole 55 (the conductive portion 44' may completely or partially fill the through hole 55) and is in direct contact with the semiconductor stacking layer of the conductive stacking region 53B. The material and structure of the conductive portion 44' may refer to the aforementioned paragraphs and drawings related to the conductive portion 44 of the pixel structure 100. In another embodiment, the conductive region 5B has an insulating layer (not shown) disposed in the through hole 55 to isolate the conductive portion 44' from the semiconductor stacking layer of the conductive stacking region 53B.

[0203] Figures 7 to 11 A manufacturing flow chart of the pixel structure 100 according to an embodiment is shown. Figure 7 As shown, a plurality of common conductive structures 4, a plurality of first chips 5, a plurality of second chips 6 and a plurality of third chips 7 are provided on temporary carriers 400, 500, 600 and 700 respectively. The common conductive structure 4 has a height H4, the first chip 5 has a height H5, the second chip 6 has a height H6, and the third chip 7 has a height H7. The structure of the temporary carriers 400, 500, 600 and 700 includes a substrate and an adhesive layer (not shown). The substrate includes a sapphire substrate, a glass substrate and a silicon substrate. The adhesive layer includes BCB (Benzocyclobutene), UV glue, thermal dissociation glue, epoxy resin or silicone resin, which is used to temporarily fix the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7.

[0204] like Figure 8 As shown, a portion of the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 are sequentially transferred from the temporary carriers 400, 500, 600 and 700 and temporarily fixed to another temporary carrier 1A, and then Figure 1The positions of the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 in the display pixel structure 100 are arranged. The common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 are all with the lower electrodes 42, 52, 62, 72 facing the temporary carrier 1A, and are temporarily fixed on the temporary carrier 1A with an adhesive layer 1B, such as BCB (Benzocyclobutene), UV glue, thermal dissociation glue, epoxy resin (Epoxy) or silicone resin (Silicone). Then, a dielectric material is covered on the temporary carrier 1A to form a dielectric layer 3'. The material of the dielectric layer 3' can refer to the aforementioned paragraph related to the dielectric layer 3. The formation method of the dielectric layer 3' includes a high temperature lamination process, a patterning process or a molding process (Molding). The dielectric layer 3' surrounds and exposes the upper electrodes 41, 51, 61, 71 of the common conductive structure 4, the first chip 5, the second chip 6, and the third chip 7. The upper surface of the dielectric layer 3' forms a first common surface 31 with the upper electrodes 41, 51, 61, 71, and the lower surface of the dielectric layer 3' forms a flat second common surface 32 with the lower electrodes 42, 52, 62, 72. In one embodiment, the common conductive structure 4, the first chip 5, the second chip 6, and the third chip 7 have the same height H4, H5, H6, and H7, and have flat upper electrodes 41, 51, 61, and 71, so the first common surface 31 is a flat surface. In another embodiment, the heights H4, H5, H6, and H7 of the common conductive structure 4, the first chip 5, the second chip 6, and the third chip 7 are partially or completely different, so the first common surface 31 is a concave-convex surface.

[0205] like Fig. 9 As shown, a transparent conductive layer 2' is formed on the first common surface 31 to electrically connect the upper electrodes 41, 51, 61, and 71 together. A transparent carrier 1' is provided on the transparent conductive layer 2' and connected to the first common surface 31 through the transparent conductive layer 2'. The structures and materials of the transparent carrier 1' and the transparent conductive layer 2' can refer to the above-mentioned relevant paragraphs and drawings. In another embodiment, the first common surface 31 is a concave-convex surface, and the transparent conductive layer 2' is conformally formed on the first common surface 31 and also has a concave-convex surface. The transparent carrier 1' is adhered to the transparent conductive layer 2' by a transparent adhesive (not shown), such as BCB (Benzocyclobutene), epoxy resin or silicone resin, or the transparent carrier 1' can be formed on the concave-convex first common surface 31 by a hot pressing process using a thermosetting transparent adhesive film, such as a thermosetting epoxy resin.

[0206] like Fig.10As shown, the adhesive layer 1B is reduced in viscosity by furnace heating, ultraviolet (UV) light irradiation, laser beam irradiation (e.g., ultraviolet (UV) laser beam with a wavelength between 315nm and 400nm or infrared (IR) laser beam with a wavelength between 1000nm and 1100nm) and the like to remove the temporary carrier 1A and expose the second common surface 32.

[0207] like Fig.11 A common pad 81, a first pad 82, a second pad 83 and a third pad 84 are formed on the second common surface 32 to respectively connect the bottom electrodes 42, 52, 62 and 72. Finally, a plurality of pixel structures 100 are formed along the dotted line 99 by a cutting process.

[0208] Fig.12 A cross-sectional view of a pixel structure 100 ′ according to an embodiment is shown. Fig.10 In the steps shown, a circuit redistribution layer 8 is first formed on the second common surface 32. A common pad 81, a first pad 82, a second pad 83 and a third pad 84 are then formed on the circuit redistribution layer 8 and are respectively electrically connected to the bottom electrodes 42, 52, 62 and 72. Finally, a plurality of pixel structures 100' are formed along the dotted line 99 by a cutting process.

[0209] Fig.13 A top view of a pixel structure 100 ′ according to an embodiment is shown. Fig.14 A bottom view of a pixel structure 100' according to an embodiment is shown. Fig.13 As shown, the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 of the pixel structure 100' are arranged in a straight line. Fig.14 As shown, the common pad 81, the first pad 82, the second pad 83 and the third pad 84 of the pixel structure 100' are arranged in an array. Since the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 are arranged in a straight line, the lower electrodes 42, 52, 62 and 72 are also arranged in a straight line. In other words, the arrangement of the common pad 81, the first pad 82, the second pad 83 and the third pad 84 is different from the arrangement of the lower electrodes 42, 52, 62 and 72.

[0210] Figures 15 to 18 A manufacturing flow chart of the pixel structure 100 according to an embodiment is shown. Fig.15 As shown, from Figure 7 On the temporary carriers 400, 500, 600, 700 shown in FIG. 1 , a portion of the common conductive structure 4, the first chip 5, the second chip 6, and the third chip 7 are sequentially transferred and temporarily fixed to the temporary carrier 1A, and then Figure 1The positions of the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 in the display pixel structure 100 are arranged. The common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7 are all with the upper electrodes 41, 51, 61, 71 facing the temporary carrier 1A, and are temporarily fixed on the temporary carrier 1A by an adhesive layer 1B. The adhesive layer 1B includes BCB (Benzocyclobutene), UV glue, thermal dissociation glue, epoxy resin or silicone resin. Then, a dielectric material is disposed on the temporary carrier 1A to form a dielectric layer 3'. The dielectric layer 3' surrounds and exposes the lower electrodes 42, 52, 62, 72 of the common conductive structure 4, the first chip 5, the second chip 6 and the third chip 7. The upper surfaces of the dielectric layer 3' and the lower electrodes 42, 52, 62, 72 form a second common surface 32 together, and the lower surfaces of the dielectric layer 3' and the upper electrodes 41, 51, 61, 71 form a flat first common surface 31 together. In one embodiment, the heights H4, H5, H6, and H7 of the common conductive structure 4, the first chip 5, the second chip 6, and the third chip 7 are substantially the same, and have flat upper electrodes 41, 51, 61, and 71, so the second common surface 32 is a flat surface. In another embodiment, since the heights H4, H5, H6, and H7 of the common conductive structure 4, the first chip 5, the second chip 6, and the third chip 7 are partially or completely different, the second common surface 32 is a concave-convex surface.

[0211] Fig.16 The steps of making the pads 81 to 84 are shown. If the second common surface 32 is a flat surface, a common pad 81, a first pad 82, a second pad 83 and a third pad 84 are formed on the second common surface 32 to connect the lower electrodes 42, 52, 62 and 72 respectively. Fig.17 As shown, the temporary carrier 1A is removed to expose the flat first common surface 31. Fig.18 As shown, a transparent conductive layer 2' is formed on the first common surface 31 to electrically connect the upper electrodes 41, 51, 61, and 71. A transparent carrier 1' is disposed under the transparent conductive layer 2' and connected to the first common surface 31 through the transparent conductive layer 2'. Finally, a plurality of pixel structures 100 separated from each other are formed by a cutting process along the dotted line 99.

[0212] Figures 19 to 21 A flowchart of manufacturing the pixel structure 100 ′ according to an embodiment is shown. Fig.15 In the structure shown in FIG. 1 , if the second common surface 32 is a concave-convex surface, as shown in FIG. Fig.19As shown, a circuit redistribution layer 8 is first formed on the second common surface 32. A common pad 81, a first pad 82, a second pad 83, and a third pad 84 are then formed on the circuit redistribution layer 8, and are electrically connected to the lower electrodes 42, 52, 62, and 72 through the circuit redistribution layer 8. The distribution pattern of the common pad 81, the first pad 82, the second pad 83, and the third pad 84 can be the same as or different from the distribution pattern of the lower electrodes 42, 52, 62, and 72. Fig.19 As shown, the lower surface 8A of the circuit redistribution layer 8 can conformally fit with the concave-convex second common surface 32, while the upper surface 8B located on the opposite side can be a flat or concave-convex surface. The common pad 81, the first pad 82, the second pad 83 and the third pad 84 (not shown) are formed on the upper surface 8B of the circuit redistribution layer 8. Fig. 20 As shown, the temporary carrier 1A is removed to expose the first common surface 31. Fig.21 As shown, a transparent conductive layer 2' is formed on the first common surface 31 to electrically connect the upper electrodes 41, 51, 61, and 71. A transparent carrier 1' is then disposed under the transparent conductive layer 2' and connected to the first common surface 31 through the transparent conductive layer 2'. Finally, a plurality of pixel structures 100' separated from each other are formed by a cutting process along the dotted line 99.

[0213] Fig.22A A cross-sectional view of a chip 9A according to an embodiment is shown. The description of the chip 9A can be referred to Figure 4 and Figure 5A and the description of the first chip 5 , the second chip 6 and the third chip 7 in the relevant paragraphs. The chip 9A has a semiconductor stack 93 , an upper electrode 97 located on the semiconductor stack 93 , and a lower electrode 92 located below the semiconductor stack 93 . Fig. 22B show Fig.22A Magnified view of the middle G region.

[0214] The semiconductor stack 93 includes an upper semiconductor layer 931, a lower semiconductor layer 932, and a multiple quantum well structure (MQW) 933 located between the upper semiconductor layer 931 and the lower semiconductor layer 932 for emitting light, wherein the material of the upper semiconductor layer 931 can refer to the aforementioned paragraphs related to the first upper semiconductor layer 531, the second upper semiconductor layer 631, and the third upper semiconductor layer 731, and the material of the lower semiconductor layer 932 can refer to the aforementioned paragraphs related to the first lower semiconductor layer 532, the second lower semiconductor layer 632, and the third lower semiconductor layer 732. The chip 9A has an upper surface 9311S2, a lower surface 932S opposite to the upper surface 9311S2, and a plurality of side surfaces 93S, each of which is located between the upper surface 9311S2 and the lower surface 932S. The light emitted by the multi-layer quantum well structure 933 can be emitted from the upper surface 9311S2. The upper surface 9311S2 is a rough surface to increase the light extraction efficiency (Light Extraction Efficiency) of the chip 9A. In one embodiment, the upper surface 9311S2 can be a regular / irregular rough surface, and the average roughness (Average Roughness; Ra) of the upper surface 9311S2 is between 0.1μm and 1μm. The lower surface 932S is a flat surface, and the average roughness of the lower surface 932S is less than that of the upper surface 9311S2. Each side surface 93S has an upper side surface 93S1 connected to the upper surface 9311S2, a lower side surface 93S2 connected to the lower surface 932S, and a middle side surface 9311S1. The middle side surface 9311S1 is located between the upper side surface 93S1 and the lower side surface 93S2 and connects the upper side surface 93S1 and the lower side surface 93S2. Fig. 22B The upper surface 93S1 and the middle surface 9311S1 have an angle θ1, and the lower surface 93S2 and the middle surface 9311S1 have an angle θ2. In one embodiment, the angle θ1 is an acute angle and the angle θ2 is an obtuse angle, the angle θ1 is between 35 degrees and 85 degrees, and the angle θ2 is between 95 degrees and 145 degrees. Fig.22AIn the cross-sectional structure diagram of the chip 9A shown, the dotted line AA' passes through and is parallel to the middle side surface 9311S1. In one embodiment, the dotted line AA' divides the upper semiconductor layer 931 into a first upper semiconductor layer 9311 and a second upper semiconductor layer 9312, wherein the first upper semiconductor layer 9311 has an upper surface 9311S2, an upper side surface 93S1, and a middle side surface 9311S1, and the second upper semiconductor layer 9312 is located between the first upper semiconductor layer 9311 and the multi-layer quantum well structure 933 and is connected to the multi-layer quantum well structure 933, wherein the maximum width of the first upper semiconductor layer 9311 is greater than the maximum width of the second upper semiconductor layer 9312, and the middle side surface 9311S1 of the first upper semiconductor layer 9311 is connected to the second upper semiconductor layer 9312.

[0215] like Fig.22A As shown, in one embodiment, the material and structure of the upper electrode 97 can refer to the aforementioned paragraphs related to the upper electrode 51, the upper electrode 61 and the upper electrode 71, and the material and structure of the lower electrode 92 can refer to the aforementioned paragraphs related to the lower electrode 52, the lower electrode 62 and the lower electrode 72. The upper electrode 97 conformally covers the upper surface 9311S2, and the lower electrode 92 covers a portion of the lower surface 932S. In one embodiment, the chip 9A further includes an ohmic contact layer 921 located between the lower semiconductor layer 932 and the lower electrode 92 to reduce the contact resistance between the lower semiconductor layer 932 and the lower electrode 92. The ohmic contact layer 921 includes a semiconductor material, such as gallium arsenide (GaAs), or an oxide conductive material, such as indium tin oxide (ITO).

[0216] like Fig.22A As shown, in one embodiment, the chip 9A selectively further includes an insulating protection layer 96 to cover the middle side surface 9311S1, the lower side surface 93S2, and a portion of the lower surface 932S not covered by the lower electrode 92. The insulating protection layer 96 includes a dielectric material, such as silicon oxide (SiOx) or silicon nitride (SiNx), and the thickness of the insulating protection layer 96 is between 1nm and 100nm and is thinner than the lower electrode 92.

[0217] like Fig.22A As shown, in one embodiment, the chip 9A optionally further includes an electrical connection portion 95 to cover the lower electrode 92 and connect to an external circuit (not shown). In one embodiment, the electrical connection portion 95 has an arc surface and a maximum thickness, and the maximum thickness is greater than the thickness of the lower electrode 92. The material of the electrical connection portion 95 includes metal, such as tin, silver or gold.

[0218] Fig.23A cross-sectional view of a chip 9B according to an embodiment is shown. The chip 9B includes a metal electrode 97B formed on a portion of the upper electrode 97. The metal electrode 97B can conduct current into the upper electrode 97. When the chip 9B is used as the first chip 5, the second chip 6 or the third chip 7 in the pixel structure 100, the metal electrode 97B will be in direct contact with the light-transmitting conductive layer 2 of the pixel structure 100 to reduce the resistance between the upper electrode 97 of the chip 9B and the light-transmitting conductive layer 2 of the pixel structure 100. The material of the metal electrode 97B includes titanium, germanium or gold. In one embodiment, in a top view, the shape of the metal electrode 97B is circular or square and is substantially located at the center of the upper surface 9311S2 of the upper semiconductor layer 931.

[0219] Fig.24 The cross-sectional view of the arrangement structure A in which the display chip 9A is temporarily disposed on a temporary carrier 800, wherein the description of the chip 9A can refer to Figure 7 The first chip 5, the second chip 6 or the third chip 7 and the related paragraphs are shown. In one embodiment, in the direction of the X-axis, the width W1C of the adhesive layer 1C is equal to or less than the maximum width W9A of the chip 9A. The temporary carrier 800 includes a sapphire substrate (Sapphire), a glass substrate and a silicon substrate. The adhesive layer 1C includes BCB (Benzocyclobutene) or epoxy resin (Epoxy). In the subsequent manufacturing process, a laser beam can be used to irradiate the adhesive layer 1C to reduce the viscosity of the adhesive layer 1C or remove the adhesive layer 1C to separate the chip 9A from the temporary carrier 800. The laser beam includes an ultraviolet (UV) laser beam with a wavelength between 200nm and 400nm or an infrared (IR) laser beam with a wavelength between 1000nm and 1100nm.

[0220] Fig.25 A cross-sectional view of an arrangement structure B showing a chip 9A according to another embodiment temporarily disposed on a temporary carrier 800' with a double adhesive layer structure 1CD. The arrangement structure B includes an adhesive layer 1D located between the adhesive layer 1C and the temporary carrier 800', wherein the adhesive layer 1C and the adhesive layer 1D are collectively referred to as a double adhesive layer structure 1CD. The adhesive layer 1C and the adhesive layer 1D include different adhesive materials, and the laser beam energy required to reduce the viscosity of the adhesive layer 1D or remove the adhesive layer 1D is less than the laser beam energy required to reduce the viscosity of the adhesive layer 1C or remove the adhesive layer 1C. In one embodiment, the laser beam energy required to reduce the viscosity of the adhesive layer 1D or remove the adhesive layer 1D is between 50 mJ / cm 2 ~200mJ / cm 2 The laser beam energy required to reduce the viscosity of the adhesive layer 1C or remove the adhesive layer 1C is between 200 mJ / cm 2 ~1000mJ / cm 2 Therefore, compared with Fig.24 In the arrangement structure shown, when the laser beam irradiates the adhesive layer 1D, the chip 9A is more easily separated from the temporary carrier 800'. In one embodiment, the adhesive layer 1C includes epoxy resin (Epoxy), and the adhesive layer 1D includes polyimide (Polyimide; PI). The absorption rate of polyimide to lasers with a wavelength between 200nm and 250nm is higher than that of epoxy resin (Epoxy). To dissociate polyimide, the laser must destroy the carbon-nitrogen (CN) bond, and to dissociate epoxy resin, the carbon-carbon (CC) and carbon-oxygen (CO) bonds must be destroyed. The carbon-nitrogen (CN) bond energy (Bond Energy) of polyimide is 3.17eV, and the carbon-carbon (CC) and carbon-oxygen (CO) bond energies of epoxy resin are 3.60eV and 3.71eV respectively. Compared with epoxy resin, polyimide has a higher absorption rate for lasers with a wavelength between 200nm and 250nm and is easier to be dissociated. Therefore, the adhesive layer 1D is easier to reduce the viscosity or be removed by the laser with a wavelength between 200nm and 250nm than the adhesive layer 1C. In one embodiment, the thickness of the adhesive layer 1C is greater than the thickness of the adhesive layer 1D, the thickness of the adhesive layer 1C is between 2μm and 20μm, and the thickness of the adhesive layer 1D is between 0.1μm and 2μm.

[0221] Figure 26 to Figure 29 A manufacturing flow chart of an arrangement structure B according to an embodiment is shown. Fig.26 According to one embodiment, a step S100 of transferring a plurality of chips 9A from a temporary carrier 800 to a supporting substrate 1000 is disclosed. Fig.26 As shown, in step S100, a plurality of chips 9A are firstly arranged on a temporary carrier 800 with an adhesive layer 1C, and the plurality of chips 9A are separated from each other and fixed on the temporary carrier 800. The description of the arrangement structure B can be referred to in Fig.24Arrangement structure A and related paragraphs are shown. The chip 9A includes a front side 9Aa and a back side 9Ab, the front side 9Aa faces away from the temporary carrier 800, and the back side 9Ab faces the temporary carrier 800. The chip 9A includes an electrical connection portion 95 located on the back side 9Ab and facing the temporary carrier 800, and the adhesive layer 1C is located between the back side 9Ab of the chip 9A and the temporary carrier 800, for fixing the chip 9A on the temporary carrier 800. The supporting substrate 1000 has an adhesive layer 1000G facing and adhering to the front side 9Aa of multiple chips 9A. The supporting substrate 1000 includes a thermal release tape, a UV release tape, a chemical release tape, a heat-resistant tape, a blue tape, or a tape with a dynamic release layer (DRL). According to another embodiment, the chip 9A can be Fig.23 The chip 9B shown is replaced, and at this time, the adhesive layer 1000G of the supporting substrate 1000 adheres to the metal electrode 97B of the chip 9B. Then, using the laser stripping technique, a laser is irradiated to the junction between the temporary carrier 800 and the adhesive layer 1C to reduce the viscosity of the adhesive layer 1C or remove part of the adhesive layer 1C, so as to strip the temporary carrier 800 and expose the adhesive layer 1C.

[0222] Then, if Fig. 27 The step S102 shown provides a temporary carrier 800' and a continuously distributed adhesive layer 1D'. The adhesive layer 1D' is disposed on the temporary carrier 800' and has a uniform thickness between 0.05μm and 5μm. In one embodiment, the adhesive layer 1D' includes a polymer having a glass transition temperature Tg, for example, between 100 and 110°C, and the polymer is in a semi-cured state. According to one embodiment, the polymer includes polyimide (PI). According to one embodiment, the manufacturing method of the adhesive layer 1D' includes spin coating to coat a liquid material on the temporary carrier 800', and then baking at a temperature T0 between 160 and 200°C to form an adhesive layer 1D' that is non-flowable and has a cross-linked structure. At this time, the adhesive layer 1D' does not have any adhesion or only has a little adhesion, for example, with an area of ​​3×3mm 2The planar metal contacts the adhesive layer 1D', and the force required to separate the planar metal and the adhesive layer 1D' by pulling is less than 1 gram. According to one embodiment, the adhesive layer 1D' can be formed on the temporary carrier 800' by dip coating, screen printing, doctor blade coating, etc. Then, the adhesive layer 1D' is heated at a first temperature T1, such as 110-130°C, and the supporting substrate 1000 is moved so that the adhesive layer 1C on the chip 9A contacts the adhesive layer 1D' on the temporary carrier 800', wherein, if the adhesive layer 1D' has a glass transition temperature Tg, the relationship between the first temperature T1 and the glass transition temperature Tg of the adhesive layer 1D' satisfies formula (1):

[0223] 0<(T1-Tg) / Tg≤70%……(1)

[0224] Wherein, T1 represents the first temperature, and Tg represents the glass transition temperature.

[0225] By applying the first temperature T1 conforming to the above formula (1) to the adhesive layer 1D', the cross-linked and cured adhesive layer 1D' can be softened and have a greater adhesion to the adhesive layer 1C on the chip 9A. For example, after the adhesive layer 1D' is heated at the first temperature T1, the adhesive layer 1C with an area of ​​3×3 mm 2 The flat metal is in contact with the adhesive layer 1D', and when the adhesive layer 1D' is cooled to room temperature (25°C), the force used to separate the metal plane and the adhesive layer 1D' is greater than 500 grams. That is to say, before the adhesive layer 1D' is heated at the first temperature T1, the adhesive layer 1D' may not have any adhesion or only have a little adhesion, but when the adhesive layer 1D' is heated at the first temperature T1, the adhesion of the adhesive layer 1D' can be improved. At this time, when the adhesive layer 1C on the chip 9A contacts the adhesive layer 1D', the chip 9A can be properly fixed to the adhesive layer 1D' and will not fall off easily. At this time, a part of the adhesive layer 1C on the chip 9A is buried in the adhesive layer 1D'. After the chip 9A is adhered to the adhesive layer 1D', the first temperature T1 can be stopped from being applied to the adhesive layer 1D', and the temperature of the adhesive layer 1D' can be reduced back to a predetermined temperature, such as room temperature. When the temperature drops back to room temperature, there is still adhesion between the adhesive layer 1C and the adhesive layer 1D′ on the chip 9A, so the chip 9A can still adhere to the adhesive layer 1D′.

[0226] then, Fig.28 In step S104 , the support substrate 1000 is peeled off by heating, UV irradiation, laser lift-off process or external force to expose the front side 9Aa of the chip 9A.

[0227] then, Fig.29In step S106, an etching process such as inductively coupled plasma (ICP) etching is performed along the -Y direction from the front side 9Aa of the chip 9A to etch the adhesive layer 1D' not shielded by the chip 9A to expose the surface 800S of the temporary carrier 800', thereby forming an adhesive layer 1D with a discrete distribution (discontinuous).

[0228] Through implementation Figure 26 to Figure 29 In the steps S100 to S106, the plurality of chips 9A are transferred from the temporary carrier 800 to the temporary carrier 800'. The plurality of chips 9A are located on the temporary carrier 800' and are separated from each other. Fig.25 The arrangement structure B is shown fixed on the temporary carrier 800 ′. According to one embodiment, the arrangement layout of the chips 9A on the temporary carrier 800 ′ is similar or identical to the arrangement layout of the chips 9A on the temporary carrier 800 .

[0229] Fig.30 A cross-sectional view of an arrangement structure C showing a flip chip 9D fixed on a temporary carrier 800' according to an embodiment. The method of fixing the flip chip 9D on the temporary carrier 800' can be referred to Fig.25 The double adhesive layer structure 1CD is shown, wherein the flip chip 9D has a first electrical connection portion 95-1 and a second electrical connection portion 95-2 located on the back side 9Db and facing the temporary carrier 800', and the adhesive layer 1C is disposed on the back side 9Db of the flip chip 9D and covers the first electrical connection portion 95-1 and the second electrical connection portion 95-2, wherein the structure and material of the first electrical connection portion 95-1 and the second electrical connection portion 95-2 can be referred to Figure 22A to Figure 22B The disclosure of the electrical connection portion 95 of the chip 9A in the related paragraphs. The adhesive layers 1C and 1D can be found in Fig.25 The disclosure about the adhesive layers 1C and 1D in the relevant paragraphs, wherein the flip chip 9D has a maximum width W9D greater than or equal to a maximum width W1C of the adhesive layers 1C and 1D.

[0230] Fig.31 Steps S200 to S208 of forming an array structure C according to an embodiment are shown. Step S200 shows that a plurality of flip-chips 9D are temporarily fixed on a surface 800AS of a temporary carrier 800A, and an adhesive layer 1C' is formed on the surface 80AS of the temporary carrier 800A by coating or spin coating and covers the plurality of flip-chips 9D. For the characteristics of the adhesive layer 1C', please refer to Fig.24and related paragraphs. The first electrical connection portion 95-1 and the second electrical connection portion 95-2 are located on the back side 9Db, and the flip chip 9D contacts the temporary carrier 800A with the front side 9Da and is fixed on the temporary carrier 800A. According to one embodiment, the temporary carrier 800A is a growth substrate that can be used for epitaxial growth, and the flip chip 9D is formed on the growth substrate. The material of the growth substrate includes but is not limited to silicon (Si), germanium (Ge), lithium aluminate (LiAlO2), zinc oxide (ZnO), silicon carbide (SiC), sapphire (Sapphire), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium phosphide (InP). According to another embodiment, the temporary carrier 800A includes a non-epitaxial material or a non-growth substrate. When the temporary carrier 800A includes non-epitaxial material or non-growth substrate, there is a connecting layer (not shown) between the front side 9Da of the flip-chip 9D and the surface 800AS of the temporary carrier 800A. The material of the connecting layer is, for example, a polymer. The connecting layer is used to temporarily fix the flip-chip 9D to the temporary carrier 800A.

[0231] Next, step S202 is performed to provide a temporary carrier 800' and an adhesive layer 1D' continuously distributed on the surface 800S of the temporary carrier 800'. The manufacturing process and structure of the temporary carrier 800' and the adhesive layer 1D' can be referred to. Fig. 27 The disclosure of the temporary carrier 800' and the adhesive layer 1D' in the relevant paragraphs is as follows: The surface 800AS of the temporary carrier 800A faces the surface 800S of the temporary carrier 800', and the adhesive layer 1D' faces the adhesive layer 1C'.

[0232] Next, as shown in step S204, the adhesive layer 1C' contacts the adhesive layer 1D', and the temporary carrier 800' and the temporary carrier 800A are bonded to each other through the adhesive layer 1C' and the adhesive layer 1D'. The bonding process is described in detail in Fig. 27 And the related paragraphs disclose the bonding process of the adhesive layer 1C and the adhesive layer 1D'.

[0233] Next, as shown in step S206, when the temporary carrier 800A is a growth substrate, the temporary carrier 800A can be separated from the flip chip 9D and the adhesive layer 1C' by laser stripping. When the temporary carrier 800A is a non-growth substrate, for example, a heat-resistant tape, a blue film or other adhesive film, the temporary carrier 800A can be stripped by heating, UV irradiation, laser stripping or direct external force to expose the front side 9Da of the flip chip 9D and the adhesive layer 1C'.

[0234] Next, as shown in step S208, an etching process is performed along the -Y direction from the front side 9Da of the flip chip 9D, such as inductively coupled plasma (ICP) etching, to etch the adhesive layer 1C' and the adhesive layer 1D' not shielded by the flip chip 9D, so as to expose the surface 800S of the temporary carrier 800', thereby forming a discretely distributed double adhesive layer structure 1CD.

[0235] Through implementation Fig.31 In the steps S200 to S208 shown, a plurality of flip chips 9D are transferred from the temporary carrier 800A to the temporary carrier 800'. The plurality of flip chips 9D are located on the temporary carrier 800' and are separated from each other. Each flip chip 9D is fixed on the temporary carrier 800' with a double adhesive layer structure 1CD. According to one embodiment, the arrangement layout of the flip chips 9D on the temporary carrier 800' is similar to or the same as the arrangement layout of the flip chips 9D on the temporary carrier 800A.

[0236] Fig.32A A cross-sectional view of a chip 9C according to an embodiment is shown. The chip 9C and Fig.23 The difference of the chip 9B shown is that the semiconductor stack 93 of the chip 9C has a through hole 93T penetrating the semiconductor stack 93, and a conductive part 98 is filled in the through hole 93T penetrating the semiconductor stack 93 and connecting the metal electrode 97B and the lower electrode 92', wherein the lower electrode 92' has a recessed part 92T covering the lower opening of the through hole 93T and connected to the conductive part 98. In one embodiment, the material of the conductive part 98 is the same as that of the metal electrode 97B and the lower electrode 92'. The structure of the chip 9C can be referred to Figure 1 The common conductive structure 4 is shown. When current flows into the chip 9C, the current flows through the conductive portion 98 with lower resistance and does not flow through the multi-layer quantum well structure 933 with higher resistance, so the chip 9C does not emit light. Fig.32B A cross-sectional view of a chip 9C′ according to an embodiment is shown. The chip 9C′ does not have an electrical connection portion 95. The structure of the chip 9C′ can be referred to Fig.32A and descriptions of the relevant paragraphs.

[0237] FIG. 33A to FIG. 33H A manufacturing flow chart of chip 9B and chip 9C according to an embodiment is shown. Fig.33AIt is shown that a growth substrate 930 is provided with a patterned surface 930S, on which a semiconductor stack 93 is formed by epitaxial growth, and then an ohmic contact layer 921 is formed on the semiconductor stack 93, wherein the semiconductor stack 93 includes an upper semiconductor layer 931, a lower semiconductor layer 932 and a multi-layer quantum well structure 933. The structures and materials of the growth substrate 930, the semiconductor stack 93 and the ohmic contact layer 921 can refer to the above-mentioned relevant paragraphs.

[0238] like Fig.33B As shown, the semiconductor stack 93 and the ohmic contact layer 921 are patterned by etching process to form platforms 93B and 93C and expose the upper semiconductor layer 931, wherein the platforms 93B and 93C have independent lower semiconductor layers 932 and multi-layer quantum well structures 933 respectively. Fig.33B As shown, two adjacent platforms 93C form a V-shaped groove 93V in a cross-sectional view. Then, lower electrodes 92 and 92' are formed on the platforms 93B and 93C respectively, wherein the lower electrode 92' covers the two adjacent platforms 93C and fills the V-shaped groove 93V. The materials and structures of the lower electrodes 92 and 92' can refer to the above-mentioned paragraphs related to the lower electrode 52, the lower electrode 62 and the lower electrode 72. Then, an insulating protection layer 96 is formed to conformally cover the upper semiconductor layer 931 and the platforms 93B and 93C and expose the lower electrodes 92 and 92'.

[0239] like Fig.33C It is shown that an adhesive layer 1E is provided on the platforms 93B and 93C by coating or spin coating, and then a temporary carrier 930A is provided on the adhesive layer 1E. The adhesive layer 1E fixes the temporary carrier 930A on the platforms 93B and 93C. The material of the adhesive layer 1E includes BCB (Benzocyclobutene) or epoxy resin. In another embodiment, the material of the adhesive layer 1E is the same as that of the adhesive layers 1C and 1D. In the subsequent manufacturing process, a laser beam can be used to irradiate the adhesive layer 1E to reduce the viscosity of the adhesive layer 1E or remove the adhesive layer 1E to separate the platforms 93B and 93C from the temporary carrier 930A. Then, using a laser lift-off technique, a laser is irradiated to the junction of the growth substrate 930 and the upper semiconductor layer 931 to remove the growth substrate 930 and expose the upper surface 9311S2 of the upper semiconductor layer 931.

[0240] like Fig.33D As shown, an upper electrode 97 is formed on the upper surface 9311S2 of the upper semiconductor layer 931. The material and structure of the upper electrode 97 can refer to the above paragraphs related to the upper electrode 51, the upper electrode 61 and the upper electrode 71. Fig.33EAs shown, the upper electrode 97, the upper semiconductor layer 931 and the insulating protection layer 96 are patterned by etching to form platforms 931B and 931C and expose the adhesive layer 1E. In addition, a through hole 93T is formed in the platform 931C and penetrates the upper semiconductor layer 931 to expose the lower electrode 92'.

[0241] like Fig.33F As shown, a conductive portion 98 is formed in the through hole 93T of the platform 931C to connect the lower electrode 92', and then a metal electrode 97B is formed on the upper electrode 97 of the platforms 931B and 931C respectively to directly contact the upper electrode 97, wherein on the platform 931C, the metal electrode 97B is connected to the conductive portion 98. In another embodiment, the metal electrode 97B and the conductive portion 98 can be formed in the same step.

[0242] like Figure 33G The adhesive layer 1E between the platforms 931B and 931C is removed. Fig.33F and 33G The adhesive layer 1E and the insulating protective layer 96 not covered by the platforms 931B and 931C are removed to expose the temporary carrier 930A, and the discretely distributed adhesive layer 1E' is formed to adhere and support the chip 9B' and the chip 9C' on the temporary carrier 930A. In one embodiment, the removal method is etching, and the etching is, for example, inductively coupled plasma (ICP) etching.

[0243] like Fig.33H It is shown that a transfer process is used to Figure 33G The chip 9B' and the chip 9C' shown are transferred from the temporary carrier 930A to the temporary carrier 930B, wherein the chip 9B' and the chip 9C' are fixed on the temporary carrier 930B respectively by a plurality of adhesive layers 1F separated laterally from each other. The metal electrodes 97B of the chip 9B' and the chip 9C' face the temporary carrier 930B, and electrical connection parts 95 are formed on the lower electrodes 92 and 92' of the chip 9B' and the chip 9C' respectively. After the above manufacturing process, the chip 9B' and the chip 9C' are renumbered as chip 9B and chip 9C respectively. In one embodiment, the transfer manufacturing process includes forming an adhesive layer 1F to fix the chip 9B' and the chip 9C' on the temporary carrier 930B and removing the adhesive layer 1E', wherein the material and manufacturing process of the adhesive layer 1F can refer to the relevant paragraphs of the aforementioned adhesive layer 1E', and the method of removing the adhesive layer 1E' includes a laser beam. In one embodiment, the materials of the temporary carriers 930A and 930B may refer to the relevant paragraphs of the temporary carrier 800 described above.

[0244] Figure 34A to Figure 34C FIG. 1 is a schematic diagram of a display device 900B according to an embodiment. Fig.34AA top view of the display device 900B is shown. Fig.34B Draw Fig.34A The cross-sectional view along the dotted line BB' is shown in FIG. Fig.34C A top view of a circuit device 90B of a display device 900B is shown. For clarity, Fig.34A The common conductive layer 20, the dielectric layer 3 and part of the common conductive structure 4' are omitted. Fig.34A As shown, the display device 900B has a circuit device 90B, a plurality of first chips 5, a plurality of second chips 6, and a plurality of third chips 7 are arranged in an array on the circuit device 90B, and a plurality of common conductive structures 4' are arranged on the circuit device 90B along the edge of the circuit device 90B, wherein three adjacent first chips 5, second chips 6, and third chips 7 can form a pixel 91'. Fig.34B As shown, the display device 900B has a dielectric layer 3 and a common conductive layer 20, wherein the dielectric layer 3 laterally surrounds the common conductive structure 4', the first chip 5, the second chip 6 and the third chip 7, and the common conductive layer 20 directly or indirectly contacts the common conductive structure 4', the first chip 5, the second chip 6 and the third chip 7, and includes a light-transmitting conductive layer or a light-transmitting carrier with a metal grid (not shown). The material and structure of the light-transmitting conductive layer can refer to the above paragraphs related to the light-transmitting conductive layer 2. Fig.34C As shown, the circuit device 90B has a plurality of common electrodes 90B1 disposed along the edge of the circuit device 90B and a plurality of lower electrodes 90B2 arranged in an array on the circuit device 90B. Fig.34BAs shown, a plurality of common conductive structures 4' are disposed on a common electrode 90B1 and are electrically connected to the common electrode 90B1, and a plurality of first chips 5, a plurality of second chips 6, and a plurality of third chips 7 are respectively disposed on a plurality of lower electrodes 90B2 and are electrically connected to the plurality of lower electrodes 90B2. In one embodiment, the circuit device 90B may be a printed circuit board (PCB), a glass circuit board, a pixel driver chip (Driver IC), or a metal oxide semiconductor (CMOS) circuit element, and the structures of the first chip 5, the second chip, and the third chip 7 may be a chip 9A or a chip 9B, and the structure of the common conductive structure 4' may be a chip 9C or a chip 9C'. In one embodiment, the common conductive structure 4' is located between the common conductive layer 20 and the common electrode 90B1 and is connected to the common conductive layer 20 and the common electrode 90B1, so as to conduct current between the common conductive layer 20 and the common electrode 90B1. The first chip 5 is located between the common conductive layer 20 and the lower electrode 90B2 and is electrically connected to the common conductive layer 20 and the lower electrode 90B2. The second chip 6 is located between the common conductive layer 20 and the lower electrode 90B2 and is electrically connected to the common conductive layer 20 and the lower electrode 90B2. The third chip 7 is located between the common conductive layer 20 and the lower electrode 90B2 and is electrically connected to the common conductive layer 20 and the lower electrode 90B2. The first chip 5 can be driven to emit a first light, the second chip 6 can be driven to emit a second light, and the third chip 7 can be driven to emit a third light, wherein the first light, the second light and the third light can be visible light of the same or different wavelength ranges, or invisible light of the same wavelength range. Visible light of the same wavelength range is, for example, blue light, visible light of different wavelength ranges is, for example, red, blue and green light, respectively, and invisible light of the same wavelength range is, for example, ultraviolet light. In order to isolate mechanical impact from the outside to improve the reliability of the display device 900B, the dielectric layer 3 laterally surrounds the common conductive structure 4', the first chip 5, the second chip 6 and the third chip 7 and is in direct or indirect contact with the common conductive layer 20 (not shown).

[0245] Fig.35 A cross-sectional view showing a chip 9D temporarily fixed to a temporary carrier 800 by an adhesive layer 1C according to an embodiment, wherein the materials of the adhesive layer 1C and the temporary carrier 800 can be referred to as Fig.24 In another embodiment, the adhesive layer 1C may be replaced by Fig.25 The chip 9D includes a light emitting area 9DA and a conductive area 9DB, wherein the light emitting area 9DA can emit a light. The structure of the chip 9D can refer to Figure 22A to Figure 22B The chip 9A and related sections shown, the conductive area 9DB can conduct electricity but does not emit light, and its structure can be referred to Fig.32A Chip 9C and related paragraphs are shown. Fig.32A In the chip 9C shown in FIG. 1 , the conductive region 9DB does not have the metal electrode 97B. In another embodiment, the structure of the conductive region 9DB may be the same as that of the conductive region 9DB. Fig.32A The same as the chip 9C shown. In one embodiment, the light emitting area 9DA and the conductive area 9DB of the chip 9D share the ohmic contact layer 921, the semiconductor stack 93 and the upper electrode 97. When the current flows through the upper electrode 97 and the lower electrode 92, the chip 9D will emit a light. When the current flows through the upper electrode 97 and the lower electrode 92', the current will pass through the conductive part 98 and the chip 9D will not emit light. In one embodiment, the chip 9D has two electrical connection parts 95 that are electrically connected or directly connected to the lower electrode 92 of the light emitting area 9DA and the lower electrode 92' of the conductive area 9DB. In another embodiment, the chip 9D may not have two electrical connection parts 95 and expose the lower electrodes 92', 92.

[0246] Fig.36 A cross-sectional view of a display device 900C according to an embodiment is shown. The display device 900C can be suitable for small displays with a pixel density (Pixels Per Inch; PPI) higher than 1000, such as displays for augmented reality (Augmented Reality; AR) devices. The display device 900C has a dielectric layer 3A located between the dielectric layer 3 and the circuit device 90B. The dielectric layer 3A contains a black substance, such as carbon black, so that the transmittance of the dielectric layer 3A is less than 20% to cover the metal circuit on the circuit device 90B, thereby increasing the contrast of the display device 900C. The first chip 5" has a light-emitting area 5C and a conductive area 5D. In one embodiment, the structure of the first chip 5" is Fig.35 In the chip 9D shown, the structure of the light-emitting region 5C is the light-emitting region 9DA of the chip 9D, and the structure of the conductive region 5D is the conductive region 9DB of the chip 9D. The conductive region 5D is located between the common conductive layer 20 and the common electrode 90B1 and is connected to the common conductive layer 20 and the first common electrode 90B1, so as to conduct current between the common conductive layer 20 and the common electrode 90B1. The light-emitting region 5C is located between the common conductive layer 20 and the lower electrode 90B2 and is connected to the common conductive layer 20 and the first lower electrode 90B2, so as to emit a light. In one embodiment, the upper electrode 97 of the chip 9D is electrically connected to the common conductive layer 20 (not shown), and the lower electrodes 92' and 92 are respectively connected to the common electrode 90B1 and the lower electrode 90B2 through the electrical connection portion 95. In one embodiment, the circuit device 90B allows a current to flow from the common electrode 90B1, through the conductive area 5D of the chip 9D and into the common conductive layer 20, and selects the current to pass through the light-emitting area 5C, the second chip 6 and / or the third chip 7 through the lower electrode 90B2 of the circuit device 90B, so as to turn on the light-emitting area 5C, the second chip 6 and / or the third chip 7 to emit light.

[0247] Fig.37 A cross-sectional view of a light emitting array device 900D according to an embodiment is shown, which is applicable to a display or light emitting device with a light emitting element density higher than 1000 (pieces / square inch), such as an augmented reality (AR) display, an adaptive driving beam headlamp (ADB Headlamp), or a light emitting module applied to silicon photonics (SiPh). The light-emitting array device 900D includes a circuit device 90B having a plurality of common electrodes 90B1 and a plurality of lower electrodes 90B2, a plurality of light-emitting elements 10 located on the circuit device 90B and electrically connected to the plurality of lower electrodes 90B2, a plurality of common conductive structures 4" located on the circuit device 90B and electrically connected to the plurality of common electrodes 90B1, and a common conductive layer 20A disposed on the plurality of light-emitting elements 10 and the plurality of common conductive structures 4" and electrically connected to the plurality of light-emitting elements 10 and the plurality of common conductive structures 4". According to one embodiment, the common conductive structure 4" is located between the common conductive layer 20A and the common electrode 90B1 and connected to the common conductive layer 20A and the common electrode 90B1 to conduct current between the common conductive layer 20A and the common electrode 90B1. The circuit device 90B can allow a current to flow from the common electrode 90B1 through the common conductive structure 4" into the common conductive layer 20A, and the circuit device 90B can select to allow the current to pass through the light-emitting element 10 through the lower electrode 90B2 to emit light.

[0248] like Fig.37 As shown, each light emitting element 10 includes a semiconductor stack 103 and a lower electrode 102 connected to the semiconductor stack 103, and the lower electrode 102 is electrically connected to the lower electrode 90B2 to introduce current into the light emitting element 10. The semiconductor stack 103 includes an upper semiconductor layer 1031, a lower semiconductor layer 1032 and a light emitting layer 1033. The materials and structures of the semiconductor stack 103, the upper semiconductor layer 1031, the lower semiconductor layer 1032 and the light emitting layer 1033 can refer to the relevant paragraphs of the first semiconductor stack 53, the first upper semiconductor layer 531, the first lower semiconductor layer 532 and the first light emitting layer 533, respectively. In one embodiment, the common conductive structure 4" may be the common conductive structure 4, the common conductive structure 4' or the metal conductive column mentioned above, wherein the metal conductive column comprises a metal single layer or a metal stack, the metal single layer is, for example, a single layer structure composed of one metal among chromium, nickel, gold, silver, copper, tin, indium, tungsten and titanium or an alloy of the above materials, and the metal stack is, for example, a stack structure composed of at least two metals among chromium, nickel, gold, silver, copper, tin, indium, tungsten and titanium. In one embodiment, the material of the common conductive layer 20A comprises a gallium nitride (GaN) series material. Fig.37 As shown, the common conductive layer 20A includes a first epitaxial layer 20A1 and a second epitaxial layer 20A2. In one embodiment, the first epitaxial layer 20A1 includes n-type gallium nitride (GaN), and the second epitaxial layer 20A2 includes undoped gallium nitride (GaN).

[0249] Fig.38A A cross-sectional view of a light-emitting array device 900E according to an embodiment is shown. The light-emitting array device 900E includes a circuit device 90B, a plurality of light-emitting elements 10', a plurality of common conductive structures 4", a common conductive layer 20B, and a dielectric layer 3. The circuit device 90B has a plurality of common electrodes 90B1 and a plurality of lower electrodes 90B2. A plurality of light-emitting elements 10' are located on the circuit device 90B and are electrically connected to the plurality of lower electrodes 90B2, respectively. A plurality of common conductive structures 4" are located on the circuit device 90B and are electrically connected to the plurality of common electrodes 90B1, respectively. The common conductive layer 20B is disposed on the plurality of light-emitting elements 10' and the plurality of common conductive structures 4" and is electrically connected to the plurality of light-emitting elements 10' and the plurality of common conductive structures 4". The dielectric layer 3 surrounds the plurality of light-emitting elements 10' from the side and directly contacts the common conductive layer 20B.

[0250] like Fig.38A As shown, in one embodiment, the light emitting element 10 ′ further includes an insulating protection layer 106 covering the sidewalls 103S and the surface 1032S of the semiconductor stack 103 , contacting the lower electrode 102 and exposing the surface 1031S. The material and function of the insulating protection layer 106 can refer to the paragraph related to the insulating protection layer 96 .

[0251] like Fig.38A As shown, the dielectric layer 3 surrounds the light emitting element 10' and directly contacts the insulating protective layer 106. The dielectric layer 3 has a lower surface 3S1 coplanar with a surface 106S of the insulating protective layer 106, and an upper surface 3S2 coplanar with a surface 1031S of the semiconductor stack 103 and contacts the common conductive layer 20B. The dielectric layer 3 is used to isolate moisture and support multiple light emitting elements 10'. In one embodiment, the transmittance of the dielectric layer 3 for the light emitted by the light emitting element 10' is greater than 70%, and the material of the dielectric layer 3 includes a heat-resistant adhesive, such as BCB (Benzocyclobutene), epoxy resin (Epoxy) or silicone resin (Silicone). In another embodiment, the dielectric layer 3 further includes a reflective material (not shown), such as titanium oxide (TiO x) or a distributed Bragg reflector (DBR) structure to reflect the light emitted by the light emitting element 10'. According to one embodiment, the common conductive structure 4" is located between the common conductive layer 20B and the common electrode 90B1 and is connected to the common conductive layer 20B and the common electrode 90B1 to conduct current between the common conductive layer 20B and the common electrode 90B1. The circuit device 90B can allow a current to flow from the common electrode 90B1, through the common conductive structure 4" into the common conductive layer 20B, and the circuit device 90B can select to allow the current to pass through the light emitting element 10' through the lower electrode 90B2 to emit light.

[0252] like Fig.38A As shown, in one embodiment, the common conductive structure 4" includes the aforementioned common conductive structure 4, common conductive structure 4' or metal conductive column, wherein the metal conductive column includes a metal single layer or a metal stack, the metal single layer is, for example, a single layer structure composed of one metal among chromium, nickel, gold, silver, copper, tin, indium, tungsten, and titanium, or an alloy of the aforementioned materials, and the metal stack is, for example, a stack structure composed of at least two metals among chromium, nickel, gold, silver, copper, tin, indium, tungsten, and titanium. In one embodiment, the material and function of the common conductive layer 20B can refer to the paragraph related to the aforementioned light-transmitting conductive layer 2.

[0253] Fig.38B A cross-sectional view showing a light emitting array device 900E' according to an embodiment, Fig.38C A top view of a light emitting array device 900E' is shown, wherein Fig.38B for Fig.38C The cross-sectional view along the dotted line XX'. Fig.38B As shown, compared to Fig.38A The light emitting array device 900E shown in the figure, the light emitting array device 900E' further includes a metal mesh 20C in contact with the common conductive layer 20B. Fig.38B As shown, in the Y direction, the metal grid 20C and the plurality of light emitting elements 10' are respectively located on opposite sides of the common conductive layer 20B and do not overlap each other; in the X direction, the metal grid 20C and the plurality of light emitting elements 10' are alternately arranged. Fig.38C As shown, the metal grid 20C is a continuous metal line segment and does not cover the plurality of light emitting elements 10'. The material of the metal grid 20C includes copper, tin, aluminum, silver, palladium, gold, alloys of the above materials, or stacked layers of the above materials to improve the ability of current to be transversely conducted in the common conductive layer 20B.

[0254] FIG. 39A to FIG. 39E A manufacturing flow chart of a light emitting array device 900E according to an embodiment is shown. Fig.39AAs shown, a growth substrate 104G is provided, and an epitaxial layer 1031A and a plurality of platform structures 103M are formed on the growth substrate 104G. The disclosure of the growth substrate 104G can be referred to Fig.33A The growth substrate 930 and related paragraphs are shown. In one embodiment, the epitaxial layer 1031A includes undoped gallium nitride (GaN), the platform structure 103M includes a semiconductor stack 103 and an insulating protection layer 106 covering the sidewall 103S and the surface 1032S of the semiconductor stack 103, the semiconductor stack 103 includes an upper semiconductor layer 1031 contacting the epitaxial layer 1031A, a lower semiconductor layer 1032 and a light-emitting layer 1033 located between the upper semiconductor layer 1031 and the lower semiconductor layer 1032, the material of the upper semiconductor layer 1031 includes n-type gallium nitride (GaN), the lower semiconductor layer 1032 includes p-type gallium nitride (GaN), and the light-emitting layer 1033 includes a multi-layer quantum well structure for emitting a light. In one embodiment, any two adjacent platform structures 103M have a fixed spacing G.

[0255] Then as Fig.39B As shown, a dielectric layer 3 is formed on the epitaxial layer 1031A and between adjacent platform structures 103M by spin coating, injection, transfer molding or compression molding. In one embodiment, the dielectric layer 3 has an upper surface 3S2 in contact with the epitaxial layer 1031A, and a lower surface 3S1 coplanar with the surface 106S of the insulating protection layer 106 in the platform structure 103M.

[0256] like Fig.39C As shown, the platform structure 103M and the dielectric layer 3 are transferred to the temporary carrier 800A, and at least one of the manufacturing processes such as laser lift-off, polishing and etching is used to remove the growth substrate 104G and the epitaxial layer 1031A, and the surface 1031S of the upper semiconductor layer 1031 in the platform structure 103M and the upper surface 3S2 of the dielectric layer 3 are exposed. The platform structure 103M and the dielectric layer 3 are fixed on the temporary carrier 800A by the adhesive layer 1G, wherein the material and the formation method of the adhesive layer 1G can refer to the above paragraphs related to the adhesive layers 1C and 1D.

[0257] like Fig.39D As shown, a common conductive layer 20B is formed on the surface 1031S of the upper semiconductor layer 1031 of each platform structure 103M and the upper surface 3S2 of the dielectric layer 3 , wherein the material and manufacturing process of the common conductive layer 20B may refer to the transparent conductive layer 2 .

[0258] like Fig.39E As shown, the plurality of platform structures 103M, the dielectric layer 3 and the common conductive layer 20B are transferred to the temporary carrier 800B, and the adhesive layer 1G is removed or the adhesive force of the adhesive layer 1G is reduced by at least one of the manufacturing processes such as laser lift-off, heating and etching, so as to remove the temporary carrier 800A and expose the surface 106S of the platform structure 103M and the lower surface 3S1 of the dielectric layer 3. The adhesive layer 1H is formed between the common conductive layer 20B and the temporary carrier 800B, and the plurality of platform structures 103M, the dielectric layer 3 and the common conductive layer 20B are fixed on the temporary carrier 800B through the adhesive layer 1H, wherein the material and the forming method of the adhesive layer 1H may be the same as or different from the adhesive layer 1G. Next, a hole is formed on the surface 106S of the insulating protection layer 106 to expose a portion of the surface 1032S of the lower semiconductor layer 1032, and a lower electrode 102 is formed in the hole by electroplating or chemical deposition to form a temporary structure D, wherein the material and structure of the lower electrode 102 can refer to the aforementioned paragraphs related to the lower electrode 52, the lower electrode 62 and the lower electrode 72.

[0259] Subsequently, a plurality of common conductive structures 4" are formed in the dielectric layer 3 of the temporary structure D and connected to the common conductive layer 20B. Then, the bottom electrode 102 and the common conductive structure 4" are connected to the common conductive layer 20B by a welding process. Fig.38A The lower electrode 90B2 of the circuit device 90B in the circuit is electrically connected to form Fig.38A The light emitting array device 900E is shown.

[0260] FIG. 40A to FIG. 40E A manufacturing flow chart of a light emitting array device 900E according to an embodiment is shown. Fig.40A The production process steps shown can be referred to Fig.39A relevant paragraphs.

[0261] like Fig.40B As shown, a manufacturing process such as spin coating, injection, transfer molding or compression molding is used to form an adhesive layer 1G to cover multiple platform structures 103M, and then a temporary carrier 800A is provided to be fixed on the adhesive layer 1G, wherein the adhesive layer 1G and the temporary carrier 800A can refer to the aforementioned related paragraphs.

[0262] like Fig.40CAs shown, the growth substrate 104G and the epitaxial layer 1031A are removed by at least one of the manufacturing processes such as laser lift-off, polishing and etching to expose the surface 1031S of the upper semiconductor layer 1031 in the platform structure 103M and the adhesive layer 1G, and a common conductive layer 20B is formed on the surface 1031S of the platform structure 103M and the adhesive layer 1G, wherein the material and manufacturing process of the common conductive layer 20B can refer to the aforementioned light-transmitting conductive layer 2.

[0263] like Fig.40D As shown, a temporary carrier 800B is provided and fixed on the common conductive layer 20B through an adhesive layer 1H, wherein the adhesive layer 1H and the temporary carrier 800B can refer to the above-mentioned related paragraphs. Then, the adhesive layer 1G is removed by at least one of the manufacturing processes such as laser debonding, heating and etching to expose the common conductive layer 20B and the platform structure 103M.

[0264] like Fig.40E As shown, a dielectric layer 3 is formed on the common conductive layer 20B and in the space between two adjacent platform structures 103M. In one embodiment, the dielectric layer 3 has an upper surface 3S2 in contact with the common conductive layer 20B, and a lower surface 3S1 coplanar with the surface 106S of the insulating protection layer 106 in the platform structure 103M. Next, a hole is formed on the surface 106S of the insulating protection layer 106 of the platform structure 103M to expose the surface 1032S of the lower semiconductor layer 1032, and a lower electrode 102 is formed in the hole by electroplating or chemical deposition to form a temporary structure D.

[0265] Subsequently, a plurality of common conductive structures 4" may be formed in the dielectric layer 3 of the temporary structure D and connected to the common conductive layer 20B, and then the bottom electrode 102 and the common conductive structure 4" may be bonded to the dielectric layer 3 of the temporary structure D by a bonding process. Fig.38A The lower electrode 90B2 of the circuit device 90B in the embodiment is electrically connected to form a light emitting array device 900E.

Claims

1. A pixel structure, comprising: A first chip is used to emit a first light and comprises a first semiconductor stack, a first upper electrode located on the first semiconductor stack, and a first lower electrode located under the first semiconductor stack; A second chip, for emitting a second light, comprising a second semiconductor stack, a second upper electrode located on the second semiconductor stack, and a second lower electrode located below the second semiconductor stack; A common conductive structure comprising a semiconductor structure, an upper electrode located above the semiconductor structure, a lower electrode located below the semiconductor structure, and a conductive portion located between the upper electrode and the lower electrode; a dielectric layer surrounding and contacting the first chip, the second chip and the common conductive structure; as well as A light-transmitting conductive layer covers and electrically connects the first upper electrode, the second upper electrode and the upper electrode; The semiconductor structure has the same structure as the first semiconductor stack, and the semiconductor structure does not emit light when current flows through it. 2 . The pixel structure as claimed in claim 1 , further comprising a light-transmitting carrier covering the light-transmitting conductive layer.

3. The pixel structure according to claim 1, wherein: The semiconductor structure has a side wall located between the upper electrode and the lower electrode, and the conductive part is in direct contact with the side wall.

4. The pixel structure according to claim 1, wherein: The conductive part is located in the semiconductor structure.

5. The pixel structure according to claim 1, wherein: The first light and the second light have different peak wavelengths.

6. The pixel structure according to claim 1, wherein: The light-transmitting conductive layer is directly connected to the first upper electrode, the second upper electrode and the upper electrode. 7 . The pixel structure as claimed in claim 1 , further comprising a plurality of electrode pads respectively connected to the first lower electrode, the second lower electrode and the lower electrode.

8. The pixel structure according to claim 1, wherein: The first semiconductor stack contains nitrogen element, and the second semiconductor stack contains arsenic element.

9. The pixel structure according to claim 1, wherein: The first semiconductor stack includes a first semiconductor layer, and the semiconductor structure and the first semiconductor stack share the first semiconductor layer. 10 . The pixel structure as claimed in claim 1 , further comprising a third chip for emitting a third light, wherein the first light, the second light and the third light emit red, blue and green light respectively.

Images