Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a substrate; a drift layer; a base layer; a trench; an oxide layer; a plurality of first trenches are provided in a fast recovery diode region, the first trenches including a first trench portion and a second trench portion, the first trench portion being located on a side of the second trench portion closer to the first main surface, the oxide layer being provided on the inner wall of the second trench portion; polysilicon; the oxide layer on the inner wall of the second trench portion separates the polysilicon in the second trench portion from the base layer, the polysilicon in the first trench portion being in contact with the base layer; a dielectric layer; and an emitter metal layer, the emitter metal layer at least partially passing through the dielectric layer and in contact with the base layer, the emitter metal layer being electrically connected to the polysilicon. Thus, carriers can flow between the polysilicon in the first trench portion and the base layer, further improving dynamic avalanche withstand, reducing reverse recovery current, and shortening reverse recovery time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] An RC-IGBT (reverse conducting-insulated gate bipolar transistor) integrates an IGBT (insulated gate bipolar transistor) and an FRD (fast recovery diode) on a single chip. Generally speaking, the industry typically integrates IGBTs and FRDs in the chip's cell area using a lumped or distributed approach, with the two sharing terminals. This creates a highly integrated RC-IGBT, eliminating the need to connect the two discrete devices through packaging.

[0003] In related technologies, the RC-IGBT's structural design is not rational. When the FRD transitions from the on-state to the off-state, the unbalanced carriers stored within it are released, generating a large reverse recovery current and resulting in significant switching losses. Furthermore, when the FRD experiences dynamic avalanche, the locally concentrated current can burn out weak areas, further damaging the device. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device with better working performance.

[0005] Another object of the present invention is to provide a method for manufacturing a semiconductor device.

[0006] According to an embodiment of the present invention, a semiconductor device includes: a substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface being spaced apart in a first direction; a drift layer of a first conductivity type, the drift layer being disposed on the substrate and located between the first main surface and the second main surface; a base layer of a second conductivity type, the base layer being disposed on a side of the drift layer facing the first main surface, the upper surface of the base layer constituting a portion of the first main surface, the thickness of the base layer extending from the first main surface toward the second main surface along the first direction; a trench, the trench thickness direction penetrating the base layer from the first main surface to reach the drift layer, the length direction of the trench extending in the second direction of the semiconductor device, the plurality of trenches being spaced apart in a third direction of the semiconductor device, wherein the first direction, the second direction, and the third direction are perpendicular to each other; an oxide layer, the semiconductor device having a fast recovery diode region and an insulated gate bipolar transistor region, the insulated gate bipolar transistor region The fast recovery diode region is circumferentially arranged around the outside of the fast recovery diode region, the plurality of trenches include a plurality of first trenches and a plurality of second trenches, the fast recovery diode region is provided with a plurality of first trenches, the insulated gate bipolar transistor region is provided with a plurality of second trenches, the first trench includes a first trench portion and a second trench portion, the first trench portion is located on a side of the second trench portion closer to the first main surface, the oxide layer is arranged on an inner wall of the second trench portion; polycrystalline silicon of a first conductivity type, the polycrystalline silicon is arranged in the first trench, the oxide layer on the inner wall of the second trench portion separates the polycrystalline silicon in the second trench portion from the base layer, and the polycrystalline silicon in the first trench portion is in contact with the base layer; a dielectric layer, the dielectric layer is arranged on the first main surface; an emitter metal layer, the emitter metal layer is arranged on a side of the dielectric layer away from the first main surface, the emitter metal layer at least partially passes through the dielectric layer and is in contact with the base layer, and the emitter metal layer is electrically connected to the polycrystalline silicon.

[0007] Therefore, by optimizing the first trench of the fast recovery diode region, the oxide layer is only provided on the inner wall of the second trench portion of the first trench, the polysilicon in the first trench portion is in contact with the base layer, and the emitter metal layer is at least partially electrically connected to the polysilicon. In this way, without affecting the normal operation of the semiconductor device, carriers can flow between the polysilicon in the first trench portion and the base layer, thereby improving the hole injection efficiency in the forward conduction of the fast recovery diode region and improving the hole extraction efficiency in the reverse recovery of the fast recovery diode region, thereby further improving the dynamic avalanche withstand capability, reducing the reverse recovery current, shortening the reverse recovery time, and further improving the working performance of the semiconductor device.

[0008] In some examples of the present invention, the width of the first groove portion in the third direction is greater than the width of the second groove portion in the third direction.

[0009] In some examples of the present invention, the width of the first groove portion in the third direction is D1, the width of the second groove portion in the third direction is D2, and D1 and D2 satisfy the relationship: D2<D1<2.5D2.

[0010] In some examples of the present invention, the thickness of the first groove portion in the first direction is smaller than the thickness of the second groove portion in the first direction.

[0011] In some examples of the present invention, the semiconductor device further includes a transition region, which is circumferentially arranged outside the fast recovery diode region, the transition region is located between the fast recovery diode region and the insulated gate bipolar transistor region, and the transition region is also provided with a plurality of the first trenches.

[0012] In some examples of the present invention, the semiconductor device further includes a connecting trench, wherein the connecting trench penetrates the base layer from the first main surface in the thickness direction to reach the drift layer, and the length direction of the connecting trench extends in the third direction of the semiconductor device. The connecting trench is located at the end of the second direction of multiple first trenches and is interconnected with the end of the second direction of multiple first trenches. The polysilicon is arranged in the connecting trench, and the polysilicon in the connecting trench is in contact with the polysilicon in the first trench. The emitter metal layer at least partially penetrates the dielectric layer and is in contact with the polysilicon in the connecting trench.

[0013] In some examples of the present invention, the connecting groove includes a third groove portion and a fourth groove portion, the third groove portion is located on the side of the fourth groove portion closer to the first main surface, the inner wall of the fourth groove portion is provided with the oxide layer, the oxide layer on the inner wall of the fourth groove portion separates the polysilicon in the fourth groove portion from the base layer, and the polysilicon in the third groove portion is in contact with the base layer.

[0014] In some examples of the present invention, there are two connecting grooves, which are respectively located at two ends of the first grooves in the second direction, and the two connecting grooves respectively connect the two ends of the first grooves in the second direction to each other.

[0015] In some examples of the present invention, a first perforation is provided in a portion of the dielectric layer corresponding to a portion between two adjacent first grooves, a first connecting protrusion is provided on the emitter metal layer, the first connecting protrusion passes through the first perforation and is in contact with the base layer; a second perforation is provided in a portion of the dielectric layer corresponding to the connecting groove, a second connecting protrusion is provided on the emitter metal layer, the second connecting protrusion passes through the second perforation and is in contact with the polysilicon.

[0016] A method for manufacturing a semiconductor device according to an embodiment of the present invention is used to manufacture the semiconductor device described above, and the method for manufacturing the semiconductor device includes the following steps: preparing a substrate, and implanting a collector layer of a second conductive type, a field stop layer of a first conductive type, a drift layer of a first conductive type, a carrier storage layer of a first conductive type, and a base layer of a second conductive type into the substrate; etching a first trench, a second trench, and a connecting trench in the substrate, and growing an oxide layer on the surface of the first trench, the second trench, the connecting trench, and the substrate; photolithography and etching the oxide layer and the substrate so that the first trench includes a first trench portion and a second trench portion, and the connecting trench includes a third trench portion and a fourth trench portion; depositing polysilicon of the first conductive type, and etching the polysilicon.

[0017] In some examples of the present invention, after the steps of depositing polysilicon of a first conductive type and etching the polysilicon, the method for manufacturing the semiconductor device may further include: injecting a first conductive type dopant on both sides of the base layer corresponding to the second trench to form an emitter layer; depositing a dielectric layer on the surface of the oxide layer and the polysilicon; etching a first perforation and a second perforation on the surface of the dielectric layer, or etching a first perforation and a third perforation on the surface of the dielectric layer; depositing an emitter metal layer; injecting a first conductive type dopant into the collector layer to form a cathode layer; and depositing a collector metal layer on the second main surface.

[0018] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0020] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0021] Figure 2 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0022] Figure 3 is a partial cross-sectional view of a semiconductor device along the AA direction according to an embodiment of the present invention;

[0023] Figure 4 is a partial cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0024] Figure 5 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0025] Figure 6 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0026] Figure 7 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0027] Figure 8 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0028] Figure 9 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0029] Figure 10 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0030] Figure 11 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0031] Figure 12 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0032] Figure 13 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0033] Reference numerals:

[0034] 100, semiconductor device; 110, active region; 1101, insulated gate bipolar transistor region; 1102, fast recovery diode region; 1103, transition region; 120, termination region; 130, gate pad;

[0035] 10. Substrate; 101. First main surface; 102. Second main surface; 11. Drift layer; 12. Base layer; 13. Carrier storage layer; 14. Field stop layer; 15. Collector layer; 16. Cathode layer; 17. Emitter layer; 18. Contact region;

[0036] 20. Oxide layer; 30. Polysilicon;

[0037] 40. dielectric layer; 41. first perforation; 42. second perforation; 43. third perforation;

[0038] 50. Emitter metal layer; 51. First connection bump;

[0039] 60. Collector metal layer;

[0040] 70, groove; 71, first groove; 711, first groove portion; 712, second groove portion; 72, second groove;

[0041] 80. Connecting groove. DETAILED DESCRIPTION

[0042] The embodiments of the present invention will be described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention will be described in detail below.

[0043] Reference below Figures 1-13 A semiconductor device according to an embodiment of the present invention is described. A semiconductor device 100 can be fabricated using a method for manufacturing the semiconductor device 100. Specifically, the semiconductor device 100 can be an RC-IGBT (reverse conducting-insulated gate bipolar transistor). In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is N-type, and the second conductivity type is P-type. Furthermore, the first direction, the second direction, and the third direction are perpendicular to each other.

[0044] Combine Figure 1-Figure 4 As shown, the semiconductor device 100 according to the present invention may mainly include: a substrate 10, a drift layer 11 of a first conductivity type, a base layer 12 of a second conductivity type, a trench 70, an oxide layer 20, polysilicon 30 of a first conductivity type, a dielectric layer 40 and an emitter metal layer 50.

[0045] Among them, the semiconductor device 100 may include an active area 110 and a terminal area 120 arranged outside the active area 110. The active area 110 may mainly include an insulated gate bipolar transistor region 1101 and a fast recovery diode region 1102. The insulated gate bipolar transistor region 1101 is circumferentially arranged outside the fast recovery diode region 1102, so that the insulated gate bipolar transistor region 1101 and the fast recovery diode region 1102 can share the terminal area 120. In this way, the insulated gate bipolar transistor region 1101 can realize forward conduction of the semiconductor device 100, and the fast recovery diode region 1102 can realize reverse conduction of the semiconductor device 100, so that the semiconductor device 100 has both forward conduction and reverse conduction characteristics.

[0046] Specifically, the substrate 10 has a first principal surface 101 and a second principal surface 102 opposite the first principal surface 101. The first principal surface 101 and the second principal surface 102 are spaced apart in a first direction. The drift layer 11 is disposed on the substrate 10 and located between the first principal surface 101 and the second principal surface 102. The base layer 12 is disposed on the side of the drift layer 11 facing the first principal surface 101. The upper surface of the base layer 12 constitutes a portion of the first principal surface 101, and the thickness of the base layer 12 extends from the first principal surface 101 along the first direction toward the second principal surface 102. Furthermore, the collector layer 15 is disposed on the second principal surface 102 and corresponds to the insulated gate bipolar transistor region 1101. The cathode layer 16 is disposed on the second principal surface 102 and corresponds to the fast recovery diode region 1102.

[0047] Furthermore, a groove 70 is provided in the substrate 10, and the groove 70 penetrates the base layer 12 from the first main surface 101 in the thickness direction to reach the drift layer 11. The length direction of the groove 70 extends in the second direction of the semiconductor device 100. There are multiple grooves 70, and the multiple grooves 70 are arranged at intervals in the third direction of the semiconductor device 100.

[0048] The plurality of trenches 70 may include a plurality of first trenches 71 and a plurality of second trenches 72. A plurality of first trenches 71 are provided in the fast recovery diode region 1102, and an oxide layer 20 and polysilicon 30 are provided in the first trenches 71, so that a virtual gate can be formed in the first trench 71 to balance the electric field distribution in the semiconductor device 100. A plurality of second trenches 72 are provided in the insulated gate bipolar transistor region 1101, and an oxide layer 20 and polysilicon 30 are sequentially provided in the second trenches 72, so that a gate can be formed in the second trench 72, and the plurality of gates are electrically connected to the gate pad 130.

[0049] Furthermore, the dielectric layer 40 is arranged on the first main surface 101, and the emitter metal layer 50 is arranged on the side of the dielectric layer 40 away from the first main surface 101. The emitter metal layer 50 at least partially passes through the dielectric layer 40 and contacts the base layer 12. The second main surface 102 of the substrate 10 is also provided with a collector metal layer 60. The emitter metal layer 50 can not only serve as the emitter lead-in terminal of the insulated gate bipolar transistor region 1101, but also as the anode lead-in terminal of the fast recovery diode region 1102. The collector metal layer 60 can not only serve as the collector lead-in terminal of the insulated gate bipolar transistor region 1101, but also as the cathode lead-in terminal of the fast recovery diode region 1102.

[0050] In which, a first perforation 41 can be provided in the portion of the dielectric layer 40 corresponding to the portion between two adjacent first grooves 71, and a first connection protrusion 51 is provided on the emitter metal layer 50. The first connection protrusion 51 passes through the first perforation 41 and is in contact and connected with the base layer 12, thereby realizing electrical connection between the emitter metal layer 50 and the base layer 12.

[0051] It is understandable that the semiconductor device 100 realizes the integration of IGBT and FRD, and can provide a freewheeling circuit for the inductive load, which not only has the advantage of size reduction, but also has obvious advantages in working performance, such as high power density and high reliability.

[0052] However, in semiconductor device 100, when fast recovery diode region 1102 transitions from an on-state to an off-state, the unbalanced carriers stored therein are released, generating a large reverse recovery current and resulting in significant switching losses. Furthermore, when dynamic avalanche occurs in fast recovery diode region 1102, the locally concentrated current may burn out the weak region, further damaging semiconductor device 100.

[0053] Combine Figure 2-Figure 4 As shown, the polysilicon 30 is arranged in the first groove 71, and the first groove 71 may include a first groove portion 711 and a second groove portion 712. The first groove portion 711 is located on the side of the second groove portion 712 closer to the first main surface 101, and the oxide layer 20 is arranged on the inner wall of the second groove portion 712 of the first groove 71. The oxide layer 20 on the inner wall of the second groove portion 712 separates the polysilicon 30 in the second groove portion 712 from the base layer 12. The polysilicon 30 in the first groove portion 711 is in contact with the base layer 12, and the emitter metal layer 50 is at least partially electrically connected to the polysilicon 30.

[0054] Specifically, by making the first groove 71 include a first groove portion 711 and a second groove portion 712, the first groove portion 711 is located on the side of the second groove portion 712 closer to the first main surface 101, and the oxide layer 20 is only set on the inner wall of the second groove portion 712, and the oxide layer 20 is not set on the inner wall of the first groove portion 711. In this way, the oxide layer 20 on the inner wall of the second groove portion 712 can separate the polysilicon 30 in the second groove portion 712 from the base layer 12, while the polysilicon 30 in the first groove portion 711 can be in direct contact with the base layer 12, and carriers can flow between the polysilicon 30 in the first groove portion 711 and the base layer 12.

[0055] It is understandable that this will form an NPN transistor composed of the first conductivity type polysilicon 30, the second conductivity type base layer 12, and the first conductivity type drift layer 11 on the anode side of the fast recovery diode region 1102. By electrically connecting the emitter metal layer 50 to the polysilicon 30 in the first trench 71, while at least partially penetrating the dielectric layer 40 and contacting the base layer 12, that is, the emitter metal layer 50 is electrically connected to the base layer 12, the emitter metal layer 50 can be short-circuited to achieve the emitter of the NPN transistor, thereby preventing the NPN transistor from turning on during the reverse recovery period.

[0056] In this way, without affecting the normal operation of the semiconductor device 100 , the operating performance of the semiconductor device 100 can be improved through the direct contact between the polysilicon 30 in the first trench portion 711 and the base layer 12 .

[0057] Specifically, during the forward conduction process of the fast recovery diode region 1102, the polysilicon 30 in the first groove portion 711 can inject electrons to recombine with the holes in the base layer 12, thereby reducing the hole injection efficiency of the anode, thereby not only reducing the reverse recovery peak current, but also avoiding excessively high di / dt causing excessively high reverse recovery peak voltage, and suppressing dynamic avalanche.

[0058] During the reverse recovery process of the fast recovery diode region 1102, the polysilicon 30 in the first trench portion 711 can provide an additional hole outflow path, which can not only improve the hole extraction efficiency and reduce the reverse recovery time, but also prevent local current concentration, improve the dynamic avalanche tolerance, expand the safe operating area of ​​the semiconductor device 100, and achieve high reliability.

[0059] Therefore, by optimizing the first trench 71 of the fast recovery diode region 1102, the oxide layer 20 is only provided on the inner wall of the second trench portion 712 of the first trench 71, the polysilicon 30 in the first trench portion 711 is in contact with the base layer 12, and the emitter metal layer 50 is at least partially electrically connected to the polysilicon 30. In this way, without affecting the normal operation of the semiconductor device 100, carriers can flow between the polysilicon 30 in the first trench portion 711 and the base layer 12, thereby improving the hole injection efficiency of the fast recovery diode region 1102 during forward conduction, and improving the hole extraction efficiency of the fast recovery diode region 1102 during reverse recovery, thereby further improving the dynamic avalanche withstand, reducing the reverse recovery current, shortening the reverse recovery time, and further improving the working performance of the semiconductor device 100.

[0060] Combine Figure 3 and Figure 4As shown, the width of the first groove portion 711 in the third direction is greater than the width of the second groove portion 712 in the third direction. Specifically, considering that the first groove portion 711 is located on the side of the second groove portion 712 facing the first main surface 101, and the etching of the first groove 71 is carried out from the first main surface 101 toward the second main surface 102, in order to facilitate the production of the semiconductor device 100, the width of the first groove portion 711 in the third direction is not less than the width of the second groove 72 in the third direction.

[0061] Furthermore, the width of the first groove portion 711 in the third direction will affect the contact area between the polysilicon 30 therein and the base layer 12, thereby affecting the hole injection efficiency of the fast recovery diode region 1102 during forward conduction and the hole extraction efficiency of the fast recovery diode region 1102 during reverse recovery. By setting the width of the first groove portion 711 in the third direction to be greater than the width of the second groove portion 712 in the third direction, the contact area between the polysilicon 30 inside the first groove portion 711 and the base layer 12 can be increased, thereby improving the hole injection efficiency of the fast recovery diode region 1102 during forward conduction and the hole extraction efficiency of the fast recovery diode region 1102 during reverse recovery, thereby further improving the dynamic avalanche withstand, reducing the reverse recovery current, reducing the reverse recovery time, and further improving the working performance of the semiconductor device 100.

[0062] Combine Figure 3 and Figure 4 As shown, the width of the first trench portion 711 in the third direction is D1, and the width of the second trench portion 712 in the third direction is D2. D1 and D2 satisfy the relationship: D2 < D1 < 2.5D2. Specifically, two adjacent first trench portions 711 are spaced apart in the third direction. Both sides of the first trench portion 711 in the third direction will contact the base layer 12 and form a depletion layer. The width of the first trench portion 711 in the third direction affects the contact area between the polysilicon 30 and the base layer 12, thereby affecting the width of the depletion layer. While the width of the first trench portion 711 in the third direction is set to be greater than the width of the second trench portion 712 in the third direction, the width of the first trench portion 711 in the third direction is also set to be less than 2.5 times the width of the second trench portion 712 in the third direction. This prevents the depletion layers of the two adjacent first trench portions 711 from connecting, ensuring normal current flow within the semiconductor device 100 and ensuring normal operation of the semiconductor device 100.

[0063] Combine Figure 3 and Figure 4As shown, the thickness of the first trench portion 711 in the first direction is less than the thickness of the second trench portion 712 in the first direction. Specifically, two adjacent first trench portions 711 are spaced apart in the third direction. Both sides of the first trench portion 711 in the third direction will contact the base layer 12 and form a depletion layer. The thickness of the first trench portion 711 in the third direction will affect the contact area between the polysilicon 30 and the base layer 12 therein, thereby affecting the width of the depletion layer. By setting the thickness of the first trench portion 711 in the first direction to be less than the thickness of the second trench portion 712 in the first direction, the depletion layers between the two adjacent first trench portions 711 can be prevented from being connected, thereby ensuring the normal flow of current within the semiconductor device 100 and the normal operation of the semiconductor device 100.

[0064] Combine Figure 1-Figure 3 As shown, the semiconductor device 100 further includes a transition region 1103, which is circumferentially disposed outside the fast recovery diode region 1102 and between the fast recovery diode region 1102 and the insulated gate bipolar transistor region 1101. The transition region 1103 is also provided with a plurality of first trenches 71. Thus, the transition region 1103 can separate the insulated gate bipolar transistor region 1101 from the fast recovery diode region 1102, thereby preventing the insulated gate bipolar transistor region 1101 and the fast recovery diode region 1102 from interfering with each other, thereby minimizing the rebound phenomenon and ensuring that the semiconductor device 100 can operate stably under high current conditions, thereby further improving the operating performance of the semiconductor device 100.

[0065] Furthermore, a plurality of first trenches 71 are also provided in the transition region 1103. It is understood that the first trenches 71 in the transition region 1103 also include a first trench portion 711 and a second trench portion 712. The polysilicon 30 in the first trench portion 711 can be in direct contact with the base layer 12, while the polysilicon 30 in the second trench portion 712 is separated from the base layer 12 by the oxide layer 20. In this way, carriers can flow between the polysilicon 30 in the first trench portion 711 in the transition region 1103 and the base layer 12, thereby further improving the hole injection efficiency of the fast recovery diode region 1102 during forward conduction and further improving the hole extraction efficiency of the fast recovery diode region 1102 during reverse recovery, thereby further enhancing the operating performance of the semiconductor device 100.

[0066] Combine Figure 2As shown, the semiconductor device 100 may further include a connecting trench 80, which penetrates the base layer 12 from the first main surface 101 in the thickness direction to reach the drift layer 11, and the length direction of the connecting trench 80 extends in the third direction of the semiconductor device 100. The connecting trench 80 is located at the end of the second direction of the plurality of first trenches 71 and is interconnected with the end of the second direction of the plurality of first trenches 71. The polysilicon 30 is arranged in the connecting trench 80, and the polysilicon 30 in the connecting trench 80 is in contact with the polysilicon 30 in the first trench 71. The emitter metal layer 50 at least partially penetrates the dielectric layer 40 and is in contact with the polysilicon 30 in the connecting trench 80.

[0067] Specifically, the connecting groove 80 is located at the end of the second direction of the multiple first grooves 71 and is interconnected with the end of the second direction of the multiple first grooves 71. The polysilicon 30 in the connecting groove 80 is in contact with the polysilicon 30 in the first groove 71. In this way, the connecting groove 80 can be connected with the multiple first grooves 71, and the current can be connected between the polysilicon 30 in the connecting groove 80 and the polysilicon 30 in the multiple first grooves 71.

[0068] Furthermore, the emitter metal layer 50 is at least partially passed through the dielectric layer 40 and is in contact with the polysilicon 30 in the connecting groove 80, so that the electrical connection between the emitter metal layer 50 and the polysilicon 30 in the connecting groove 80 can be achieved. Since the current can be connected between the polysilicon 30 in the connecting groove 80 and the polysilicon 30 in the multiple first grooves 71, the electrical connection between the emitter metal layer 50 and the polysilicon 30 in the multiple first grooves 71 can be achieved, which can make the electrical connection between the emitter metal layer 50 and the polysilicon 30 in the multiple first grooves 71 simpler and more convenient.

[0069] Combine Figure 2 As shown, a second through-hole 42 is provided at a portion of the dielectric layer 40 corresponding to the connection groove 80, and a second connection protrusion is provided on the emitter metal layer 50. The second connection protrusion penetrates the second through-hole 42 and is in contact with the polysilicon 30. Specifically, the second through-hole 42 can be provided at a portion of the dielectric layer 40 corresponding to the connection groove 80, and a second connection protrusion can be provided on the emitter metal layer 50. In this way, the second connection protrusion only needs to penetrate the second through-hole 42 so that the second connection protrusion can contact the polysilicon 30 in the connection groove 80, thereby achieving electrical connection between the emitter metal layer 50 and the polysilicon 30 in the connection groove 80, making the electrical connection between the emitter metal layer 50 and the polysilicon 30 in the connection groove 80 simpler and more reliable.

[0070] Thus, unlike the embodiment in which the third through-hole 43 for the emitter metal layer 50 to penetrate and contact the polysilicon 30 is directly provided in the portion of the dielectric layer 40 corresponding to the first trench 71, in which the distance between the third through-hole 43 and the first through-hole 41 is too close, resulting in excessive difficulty in opening the hole in the dielectric layer 40 or even failure, the present embodiment facilitates the opening of the hole in the dielectric layer 40 by designing the second trench 72 corresponding to the connecting trench 80, thereby improving the structural reliability of the semiconductor device 100, facilitating the production and manufacturing of the semiconductor device 100, and achieving further optimization of the structural design of the semiconductor device 100.

[0071] In some embodiments of the present invention, there are two connecting trenches 80, each located at the two ends of the plurality of first trenches 71 in the second direction. The two connecting trenches 80 interconnect the two ends of the plurality of first trenches 71 in the second direction. In this way, electrical connections between the two connecting trenches 80 and the emitter metal layer 50 can be achieved, thereby achieving electrical connections between the plurality of first trenches 71 and the emitter metal layer 50. While ensuring improved hole injection efficiency in the fast recovery diode region 1102 during forward conduction and improved hole extraction efficiency in the fast recovery diode region 1102 during reverse recovery, the current uniformity within the semiconductor device 100 can be improved, thereby further improving the operating performance of the semiconductor device 100.

[0072] In some embodiments of the present invention, the connecting groove 80 may mainly include a third groove portion and a fourth groove portion, the third groove portion is located on the side of the fourth groove portion closer to the first main surface 101, and the inner wall of the fourth groove portion of the connecting groove 80 is provided with an oxide layer 20. The oxide layer 20 on the inner wall of the fourth groove portion separates the polysilicon 30 in the fourth groove portion from the base layer 12, and the polysilicon 30 in the third groove portion is in contact with the base layer 12.

[0073] Specifically, by making the connecting groove 80 include a third groove portion and a fourth groove portion, the third groove portion is located on the side of the fourth groove portion that is closer to the first main surface 101, and the oxide layer 20 is only provided on the inner wall of the fourth groove portion, so that the oxide layer 20 on the inner wall of the fourth groove portion can separate the polysilicon 30 in the fourth groove portion from the base layer 12, while the polysilicon 30 in the third groove portion is in contact with the base layer 12, and carriers can flow between the polysilicon 30 in the third groove portion and the base layer 12, thereby further improving the hole injection efficiency in the forward conduction of the fast recovery diode region 1102, and further improving the hole extraction efficiency during reverse recovery of the fast recovery diode region 1102, which can further improve the working performance of the semiconductor device 100.

[0074] Combine Figure 5-Figure 13As shown, the method for manufacturing the semiconductor device 100 according to the present invention can be applied to the above-mentioned semiconductor device 100 .

[0075] Combine Figure 5-Figure 9 As shown, the manufacturing method of the semiconductor device 100 may mainly include the following steps: preparing a substrate 10, implanting a collector layer 15 of a second conductivity type, a field stop layer 14 of a first conductivity type, a drift layer 11 of a first conductivity type, a carrier storage layer 13 of a first conductivity type, and a base layer 12 of a second conductivity type into the substrate 10; etching a first trench 71, a second trench 72, and a connecting trench 80 in the substrate 10, and growing an oxide layer 20 on the surface of the first trench 71, the second trench 72, the connecting trench 80, and the substrate 10; photolithography and etching the oxide layer 20 and the substrate so that the first trench 71 includes a first trench portion 711 and a second trench portion 712, and the connecting trench 80 includes a third trench portion and a fourth trench portion; depositing polysilicon 30 of a first conductivity type, and etching the polysilicon 30.

[0076] Specifically, when manufacturing the semiconductor device 100, a substrate 10 can be provided first. The substrate 10 has a first main surface 101 and a second main surface 102. Different concentrations of first conductive type dopants and different concentrations of second conductive type dopants are sequentially injected into the substrate 10 to form a second conductive type collector layer 15, a first conductive type field stop layer 14, a first conductive type drift layer 11, a first conductive type carrier storage layer 13, and a second conductive type base layer 12 arranged in sequence.

[0077] Then, a first trench 71, a second trench 72 and a connecting trench 80 are etched in the substrate 10 so that the depth direction of the first trench 71, the second trench 72 and the connecting trench 80 penetrates the base layer 12 and the field stop layer 14 from the first main surface 101 along the first direction to reach the drift layer 11, the length direction of the first trench 71 and the second trench 72 extends in the second direction of the semiconductor device 100, and the length direction of the connecting trench 80 extends in the third direction of the semiconductor device 100, and the rounding process is completed, and an oxide layer 20 is grown on the surface of the substrate 10 and the first trench 71, the second trench 72 and the connecting trench 80.

[0078] Then, by photolithography and etching of the oxide layer 20 and the substrate 10, the first groove 71 includes a first groove portion 711 and a second groove portion 712, and the connecting groove 80 includes a third groove portion and a fourth groove portion. Then, the first conductive type polysilicon 30 is deposited and the polysilicon 30 is etched so that the polysilicon 30 in the first groove portion 711 and the third groove portion can be in direct contact with the base layer 12, and the polysilicon 30 in the second groove portion 712 and the fourth groove portion can be separated from the base layer 12 by the oxide layer 20.

[0079] Combine Figure 5 as well as Figure 10-13 As shown, after the steps of depositing the first conductive type polysilicon 30 and etching the polysilicon 30, the manufacturing method of the semiconductor device 100 may also mainly include the following steps: injecting the first conductive type dopant on both sides of the base layer 12 corresponding to the second trench 72 to form an emitter layer 17; depositing a dielectric layer 40 on the surface of the oxide layer 20 and the polysilicon 30; etching the first through-hole 41 and the second through-hole 42 on the surface of the dielectric layer 40, or etching the first through-hole 41 and the third through-hole 43 on the surface of the dielectric layer 40; depositing an emitter metal layer 50; injecting the first conductive type dopant into the collector layer 15 to form a cathode layer 16; and depositing a collector metal layer 60 on the second main surface 102.

[0080] Specifically, after depositing polysilicon 30 and etching the polysilicon 30 , first conductive type dopants can be implanted on both sides of the base layer 12 corresponding to the second trench 72 to form an emitter layer 17 , which is used to be electrically connected to the emitter metal layer 50 later.

[0081] Then, a dielectric layer 40 is deposited on the oxide layer 20 and the polysilicon 30 . The dielectric layer 40 can protect the oxide layer 20 and the polysilicon 30 , thereby ensuring the first main surface 101 of the substrate 10 and reducing the risk of damage to the semiconductor device 100 .

[0082] Then, by etching the first through-hole 41 and the second through-hole 42, or etching the first through-hole 41 and the third through-hole 43 on the surface of the dielectric layer 40 and the oxide layer 20, and then depositing the emitter metal layer 50, it is convenient for the emitter metal layer 50 to contact the emitter layer 17 through the first through-hole 41, and convenient for the emitter metal layer 50 to be electrically connected to the polysilicon 30 in the first groove portion 711 through the second through-hole 42 or the third through-hole 43, thereby ensuring the normal operation of the semiconductor device 100.

[0083] It is understandable that the second through-hole 42 or the third through-hole 43 can be formed simultaneously with the first through-hole 41 , and the manufacture of the second through-hole 42 or the third through-hole 43 can be compatible with existing processes.

[0084] It should be noted that, considering the relatively small sizes of the first through-hole 41, the second through-hole 42, and the third through-hole 43, a tungsten plug can be implanted into the first through-hole 41, the second through-hole 42, or the third through-hole 43, and then Ti / TiN can be deposited on the tungsten plug to form the emitter metal layer 50. Furthermore, before depositing the emitter metal layer 50, a dopant of the second conductivity type can be implanted into the portion of the base layer 12 corresponding to the first through-hole 41 to form a contact region 18, so that the contact region 18 is in contact with the emitter metal layer 50.

[0085] Finally, a first conductive type dopant is implanted into the collector layer 15 to form a cathode layer 16 , and then a collector metal layer 60 is deposited on the second main surface 102 .

[0086] In this way, the semiconductor device 100 can be manufactured and the semiconductor device 100 can operate better. Moreover, the manufacturing of the semiconductor device 100 is also compatible with existing processes, and only one process step is added, which can save process steps and time costs.

[0087] It should be noted that other structures and operations of the semiconductor device 100 according to the embodiment of the present invention are well known to those skilled in the art and will not be described in detail here.

[0088] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0089] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0090] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a first direction; a drift layer of a first conductivity type, the drift layer being disposed on the substrate and located between the first main surface and the second main surface; a base layer of a second conductivity type, the base layer being arranged on a side of the drift layer facing the first main surface, the upper surface of the base layer constituting a portion of the first main surface, and the base layer extending from the first main surface along a first direction toward the second main surface; a trench, wherein the trench penetrates the base layer from the first main surface in a thickness direction to reach the drift layer, the length direction of the trench extending in a second direction of the semiconductor device, the plurality of trenches being provided, the plurality of trenches being spaced apart in a third direction of the semiconductor device, wherein the first direction, the second direction, and the third direction are perpendicular to each other; an oxide layer, the semiconductor device comprising a fast recovery diode region and an insulated gate bipolar transistor region, the insulated gate bipolar transistor region being circumferentially arranged outside the fast recovery diode region, the plurality of trenches comprising a plurality of first trenches and a plurality of second trenches, the fast recovery diode region being provided with a plurality of the first trenches, the insulated gate bipolar transistor region being provided with a plurality of the second trenches, the first trench comprising a first trench portion and a second trench portion, the first trench portion being located on a side of the second trench portion closer to the first main surface, and the oxide layer being arranged on an inner wall of the second trench portion; Polycrystalline silicon of a first conductivity type, the polycrystalline silicon being disposed in the first trench, the oxide layer on the inner wall of the second trench portion separating the polycrystalline silicon in the second trench portion from the base layer, and the polycrystalline silicon in the first trench portion being in contact with the base layer; a dielectric layer, the dielectric layer being disposed on the first main surface; an emitter metal layer, the emitter metal layer being disposed on a side of the dielectric layer away from the first main surface, the emitter metal layer at least partially passing through the dielectric layer to contact the base layer, and the emitter metal layer being electrically connected to the polysilicon; The width of the first groove portion in the third direction is greater than the width of the second groove portion in the third direction.

2. The semiconductor device according to claim 1, wherein The width of the first groove portion in the third direction is D1, the width of the second groove portion in the third direction is D2, and D1 and D2 satisfy the relationship: D2<D1<2.5D2.

3. The semiconductor device according to claim 1, wherein The thickness of the first groove portion in the first direction is smaller than the thickness of the second groove portion in the first direction.

4. The semiconductor device according to claim 1, wherein The semiconductor device further includes a transition region, which is circumferentially arranged outside the fast recovery diode region and between the fast recovery diode region and the insulated gate bipolar transistor region. The transition region is also provided with a plurality of the first trenches.

5. The semiconductor device according to claim 1, wherein The semiconductor device further includes a connecting trench, wherein the connecting trench penetrates the base layer from the first main surface in the thickness direction to reach the drift layer, and the length direction of the connecting trench extends in the third direction of the semiconductor device. The connecting trench is located at the end of the plurality of first trenches in the second direction and is interconnected with the end of the plurality of first trenches in the second direction. The polysilicon is arranged in the connecting trench, and the polysilicon in the connecting trench is in contact with the polysilicon in the first trench. The emitter metal layer at least partially penetrates the dielectric layer and is in contact with the polysilicon in the connecting trench.

6. The semiconductor device according to claim 5, wherein The connecting groove includes a third groove portion and a fourth groove portion, the third groove portion is located on the side of the fourth groove portion closer to the first main surface, the inner wall of the fourth groove portion is provided with the oxide layer, the oxide layer on the inner wall of the fourth groove portion separates the polysilicon in the fourth groove portion from the base layer, and the polysilicon in the third groove portion is in contact with the base layer.

7. The semiconductor device according to claim 5, wherein There are two connecting grooves, and the two connecting grooves are respectively located at two ends of the first grooves in the second direction. The two connecting grooves respectively connect the two ends of the first grooves in the second direction to each other.

8. The semiconductor device according to claim 5, wherein The dielectric layer is provided with a first through-hole at a portion corresponding to a portion between two adjacent first grooves, and the emitter metal layer is provided with a first connecting protrusion, which passes through the first through-hole and contacts and connects with the base layer; A second through-hole is provided on a portion of the dielectric layer corresponding to the connection groove. A second connection protrusion is provided on the emitter metal layer. The second connection protrusion passes through the second through-hole and is in contact with the polysilicon.

9. A method for manufacturing a semiconductor device, applicable to the semiconductor device according to any one of claims 1 to 8, characterized in that: The following steps are involved: Prepare a substrate, and implant into the substrate a collector layer of the second conductivity type, a field stop layer of the first conductivity type, a drift layer of the first conductivity type, a carrier storage layer of the first conductivity type, and a base layer of the second conductivity type; Etching a first trench, a second trench, and a connecting trench in the substrate, and growing an oxide layer on the surfaces of the first trench, the second trench, the connecting trench, and the substrate; By photolithography and etching the oxide layer and the substrate, the first trench includes a first trench portion and a second trench portion, and the connecting trench includes a third trench portion and a fourth trench portion; Polysilicon of a first conductivity type is deposited and the polysilicon is etched.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: After the steps of depositing polysilicon of the first conductivity type and etching the polysilicon, the method further includes: implanting first conductive type dopants on both sides of the base layer corresponding to the second trench to form an emission layer; Depositing a dielectric layer on the surface of the oxide layer and the polysilicon; Etching a first through-hole and a second through-hole on the surface of the dielectric layer, or etching a first through-hole and a third through-hole on the surface of the dielectric layer; depositing an emitter metal layer; Implanting a first conductive type dopant into the collector layer to form a cathode layer; A collector metal layer is deposited on the second major surface.

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