Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a substrate; a drift layer; a well layer; a trench; a collector layer; and a cathode layer. The well layer includes multiple sub-well layers. One of the multiple sub-well layers in the fast recovery diode region that is closest to the insulated gate bipolar transistor region is defined as a boundary sub-well layer. Compared with the boundary sub-well layer, the multiple sub-well layers in the fast recovery diode region that is farther away from the insulated gate bipolar transistor region is defined as a non-boundary sub-well layer. The depth of the boundary sub-well layer extends from a first main surface along a first direction toward the cathode layer. The depth of the boundary sub-well layer is greater than the depth of the non-boundary sub-well layer and greater than the depth of the trench. Thus, not only can the boundary sub-well layer block laterally flowing electrons and avoid voltage foldback, but the withstand voltage of the fast recovery diode region can also be enhanced, which can facilitate the fast recovery diode region to operate in scenarios with fast switching speeds and large surge currents.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] An RC-IGBT (reverse conducting-insulated gate bipolar transistor) integrates an IGBT (insulated gate bipolar transistor) and an FRD (fast recovery diode) on a single chip. Generally speaking, the industry typically integrates IGBTs and FRDs in the chip's cell area using a lumped or distributed approach, with the two sharing terminals. This creates a highly integrated RC-IGBT, eliminating the need to connect the two discrete devices through packaging.

[0003] In related technologies, the structural design of RC-IGBT is not reasonable enough. Although it has the advantages of size reduction and some performance advantages, such as high power density and high reliability, RC-IGBT has a voltage snapback phenomenon during forward conduction, that is, a negative resistance phenomenon caused by switching from MOSFET mode to IGBT mode, resulting in unstable operation. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device that can avoid voltage foldback and has better stability.

[0005] Another object of the present invention is to provide a method for manufacturing a semiconductor device.

[0006] According to an embodiment of the present invention, a semiconductor device includes: a substrate, the substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface being spaced apart in a first direction; a drift layer of a first conductivity type, the drift layer being arranged on the substrate and located between the first main surface and the second main surface; a well layer of a second conductivity type, the well layer being arranged on a side of the drift layer facing the first main surface, the upper surface of the well layer constituting a part of the first main surface; a trench, the depth direction of the trench penetrating the well layer from the first main surface along the first direction to reach the drift layer, the length direction of the trench extending in the second direction of the semiconductor device, the number of the trenches being multiple, and the multiple trenches being spaced apart in a third direction of the semiconductor device, wherein the first direction, the second direction and the third direction are perpendicular to each other; a collector layer of a second conductivity type, the semiconductor device having a fast recovery diode region and an insulated gate bipolar transistor region, the insulated gate bipolar transistor region is arranged around the outside of the fast recovery diode region, the collector layer is arranged on the second main surface and corresponds to the insulated gate bipolar transistor region; a cathode layer of a first conductivity type, the cathode layer is arranged on the second main surface and corresponds to the fast recovery diode region, the well layer includes a plurality of sub-well layers, the sub-well layer is located between two adjacent trenches, and the one of the plurality of sub-well layers in the fast recovery diode region that is closest to the insulated gate bipolar transistor region is set as a boundary sub-well layer. Compared with the boundary sub-well layer, the plurality of sub-well layers in the fast recovery diode region that is farther away from the insulated gate bipolar transistor region is a non-boundary sub-well layer. The depth of the boundary sub-well layer extends from the first main surface along a first direction toward the cathode layer, and the depth of the boundary sub-well layer is greater than the depth of the non-boundary sub-well layer and greater than the depth of the trench.

[0007] Therefore, by extending the depth of the boundary sub-well layer from the first main surface along the first direction toward the cathode layer, the depth of the boundary sub-well layer is greater than the depth of the non-boundary sub-well layer and greater than the depth of the groove. This not only enables the boundary sub-well layer to block electrons flowing laterally and avoid voltage foldback, but also enhances the withstand voltage of the fast recovery diode area, which is beneficial for the fast recovery diode area to operate in scenarios with fast switching speed and large surge current.

[0008] In some examples of the present invention, the boundary sub-well layer extends from the first main surface along a first direction to the cathode layer and contacts the cathode layer.

[0009] In some examples of the present invention, the depth of the drift layer is D1, the depth of the boundary sub-well layer is D2, and D1 and D2 satisfy the relationship: 1 / 2<D2 / D1≤1.

[0010] In some examples of the present invention, the semiconductor device further includes: a field stop layer of a first conductivity type, the field stop layer is located between the collector layer and the drift layer, and the cathode layer is disposed adjacent to the drift layer in a first direction.

[0011] In some examples of the present invention, a depth of at least a portion of the boundary sub-well layer closer to the insulated gate bipolar transistor region extends from the first main surface along the first direction to the cathode layer.

[0012] In some examples of the present invention, the width of the boundary sub-well layer in the third direction is D3, and the width of the portion of the boundary sub-well layer extending toward the cathode layer in the third direction is D4, and D3 and D4 satisfy the relationship: 1 / 3≤D4 / D3≤1.

[0013] A method for manufacturing a semiconductor device according to an embodiment of the present invention is used to manufacture the semiconductor device described above, and the method for manufacturing the semiconductor device includes the following steps: preparing a substrate, injecting a first conductive type dopant into the substrate to form a drift layer; etching a groove in the substrate, and growing an oxide insulating layer on the surface of the substrate and the groove; depositing polysilicon on the surface of the oxide insulating layer; etching the polysilicon; injecting a second conductive type dopant into the substrate to form a plurality of sub-well layers, the plurality of sub-well layers including but not limited to boundary sub-well layers and non-boundary sub-well layers, and injecting a first conductive type dopant on both sides of the sub-well layer corresponding to the groove to form a source region, wherein the depth of the boundary sub-well layer is greater than the depth of the non-boundary sub-well layer and greater than the depth of the groove.

[0014] In some examples of the present invention, the second conductive type dopant is injected into the substrate to form multiple sub-well layers, including but not limited to boundary sub-well layers and non-boundary sub-well layers, and the first conductive type dopant is injected on both sides of the sub-well layer corresponding to the trench to form a source region, wherein the depth of the boundary sub-well layer is greater than the depth of the non-boundary sub-well layer and greater than the depth of the trench may include: injecting the second conductive type dopant between two adjacent trenches to form multiple sub-well layers; deeply injecting the second conductive type dopant between the two trenches closest to the insulated gate bipolar transistor region to form a boundary sub-well layer; and injecting the first conductive type dopant on both sides of the trench corresponding to the sub-well layer in the insulated gate bipolar transistor region to form a source region.

[0015] In some examples of the present invention, the second conductive type dopant is injected into the substrate to form multiple sub-well layers, including but not limited to boundary sub-well layers and non-boundary sub-well layers, and the first conductive type dopant is injected on both sides of the sub-well layer corresponding to the trench to form a source region, wherein the depth of the boundary sub-well layer is greater than the depth of the non-boundary sub-well layer and greater than the depth of the trench. After the step, the manufacturing method of the semiconductor device further includes: depositing an interlayer insulating film on the surface of the oxidized insulating layer and the polysilicon, and etching contact holes on the surface of the interlayer insulating film and the oxidized insulating layer; and setting an emitter metal layer on the upper surface of the interlayer insulating film and the contact hole.

[0016] In some examples of the present invention, after the step of setting an emitter metal layer on the upper surface of the interlayer insulating film and the contact hole, the method for manufacturing the semiconductor device further includes: sequentially injecting a first conductive type dopant and a second conductive type dopant on the side of the drift layer facing the second main surface to form a field stop layer and a collector layer; injecting a first conductive type dopant into the collector layer to form a cathode layer; and depositing a collector metal layer on the second main surface.

[0017] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0019] Figure 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0020] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0021] Figure 3 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0022] Figure 4 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0023] Figure 5 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0024] Figure 6 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0025] Figure 7is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0026] Figure 8 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention;

[0027] Figure 9 is a state diagram of a manufacturing process of a transistor module according to an embodiment of the present invention.

[0028] Reference numerals:

[0029] 100, semiconductor device; 110, active region; 1101, insulated gate bipolar transistor region; 1102, fast recovery diode region; 120, terminal region;

[0030] 10. Substrate; 101. First main surface; 102. Second main surface; 11. Drift layer; 12. Well layer; 121. Subwell layer; 1211. Boundary subwell layer; 1212. Non-boundary subwell layer; 13. Trench; 14. Collector layer; 15. Cathode layer; 16. Field stop layer; 17. Source region;

[0031] 20. Oxide insulating layer; 30. Polysilicon; 40. Interlayer insulating film; 41. Contact hole; 50. Emitter metal layer; 60. Collector metal layer. DETAILED DESCRIPTION

[0032] The embodiments of the present invention will be described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention will be described in detail below.

[0033] Reference below Figures 1-9 A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 may employ a method for manufacturing the semiconductor device 100. The semiconductor device 100 may be an RC-IGBT (reverse conducting-insulated gate bipolar transistor). In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is N-type and the second conductivity type is P-type. Furthermore, the first direction, the second direction, and the third direction are perpendicular to each other.

[0034] Combine Figure 1 As shown, the semiconductor device 100 according to the present invention may mainly include: a substrate 10, a drift layer 11 of a first conductivity type, a well layer 12 of a second conductivity type, a trench 13, a collector layer 14 of a second conductivity type, and a cathode layer 15 of a first conductivity type.

[0035] Among them, the semiconductor device 100 may include an active area 110 and a terminal area 120 arranged outside the active area 110. The active area 110 may mainly include an insulated gate bipolar transistor region 1101 and a fast recovery diode region 1102. The insulated gate bipolar transistor region 1101 is circumferentially arranged outside the fast recovery diode region 1102, so that the insulated gate bipolar transistor region 1101 and the fast recovery diode region 1102 can share the terminal area 120. In this way, the insulated gate bipolar transistor region 1101 can realize forward conduction of the semiconductor device 100, and the fast recovery diode region 1102 can realize reverse conduction of the semiconductor device 100, so that the semiconductor device 100 has both forward conduction and reverse conduction characteristics.

[0036] Specifically, the substrate 10 has a first main surface 101 and a second main surface 102 on the opposite side of the first main surface 101. The first main surface 101 and the second main surface 102 are spaced apart in the first direction. The drift layer 11 is arranged on the substrate 10 and is located between the first main surface 101 and the second main surface 102. The well layer 12 is arranged on the side of the drift layer 11 facing the first main surface 101. The upper surface of the well layer 12 constitutes a part of the first main surface 101. The collector layer 14 is arranged on the second main surface 102 and corresponds to the insulated gate bipolar transistor region 1101. The cathode layer 15 is arranged on the second main surface 102 and corresponds to the fast recovery diode region 1102. The well layer 12 includes multiple sub-well layers 121, and the sub-well layer 121 is located between two adjacent trenches 13.

[0037] Furthermore, a groove 13 is provided in the substrate 10, and the depth direction of the groove 13 penetrates the well layer 12 along the first direction from the first main surface 101 to reach the drift layer 11, and the length direction of the groove 13 extends in the second direction of the semiconductor device 100. There are multiple grooves 13, and the multiple grooves 13 are arranged at intervals in the third direction of the semiconductor device 100.

[0038] Part of the plurality of trenches 13 is located in the insulated gate bipolar transistor region 1101, and an oxide insulating layer 20 and polysilicon 30 are sequentially disposed within this portion of the trenches 13. This allows a gate to be formed in the first trench 13, and the plurality of first trenches 13 are electrically connected to the gate pad. Furthermore, another portion of the plurality of trenches 13 is located in the fast recovery diode region 1102, and an oxide insulating layer 20 and polysilicon 30 are disposed within this portion of the trenches 13. The second trenches 13 are electrically connected to the emitter metal layer 50.

[0039] Furthermore, an interlayer insulating film 40 is provided on the first main surface 101, and an emitter metal layer 50 is provided on the side of the interlayer insulating film 40 facing away from the first main surface 101. A collector metal layer 60 is also provided on the second main surface 102 of the substrate 10. The emitter metal layer 50 can not only serve as the emitter lead-in terminal of the insulated gate bipolar transistor region 1101, but also as the anode lead-in terminal of the fast recovery diode region 1102. The collector metal layer 60 can not only serve as the collector lead-in terminal of the insulated gate bipolar transistor region 1101, but also as the cathode lead-in terminal of the fast recovery diode region 1102.

[0040] It can be understood that the semiconductor device 100 realizes the integration of IGBT and FRD, which not only has the advantage of size reduction, but also has obvious advantages in working performance, such as high power density and high reliability.

[0041] However, the semiconductor device 100 may experience a voltage snapback phenomenon during forward conduction, ie, a negative resistance phenomenon caused by switching from a MOSFET mode to an IGBT mode, which may cause instability of the semiconductor device 100 .

[0042] Combine Figure 1 As shown, the one of the multiple sub-well layers 121 in the fast recovery diode region 1102 that is closest to the insulated gate bipolar transistor region 1101 is set as a boundary sub-well layer 1211. Compared with the boundary sub-well layer 1211, the one of the multiple sub-well layers 121 in the fast recovery diode region 1102 that is far away from the insulated gate bipolar transistor region 1101 is a non-boundary sub-well layer 1212. The depth of the boundary sub-well layer 1211 extends from the first main surface 101 along the first direction toward the cathode layer 15. The depth of the boundary sub-well layer 1211 is greater than the depth of the non-boundary sub-well layer 1212 and greater than the depth of the trench 13.

[0043] Specifically, when a low forward voltage is applied between the collector and the emitter, electrons in the IGBT region 1101 flow from the emitter to the collector, and electrons in the IGBT region 1101 may flow laterally toward the fast recovery diode region 1102. By providing the boundary sub-well layer 1211, the depth of the boundary sub-well layer 1211 is extended from the first main surface 101 along the first direction toward the cathode layer 15. The depth of the boundary sub-well layer 1211 is greater than the depth of the non-boundary sub-well layer 1212 and greater than the depth of the trench 13. In this way, the boundary sub-well layer 1211 can block laterally flowing electrons, thereby preventing the semiconductor device 100 from entering the MOSFET mode first, avoiding voltage foldback, and improving the stability of the semiconductor device 100. The lateral direction is perpendicular to the first direction.

[0044] Furthermore, through the boundary sub-well layer 1211, a lateral electric field can be formed in the fast recovery diode region 1102 between the boundary sub-well layer 1211 and the drift layer 11. This can introduce a lateral electric field effect into the original longitudinal space charge region, thereby enhancing the withstand voltage of the fast recovery diode region 1102, making the withstand voltage of the fast recovery diode region 1102 higher than that of the insulated gate bipolar transistor region 1101. This can facilitate the operation of the fast recovery diode region 1102 in scenarios with fast switching speeds and large surge currents, preventing the fast recovery diode region 1102 from being damaged before the insulated gate bipolar transistor region 1101, and improving the reliability of the semiconductor device 100. The longitudinal direction is the same as the first direction.

[0045] Therefore, by extending the depth of the boundary sub-well layer 1211 from the first main surface 101 along the first direction toward the cathode layer 15, the depth of the boundary sub-well layer 1211 is greater than the depth of the non-boundary sub-well layer 1212 and greater than the depth of the groove 13. This not only enables the boundary sub-well layer 1211 to block the laterally flowing electrons and avoid the voltage foldback phenomenon, but also enhances the withstand voltage of the fast recovery diode region 1102, which is beneficial for the fast recovery diode region 1102 to operate in a scenario with fast switching speed and large surge current.

[0046] Combine Figure 1 As shown, the boundary sub-well layer 1211 extends from the first main surface 101 along the first direction to the cathode layer 15 and contacts the cathode layer 15 .

[0047] Specifically, it is understood that the length of the boundary sub-well layer 1211 in the first direction affects the blocking effect of the boundary sub-well layer 1211 on laterally flowing electrons. By extending the boundary sub-well layer 1211 from the first main surface 101 along the first direction to the cathode layer 15 and contacting the cathode layer 15, when a low positive voltage is applied between the collector and the emitter, the boundary sub-well layer 1211 can completely block laterally flowing electrons, thereby more effectively and reliably preventing the semiconductor device 100 from initially entering the MOSFET mode, avoiding voltage foldback, and improving the stability of the semiconductor device 100.

[0048] Furthermore, it is understood that the length of the boundary sub-well layer 1211 in the first direction affects the strength of the introduced lateral electric field effect. By extending the boundary sub-well layer 1211 from the first main surface 101 along the first direction to the cathode layer 15 and contacting the cathode layer 15, a stronger lateral electric field effect can be introduced into the original longitudinal space charge region, thereby effectively enhancing the withstand voltage of the fast recovery diode region 1102. This further facilitates the fast recovery diode region 1102 to operate in scenarios with fast switching speeds and large surge currents, preventing the fast recovery diode region 1102 from being damaged before the insulated gate bipolar transistor region 1101, and improving the reliability of the semiconductor device 100.

[0049] Furthermore, the boundary sub-well layer 1211 extends from the first main surface 101 along the first direction to the cathode layer 15 and contacts the cathode layer 15. In this way, the boundary sub-well layer 1211 and the cathode layer 15 can directly form a PN junction, thereby facilitating forward conduction of the fast recovery diode region 1102. In this case, when the collector-emitter bias of the IGBT region 1101 is reversed, the easier it is for the fast recovery diode region 1102 to conduct forward, which helps reduce the reverse bias pressure of the IGBT region 1101, thereby partially protecting the IGBT region 1101, preventing the IGBT region 1101 from being in a reverse biased state for a long time, and improving the reliability of the semiconductor device 100.

[0050] Combine Figure 1 As shown, the depth of the drift layer 11 is D1, and the depth of the boundary sub-well layer 1211 is D2. D1 and D2 satisfy the relationship: 1 / 2 < D2 / D1 ≤ 1. Specifically, the length of the boundary sub-well layer 1211 in the first direction affects the blocking effect of the boundary sub-well layer 1211 on laterally flowing electrons, and the length of the boundary sub-well layer 1211 in the first direction affects the intensity of the introduced lateral electric field effect.

[0051] By setting the ratio of the depth of the drift layer 11 to the depth of the boundary sub-well layer 1211 to be greater than 1 / 2, the depth of the boundary sub-well layer 1211 can be avoided from being too small, and the boundary sub-well layer 1211 can be ensured to have a better blocking effect on laterally flowing electrons and introduce a stronger lateral electric field effect, thereby effectively avoiding the voltage foldback phenomenon of the semiconductor device 100, ensuring the stability of the semiconductor device 100, and ensuring the withstand voltage of the fast recovery diode region 1102, thereby ensuring the reliability of the semiconductor device 100.

[0052] By setting the ratio of the depth of the drift layer 11 to the depth of the boundary sub-well layer 1211 to no more than 1, the boundary sub-well layer 1211 can be prevented from contacting the collector layer 14, thereby ensuring normal switching of the semiconductor device 100 and ensuring normal operation of the semiconductor device 100.

[0053] Combine Figure 1 As shown, the semiconductor device 100 may further include a field-stop layer 16 of the first conductivity type, located between the collector layer 14 and the drift layer 11. The cathode layer 15 is disposed adjacent to the drift layer 11 in a first direction. The doping concentration of the field-stop layer 16 is higher than that of the drift layer 11. As such, the field-stop layer 16 not only helps control and limit the distribution of the electric field in the reverse bias state of the insulated gate bipolar transistor region 1101, thereby improving the withstand voltage, but also reduces switching losses, improves thermal stability, and optimizes dynamic characteristics, thereby enhancing the performance of the semiconductor device 100.

[0054] Combine Figure 1 As shown, the depth of at least a portion of the boundary sub-well layer 1211 that is closer to the insulated gate bipolar transistor region 1101 extends from the first main surface 101 along the first direction to the cathode layer 15. In this way, it can be ensured that the boundary sub-well layer 1211 extends from the first main surface 101 along the first direction to the cathode layer 15 and is located at the intersection of the insulated gate bipolar transistor region 1101 and the fast recovery diode region 1102, thereby ensuring that the boundary sub-well layer 1211 can block the electrons flowing laterally in the insulated gate bipolar transistor region 1101 at the intersection of the insulated gate bipolar transistor region 1101 and the fast recovery diode region 1102, thereby more reliably preventing the semiconductor device 100 from entering the MOSFET mode first, avoiding the voltage foldback phenomenon, and improving the stability of the semiconductor device 100.

[0055] Further, combined with Figure 1 As shown, the width of the boundary sub-well layer 1211 in the third direction is D3, and the width of the portion of the boundary sub-well layer 1211 extending toward the cathode layer 15 in the third direction is D4, and D3 and D4 satisfy the relationship: 1 / 3≤D4 / D3≤1.

[0056] Specifically, it can be understood that the width of the boundary sub-well layer 1211 in the third direction not only affects the blocking effect of the boundary sub-well layer 1211 on laterally flowing electrons and the strength of the introduced lateral electric field effect, but also affects the working performance of the fast recovery diode region 1102.

[0057] By setting the ratio of the width of the portion of the boundary sub-well layer 1211 extending toward the cathode layer 15 in the third direction to the width of the boundary sub-well layer 1211 in the third direction to be no less than 1 / 3, it is possible to avoid the width of the portion of the boundary sub-well layer 1211 extending toward the cathode layer 15 in the third direction being too small, thereby ensuring that the boundary sub-well layer 1211 has a better blocking effect on laterally flowing electrons and introduces a stronger lateral electric field effect, thereby effectively avoiding the voltage foldback phenomenon of the semiconductor device 100, ensuring the stability of the semiconductor device 100, and ensuring the withstand voltage of the fast recovery diode region 1102, thereby ensuring the reliability of the semiconductor device 100.

[0058] By setting the ratio of the width of the portion of the boundary sub-well layer 1211 extending toward the cathode layer 15 in the third direction to the width of the boundary sub-well layer 1211 in the third direction to be no greater than 1, it is possible to avoid the width of the portion of the boundary sub-well layer 1211 extending toward the cathode layer 15 in the third direction being too large, thereby avoiding reducing other performance characteristics of the fast recovery diode region 1102.

[0059] In this way, by setting the ratio of the width of the portion of the boundary sub-well layer 1211 extending toward the cathode layer 15 in the third direction to the width of the boundary sub-well layer 1211 in the third direction within a reasonable range, the various performances of the semiconductor device 100 can be more balanced, thereby improving the product competitiveness of the semiconductor device 100.

[0060] Combine Figure 2-Figure 9 As shown, the method for manufacturing the semiconductor device 100 according to the present invention can be applied to the above-mentioned semiconductor device 100 .

[0061] Combine Figure 2-Figure 7 As shown, the manufacturing method of the semiconductor device 100 may mainly include the following steps: preparing a substrate 10, injecting a first conductive type dopant into the substrate 10 to form a drift layer 11; etching a groove 13 in the substrate 10, and growing an oxide insulating layer 20 on the surface of the substrate 10 and the groove 13; depositing polysilicon 30 on the surface of the oxide insulating layer 20; etching the polysilicon 30; injecting a second conductive type dopant into the substrate 10 to form a plurality of sub-well layers 121, the plurality of sub-well layers 121 including but not limited to a boundary sub-well layer 1211 and a non-boundary sub-well layer 1212, and injecting a first conductive type dopant on both sides of the sub-well layer 121 corresponding to the groove 13 to form a source region 17, wherein the depth of the boundary sub-well layer 1211 is greater than the depth of the non-boundary sub-well layer 1212 and greater than the depth of the groove 13.

[0062] Specifically, when manufacturing the semiconductor device 100, a substrate 10 can be provided first. The substrate 10 has a first main surface 101 and a second main surface 102. A first guide type dopant is implanted into a portion of the substrate 10 adjacent to the first main surface 101 to form a drift layer 11 of a first conductive type. Then, a groove 13 is etched in the drift layer 11 so that the depth direction of the groove 13 penetrates the well layer 12 from the first main surface 101 along the first direction to reach the drift layer 11. The length direction of the groove 13 extends in the second direction of the semiconductor device 100. There are multiple grooves 13, and the multiple grooves 13 are spaced apart in the third direction of the semiconductor device 100. After completing processes such as rounding and oxide layer growth, an oxide insulating layer 20 is grown on the surface of the substrate 10 and the groove 13.

[0063] Then, polysilicon 30 is deposited on the surface of the oxide insulating layer 20 and etched to locate the polysilicon 30 in the trench 13 . Then, second conductivity type dopants are implanted into the substrate 10 to form a plurality of second conductivity type sub-well layers 121 .

[0064] Among them, multiple sub-well layers 121 include but are not limited to boundary sub-well layers 1211 and non-boundary sub-well layers 1212, and first conductive type dopants are injected on both sides of the trench 13 corresponding to the sub-well layer 121 to form a source region 17, wherein the depth of the boundary sub-well layer 1211 is greater than the depth of the non-boundary sub-well layer 1212 and greater than the depth of the trench 13.

[0065] In this way, the formation process of the boundary sub-well layer 1211 can be made compatible with the formation process of the original well layer 12 of the semiconductor device 100 , thereby eliminating the need for additional process steps and saving process steps and time costs.

[0066] Furthermore, a second conductive type dopant is injected into the substrate 10 to form a plurality of sub-well layers 121, including but not limited to a boundary sub-well layer 1211 and a non-boundary sub-well layer 1212, and a first conductive type dopant is injected on both sides of the trench 13 corresponding to the sub-well layer 121 to form a source region 17, wherein the step of the depth of the boundary sub-well layer 1211 being greater than the depth of the non-boundary sub-well layer 1212 and greater than the depth of the trench 13 may specifically include the following steps: injecting a second conductive type dopant between two adjacent trenches 13 to form a plurality of sub-well layers 121; deeply injecting a second conductive type dopant between the two trenches 13 closest to the insulated gate bipolar transistor region 1101 to form a boundary sub-well layer 1211; and injecting a first conductive type dopant on both sides of the trench 13 corresponding to the sub-well layer 121 of the insulated gate bipolar transistor region 1101 to form a source region 17.

[0067] Specifically, when the second conductive type dopant is injected into the substrate 10 to form multiple second conductive type sub-well layers 121, the second conductive type dopant can be deeply injected between the two trenches 13 closest to the insulated gate bipolar transistor region 1101 according to the position of the sub-well layer 121, and the second conductive type dopant can be shallowly injected between the other two trenches 13, thereby forming a boundary sub-well layer 1211 and a non-boundary sub-well layer 1212, which can make the formation of the boundary sub-well layer 1211 and the non-boundary sub-well layer 1212 simpler and more convenient.

[0068] It should be noted that the boundary sub-well layer 1211 may be deeply implanted in the first direction until the boundary sub-well layer 1211 may contact the cathode layer 15 formed by implantation later in the first direction.

[0069] Furthermore, first conductive type dopants are implanted on both sides of the trench 13 corresponding to the sub-well layer 121 of the IGBT region 1101 to form source regions 17 , thereby ensuring the normal operation of the IGBT region 1101 .

[0070] Combine Figure 2 ,as well as Figure 8 and Figure 9 As shown, a second conductive type dopant is injected into the substrate 10 to form a plurality of sub-well layers 121, wherein the plurality of sub-well layers 121 include but are not limited to a boundary sub-well layer 1211 and a non-boundary sub-well layer 1212, and a first conductive type dopant is injected on both sides of the trench 13 corresponding to the sub-well layer 121 to form a source region 17, wherein the depth of the boundary sub-well layer 1211 is greater than the depth of the non-boundary sub-well layer 1212 and greater than the depth of the trench 13. After the step, the manufacturing method of the semiconductor device 100 may further include: depositing an interlayer insulating film 40 on the surface of the oxidized insulating layer 20 and the polysilicon 30, and etching contact holes 41 on the surfaces of the interlayer insulating film 40 and the oxidized insulating layer 20; and setting an emitter metal layer 50 on the upper surface of the interlayer insulating film 40 and the contact hole 41.

[0071] Specifically, by depositing an interlayer insulating film 40 on the oxidized insulating layer 20 and the polysilicon 30, the interlayer insulating film 40 can protect the oxidized insulating layer 20 and the polysilicon 30, thereby ensuring the first main surface 101 of the substrate 10 is secure and reducing the risk of damage to the semiconductor device 100. Furthermore, by etching contact holes 41 on the surfaces of the interlayer insulating film 40 and the oxidized insulating layer 20, and then providing an emitter metal layer 50 on the upper surface of the interlayer insulating film 40 and at the contact holes 41, it is possible to facilitate contact between the emitter metal layer 50 and the source region 17 through the contact holes 41, thereby ensuring the normal operation of the semiconductor device 100.

[0072] Combine Figure 2 and Figure 9As shown, after the step of setting the emitter metal layer 50 on the upper surface of the interlayer insulating film 40 and the contact hole 41, the manufacturing method of the semiconductor device 100 may also include: injecting the first conductive type dopant and the second conductive type dopant in sequence on the side of the drift layer 11 facing the second main surface 102 to form a field stop layer 16 and a collector layer 14; injecting the first conductive type dopant into the collector layer 14 to form a cathode layer 15; and depositing the collector metal layer 60 on the second main surface 102, thereby completing the process of the second main surface 102 of the substrate 10.

[0073] Specifically, a field stop layer 16 and a collector layer 14 are formed by sequentially injecting a first conductive type dopant and a second conductive type dopant into the side of the drift layer 11 facing the second main surface 102, and further, a first conductive type dopant is injected into the collector layer 14 to form a cathode layer 15, and in the third direction, the boundary sub-well layer 1211 is adjacent to the position where the cathode layer 15 contacts the collector layer 14, so that the area corresponding to the collector layer 14 is the insulated gate bipolar transistor area 1101, and the area corresponding to the cathode layer 15 is the fast recovery diode area 1102.

[0074] Furthermore, a collector metal layer 60 is deposited on the second main surface 102 , and the fast recovery diode region 1102 and the insulated gate bipolar transistor region 1101 share the collector metal layer 60 .

[0075] In this way, the semiconductor device 100 can be manufactured and the semiconductor device 100 can operate better. Furthermore, the manufacturing of the semiconductor device 100 is compatible with existing processes without adding additional process steps, thus saving process steps and time costs.

[0076] It should be noted that other structures and operations of the semiconductor device 100 according to the embodiment of the present invention are well known to those skilled in the art and will not be described in detail here.

[0077] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0078] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0079] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a first direction; a drift layer of a first conductivity type, the drift layer being disposed on the substrate and located between the first main surface and the second main surface; a well layer of a second conductivity type, the well layer being provided on a side of the drift layer facing the first main surface, wherein an upper surface of the well layer constitutes a portion of the first main surface; a trench, wherein a depth direction of the trench penetrates the well layer along a first direction from the first main surface to the drift layer, and a length direction of the trench extends in a second direction of the semiconductor device, wherein the trench is multiple and the multiple trenches are spaced apart in a third direction of the semiconductor device, wherein the first direction, the second direction, and the third direction are perpendicular to each other; a collector layer of a second conductivity type, the semiconductor device having a fast recovery diode region and an insulated gate bipolar transistor region, the insulated gate bipolar transistor region being arranged around the outside of the fast recovery diode region, and the collector layer being arranged on the second main surface and corresponding to both the insulated gate bipolar transistor regions; a cathode layer of a first conductivity type, the cathode layer being disposed on the second main surface and corresponding to the fast recovery diode region, the well layer comprising a plurality of sub-well layers, the sub-well layer being located between two adjacent trenches, the one of the plurality of sub-well layers in the fast recovery diode region that is closest to the insulated gate bipolar transistor region being a boundary sub-well layer, and the plurality of sub-well layers in the fast recovery diode region that is farther away from the insulated gate bipolar transistor region being a non-boundary sub-well layer compared to the boundary sub-well layer, the depth of the boundary sub-well layer extending from the first main surface along a first direction toward the cathode layer, the depth of the boundary sub-well layer being greater than the depth of the non-boundary sub-well layer and greater than the depth of the trench; The depth of the drift layer is D1, the depth of the boundary sub-well layer is D2, and D1 and D2 satisfy the relationship: 1 / 2<D2 / D1≤1; The width of the boundary sub-well layer in the third direction is D3, and the width of the portion of the boundary sub-well layer extending toward the cathode layer in the third direction is D4. D3 and D4 satisfy the relationship: 1 / 3≤D4 / D3≤1.

2. The semiconductor device according to claim 1, wherein The boundary sub-well layer extends from the first main surface along a first direction to the cathode layer and contacts the cathode layer.

3. The semiconductor device according to claim 1, wherein Also includes: A field stop layer of a first conductivity type is located between the collector layer and the drift layer. The cathode layer is disposed adjacent to the drift layer in a first direction.

4. The semiconductor device according to claim 1, wherein A depth of at least a portion of the boundary sub-well layer closer to the IGBT region extends from the first main surface along the first direction to the cathode layer.

5. A method for manufacturing a semiconductor device, suitable for manufacturing the semiconductor device according to any one of claims 1 to 4, characterized in that: The following steps are involved: preparing a substrate, and implanting a first conductive type dopant into the substrate to form a drift layer; Etching a groove in the substrate and growing an oxide insulating layer on the surfaces of the substrate and the groove; depositing polysilicon on the surface of the oxide insulating layer; etching the polysilicon; A second conductive type dopant is injected into the substrate to form a plurality of sub-well layers, the plurality of sub-well layers including a boundary sub-well layer and a non-boundary sub-well layer, and a first conductive type dopant is injected into both sides of the sub-well layer corresponding to the trench to form a source region, wherein the depth of the boundary sub-well layer is greater than the depth of the non-boundary sub-well layer and greater than the depth of the trench.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The step of implanting a second conductive type dopant into the substrate to form a plurality of sub-well layers, the plurality of sub-well layers including a boundary sub-well layer and a non-boundary sub-well layer, and implanting a first conductive type dopant into the sub-well layers on both sides corresponding to the trench to form a source region, wherein the depth of the boundary sub-well layer is greater than the depth of the non-boundary sub-well layer and greater than the depth of the trench comprises: implanting a second conductive type dopant between two adjacent trenches to form a plurality of sub-well layers; Deeply implanting a second conductive type dopant between two trenches closest to the insulated gate bipolar transistor region to form a boundary sub-well layer; Dopants of the first conductive type are implanted into both sides of the trench corresponding to the sub-well layer in the insulated gate bipolar transistor region to form a source region.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: After the step of implanting a second conductive type dopant into the substrate to form a plurality of sub-well layers, the plurality of sub-well layers including boundary sub-well layers and non-boundary sub-well layers, and implanting a first conductive type dopant into the sub-well layers on both sides corresponding to the trench to form a source region, wherein the depth of the boundary sub-well layer is greater than the depth of the non-boundary sub-well layer and greater than the depth of the trench, the method further comprises: Depositing an interlayer insulating film on the surfaces of the oxidized insulating layer and the polysilicon, and etching contact holes on the surfaces of the interlayer insulating film and the oxidized insulating layer; An emitter metal layer is provided on the upper surface of the interlayer insulating film and at the contact hole.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: After the step of providing an emitter metal layer on the upper surface of the interlayer insulating film and the contact hole, the method further includes: sequentially implanting a first conductivity type dopant and a second conductivity type dopant into a side of the drift layer facing the second main surface to form a field stop layer and a collector layer; Implanting a first conductive type dopant into the collector layer to form a cathode layer; A collector metal layer is deposited on the second major surface.

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