Semiconductor structure and method of fabricating the same

Abstract

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a source electrode, a gate electrode and a drain electrode stacked on the substrate, a first isolation layer between the gate electrode and the drain electrode, a second isolation layer between the first isolation layer and the drain electrode, a channel layer penetrating through the gate electrode, the first isolation layer and the second isolation layer, the channel layer being arranged on the source electrode, a gate dielectric layer between the gate electrode and the channel layer, an insulating layer arranged on the inner side of the channel layer, a contact pad arranged on the insulating layer, and a content of nitrogen component of the second isolation layer being greater than a content of nitrogen component of the first isolation layer. The second isolation layer protects the first isolation layer in the etching or grinding process, avoids the first isolation layer from being damaged, protects the integrity of the semiconductor structure, and is conducive to improving the product yield of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] With the development of semiconductor technology, integrated circuits are developing towards miniaturization, and it is required that the corresponding integrated circuits have higher integration density and smaller feature size, that is, as many semiconductor devices as possible are arranged on a smaller substrate to obtain higher performance.

[0003] However, the size miniaturization of semiconductor devices has almost reached the limit, and the size miniaturization of semiconductor devices increases the difficulty of manufacturing processes, which may affect the performance of semiconductor devices and product yield. SUMMARY

[0004] Therefore, the present application provides a semiconductor structure and a manufacturing method thereof.

[0005] In a first aspect, the present application provides a semiconductor structure, comprising:

[0006] a substrate;

[0007] a source electrode, a gate electrode and a drain electrode stacked on the substrate;

[0008] a first isolation layer arranged between the gate electrode and the drain electrode;

[0009] a second isolation layer arranged between the first isolation layer and the drain electrode;

[0010] a channel layer penetrating through the gate electrode, the first isolation layer and the second isolation layer, the channel layer being arranged on the source electrode;

[0011] a gate dielectric layer arranged between the gate electrode and the channel layer;

[0012] an insulating layer arranged on the inner side of the channel layer;

[0013] a contact pad arranged on the insulating layer;

[0014] The content of nitrogen component of the second isolation layer is greater than the content of nitrogen component of the first isolation layer.

[0015] Optionally, the top surface of the second isolation layer directly contacts the bottom surface of the drain electrode.

[0016] Optionally, the semiconductor structure further comprises:

[0017] a third isolation layer arranged between the first isolation layer and the gate electrode, the material of the third isolation layer being the same as the material of the second isolation layer.

[0018] Optionally, an isolation sidewall is further included between adjacent drain electrodes, a bottom surface of the isolation sidewall is lower than a bottom surface of the second isolation layer.

[0019] Optionally, a top surface of the insulating layer is lower than a bottom surface of the second isolation layer.

[0020] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0021] providing a substrate;

[0022] forming a source electrode on the substrate;

[0023] forming a gate electrode on the source electrode;

[0024] forming a first isolation layer and a second isolation layer on the gate electrode in sequence, a nitrogen component content of the second isolation layer is greater than a nitrogen component content of the first isolation layer;

[0025] forming a channel hole, the channel hole penetrates through the gate electrode, the first isolation layer and the second isolation layer, and exposes part of the gate electrode;

[0026] forming a gate dielectric layer, the gate dielectric layer covers the gate electrode exposed by the channel hole;

[0027] forming a channel layer, the channel layer covers the gate dielectric layer;

[0028] forming an insulating layer, the insulating layer covers the channel layer and fills the channel hole, and a top surface of the insulating layer is lower than a top surface of the channel layer;

[0029] forming a contact pad on the insulating layer, a top surface of the contact pad is at the same level as a top surface of the second isolation layer;

[0030] forming a drain electrode on the contact pad.

[0031] Optionally, before the first isolation layer and the second isolation layer are formed on the gate electrode in sequence, the method further comprises:

[0032] forming a third isolation layer, the third isolation layer is arranged between the first isolation layer and the gate electrode, and a material of the third isolation layer is the same as a material of the second isolation layer.

[0033] Optionally, the forming of the insulating layer comprises:

[0034] grinding to remove the insulating layer and the channel layer on a top surface of the second isolation layer, so that a top surface of the remaining insulating layer, a top surface of the channel layer and a top surface of the second isolation layer are at the same level;

[0035] etching the insulating layer to a top surface lower than a top surface of the channel layer.

[0036] Optionally, a top surface of the insulating layer after etching is lower than a bottom surface of the second isolation layer.

[0037] Optionally, the manufacturing method further comprises:

[0038] forming an isolation sidewall covering sidewalls of the drain and filling between adjacent drains, a bottom surface of the isolation sidewall being lower than a bottom surface of the second isolation layer.

[0039] The semiconductor structure and the manufacturing method thereof of the present disclosure set the second isolation layer with a higher nitrogen component between the first isolation layer and the drain, which is used to protect the first isolation layer in the etching or grinding process, avoid damaging the first isolation layer, protect the integrity of the semiconductor structure, and facilitate improving the product yield of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0041] Figure 1 A structural schematic diagram of a semiconductor structure provided in an embodiment;

[0042] Figure 2 A process flow diagram of a manufacturing method of a semiconductor structure provided in an embodiment;

[0043] Figure 3 A structural schematic diagram after forming a source and a gate on a substrate in an embodiment;

[0044] Figure 4 A structural schematic diagram after forming a third insulating layer, a first insulating layer and a second insulating layer in an embodiment;

[0045] Figure 5 A structural schematic diagram after forming a first via in an embodiment;

[0046] Figure 6 A structural schematic diagram after forming a channel hole and a gate dielectric layer in an embodiment;

[0047] Figure 7 A structural schematic diagram after forming a channel layer in an embodiment;

[0048] Figure 8 FIG. 10 is a schematic diagram of a structure after forming an insulating layer in an embodiment;

[0049] Figure 9 FIG. 11 is a schematic diagram of a structure after removing the insulating layer and the channel layer on the top surface of the second insulating layer in an embodiment;

[0050] Figure 10 FIG. 12 is a schematic diagram of a structure after etching the insulating layer to a top surface lower than the top surface of the channel layer in an embodiment;

[0051] Figure 11 FIG. 13 is a schematic diagram of a structure after forming a contact pad in an embodiment;

[0052] Figure 12 FIG. 14 is a schematic diagram of a structure after forming a first metal layer in an embodiment;

[0053] Figure 13 FIG. 15 is a schematic diagram of a structure after forming an isolation groove to divide the first metal layer into individual drain electrodes in an embodiment;

[0054] Figure 14 FIG. 16 is a schematic diagram of a structure after forming a nitride layer in an embodiment;

[0055] Figure 15 FIG. 17 is a schematic diagram of a structure of a semiconductor structure after forming an insulating sidewall in an embodiment.

[0056] BRIEF DESCRIPTION OF DRAWINGS

[0057] 10, substrate; 11, source; 111, source metal layer; 1111, first source barrier layer; 1112, source conductive layer; 1113, second source barrier layer; 112, source contact layer; 12, gate; 13, channel layer; 14, gate dielectric layer; 15, insulating layer; 161, contact pad; 162, drain; 162a, first metal layer; 21, first insulating layer; 22, second insulating layer; 23, third insulating layer; 30, channel hole; 31, first via; 41, first dielectric layer; 42, second dielectric layer; 43, insulating sidewall; 44, isolation groove. DETAILED DESCRIPTION

[0058] In order to facilitate the understanding of the present application, a more complete understanding of the present application can be had by reference to the following description and the accompanying drawings. In the Figures, preferred embodiments of the application are disclosed. However, the application can be realized in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. The embodiments are presented in the best mode to enable those skilled in the art to make and use the application.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0060] It is to be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.).

[0061] According to an exemplary embodiment, the present embodiment provides a semiconductor structure, as shown in Figure 1 The semiconductor structure includes a substrate 10, a source 11, a gate 12 and a drain 162 stacked on the substrate 10, and a first isolation layer 21, a second isolation layer 22, a channel layer 13, an insulating layer 15 and a contact pad 161; the source 11, the gate 12 and the drain 162 are sequentially stacked on the substrate 10 and do not directly contact each other. The first isolation layer 21 is arranged between the gate 12 and the drain 162; the second isolation layer 22 is arranged between the first isolation layer 21 and the drain 162; the channel layer 13 penetrates through the gate 12, the first isolation layer 21 and the second isolation layer 22, and is arranged on the source 11; the gate dielectric layer 14 is arranged between the gate 12 and the channel layer 13; the insulating layer 15 is arranged on the inner side of the channel layer 13; the contact pad 161 is arranged on the insulating layer 15; the content of nitrogen component of the second isolation layer 22 is greater than that of the first isolation layer 21.

[0062] The substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon-on-insulator substrate, and the like.

[0063] The second isolation layer 22 has a higher content of nitrogen component than the first isolation layer 21, and has a higher etching resistance than the first isolation layer 21. The first isolation layer 21 is arranged between the gate 12 and the drain 162, and is used for electrical isolation between the gate 12 and the drain 162. The second isolation layer 22 is arranged between the first isolation layer 21 and the drain 162, and is used for protecting the first isolation layer 21 during etching or grinding of the semiconductor structure, so as to avoid damage to the first isolation layer 21, protect the integrity of the semiconductor structure, and improve the yield of the semiconductor structure.

[0064] In some embodiments, the top surface of the second isolation layer 22 directly contacts the bottom surface of the drain 162. The second isolation layer 22 has better connection stability, and the contact between the second isolation layer 22 and the bottom surface of the drain 162 increases the stability of the semiconductor structure, and reduces the risk of damage, delamination, and falling off of the semiconductor structure.

[0065] For example, the material of the second isolation layer 22 can include at least one of nitrogen-doped silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiNO), silicon oxycarbide (SiNC), silicon oxynitride (SiON), silicon oxycarbide nitride (SiOCN), silicon boron nitride (SiBN), silicon oxycarbide nitride (SiOBN), and silicon oxycarbide (SiOC).

[0066] The material of the first isolation layer 21 can include silicon oxide, silicon oxycarbide, or other high-density plasma (HDP) oxide.

[0067] In one example, the material of the first isolation layer 21 includes silicon oxide, and the material of the second isolation layer 22 includes silicon nitride. In another example, the material of the first isolation layer 21 includes silicon oxide, and the material of the second isolation layer 22 includes silicon oxynitride. In yet another example, the material of the first isolation layer 21 includes silicon oxycarbide, and the material of the second isolation layer 22 includes silicon nitride.

[0068] The channel layer 13 penetrates the gate 12, the first isolation layer 21, and the second isolation layer 22, and has a bottom surface in contact with the source 11. The channel layer 13 has a “U”-shaped opening facing away from the substrate 10. The insulating layer 15 and the contact pad 161 are sequentially arranged in the “U”-shaped opening of the channel layer 13 in a direction away from the substrate 10. The insulating layer 15 is arranged between the contact pad 161 and the bottom surface of the channel layer 13, so as to avoid short circuiting of the contact pad 161 to the source 11 through the channel layer 13.

[0069] For example, the material of the channel layer 13 can include doped polysilicon.

[0070] In one example, the source 11 includes a source metal layer 111 and a source contact layer 112 which are sequentially stacked on the substrate 10. In one example, the source metal layer 111 includes a first source barrier layer 1111, a source conductive layer 1112 and a second source barrier layer 1113 which are sequentially stacked between the substrate 10 and the source contact layer 112.

[0071] The insulating layer 15 covers the bottom surface of the channel layer 13 and part of the inner sidewall of the channel layer 13, and the contact pad 161 covers the top surface of the insulating layer 15 and another part of the inner sidewall of the channel layer 13.

[0072] In some embodiments, please continue to refer to Figure 1 The top surface of the insulating layer 15 is lower than the bottom surface of the second isolation layer 22. In other words, the bottom surface of the contact pad 161 is lower than the bottom surface of the second isolation layer 22.

[0073] The top surface of the contact pad 161 is in contact with the drain 162, and the drain 162 is in contact with the channel layer 13 through the contact pad 161. The contact area of the contact pad 161 with the channel layer 13 is larger and the contact resistance is smaller, which can reduce the contact resistance between the drain 162 and the channel layer 13, reduce the overall resistance of the semiconductor structure, and improve the electrical performance and response speed of the semiconductor structure.

[0074] The drain 162 includes a first metal layer, and the material of the contact pad 161 includes a doped semiconductor material. In one example, the material of the drain 162 includes tungsten or a compound of tungsten, and the material of the contact pad 161 includes doped polysilicon.

[0075] In one example, the material of the drain 162 includes tungsten, and the material of the contact pad 161 includes doped polysilicon.

[0076] The gate 12 continuously surrounds and covers part of the outer sidewall of the channel layer 13, and the gate 12 is separated from the outer sidewall of the channel layer 13 by the gate dielectric layer 14. The material of the gate 12 includes tungsten or a compound of tungsten, and the material of the gate dielectric layer 14 includes an oxide such as silicon oxide, silicon nitride, silicon oxynitride or a high-k material.

[0077] In some embodiments, please continue to refer to Figure 1 The semiconductor structure further includes a third isolation layer 23 which is disposed between the first isolation layer 21 and the gate 12, and the material of the third isolation layer 23 is the same as that of the second isolation layer 22.

[0078] In this way, the third isolation layer 23, the first isolation layer 21 and the second isolation layer 22 are sequentially stacked between the gate 12 and the drain 162, the third isolation layer 23 is in contact with the gate 12, the filling property and the connection stability of the third isolation layer 23 are better than those of the first isolation layer 21, the first isolation layer 21 is connected with the gate 12 through the third isolation layer 23, the connection strength between the first isolation layer 21 and the gate 12 is enhanced, the stability of the semiconductor structure is increased, and the risk of damage, delamination and peeling of the semiconductor structure is reduced.

[0079] For example, the material of the first isolation layer 21 includes silicon oxide, the material of the second isolation layer 22 includes silicon nitride, and the material of the third isolation layer 23 includes silicon nitride.

[0080] In some embodiments, please continue to refer to Figure 1 The semiconductor structure further includes an isolation side wall 43 between adjacent drains 162, and a bottom surface of the isolation side wall 43 is lower than a bottom surface of the second isolation layer 22.

[0081] The material of the isolation side wall 43 has a dielectric constant lower than that of the material of the second isolation layer 22. For example, the material of the isolation side wall 43 can include silicon oxide.

[0082] The isolation side wall 43 extends towards the substrate 10, and the isolation side wall 43 penetrates the second isolation layer 22 and extends into the first isolation layer 21. In this way, the proportion of the second isolation layer 22 between devices is reduced, the dielectric constant of the inter-device isolation medium is reduced, which is beneficial to reduce the parasitic capacitance of the semiconductor structure and improve the product quality and electrical performance.

[0083] In some embodiments, the first isolation layer 21 and the second isolation layer 22 are stacked between the gate 12 and the drain 162, the isolation side wall 43 extends to the first isolation layer 21, a bottom surface of the isolation side wall 43 is higher than a bottom surface of the first isolation layer 21, or the bottom surface of the isolation side wall 43 is at the same level as the bottom surface of the first isolation layer 21.

[0084] In another embodiment, the third isolation layer 23, the first isolation layer 21 and the second isolation layer 22 are stacked between the gate 12 and the drain 162. The isolation side wall 43 extends to the first isolation layer 21, and a bottom surface of the isolation side wall 43 is higher than a bottom surface of the first isolation layer 21.

[0085] According to an exemplary embodiment, the present embodiment provides a manufacturing method of a semiconductor structure, as shown in Figure 2 The manufacturing method of the semiconductor structure includes the following steps:

[0086] Step S10: providing a substrate 10;

[0087] Step S20: forming a source 11 on the substrate 10;

[0088] Step S30: Forming the gate 12 on the source 11;

[0089] Step S40: Forming the first isolation layer 21 and the second isolation layer 22 on the gate 12 in sequence, the content of the nitrogen component of the second isolation layer 22 is greater than that of the first isolation layer 21;

[0090] Step S50: Forming the channel hole 30, the channel hole 30 penetrates the gate 12, the first isolation layer 21 and the second isolation layer 22, and the channel hole 30 exposes part of the gate 12;

[0091] Step S60: Forming the gate dielectric layer 14, the gate dielectric layer 14 covers the gate 12 exposed by the channel hole 30;

[0092] Step S70: Forming the channel layer 13, the channel layer 13 covers the gate dielectric layer 14;

[0093] Step S80: Forming the insulating layer 15, the insulating layer 15 covers the channel layer 13 and fills the channel hole 30, and the top surface of the insulating layer 15 is lower than the top surface of the channel layer 13;

[0094] Step S90: Forming the contact pad 161 on the insulating layer 15, the top surface of the contact pad 161 is at the same horizontal height as the top surface of the second isolation layer 22;

[0095] Step S100: Forming the drain 162 on the contact pad 161.

[0096] The manufacturing method of the semiconductor structure of the embodiment forms the first isolation layer 21 and the second isolation layer 22 on the gate 12 in sequence, the content of the nitrogen component of the second isolation layer 22 is greater than that of the first isolation layer 21, the etching resistance of the second isolation layer 22 is greater than that of the first isolation layer 21, the second isolation layer 22 protects the first isolation layer 21, avoids the first isolation layer 21 from being etched and even the gate 12 from being damaged in the process of forming the channel hole 30, avoids the short circuit between the filled conductive material and the gate 12, ensures the structure and performance of the formed semiconductor structure, is conducive to improving the product yield, and is suitable for the development demand of semiconductor structure to smaller feature size.

[0097] Next, the manufacturing method of the semiconductor structure of the embodiment will be described in detail. Figures 3-15 The manufacturing method of the semiconductor structure of the embodiment will be described in detail.

[0098] In step S10, referring to FIG. 1, the substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon-on-insulator substrate, and the like. Figure 3

[0099] In step S20, referring to FIG. 2, the gate 12 can be formed by a variety of methods, such as a physical vapor deposition method, a chemical vapor deposition method, a sputtering method, a plasma enhanced chemical vapor deposition method, and the like. Figure 3 ​The source metal layer 111 and the source contact layer 112 are formed on the substrate 10 by a physical vapor deposition (PVD) process, and the source metal layer 111 and the source contact layer 112 are patterned to form the source 11.

[0100] In some embodiments, the source metal layer 111 includes a first source barrier layer 1111, a source conductive layer 1112 and a second source barrier layer 1113 which are sequentially stacked between the substrate 10 and the source contact layer 112. For example, the first source barrier layer 1111 and the second source barrier layer 1113 can be made of titanium nitride, and the source conductive layer 1112 can be made of tungsten. The source contact layer 112 can be made of a semiconductor material, such as doped polysilicon.

[0101] After the source 11 is formed on the substrate 10, a first dielectric layer 41 is formed on the source 11 by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, and the first dielectric layer 41 covers the source 11, the top surface of the substrate 10 exposed by the source 11 and the space between the sources 11.

[0102] In step S30, referring to Figure 3 The gate conductive layer is formed on the first dielectric layer 41 by a PVD process, and then the gate conductive layer is patterned and etched to form the gate 12.

[0103] For example, as shown in the example diagram, the gate 12 can include a gate barrier layer and a gate metal layer which are sequentially stacked from bottom to top, or the gate 12 can further include a gate semiconductor layer and / or a gate metal silicide layer. The gate semiconductor layer can be located on the gate metal layer, and the gate metal silicide layer can be located on the gate semiconductor layer or the gate metal layer.

[0104] In this embodiment, after the gate 12 is formed, the second dielectric layer 42 is formed by a CVD or ALD process to fill the space between the gates 12. For example, the material of the second dielectric layer 42 includes silicon oxide.

[0105] In step S40, referring to Figure 4 The first isolation layer 21 and the second isolation layer 22 can be sequentially formed on the top surface of the second dielectric layer 42 by a CVD or ALD process.

[0106] The second isolation layer 22 has a higher nitrogen content than the first isolation layer 21. For example, the material of the second isolation layer 22 can include at least one of nitrogen-doped silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiNO), silicon oxycarbide (SiNC), silicon oxynitride (SiON), silicon oxycarbide nitride (SiOCN), silicon boron nitride (SiBN), silicon oxycarbide nitride (SiOBN), silicon oxycarbide (SiOC).

[0107] The material of the first isolation layer 21 can include silicon oxide, silicon oxycarbide, or other high-density plasma (HDP) oxide.

[0108] In one example, the material of the first isolation layer 21 includes silicon oxide, and the material of the second isolation layer 22 includes silicon nitride. In another example, the material of the first isolation layer 21 includes silicon oxide, and the material of the second isolation layer 22 includes silicon oxynitride. In yet another example, the material of the first isolation layer 21 includes silicon oxycarbide, and the material of the second isolation layer 22 includes silicon nitride.

[0109] In step S50, step S60, first, referring to Figure 5 , the second isolation layer 22, the first isolation layer 21, and the gate 12 are etched to form the first via 31, which exposes the top surface of the first dielectric layer 41.

[0110] Then, the gate dielectric material layer (not shown in the figure) can be deposited by ALD, which covers the gate 12 exposed by the first via 31.

[0111] Next, referring to Figure 6 , the gate dielectric material layer of the bottom wall of the first via 31 and the first dielectric layer 41 exposed by the first via 31 are etched to expose the top surface of the source 11, and the first via 31 is extended downward to form the channel hole 30.

[0112] The anisotropic etching process is used to etch the gate dielectric material layer and the first dielectric layer 41, and the etching rate along the direction perpendicular to the substrate 10 is much greater than the etching rate along the direction parallel to the substrate 10, so as to ensure that the gate dielectric material layer of the side wall of the first via 31 is completely reserved as the gate dielectric layer 14. The material of the gate dielectric layer 14 includes oxide, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k material.

[0113] For example, the dry process can be used to etch the gate dielectric material layer and the first dielectric layer 41.

[0114] In step S70, as Figure 7As shown, the channel layer 13 can be deposited by CVD or ALD, covering the top surface of the gate 12 and the source 11 exposed by the channel hole 30, and covering the top surface of the second isolation layer 22.

[0115] For example, the material of the channel layer 13 can include doped polysilicon.

[0116] In step S80, as shown, the insulating layer 15 can be deposited by CVD or ALD, covering the channel layer 13 and filling the area of the channel hole 30 not filled. Figure 8

[0117] For example, the material of the insulating layer 15 can include low-k dielectric material or silicon oxide, and the low-k dielectric material can be a material having a lower dielectric constant than silicon oxide. The low-k dielectric material can include one or more of flowable oxide (FOX), tetraethyl orthosilicate (TEOS), undoped silicon dioxide glass (USG), boron silicon glass (BSG), phosphorus silicon glass (PSG), boron phosphorus silicon glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma enhanced oxide (PEOX), or flowable CVD (FCVD) oxide.

[0118] In some embodiments, forming the insulating layer 15 includes the following steps:

[0119] Step S81: grinding to remove the insulating layer 15 and the channel layer 13 on the top surface of the second isolation layer 22, so that the top surface of the remaining insulating layer 15 and the top surface of the channel layer 13 are at the same level as the top surface of the second isolation layer 22;

[0120] As shown, the top surface of the second isolation layer 22 is used as the grinding end point, and the insulating layer 15 and the channel layer 13 are ground by a chemical mechanical polishing (CMP) process, stopping etching at the second isolation layer 22, and only leaving the insulating layer 15 and the channel layer 13 inside the channel hole 30, to disconnect the channel layer 13 inside each channel hole 30 and avoid shorting between adjacent devices. Figure 9 Step S82: etching the insulating layer 15 to a top surface lower than the top surface of the channel layer 13.

[0121] As shown, the insulating layer 15 is etched back to a top surface lower than the top surface of the channel layer 13, to expose part of the inner sidewall of the top of the channel layer 13, for increasing the contact area between the channel layer 13 and the contact pad 161 formed subsequently.

[0122] Figure 10 As shown, the insulating layer 15 is etched back to a top surface lower than the top surface of the channel layer 13, to expose part of the inner sidewall of the top of the channel layer 13, for increasing the contact area between the channel layer 13 and the contact pad 161 formed subsequently.

[0123] ​​The manufacturing method of the embodiment has the following advantages. On the one hand, the second isolation layer 22 is used to protect the first isolation layer 22, so that the first isolation layer 22 is not damaged in the grinding process, and problems such as short circuit between devices caused by damage of the first isolation layer 22 are avoided, so that the structure and performance of the semiconductor structure are complete, the product yield is improved, and the development demand of the semiconductor structure to smaller feature size is met. On the other hand, the top surface of the second isolation layer 22 is used as the grinding endpoint, and the insulating layer 15 and the channel layer 13 on the second isolation layer 22 are removed by one grinding process, so that the process procedure is saved, the manufacturing efficiency is improved, and the production cost is reduced.

[0124] In some embodiments, the top surface of the etched insulating layer 15 is lower than the bottom surface of the second isolation layer 22. In this way, the contact area between the channel layer 13 and the subsequently formed contact pad 161 is large enough, and the contact resistance between the channel layer 13 and the contact pad 161 is reduced.

[0125] Further, the top surface of the etched insulating layer 15 should be higher than the top surface of the gate 12, so that the gate 12 and the subsequently formed contact pad 161 do not have a direct contact area, which is beneficial to reduce the parasitic capacitance of the semiconductor structure and improve the response speed of the semiconductor structure.

[0126] In step S90, a contact material layer (not shown in the figure) can be deposited by CVD or ALD, the contact material layer fills the channel hole 30 and covers the top surface of the second isolation layer.

[0127] Then, referring to Figure 10 , Figure 11 , the top surface of the second isolation layer 22 is used as the grinding endpoint, and the contact material layer on the second isolation layer 22 is removed by CMP grinding, and the contact material layer in the channel hole 30 is retained to form the contact pad 161.

[0128] In the embodiment, the second isolation layer 22 is used to protect the first isolation layer 22, so that the first isolation layer 22 is not damaged in the process of grinding the contact material layer.

[0129] In step S100, as shown in Figure 12 , a first metal layer 162a can be deposited by PVD to cover the top surface of the contact pad 161 and the top surface of the second isolation layer 22.

[0130] Referring to Figure 13 , the first metal layer 162a is patterned to form a drain 162, the bottom surface of the drain 162 is in contact with the top surface of the contact pad 161, and part of the bottom surface of the drain 162 is in direct contact with the top surface of the second isolation layer 22 around the contact pad 161.

[0131] In this way, on the one hand, the drain 162 is connected to the channel layer 13 through the contact pad 161, which reduces the contact resistance between the drain 162 and the channel layer 13, and is conducive to improving the electrical performance and response speed of the semiconductor structure; on the other hand, the connection strength between the second isolation layer 22 and the drain 162 is better, which increases the stability of the semiconductor structure and reduces the risk of damage, delamination, and falling off of the semiconductor structure.

[0132] In some embodiments, referring to Figure 4 As shown in the figure, before the first isolation layer 21 and the second isolation layer 22 are sequentially formed on the gate 12, the following step S50-1 is further performed: forming a third isolation layer 23, the third isolation layer 23 is arranged between the first isolation layer 21 and the gate 12, and the material of the third isolation layer 23 is the same as that of the second isolation layer 22.

[0133] That is, in step S50, the third isolation layer 23, the first isolation layer 21, and the second isolation layer 22 can be sequentially deposited to form a stack. The material of the third isolation layer 23 is the same as that of the second isolation layer 22, so that the third isolation layer 23 is in contact with the gate 12, and the filling property and connection stability of the third isolation layer 23 are better than those of the first isolation layer 21. The first isolation layer 21 is connected to the gate 12 through the third isolation layer 23, which enhances the connection strength between the first isolation layer 21 and the gate 12, increases the stability of the semiconductor structure, and reduces the risk of damage, delamination, and falling off of the semiconductor structure.

[0134] For example, the material of the first isolation layer 21 includes silicon oxide, the material of the second isolation layer 22 includes silicon nitride, and the material of the third isolation layer 23 includes silicon nitride.

[0135] In some embodiments, the manufacturing method performs the following step S110: forming an isolation side wall 43, the isolation side wall 43 covers the side wall of the drain 162 and fills between adjacent drains 162, and the bottom surface of the isolation side wall 43 is lower than the bottom surface of the second isolation layer 22.

[0136] Referring to Figure 13 As shown in the figure, in the process of patterning the first metal layer 162a to form the drain 162 in step S100, a mask is formed on the top surface of the first metal layer 162a, and the first metal layer 162a is etched according to the mask to etch the first metal layer 162a into a discrete drain 162.

[0137] In this embodiment, after the first metal layer 162a is etched to expose the top surface of the second isolation layer 22, the second isolation layer 22 and part of the first isolation layer 21 are further etched to form an isolation groove 44, the isolation groove 44 divides the first metal layer 162a into a plurality of discrete drains 162, and the bottom surface of the isolation groove 44 is lower than the bottom surface of the second isolation layer 22, which can avoid the possibility of residual conductive material and further reduce the risk of short circuit between devices.

[0138] Then, referring to Figure 14 , a nitride layer is formed to cover the sidewall of the drain 162 exposed by the isolation trench 44, the nitride layer is used to prevent the metal material in the drain 162 from diffusing into other devices or film layers, further reducing the risk of short circuit between devices.

[0139] For example, the material of the nitride layer includes silicon nitride.

[0140] Next, referring to Figure 15 The isolation sidewall 43 can be formed by filling the isolation trench 44 with an insulating material deposited by CVD or ALD, the isolation sidewall 43 extends towards the substrate 10, the isolation sidewall 43 penetrates the second isolation layer 22 and extends into the first isolation layer 21, and the isolation sidewall 43 is used to isolate the drain 162.

[0141] The material of the isolation sidewall 43 has a dielectric constant lower than that of the material of the second isolation layer 22. For example, the material of the isolation sidewall 43 can include silicon oxide. In this way, the proportion of the second isolation layer 22 between devices is reduced, the dielectric constant of the isolation medium between devices is reduced, which is beneficial to reduce the parasitic capacitance of the formed semiconductor structure, and improve the product quality and electrical performance.

[0142] According to an exemplary embodiment, the present embodiment provides an electronic device comprising a semiconductor structure as described in the above embodiments, or a semiconductor structure obtained by a manufacturing method as described in the above embodiments. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0143] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered as within the scope of the present disclosure.

[0144] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as limiting the scope of the patent application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The source, gate, and drain are stacked on the substrate from bottom to top; An isolation layer is disposed between the gate and the drain, and includes a first isolation layer, a second isolation layer and a third isolation layer; The second isolation layer is disposed between the first isolation layer and the drain electrode; The third isolation layer is disposed between the first isolation layer and the gate, and the bottom surface of the third isolation layer directly contacts the top surface of the gate. A channel layer extends through the gate and the isolation layer, and the channel layer is disposed on the source. A gate dielectric layer is disposed between the gate and the channel layer; An insulating layer is provided on the inner side of the channel layer; A contact pad is disposed on the insulating layer; The nitrogen content of the second isolation layer is greater than that of the first isolation layer.

2. The semiconductor structure according to claim 1, characterized in that, The top surface of the second isolation layer is in direct contact with the bottom surface of the drain electrode.

3. The semiconductor structure according to claim 1, characterized in that, The material of the third isolation layer is the same as that of the second isolation layer.

4. The semiconductor structure according to claim 1, characterized in that, It also includes an isolation sidewall located between adjacent drain electrodes, the bottom surface of which is lower than the bottom surface of the second isolation layer.

5. The semiconductor structure according to claim 1, characterized in that, The top surface of the insulating layer is lower than the bottom surface of the second insulating layer.

6. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A source electrode is formed on the substrate; A gate is formed on the source electrode, and a second dielectric layer fills the space between the gates; An isolation layer is formed to cover the top surface of the gate and the second dielectric layer. The isolation layer includes a third isolation layer, a first isolation layer, and a second isolation layer in sequence. The nitrogen content of the second isolation layer is greater than that of the first isolation layer. A channel is formed, the channel penetrating the gate and the isolation layer, and the channel exposing a portion of the gate; A gate dielectric layer is formed, the gate dielectric layer covering the gate exposed by the channel via; A channel layer is formed, the channel layer covering the gate dielectric layer; An insulating layer is formed, which covers the channel layer and fills the channel holes, with the top surface of the insulating layer being lower than the top surface of the channel layer; A contact pad is formed on the insulating layer, and the top surface of the contact pad is at the same horizontal height as the top surface of the second insulating layer; A drain electrode is formed on the contact pad.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The material of the third isolation layer is the same as that of the second isolation layer.

8. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The formation of the insulating layer includes: Grinding removes the insulating layer and the channel layer on the top surface of the second isolation layer, so that the top surface of the remaining insulating layer, the top surface of the channel layer, and the top surface of the second isolation layer are at the same horizontal level. The insulating layer is etched until its top surface is lower than the top surface of the channel layer.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The top surface of the etched insulating layer is lower than the bottom surface of the second insulating layer.

10. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The manufacturing method further includes: An isolation sidewall is formed, which covers the sidewall of the drain electrode and fills the space between adjacent drain electrodes, with the bottom surface of the isolation sidewall being lower than the bottom surface of the second isolation layer.

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