Tunnel oxide passivated back contact solar cell and method of manufacturing the same, photovoltaic module, photovoltaic system

Abstract

The embodiment of the present application provides a tunnel oxide passivated back contact solar cell and a preparation method thereof, a photovoltaic module and a photovoltaic system. The tunnel oxide passivated back contact solar cell comprises a substrate, a first tunnel oxide layer located at the back surface of the substrate, a first phosphorus doped layer located at the side of the first tunnel oxide layer away from the substrate, a second tunnel oxide layer located at the partial area of the side of the first phosphorus doped layer away from the first tunnel oxide layer, the second tunnel oxide layer is arranged at intervals, and the area between two adjacent second tunnel oxide layers is an electrode connection area, and a second phosphorus doped layer located at the side surface of the second tunnel oxide layer away from the first phosphorus doped layer and the electrode connection area. The tunnel oxide passivated back contact solar cell has a high yield and good contact.

Description

1.1.1 TECHNICAL FIELD

[0002] The present application relates to the technical field of solar cells, and in particular to a tunnel oxide passivated back contact solar cell, a preparation method thereof, a photovoltaic module and a photovoltaic system. 1.1.2 BACKGROUND

[0004] With the rapid development of photovoltaic technology, the conversion efficiency of crystalline silicon solar cells is increasing year by year. At present, the mainstream P-type double-sided PERC (emitter and back passivation) cell has encountered an efficiency bottleneck, and various manufacturers have also begun to layout N-type high-efficiency cells. Among them, the TOPCon (tunnel oxide passivated back contact solar cell) cell stands out with many advantages such as high efficiency, low decay, and high compatibility with PERC production lines. The TOPCon cell has replaced the PERC cell as the mainstream in the industry.

[0005] At present, in order to improve the open-circuit voltage of the TOPCon cell, a double-layer tunneling structure is adopted instead of the single-layer tunneling passivation contact structure in the early stage of research and development, but the double-layer tunneling structure seriously compresses the selection window of the electrode paste and the process window of sintering, and at the same time easily causes the yield of the cell to fluctuate.

[0006] It should be noted that the above content is not necessarily prior art, and is not used to limit the patent protection scope of the present application. 1.1.3 SUMMARY

[0008] Embodiments of the present application provide a tunnel oxide passivated back contact solar cell and a preparation method thereof, a photovoltaic module and a photovoltaic system, to solve or alleviate one or more technical problems raised above.

[0009] In a first aspect, a tunnel oxide passivated back contact solar cell is provided, comprising: a substrate; a first tunnel oxide layer located on the back surface of the substrate; a first phosphorus-doped layer located on the side of the first tunnel oxide layer away from the substrate; a second tunnel oxide layer located in a partial region of the side of the first phosphorus-doped layer away from the first tunnel oxide layer, the second tunnel oxide layer being arranged at intervals, and the region between two adjacent second tunnel oxide layers being an electrode connection region; and a second phosphorus-doped layer located on the side surface of the second tunnel oxide layer away from the first phosphorus-doped layer and in the electrode connection region.

[0010] The tunneling oxide layer passivated back contact solar cell has high yield, good contact and high photoelectric conversion efficiency. The second tunneling oxide layer is arranged in intervals, and the interval region is an electrode connection region. In the subsequent process of forming the first electrode, the burning process of the first electrode avoids the block of the second tunneling oxide layer, so that a good contact is formed between the first electrode and the first phosphorus doped layer, and a perfect double-layer tunneling layer passivated contact structure is realized. The contact between the first electrode and the first phosphorus doped layer is formed without damaging the first tunneling oxide layer, thereby improving the passivation effect of the cell and the yield of the cell.

[0011] According to the embodiment of the present application, the thickness of the first tunneling oxide layer is 0.8-2nm.

[0012] According to the embodiment of the present application, the thickness of the second tunneling oxide layer is 0.5-1.6nm.

[0013] According to the embodiment of the present application, in the extension direction of the second phosphorus doped layer, the length of the second phosphorus doped layer is 1:(0.5-2.5) times the length of the electrode connection region.

[0014] According to the embodiment of the present application, the first electrode is further included, which is in contact with the first phosphorus doped layer through the electrode connection region, and in the extension direction of the second phosphorus doped layer, the length of the electrode is 1:(1-2) times the length of the electrode connection region.

[0015] In a second aspect, a preparation method of the tunneling oxide layer passivated back contact solar cell is provided, and the method comprises the following steps: providing a substrate; depositing a first tunneling oxide layer on the back surface of the substrate; depositing a first phosphorus doped layer on the side of the first tunneling oxide layer away from the substrate; depositing a second tunneling oxide layer arranged in intervals on the part of the side of the first phosphorus doped layer away from the first tunneling oxide layer; and depositing a second phosphorus doped layer on the side of the second tunneling oxide layer away from the first phosphorus doped layer.

[0016] The method of the embodiment of the present application deposits the second tunneling oxide layer in a spaced arrangement on the part of the first phosphorus-doped layer away from the side surface of the substrate, so that the tunneling oxide layer passivated back contact solar cell obtained has better contact and yield. In addition, the method of the embodiment of the present application forms the second tunneling oxide layer in a spaced arrangement, so that an electrode connecting area is formed between the two adjacent second tunneling oxide layers. The electrode connecting area can reduce the process conditions of the subsequent formation of the first electrode. That is, the contact between the first electrode and the first phosphorus-doped layer is formed under the premise that the first tunneling oxide layer is almost not damaged, so that the selection window of the electrode paste becomes wider (the formula of the paste can be selected in a wider range, such as a less corrosive electrode paste), and the process window of the sintering of the electrode paste is also reduced (the sintering peak temperature is 660-770℃).

[0017] According to the embodiment of the present application, the method of depositing the second tunneling oxide layer comprises: after depositing the third tunneling oxide layer on the side surface of the first phosphorus-doped layer away from the substrate, etching the third tunneling oxide layer according to a predetermined pattern to obtain the second tunneling oxide layer in a spaced arrangement, and the area between the two adjacent second tunneling oxide layers forms an electrode connecting area.

[0018] According to the embodiment of the present application, the method of depositing the second tunneling oxide layer comprises: depositing the second tunneling oxide layer on the side surface of the first phosphorus-doped layer away from the first tunneling oxide layer according to a predetermined pattern to obtain the second tunneling oxide layer in a spaced arrangement, and the area between the two adjacent second tunneling oxide layers forms an electrode connecting area.

[0019] According to the embodiment of the present application, the method further comprises preparing a passivation layer and a first electrode, the passivation layer is deposited on the side surface of the second phosphorus-doped layer away from the substrate; and the first electrode is formed on the side surface of the passivation layer away from the second phosphorus-doped layer and contacts the first phosphorus-doped layer through the electrode connecting area.

[0020] According to the embodiment of the present application, the process of forming the first electrode comprises sintering, and the peak temperature of the sintering is 600-770℃.

[0021] In a third aspect, a photovoltaic module is provided. The photovoltaic module uses the tunneling oxide layer passivated back contact solar cell of the first aspect.

[0022] The photovoltaic module of the embodiment of the present application has good reliability. This is because in the process of preparing the photovoltaic module, the soldering area is protected by the isolation adhesive, which can block the inflow of the adhesive film into the soldering area during lamination, thereby preventing problems such as poor soldering.

[0023] In a fourth aspect, a photovoltaic system is provided, comprising the photovoltaic module of the third aspect. The photovoltaic system has the advantages of the photovoltaic module, which will not be repeated here. 1.1.4 BRIEF DESCRIPTION OF DRAWINGS

[0025] In the drawings, like reference numerals refer to like elements throughout the various drawings. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the application. It should be understood that the drawings are merely schematic and that the application can be embodied in many different forms.

[0026] Figure 1 is a structural schematic diagram of a substrate provided by an embodiment of the present application;

[0027] Figure 2 is a structural schematic diagram of a substrate with a boron-doped layer provided by an embodiment of the present application;

[0028] Figure 3 is a structural schematic diagram of a substrate after etching after forming a boron-doped layer provided by an embodiment of the present application;

[0029] Figure 4 is a structural schematic diagram of a substrate with a first tunneling oxide layer and a first phosphorus-doped layer provided by an embodiment of the present application;

[0030] Figure 5 is a structural schematic diagram of a substrate with a third tunneling oxide layer provided by an embodiment of the present application;

[0031] Figure 6 is a structural schematic diagram of a substrate with a second tunneling oxide layer and an electrode connecting region provided by an embodiment of the present application;

[0032] Figure 7 is a structural schematic diagram of a substrate with a second phosphorus-doped layer provided by an embodiment of the present application;

[0033] Figure 8 is a structural schematic diagram of a substrate with a passivation layer provided by an embodiment of the present application;

[0034] Figure 9 is a structural schematic diagram of a substrate with a first electrode provided by an embodiment of the present application.

[0035] BRIEF DESCRIPTION OF DRAWINGS

[0036] 1: boron-doped layer; 2: first tunneling oxide layer; 3: first phosphorus-doped layer; 4: third tunneling oxide layer; 5: second tunneling oxide layer; 6: electrode connecting region; 7: second phosphorus-doped layer; 8: passivation layer; 9: first electrode. 1.1.5 DETAILED DESCRIPTION

[0038] Embodiments of the present application are described in detail below with reference to examples shown in the attached drawings. In the drawings, the size and relative sizes of layers, regions, elements, and the like can be exaggerated for clarity. Like or similar elements or components throughout the figures are denoted with like reference numbers, and, as such, their function can be referred to throughout. The examples described below are intended to be illustrative and are not intended to limit the scope of the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other under the condition of no conflict.

[0039] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application, and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0040] In the present application, unless specifically defined otherwise, the terms "mounting", "connected", "connecting", "fixed", and the like, should be understood broadly, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements, unless specifically defined otherwise. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0041] It is to be understood that the terms "first", "second", and the like, used in the description and the claims of the present application as well as the above description of the drawings merely refer to categories and do not necessarily imply a sequence or order unless otherwise indicated by the context. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of accomplishing the same objectives if replaced in sequence or order. Furthermore, the terms "comprise", "comprising", "include", "including", and the like, used in the description and the claims of the present application, are used in the sense of "including but not limited to", and indicate the presence of what is listed (but not to the exclusion of other elements). It is further understood that where the description above refers to determining, calculating, or computing values, such values can be determined, calculated, or computed by any means including but not limited to a computer system, a computer program, or a computer program operating on a computer system.

[0042] In the present application, when referring to a numerical interval (i.e. a numerical range), the distribution of the selectable values within the numerical interval is considered continuous and includes both numerical endpoints (i.e. the minimum and maximum values) of the numerical interval and every value between the two numerical endpoints, unless otherwise specified. When a numerical interval refers only to integers within the numerical interval, including both endpoints and every integer between the two endpoints, it is equivalent to listing each integer directly, unless otherwise specified. When multiple numerical ranges are provided to describe a characteristic or property, the numerical ranges can be combined. In other words, unless otherwise indicated, numerical ranges disclosed in the present application are to be understood to include any and all sub-ranges subsumed therein. A "value" in a numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. A "numerical interval" is intended to broadly include quantitative intervals such as percentage intervals, ratio intervals, value intervals, etc.

[0043] In a first aspect, the present application provides a tunnel oxide passivated back contact solar cell, comprising: a substrate; a first tunnel oxide layer, the first tunnel oxide layer is located on the back surface of the substrate; a first phosphorus doped layer, the first phosphorus doped layer is located on the side of the first tunnel oxide layer away from the substrate; a second tunnel oxide layer, the second tunnel oxide layer is located on a part of the side of the first phosphorus doped layer away from the first tunnel oxide layer, the second tunnel oxide layer is arranged in intervals, and the area between two adjacent second tunnel oxide layers is an electrode connection area; and a second phosphorus doped layer, the second phosphorus doped layer is located on the side surface of the second tunnel oxide layer away from the first phosphorus doped layer and the electrode connection area.

[0044] The tunneling oxide layer passivated back contact solar cell has high yield, good contact and high photoelectric conversion efficiency. This is because the second tunneling oxide layer is arranged in intervals, and the interval area is the electrode connection area. In the subsequent process of forming the first electrode, the burning process of the first electrode avoids the blockage of the second tunneling oxide layer, thereby forming good contact between the first electrode and the first phosphorus doped layer, and realizing the perfect double-layer tunneling layer passivated contact structure. The contact effect between the first electrode and the first phosphorus doped layer is formed without damaging the first tunneling oxide layer, thereby improving the passivation of the cell and the yield of the cell.

[0045] In some embodiments, the substrate comprises a silicon substrate, and the substrate has a textured structure.

[0046] In some embodiments, the first tunneling oxide layer and the second tunneling oxide layer each independently comprises silicon dioxide.

[0047] In some embodiments, the thickness of the first tunneling oxide layer is 0.8-2nm. In this way, the tunneling of electrons is facilitated.

[0048] In some embodiments, the thickness of the second tunneling oxide layer is 0.5-1.6nm. In this way, the secondary tunneling of electrons is facilitated.

[0049] In some embodiments, the thickness of the first phosphorus doped layer and the second phosphorus doped layer is independently 1-100nm.

[0050] In some embodiments, in the extension direction of the second phosphorus doped layer, the length of the second phosphorus doped layer to the length of the electrode connection area is 1:(0.5-2.5), for example 1:0.5, 1:01, 1:1.5, 1:2, 1:2.5. In this way, the photoelectric conversion efficiency and yield of the tunneling oxide layer passivated back contact solar cell can be improved.

[0051] In some embodiments, a first electrode is further included, and the first electrode is in contact with the first phosphorus doped layer through the electrode connection area.

[0052] Optionally, in the extension direction of the second phosphorus doped layer, the length of the electrode to the length of the electrode connection area is 1:(1-2), for example 1:1, 1:1.1, 1:1.3, 1:1.5, 1:1.8, 1:2. In this way, the photoelectric conversion efficiency and yield of the tunneling oxide layer passivated back contact solar cell can be improved.

[0053] In some embodiments, further comprising: a boron doped layer, the boron doped layer is located on the front side of the substrate. The thickness of the boron doped layer is 700-1200 nm. The boron doped layer with the aforementioned thickness range can reduce the risk of electrode burn-through and the current loss caused by free carrier absorption.

[0054] In some embodiments, further comprising: a second electrode, the second electrode is located on the surface of the boron doped layer.

[0055] In some embodiments, the first electrode and the second electrode respectively independently comprise a silver electrode or an aluminum electrode.

[0056] In some embodiments, further comprising: a passivation layer, the passivation layer is located on the side of the second phosphorus doped layer away from the substrate. The design of the passivation layer is conducive to improving the photoelectric efficiency of the battery.

[0057] Optionally, the thickness of the passivation layer is 10-70 nm.

[0058] Optionally, the material of the passivation layer comprises one or more of ALD (aluminum trioxide), silicon nitride, silicon oxynitride, and silicon dioxide.

[0059] The second aspect of the embodiments of the present application provides a method for manufacturing a tunnel oxide passivated back contact solar cell, comprising the following steps: (1) providing a substrate; (2) depositing a first tunnel oxide layer on the back side of the substrate; (3) depositing a first phosphorus doped layer on the side of the first tunnel oxide layer away from the substrate; (4) depositing a second tunnel oxide layer in a spaced arrangement on a partial area of the side of the first phosphorus doped layer away from the first tunnel oxide layer; and (5) depositing a second phosphorus doped layer on the side of the second tunnel oxide layer away from the first phosphorus doped layer.

[0060] The method of the embodiments of the present application deposits the second tunnel oxide layer in a spaced arrangement on a partial area of the side of the first phosphorus doped layer away from the substrate, so that the tunnel oxide passivated back contact solar cell obtained has better contact and yield. In addition, the method of the embodiments of the present application forms the second tunnel oxide layer in a spaced arrangement, so that an electrode connection area is formed between the two adjacent second tunnel oxide layers. The electrode connection area can reduce the process conditions for forming the first electrode. That is, the contact between the first electrode and the first phosphorus doped layer is formed under the premise of almost not damaging the first tunnel oxide layer, so that the selection window of the electrode paste becomes wider (the formula of the paste can be selected in a wider range, such as a less corrosive electrode paste), and the process window of the sintering of the electrode paste is also reduced (the sintering peak temperature is 660-770 ℃).

[0061] According to the method of the embodiments of the present application, in step (1), a substrate is provided.

[0062] In some embodiments, referring to Figure 1 , the substrate is also subjected to texturing cleaning to remove dirt and metal impurities on the surface of the substrate and remove the mechanical damage layer generated during the cutting process, reduce the recombination center, and form a rough surface to improve the absorption of sunlight by the silicon wafer and reduce the reflectivity.

[0063] Optionally, a uniform "positive pyramid" texture is formed on the opposite surfaces of the substrate, and the texture height is 0.5-3 μm.

[0064] In some embodiments, referring to Figure 2 , after step (1) and before step (2), the front surface of the substrate is subjected to boron doping to form a boron-doped layer 1 and a borosilicate glass layer on the surface of the substrate, and the borosilicate glass layer includes a boron-rich layer. P-type impurities are diffused on the substrate to achieve a suitable doping concentration and sheet resistance, and to obtain a depth suitable for the PN junction of a solar cell. The surface of the boron-doped layer also generates a borosilicate glass layer composed of a boron-rich layer and an oxidation layer stacked, and the oxidation layer is close to the boron-doped layer.

[0065] In some embodiments, in step (1), the temperature during boron doping diffusion is 600-1000°C, and the time is 60-120s. After boron diffusion, P-type impurities are diffused on the N-type substrate to form a PN junction and achieve a suitable doping concentration ρ / sheet resistance R.

[0066] In some embodiments, the boron source during boron doping diffusion includes at least one of BCl3 and BBr3.

[0067] In some embodiments, the substrate includes an N-type silicon wafer.

[0068] In some embodiments, the thickness of the boron-doped layer is 70-1200 nm, such as 70 nm, 160 nm, 260 nm, 380 nm, 500 nm, 600 nm, 800 nm, 900 nm, 1100 nm, 120 nm, etc.

[0069] In some embodiments, referring to Figure 3 , the back surface and the side edges of the substrate after forming the boron-doped layer 1 are subjected to first degree etching, respectively. To remove the borosilicate glass layer on the back surface and the side edges and etch and polish the back surface to improve the reflectivity of the back surface, to improve the long-wave absorption of the silicon wafer, and to make the back surface more convex to reduce the recombination of surface dangling bonds.

[0070] In some embodiments, the borosilicate glass layer on the back surface and the side edges is removed by using HF solution to chain etch the substrate after the first degree etching.

[0071] Optionally, the concentration of the HF is 0.5-10wt%, such as 0.5wt%, 1wt%, 2wt%, 5wt%, 10wt%, etc.

[0072] In some embodiments, the back etching further comprises a polishing process, and the polishing process is performed in an alkaline solution, and the alkaline solution comprises a sodium hydroxide solution or a potassium hydroxide solution.

[0073] Optionally, the concentration of the sodium hydroxide solution is 0.5-5wt%, such as 0.5wt%, 1wt%, 2wt%, 3wt%, 4wt%, 5wt%, etc.

[0074] According to the method of the embodiment of the present application, in step (2), the first tunneling oxide layer 2 is deposited on the back of the substrate. Figure 4 The first tunneling oxide layer can provide a tunneling channel, selectively pass through electrons, and form an interface chemical passivation to block excessive phosphorus in the N-type doped layer from entering the silicon wafer.

[0075] In some embodiments, the method of depositing the first tunneling oxide layer comprises using an LPCVD device to grow the first tunneling oxide layer on the front and back of the silicon wafer at a temperature of 400-650°C.

[0076] According to the method of the embodiment of the present application, in step (3), the first phosphorus doped layer 3 is deposited on the side of the first tunneling oxide layer away from the substrate. Figure 4 The N+ layer is formed on the back, a heavily doped polysilicon is formed, and a good passivation contact structure is formed.

[0077] In some embodiments, the method of depositing the first phosphorus doped layer comprises loading the silicon wafer after depositing amorphous silicon into a tube phosphorus diffusion furnace tube, using POCl3 diffusion to diffuse and anneal phosphorus on the back of the cell, and forming a first phosphorus doped layer and a phosphosilicate glass layer on the back.

[0078] In other embodiments, the method of depositing the first phosphorus doped layer comprises using a back in-situ doping and back crystallization annealing method to form the tunneling oxide layer and the N-type doped layer, and the conditions include: using an electric field to ionize laughing gas to form a plasma gas, and then reacting with silicon to form a tunneling oxide layer, and then using PEVCD (enhanced plasma deposition) to pass in silane and phosphine to react and in-situ dope to form an N-type doped layer, i.e., the first phosphorus doped layer.

[0079] According to the method of the embodiment of the present application, in step (4), the second tunneling oxide layer is deposited on the part of the side of the first phosphorus doped layer away from the first tunneling oxide layer.

[0080] In some embodiments, the second tunneling oxide layer is deposited on the part of the side of the first phosphorus doped layer away from the first tunneling oxide layer. Figure 5 and 6The method of depositing the second tunneling oxide layer includes: using a PEVCD device to deposit a third tunneling oxide layer 4 on the side of the first phosphorus-doped layer 3 away from the substrate, etching the third tunneling oxide layer 4 according to a predetermined pattern to obtain the second tunneling oxide layers 5 arranged at intervals, and the area between two adjacent second tunneling oxide layers 5 forming an electrode connecting area 6.

[0081] Optionally, the etching is performed by using a laser. The conditions of the laser include a wavelength of 500-600 nm, an energy density of 0.17-0.87 J / cm 2 , and a pulse width of 10-60 ps.

[0082] In some other embodiments, the method of depositing the second tunneling oxide layer includes: depositing a second tunneling oxide layer on the side of the first phosphorus-doped layer away from the substrate according to a predetermined pattern to obtain the second tunneling oxide layers arranged at intervals, and the area between two adjacent second tunneling oxide layers forming an electrode connecting area. The second tunneling oxide layer is deposited after being patterned, which is simple and beneficial to reducing the damage to the cell caused by etching.

[0083] According to the method of the embodiments of the present application, in step (5), a second phosphorus-doped layer 7 is deposited on the side of the second tunneling oxide layer 5 away from the first phosphorus-doped layer. Figure 7

[0084] In some embodiments, the method of depositing the second phosphorus-doped layer includes: loading the silicon wafer after depositing amorphous silicon into a tube-type phosphorus diffusion furnace tube, diffusing phosphorus on the back surface by using a POCl3 diffusion method and annealing, and forming a second phosphorus-doped layer and a phosphosilicate glass layer on the back surface.

[0085] In some other embodiments, the method of depositing the second phosphorus-doped layer includes: forming a tunneling oxide layer and an N-type doped layer by using a back surface in-situ doping and back surface crystallization annealing method, which includes: ionizing laughing gas to form a plasma gas by using an electric field, and reacting the plasma gas with silicon to form a tunneling oxide layer, and then introducing silane and phosphine to react by using a PEVCD (enhanced plasma deposition) method to in-situ dope into an N-type doped layer, i.e., the second phosphorus-doped layer.

[0086] In some embodiments, the method further includes step (6): removing the phosphosilicate glass layer on the front surface, the edge and the back surface, and the oxide layer on the front surface includes sequentially performing acid washing, water washing, pre-dehydration and drying steps, wherein the acid washing uses hydrofluoric acid for 200-300 s; the water washing uses deionized water for 100-200 s; the pre-dehydration time is 5-20 s, and the acid washing, water washing and pre-dehydration can be performed at room temperature (20-30 °C). The drying is performed by using hot air drying for 400-700 s at a temperature of 80-100 °C.

[0087] ​In some embodiments, referring to Figure 8 Further comprising step (7): preparing a passivation layer 8, which is deposited on the side of the second phosphorus-doped layer 7 away from the substrate.

[0088] In some embodiments, the passivation layer comprises a combination of one or more of aluminum trioxide, silicon nitride, silicon oxynitride, and silicon dioxide.

[0089] In some embodiments, the passivation layer has a thickness of 3-10 nm.

[0090] In some embodiments, referring to Figure 9 The back side of the silicon wafer is metallized to form a first electrode 9. The first electrode is in contact with the first tunneling oxide layer through the electrode connection area.

[0091] Further, the first electrode is formed by sintering, and the peak temperature of the sintering is 600-770 ℃. This is because the second tunneling oxide layer is arranged in intervals, and the interval area is the electrode connection area. Thus, the burn-through process of the first electrode is avoided from being blocked by the second tunneling oxide layer during the formation of the first electrode, so that a good contact is formed between the first electrode and the phosphorus-doped layer, and thus a perfect double-layer tunneling layer passivation contact structure is achieved.

[0092] In some embodiments, the front side of the silicon wafer is metallized to form a second electrode.

[0093] Optionally, the silver paste electrode is printed on the back side of the silicon wafer, and the silver-aluminum paste electrode is printed on the front side of the silicon wafer by screen printing, and then sintered to prepare the battery.

[0094] A third aspect of the embodiments of the present application provides a photovoltaic module. The photovoltaic module adopts the tunneling oxide layer passivation back contact solar cell of the first aspect.

[0095] The photovoltaic module of the embodiments of the present application has good reliability. This is because the soldering area is protected by the isolation glue during the preparation of the photovoltaic module, which can block the inflow of the adhesive film into the soldering area during lamination, and thus prevent problems such as poor soldering.

[0096] A fourth aspect of the embodiments of the present application provides a photovoltaic system, which comprises the photovoltaic module of the third aspect. The photovoltaic system also has the advantages of the photovoltaic module, which will not be described here.

[0097] In some embodiments, the photovoltaic system can be applied in a wide range of fields, not limited to photovoltaic power stations, such as ground power stations, roof power stations, and water surface power stations, but also including various devices and apparatuses utilizing solar energy for power generation, such as user solar power sources, solar street lamps, solar vehicles, and solar buildings, etc. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to the above, that is, the photovoltaic system can be applied in all fields requiring solar energy for power generation. Taking a photovoltaic power generation system network as an example, the photovoltaic system can include a photovoltaic array, a combiner box, and an inverter, the photovoltaic array can be an array combination of a plurality of photovoltaic components, for example, a plurality of photovoltaic components can form a plurality of photovoltaic arrays, the photovoltaic array is connected to the combiner box, the combiner box can combine the current generated by the photovoltaic array, the combined current flows through the inverter to convert into alternating current required by the power grid, and then is connected to the power network to realize solar power supply.

[0098] Hereinafter, example embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the example embodiments can be implemented in various manners, and should not be interpreted as being limited to the embodiments set forth herein.

[0099] Embodiment 1

[0100] S1: Texturing and cleaning

[0101] An N-type silicon wafer with a thickness of 120 μm was subjected to texturing and cleaning to form uniform "positive pyramid" textures on the opposite surfaces of the silicon wafer, and the texture height was 3 μm.

[0102] S2: Boron doping on the front surface of the N-type silicon wafer

[0103] A 10 nm-thick boron-doped layer was diffused on the front surface of the silicon wafer after texturing and cleaning.

[0104] S3: First winding etching

[0105] A 5wt% HF solution was used to chain-etch the substrate after boron doping.

[0106] A 5wt% sodium hydroxide solution was used to etch the back surface of the substrate.

[0107] S4: Removal of the boron-rich layer

[0108] The removal treatment was carried out by tank etching using a 3wt% HF solution.

[0109] S5: First tunneling oxide layer and first phosphorus-doped layer

[0110] The LPCVD equipment is used to grow the tunneling oxide layer and the intrinsic amorphous silicon layer (a-Si) on the front and back surfaces of the silicon wafer at 650℃, wherein the first tunneling oxide layer has a thickness of 1.5nm and the intrinsic amorphous silicon layer has a thickness of 100nm.

[0111] The phosphorus diffusion is to load the silicon wafer after depositing the amorphous silicon into the tube type phosphorus diffusion furnace tube, and the POCl3 diffusion is used to diffuse and anneal the phosphorus on the back surface of the cell to form the phosphorus-doped polysilicon layer and the phosphosilicate glass layer on the back surface.

[0112] S6: Preparation of the second tunneling oxide layer

[0113] After the third tunneling oxide layer is deposited on the side of the first phosphorus-doped layer away from the substrate by the PEVCD equipment, the third tunneling oxide layer is etched according to the predetermined pattern to obtain the second tunneling oxide layer with a thickness of 1nm arranged at intervals, and the area between the adjacent two second tunneling oxide layers forms the electrode connecting area. In the extension direction of the second phosphorus-doped layer, the length of the second phosphorus-doped layer and the length of the electrode connecting area are in a ratio of 1:1. The length of the electrode and the length of the electrode connecting area are in a ratio of 1:1.5.

[0114] S7: Preparation of the second phosphorus-doped layer

[0115] The silicon wafer after depositing the amorphous silicon is loaded into the tube type phosphorus diffusion furnace tube, and the POCl3 diffusion is used to diffuse and anneal the phosphorus on the back surface of the cell to form the second phosphorus-doped layer with a thickness of 60nm and the phosphosilicate glass layer on the back surface.

[0116] S8: Second degree etching on the front surface

[0117] The obtained product of step S7 is sequentially subjected to the steps of acid washing, water washing, pre-dehydration and drying, wherein the acid washing uses hydrofluoric acid for 300s; the water washing uses deionized water for 200s; the pre-dehydration time is 20s, and the acid washing, water washing and pre-dehydration can be carried out at room temperature. The drying uses hot air drying for 700s at a temperature of 100℃.

[0118] S9: Deposition of passivation layer

[0119] A 5nm passivation layer is deposited on the front surface of the obtained product after the degree etching on the front surface.

[0120] S10: Deposition of reflective film

[0121] The reflective film with a thickness of 30nm is deposited on the front surface and the back surface of the cell wafer after the deposition of the passivation film.

[0122] S11: Formation of metal electrode

[0123] The front side and the back side of the solar cell are respectively provided with a first silver electrode and a second silver electrode.

[0124] S12: Light injection

[0125] The solar cell obtained in S11 is subjected to light injection treatment to form a solar cell, wherein the light injection temperature is 220°C, and the time is 120s, so as to obtain a tunnel oxide passivated back contact solar cell.

[0126] Examples 2 and 3

[0127] The tunnel oxide passivated back contact solar cell is prepared in the manner of Example 1, except that the length ratio of the second phosphorus-doped layer to the electrode connecting area in the extension direction of the second phosphorus-doped layer is 1:0.5 and 1:2.5, respectively.

[0128] Examples 4 and 5

[0129] The tunnel oxide passivated back contact solar cell is prepared in the manner of Example 1, except that the length ratio of the electrode to the electrode connecting area in the extension direction of the second phosphorus-doped layer is 1:1.1 and 1:2.

[0130] Comparative Example 1

[0131] The tunnel oxide passivated back contact solar cell is prepared in the manner of Example 1, except that the second tunnel oxide layer is a continuous intermediate layer without interruption.

[0132] Test Example

[0133] (1) The production line efficiency and yield of the above solar cell are tested, and the results are shown in Table 1:

[0134] Efficiency test: The specific test method is to place the cell under simulated sunlight with a light source of 100 mW / cm 2 AM 1.5G at 25°C to obtain a four-wire method source table test.

[0135] Yield test: The yield test is to study the quality and performance of the cells prepared in the above examples and comparative examples on a PL tester, 2000 parallel samples are prepared for each example and comparative example, and the yield is sorted and counted.

[0136] Test data are shown in Table 1:

[0137] Table 1

[0138]

[0139] According to the above table results, by comparing the examples 1-5 and the comparative example 1, it can be seen that the batteries of the examples have better photoelectric conversion efficiency and higher yield. This is because the second tunneling oxide layer is arranged in intervals, and the interval area is the electrode connecting area. Thus, in the process of forming the first electrode, the burning-through process of the first electrode avoids the block of the second tunneling oxide layer, so that a good contact is formed between the first electrode and the phosphorus doped layer, and thus a perfect double-layer tunneling layer passivation contact structure is realized. The contact between the first electrode and the first phosphorus doped layer is formed without damaging the first tunneling oxide layer, so as to improve the passivation of the battery, and thus improve the yield of the battery.

[0140] It should also be noted that the "some embodiments", "other embodiments", "embodiments", etc. mentioned in the present application refer to the specific features, structures or characteristics described in conjunction with the embodiments, which are included in at least one embodiment described in the general description of the present application. The same expression appears in several places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the implementation of this feature, structure or characteristic in conjunction with other embodiments also falls within the scope of the present application.

[0141] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0142] It should also be noted that the above is only the preferred embodiment of the present application, and does not limit the patent protection scope of the present application. Any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A tunneling oxide passivated back contact solar cell, characterized in that: include: substrate; a first tunneling oxide layer, wherein the first tunneling oxide layer is located on the back side of the substrate; a first phosphorus-doped layer, wherein the first phosphorus-doped layer is located on a side of the first tunnel oxide layer away from the substrate; a second tunneling oxide layer, the second tunneling oxide layer being located in a partial region of a side surface of the first phosphorus-doped layer away from the first tunneling oxide layer, the second tunneling oxide layers being arranged at intervals, and a region between two adjacent second tunneling oxide layers being an electrode connection region; A second phosphorus-doped layer is located on a surface of the second tunneling oxide layer that is away from the first phosphorus-doped layer, and is located in the electrode connection region.

2. The tunneling oxide passivated back contact solar cell according to claim 1, characterized in that: The thickness of the first tunnel oxide layer is 0.8-2 nm; And / or, the thickness of the second tunneling oxide layer is 0.5-1.6 nm.

3. The tunneling oxide passivated back contact solar cell according to claim 1 or 2, characterized in that: In the extension direction of the second phosphorus-doped layer, the ratio of the length of the second phosphorus-doped layer to the length of the electrode connection region is 1:(0.5-2.5).

4. The tunneling oxide passivated back contact solar cell according to claim 1 or 2, characterized in that: The invention further comprises a first electrode, wherein the first electrode contacts the first phosphorus-doped electrode through the electrode connection region. In the extension direction of the second phosphorus-doped layer, the ratio of the length of the electrode to the length of the electrode connection region is 1:(1-2).

5. A method for preparing a tunneling oxide layer passivated back contact solar cell, characterized in that: The following steps are involved: providing a substrate; Depositing a first tunneling oxide layer on the back side of the substrate; Depositing a first phosphorus-doped layer on a side of the first tunnel oxide layer away from the substrate; Depositing second tunnel oxide layers arranged in an alternating pattern on a portion of a side of the first phosphorus-doped layer away from the first tunnel oxide layer; A second phosphorus-doped layer is deposited on a side of the second tunnel oxide layer away from the first phosphorus-doped layer.

6. The preparation method according to claim 5, characterized in that The method of depositing the second tunnel oxide layer includes: After depositing a third tunnel oxide layer on a side of the first phosphorus-doped layer away from the substrate, the third tunnel oxide layer is etched according to a predetermined pattern to obtain the second tunnel oxide layers arranged at intervals, and the area between two adjacent second tunnel oxide layers forms an electrode connection area.

7. The preparation method according to claim 5, characterized in that The method of depositing the second tunneling oxide layer includes: depositing the second tunneling oxide layer on a side of the first phosphorus-doped layer away from the first tunneling oxide layer according to a predetermined pattern to obtain the second tunneling oxide layers arranged at intervals, and the area between two adjacent second tunneling oxide layers forms an electrode connection area.

8. The preparation method according to any one of claims 6 to 7, characterized in that The method further comprises preparing a passivation layer and a first electrode, The passivation layer is deposited on a side of the second phosphorus-doped layer away from the substrate; The first electrode is formed on a side of the passivation layer away from the second phosphorus-doped layer and contacts the first phosphorus-doped layer through the electrode connection region.

9. The preparation method according to claim 8, characterized in that The process of forming the first electrode includes sintering, The peak temperature of the sintering is 600-770°C.

10. A photovoltaic module, characterized in that: The photovoltaic module comprises the tunnel oxide layer passivated back contact solar cell according to any one of claims 1 to 4.

11. A photovoltaic system, characterized in that: The photovoltaic system includes the photovoltaic assembly according to claim 10.

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