Dual-color LED and preparation method thereof

Abstract

The present invention discloses a dual-color LED and a method for manufacturing the same. The method includes: sequentially stacking an N-type layer and a mask layer on a substrate surface; removing a portion of the mask layer to form a plurality of spaced first blank areas exposing the N-type layer; forming a nanopillar within each first blank area; forming a first light-emitting structure on the top surface of each nanopillar, and forming a protective layer covering the side surfaces of the first light-emitting structure; forming a second light-emitting structure on at least a portion of the side surfaces of each nanopillar; forming a conductive layer covering the surface of the second light-emitting structure on the surface of the mask layer; forming an N-electrode, a first P-electrode corresponding to each first light-emitting structure, and a second P-electrode corresponding to each second light-emitting structure; wherein the first P-electrode is disposed on each first light-emitting structure, the second P-electrode is disposed on the conductive layer, and the N-electrode is disposed on the N-type layer. The present invention achieves the integration of nanopillar dual-color LEDs, reduces optical crosstalk between light-emitting structures, and enables interconnected electrodes to control the nanopillars.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a dual-color LED and a preparation method thereof. Background Art

[0002] In the research and application of modern optoelectronic devices, LED (Light-Emitting Diode) technology has become one of the core technologies, especially in the fields of lighting and display, and has a wide range of applications.

[0003] As technology advances, researchers are exploring more complex LED structures, such as nanopillar LEDs, to further enhance the performance and diverse applications of optoelectronic devices. Compared to traditional planar LEDs, nanopillar LEDs demonstrate higher light extraction efficiency and flexible wavelength control. The high surface area of ​​nanopillars provides more area for light generation and extraction, which is particularly important for improving the overall efficiency of LEDs.

[0004] Nanopillar LEDs typically have either an axial or radial structure. In axially structured LEDs, the quantum well and p-type layer are grown on the top of the nanopillar (i.e., in the axial direction), while in radially structured LEDs, the quantum well and p-type layer are grown on the sidewalls of the nanopillar (i.e., in the radial direction). By combining these two structures, growing the quantum well and p-type layer in the axial and radial directions, respectively, a dual-color LED can be created. The two structures are independent of each other during growth, and the separation between them is very small, enabling excellent color mixing.

[0005] Dual-color LED chips typically utilize a stacked structure with quantum wells emitting at different wavelengths, or by integrating two separate LED devices together after fabrication. However, stacked quantum wells face challenges with material quality due to the multi-layer structure and light absorption by the upper quantum well from the lower. Integrating two separate LED devices leads to uneven light output and poor color mixing, and also poses difficulties in miniaturizing the chip size. Using a nanopillar structure to grow quantum wells of two wavelengths in both the axial and radial directions, integrated dual-color LED fabrication can effectively address these issues and further reduce chip size. However, this still presents challenges such as limited design flexibility, a narrow application range, and optical crosstalk.

[0006] The present invention solves at least one of the above problems. Summary of the Invention

[0007] The purpose of the present invention is to provide a dual-color LED and a preparation method thereof, which are used to achieve miniaturization and energy efficiency improvement of dual-color LEDs and expand the application field of nanocolumn LEDs.

[0008] A first aspect of the present invention provides a method for preparing a dual-color LED, comprising:

[0009] Providing a substrate, and sequentially stacking an N-type layer and a mask layer on the surface of the substrate;

[0010] removing a portion of the mask layer so that the mask layer forms a plurality of spaced first blank areas exposing the N-type layer, and forming a nanorod in each of the first blank areas;

[0011] forming a first light-emitting structure on the top surface of each of the nanocolumns, and forming a protective layer covering the side surfaces of the first light-emitting structure;

[0012] forming a second light-emitting structure on at least a portion of a side surface of each of the nanorods;

[0013] forming a conductive layer on the surface of the mask layer to cover the surface of the second light-emitting structure;

[0014] forming an N electrode, a first P electrode corresponding to each of the first light emitting structures, and a second P electrode corresponding to each of the second light emitting structures;

[0015] The first P-electrode is disposed on each of the first light-emitting structures, the second P-electrode is disposed on the conductive layer, and the N-electrode is disposed on the N-type layer.

[0016] In some possible implementations, forming a protective layer covering a side surface of the first light-emitting structure includes:

[0017] forming a protective layer on the top surface of the first light-emitting structure and extending to the side surfaces corresponding to the nanocolumns;

[0018] Etching away a portion of the protective layer at a preset etching angle to expose at least a portion of the side surfaces of the nanorods, so that the remaining protective layer at least covers the top surface and side surfaces of the first light-emitting structure;

[0019] The preset etching angle ranges from 30° to 60°.

[0020] In some possible implementations, forming a conductive layer covering a surface of the second light-emitting structure on a surface of the mask layer includes:

[0021] forming the conductive layer on the surface of the mask layer and the protective layer; removing part of the conductive layer on the surface of the second light-emitting structure so that the remaining conductive layer covers the second light-emitting structure and the top surface of the conductive layer covering the second light-emitting structure does not exceed the top surface of the first light-emitting structure;

[0022] Alternatively, the conductive layer is formed on the surface of the mask layer so that the top surface of the conductive layer covering the surface of the second light emitting structure is not higher than the top surface of the protective layer.

[0023] In some possible implementations, forming an N electrode, a first P electrode corresponding to each first light emitting structure, and a second P electrode corresponding to each second light emitting structure includes:

[0024] forming a second P-electrode on the top surface of the conductive layer covering the surface of the second light emitting structure;

[0025] forming a first dielectric layer on the surface of the conductive layer, wherein the first dielectric layer at least covers a side surface of the second P-electrode;

[0026] Sequentially removing a portion of the first dielectric layer, a portion of the conductive layer, and a portion of the protective layer on the top surface of the first light-emitting structure until the first light-emitting structure is exposed, and forming the first P-electrode on the first light-emitting structure;

[0027] A portion of the first dielectric layer, a portion of the conductive layer, and a portion of the mask layer are removed in sequence until the N-type layer is exposed, and the N-electrode is formed on the N-type layer.

[0028] In some possible implementations, forming the first light-emitting structure on the top surface of the nanopillar includes: sequentially growing a stacked first quantum well layer and a first P-type layer on the top surface of the nanopillar to obtain the first light-emitting structure; and / or,

[0029] Forming a second light-emitting structure on at least part of the side surface of the nanorod includes: sequentially growing a stacked second quantum well layer and a second P-type layer along the radial direction of the nanorod on at least part of the side surface of the nanorod to obtain the second light-emitting structure; and / or,

[0030] The first quantum well layer includes a plurality of first quantum well structures sequentially stacked and grown along the top surface of the nanocolumn; the first quantum well structure includes a stacked first In a Ga 1-a N well layer and the first GaN barrier layer, growing the first quantum well layer on the top surface of the nanocolumn includes: growing the first In under the first growth condition a Ga 1-a N well layer, the first GaN barrier layer is grown under the second growth condition; or the first quantum well structure includes a stacked first Al x1 Ga 1-x1 The N well layer and the first Al y1 Ga 1-y1 N barrier layer, and growing the first quantum well layer on the top surface of the nanocolumn includes: growing the first Al x1 Ga 1-x1 The N well layer is grown under the fourth growth condition. y1 Ga 1-y1 N-barrier layer; and / or,

[0031] The second quantum well layer includes a plurality of second quantum well structures sequentially stacked and grown along the side of the nanocolumn, and the second quantum well structure includes a stacked second In b Ga 1-b N well layer and a second GaN barrier layer; growing a second quantum well layer on at least part of the side of the nanocolumn includes: growing the second In under the first growth condition b Ga 1-b N layer, growing the second GaN barrier layer under the second growth condition; or the second quantum well structure includes a stacked second Al x2 Ga 1-x2 N well layer and the second Al x2 Ga 1-x2 N well layer, growing the second quantum well layer on at least part of the side of the nano column includes: growing the second Al x2 Ga 1-x2 N well layer, growing the second Al under the fourth growth condition y2 Ga 1-y2 N barrier layer;

[0032] Among them, 0.08 <a<0.3,0.08<b<0.3,0.1<x1<0.5,0.2<y1<0.6,0.3<x2<0.6,0.4<y2<0.8。

[0033] In some possible embodiments, the first growth conditions include: a growth thickness of 2-3 nm, a growth temperature of 700-800° C., a growth pressure of 200-600 mbar, a V-III ratio of 10,000-40,000, and a carrier gas of N 2 ; and / or

[0034] The second growth conditions include a growth thickness of 8-15 nm, a growth temperature of 830-950° C., a growth pressure of 200-600 mbar, a V-III ratio of 5000-20000, and a carrier gas of N 2 ; and / or,

[0035] The third growth condition includes: a growth thickness of 1-3 nm, a growth temperature of 1100-1250° C., a growth pressure of 50-200 mbar, a V-III ratio of 500-3000, and a carrier gas of H2; and / or the fourth growth condition includes: a growth thickness of 5-15 nm, a growth temperature of 1100-1250° C., a growth pressure of 50-200 mbar, a V-III ratio of 100-3000, and a carrier gas of H2;

[0036] The growth period of the first quantum well structure is 1 to 10, and the growth period of the second quantum well structure is 1 to 10.

[0037] In some possible embodiments, the material of the first P-type layer and / or the second P-type layer is GaN or Al z Ga 1-z N, where z < y1 or z < y2;

[0038] When the material of the first P-type layer and / or the second P-type layer is GaN, the growth conditions include: a growth thickness of 50 - 300 nm, a growth temperature of 950 - 1100 °C, a growth pressure of 100 - 400 mbar, a V-III ratio of 5000 - 20000, and a carrier gas of H2 or a carrier gas of a mixture of H2 and N2;

[0039] When the material of the first P-type layer and / or the second P-type layer is Al z Ga 1-z N, the growth conditions include: a growth thickness of 50 - 300 nm, a growth temperature of 1100 - 1250 °C, a growth pressure of 50 - 200 mbar, a V-III ratio of 500 - 3000, and a carrier gas of H2.

[0040] Where, 0.15 < z < 0.65.

[0041] In some possible embodiments, after forming a conductive layer on the surface of the mask layer, the preparation method further includes:

[0042] Removing a part of the conductive layer until the mask layer is exposed, so that a second blank area located between the conductive layers corresponding to adjacent two second light-emitting structures is formed on the surface of the mask layer;

[0043] Forming an insulating layer in the second blank area, and the top surface of the insulating layer is flush with the top surface of the conductive layer;

[0044] Removing another part of the conductive layer until the top surface of the second light-emitting structure is exposed, so that a third blank area is formed on the top surface of the second light-emitting structure.

[0045] Forming a second dielectric layer in the third blank area, and the top surface of the second dielectric layer is flush with the top surface of the conductive layer.

[0046] In some possible embodiments, forming the N electrode, the first P electrode corresponding to each first light-emitting structure, and the second P electrode corresponding to each second light-emitting structure includes:

[0047] Forming a second P electrode on the top surface of the conductive layer covering the surface of the second light-emitting structure;

[0048] Sequentially removing a part of the conductive layer and a part of the protective layer on the top surface of the first light-emitting structure until the first light-emitting structure is exposed, and forming the first P electrode on the first light-emitting structure;

[0049] Part of the conductive layer and part of the mask layer are removed in sequence until the N-type layer is exposed, and the N-electrode is formed on the N-type layer.

[0050] A second aspect of the present invention provides a dual-color LED, comprising:

[0051] substrate;

[0052] An N-type layer and a mask layer are sequentially arranged on the surface of the substrate, wherein the mask layer has a plurality of spaced blank areas exposing the N-type layer;

[0053] A plurality of nanopillars, with one nanopillar being provided in each blank area;

[0054] A first light-emitting structure is provided on the top surface of the nanocolumn, and a second light-emitting structure is provided on at least part of the side surface of the nanocolumn and located on the surface of the mask layer, wherein the first light-emitting structure and the second light-emitting structure emit light of different colors;

[0055] A first P-electrode is provided on the top surface of the first light-emitting structure, and a completely covering protective layer is provided on the side surface of the first light-emitting structure;

[0056] a conductive layer, disposed on a surface of the mask layer and covering a surface of the second light-emitting structure;

[0057] a second P electrode, located on the surface of the conductive layer outside the outermost nanopillars and the surface of the conductive layer between the nanopillars;

[0058] The N-electrode is arranged on the surface of the N-type layer and is located on the other outer side of the outermost nanocolumn.

[0059] In some possible implementations, the bi-color LED further includes an insulating layer and a second dielectric layer, the insulating layer being disposed on the surface of the mask layer and between the conductive layers corresponding to two adjacent second light-emitting structures, and the second dielectric layer being disposed around the protective layer; and / or

[0060] The dual-color LED further includes a first dielectric layer, which is disposed on the surface of the conductive layer and covers at least the side surfaces of the first P-electrode and / or the second P-electrode; and / or

[0061] The top surface of the conductive layer is flush with the top surface of the protective layer.

[0062] Compared with the prior art, the beneficial effects of the present invention are: by preparing the second light-emitting structure and the first light-emitting structure respectively in selected areas in different directions on the nanopillar, using the nanopillar as the core, light-emitting structures with different light-emitting wavelengths are formed in different axial and radial directions, thereby realizing the integration of two-color LEDs based on nanopillars; through the structural design of the protective layer, the second light-emitting structure and the first light-emitting structure are effectively isolated, reducing the optical crosstalk between the light-emitting structures; through the structural design of the conductive layer, the nanopillars are controlled by interconnected electrodes, and the entire chip is used to emit light or the light-emitting structures on multiple nanopillars are controlled to work simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 This is a schematic diagram of the structure of a dual-color LED in step 1 of the preparation method of the present invention;

[0064] Figure 2 This is a schematic diagram of the structure of a dual-color LED in step 2 of the preparation method of the present invention;

[0065] Figure 3 This is a schematic diagram of the structure of the dual-color LED in step 3 of the preparation method of the present invention;

[0066] Figure 4 This is a schematic structural diagram of a dual-color LED in step 321 of the preparation method of the present invention;

[0067] Figure 5 This is a schematic structural diagram of a dual-color LED in step 322 of the preparation method of the present invention;

[0068] Figure 6 This is a schematic diagram of the structure of a dual-color LED in step 4 of the preparation method of the present invention;

[0069] Figure 7a Schematic diagram of the structure of the dual-color LED in step 51a and step 52a of the preparation method of the present invention;

[0070] Figure 7b Schematic diagram of the structure of the dual-color LED in step 51b and step 52b of the preparation method of the present invention;

[0071] Figure 8a Schematic diagram of the structure of the dual-color LED in step 61a of the preparation method of the present invention Figure 1 ;

[0072] Figure 8b Schematic diagram of the structure of the dual-color LED in step 61a of the preparation method of the present invention Figure 2 ;

[0073] Figure 9a Schematic diagram of the structure of the dual-color LED in step 62a of the preparation method of the present invention Figure 1 ;

[0074] Figure 9b Schematic diagram of the structure of the dual-color LED in step 62a of the preparation method of the present invention Figure 2 ;

[0075] Figure 9c Schematic diagram of the structure of the dual-color LED in step 62a of the preparation method of the present invention Figure 3 ;

[0076] Figure 9d Schematic diagram of the structure of the dual-color LED in step 62a of the preparation method of the present invention Figure 4 ;

[0077] Figure 10a Schematic diagram of the structure of the dual-color LED in step 63a of the preparation method of the present invention Figure 1 ;

[0078] Figure 10b Schematic diagram of the structure of the dual-color LED in step 63a of the preparation method of the present invention Figure 2 ;

[0079] Figure 10c Schematic diagram of the structure of the dual-color LED in step 63a of the preparation method of the present invention Figure 3 ;

[0080] Figure 10d Schematic diagram of the structure of the dual-color LED in step 63a of the preparation method of the present invention Figure 4 ;

[0081] Figure 11a Schematic diagram of the structure of the dual-color LED in step 64a of the preparation method of the present invention Figure 1 ;

[0082] Figure 11b Schematic diagram of the structure of the dual-color LED in step 64a of the preparation method of the present invention Figure 2 ;

[0083] Figure 11c Schematic diagram of the structure of the dual-color LED in step 64a of the preparation method of the present invention Figure 3 ;

[0084] Figure 11d Schematic diagram of the structure of the dual-color LED in step 64a of the preparation method of the present invention Figure 4 ;

[0085] Figure 12 This is a schematic structural diagram of a dual-color LED in step 62b of the preparation method of the present invention;

[0086] Figure 13 This is a schematic structural diagram of a dual-color LED in step 63b of the preparation method of the present invention;

[0087] Figure 14This is a schematic structural diagram of a dual-color LED in step 64b of the preparation method of the present invention;

[0088] Figure 15 This is a schematic structural diagram of a dual-color LED in step 651 of the preparation method of the present invention;

[0089] Figure 16 This is a schematic diagram of the structure of the dual-color LED in step 652 of the preparation method of the present invention;

[0090] Figure 17 This is a schematic diagram of the structure of the dual-color LED in step 653 of the preparation method of the present invention;

[0091] Figure 18 This is a schematic diagram of the structure of the dual-color LED in step 654 of the preparation method of the present invention;

[0092] Figure 19 Another structural schematic diagram of the dual-color LED provided by the present invention;

[0093] Figure 20 Schematic diagram of the structure of the dual-color LED in comparative example 1.

[0094] In the figure, 1. substrate; 2. N-type layer; 3. mask layer; 4. nanopillar; 5. first light-emitting structure; 51. first quantum well layer; 52. first P-type layer; 6. protective layer; 7. second light-emitting structure; 71. second quantum well layer; 72. second P-type layer; 8. conductive layer; 9. first dielectric layer; 10. first P-electrode; 11. second P-electrode; 12. N-electrode; 13. insulating layer; 14. second dielectric layer. DETAILED DESCRIPTION

[0095] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the drawings represent identical or similar structures, and thus repeated descriptions thereof will be omitted.

[0096] The words expressing positions and directions described in the present invention are all explained with reference to the accompanying drawings as examples, but can be modified as needed, and all such modifications are within the scope of protection of the present invention.

[0097] Please refer to Figures 1 to 6 This embodiment provides a method for preparing a dual-color LED, including steps 1 to 6.

[0098] Step 1: Provide a substrate 1, and sequentially stack an N-type layer 2 and a mask layer 3 on the top surface of the substrate 1. Figure 1 shown.

[0099] The substrate 1 may be a Si substrate, a SiC substrate, a silicon germanium substrate, a III-V compound substrate (such as a gallium nitride substrate or an aluminum nitride substrate), a silicon carbide substrate or a stacked structure thereof, a diamond, a sapphire substrate or other semiconductor material substrates known to those skilled in the art.

[0100] In one embodiment, sequentially stacking the N-type layer 2 and the mask layer 3 on the top surface of the substrate 1 includes the following steps:

[0101] Step 11: epitaxially grow an N-type layer 2 on the top surface of the substrate 1 by MOCVD (Metal-organic Chemical Vapor Deposition).

[0102] The material of the N-type layer 2 can be n-type GaN; the thickness of the N-type layer 2 is 500 nm to 2 μm. The growth conditions of the N-type layer 2 include: temperature of 1000-1100°C, growth pressure of 100-400 mbar, V / III ratio of 500-3000, and carrier gas of H2 (or a mixture of H2 and N2).

[0103] It is worth noting that the V / III ratio in the present invention refers to the molar flow ratio of group V elements to group III elements.

[0104] In some embodiments, the N-type layer 2 may be epitaxially grown on the substrate 1 by MBE (Molecular beam epitaxy) or HVPE (Hydride Vapor Phase Epitaxy).

[0105] Step 12: Deposit a mask layer 3 on the top surface of the N-type layer 2 by PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0106] The mask layer 3 is used as a base layer for the growth of the nanorods 4. The material of the mask layer 3 can be SiN x , SiO2, or Al2O3, and the deposition thickness of mask layer 3 is 30-200 nm. The deposition conditions of mask layer 3 include: deposition pressure of 200-600 mbar, RF power of 30-70 W, N2O flow rate of 100-500 sccm, and NH3 flow rate of 10-50 sccm.

[0107] In some embodiments, the mask layer 3 may be deposited on the N-type layer 2 by methods such as LPCVD (Low Pressure Chemical Vapor Deposition), ALD (atomic layer deposition), or magnetron sputtering.

[0108] Step 2: remove part of the mask layer 3 so that the mask layer 3 forms a plurality of first blank areas exposing the N-type layer 2, and form a nanorod 4 in each first blank area. Figure 2 shown.

[0109] The material of the nanorods 4 may be GaN. It should be noted that the conductivity type of the nanorods 4 is n-type by Si doping, Ge doping or unintentional doping.

[0110] In one embodiment, step 2 includes step 21 and step 22.

[0111] Step 21 : removing a portion of the mask layer 3 by standard photolithography and etching processes, so that the mask layer 3 forms a plurality of spaced first blank areas exposing the N-type layer 2 .

[0112] The etched depth of the mask layer 3 is consistent with the thickness of the mask layer 3, that is, its thickness is 30-200 nm. The first blank area is used as a growth window for the nanorods 4, and its diameter is 300-2000 nm. The spacing between two adjacent first blank areas is 500-3000 nm.

[0113] Step 22: Growing a nanorod 4 in each first blank area by MOCVD.

[0114] The thickness of the nanopillars 4 is 500-5000 nm. The growth conditions of the nanopillars 4 include: a temperature of 850-1000°C, a growth pressure of 50-200 mbar, a V / III ratio of 50-400, and a carrier gas of H2 (or a mixture of H2 and N2).

[0115] The above scheme achieves selective epitaxial growth of nanopillars 4. By growing an n-type layer 2 and depositing a mask layer 3 on substrate 1, photolithography and etching processes are used to form multiple first blank areas arranged in an array, allowing for controllable diameter and spacing of the growth windows for nanopillars 4. Nanopillars 4 are grown within these first blank areas using MOCVD technology and then doped to achieve n-type conductivity. This process ensures the dimensional accuracy and growth consistency of the nanopillars 4, providing a stable growth foundation for the integrated dual-color quantum well layer.

[0116] Step 3: Form a first light emitting structure 5 on the top surface of each nanorod 4, and form a protective layer 6 covering the side surfaces of the first light emitting structure 5. Figure 3 and Figure 4 shown.

[0117] In one embodiment, step 3 includes step 31 and step 32 .

[0118] Step 31 : sequentially growing a stacked first quantum well layer 51 and a first P-type layer 52 on the top surface of the nanorod 4 to obtain a first light-emitting structure 5 .

[0119] In one embodiment, step 31 includes step 311 and step 312 .

[0120] Step 311 : growing a first quantum well layer 51 on the top surface of the nanorod 4 by MOCVD.

[0121] The first quantum well layer 51 includes a plurality of first quantum well structures sequentially stacked and grown along the top surface of the nanorod 4 ; the material and composition of the first quantum well structure can be set according to the requirements of the light emission wavelength.

[0122] In one embodiment, the luminescent color of the first quantum well structure is blue light, and the first quantum well structure includes a stacked first In a Ga 1-a The growth cycle of the N-well layer and the first GaN barrier layer is 1 to 10. The first quantum well structure is grown using the following scheme:

[0123] A1) Under the first growth condition, a first In is grown on the top surface of the nanorod 4. a Ga 1-a N-well layer.

[0124] First In a Ga 1-a The N-well layer is grown to a thickness of 2 to 3 nm. The first growth conditions include: a growth temperature of 700 to 800°C, a growth pressure of 200 to 600 mbar, a V-III ratio of 10,000 to 40,000, and N2 as a carrier gas.

[0125] A2) Under the second growth condition, a Ga 1-a A first GaN barrier layer is grown on the top surface of the N-well layer.

[0126] The first GaN barrier layer is grown to a thickness of 8 to 15 nm. The second growth conditions include: a growth temperature of 830 to 950°C, a growth pressure of 200 to 600 mbar, a V-III ratio of 5,000 to 20,000, and N2 as a carrier gas.

[0127] It should be noted that 0.08 <a<0.3。

[0128] In another embodiment, the luminescent color of the first quantum well structure is ultraviolet light, and the first quantum well structure includes a stacked first Al x1 Ga 1-x1 The N well layer and the first Al y1 Ga 1-y1 The growth cycle of the N barrier layer and the first quantum well structure is 1 to 10. The following scheme is used to grow the first quantum well structure:

[0129] B1) Under the third growth condition, a first Al x1 Ga 1-x1 N-well layer.

[0130] First Al x1 Ga 1-x1 The N-well layer is grown to a thickness of 1 to 3 nm. The third growth conditions include: a growth temperature of 1100 to 1250°C, a growth pressure of 50 to 200 mbar, a V-III ratio of 500 to 3000, and a carrier gas of H2.

[0131] B2) Under the fourth growth condition, the first Al x1 Ga 1-x1 The first Al y1 Ga 1-y1 N layers.

[0132] First Al y1 Ga 1-y1 The N barrier layer is grown to a thickness of 5 to 15 nm. The fourth growth conditions include: a growth temperature of 1100 to 1250°C, a growth pressure of 50 to 200 mbar, a V-III ratio of 100 to 3000, and a carrier gas of H2.

[0133] It should be noted that 0.1 <x1<0.5,0.2<y1<0.6,x1<y1。

[0134] Step 312 : growing a first P-type layer 52 on the top surface of the first quantum well layer 51 by MOCVD.

[0135] In one embodiment, the material of the first P-type layer 52 can be p-type GaN; the growth thickness of the first P-type layer 52 is 50~300nm; the growth conditions of the first P-type layer 52 include: temperature of 950~1100ºC, growth pressure of 100~400mbar, V / III ratio of 5000~20000, and carrier gas of H2 (or a mixture of H2 and N2).

[0136] In another embodiment, the material of the first P-type layer 52 can be p-type Al z Ga 1-zN; the growth thickness of the first P-type layer 52 is 50~300nm; the growth conditions of the first P-type layer 52 include: a growth temperature of 1100~1250ºC, a growth pressure of 50~200mbar, a V-III ratio of 500~3000, and a carrier gas of H2.

[0137] It should be noted that 0.15 <z<0.65,z<y1。

[0138] By growing the first quantum well structure and the first P-type layer 52 on the top of the nanorod 4, the first axial light-emitting structure 5 is grown. The first light-emitting structure 5 emits light on the top of the nanorod 4, providing a light source for the dual-color LED.

[0139] Step 32 : forming a protection layer 6 on the top surface of the first light emitting structure 5 to cover the side surfaces of the first light emitting structure 5 .

[0140] In one embodiment, step 32 includes step 321 and step 322 .

[0141] Step 321: forming a protective layer 6 on the top surface of the first light emitting structure 5 and extending to the side surface of the corresponding nanorod 4. Figure 4 shown.

[0142] The protective layer 6 can be made of one or more of SiNx, SiO2, or Al2O3, and has a growth or deposition thickness of 20 to 200 nm. The protective layer 6 effectively isolates the first light-emitting structure 5 from the second light-emitting structure 7, preventing them from connecting and achieving conduction, and reducing optical crosstalk between them.

[0143] In one embodiment, after the first light-emitting structure 5 is grown by MOCVD, SiH4 and NH3 are simultaneously introduced into the MOCVD reaction chamber, and a protective layer 6 is grown on the top surface of the first P-type layer 52 of the first light-emitting structure 5 and extends to the side of the corresponding nanopillar 4. The growth conditions of the protective layer 6 include: a growth temperature of 1050~1150 ºC, a growth pressure of 50~200 mbar, an NH3 flow rate of 3000~5000sccm, a SiH4 flow rate of 20~50sccm, and a carrier gas of H2.

[0144] In another embodiment, a protective layer 6 extending to the side of the corresponding nanopillar 4 is formed by PECVD deposition on the top surface of the first P-type layer 52 of the first light-emitting structure 5. The deposition conditions of the protective layer 6 include: deposition pressure of 200~600mbar, RF power of 30~70W, SiH4 flow rate of 50~250sccm, and NH3 flow rate of 10~50sccm.

[0145] It should be noted that the protective layer 6 extending to the side surfaces of the corresponding nanopillars 4 can also be formed on the top surface of the first light-emitting structure 5 by LPCVD (Low Pressure Chemical Vapor Deposition), ALD (atomic layer deposition) or magnetron sputtering.

[0146] Step 322: Etch and remove part of the protective layer 6 at a preset etching angle to expose at least part of the side surface of the nanorod 4, so that the remaining protective layer 6 at least covers the top surface and side surfaces of the first light-emitting structure 5. Figure 5 shown.

[0147] Part of the protective layer 6 located on the sidewalls of the nanorods 4 is removed by standard photolithography and etching processes. The etching depth of the part of the protective layer 6 is consistent with the thickness of the protective layer 6, which is 20-200 nm.

[0148] Furthermore, by controlling the conditions during the photolithography and etching processes, the protective layer 6 on the sidewalls of the nanorods 4 is etched at a certain angle (i.e., a preset etching angle), so that the remaining protective layer 6 at least covers the first light-emitting structure 5. The preset etching angle ranges from 30° to 60°.

[0149] After the growth of the first light-emitting structure 5 is completed, a protective layer 6 is prepared, and the protective layer 6 on the side wall is removed by photolithography and etching processes to ensure that when the second light-emitting structure 7 is grown, epitaxial growth is only performed on the exposed side walls of the nanopillars 4. The protective layer 6 effectively prevents the influence of radial growth on the axial structure, ensuring the independence and controllability of the dual-color quantum well LED.

[0150] Step 4: forming a second light emitting structure 7 on at least part of the side surface of each nanorod 4. Figure 6 shown.

[0151] A second quantum well layer 71 and a second P-type layer 72 are sequentially grown and stacked on at least part of the side surfaces of the nanorods 4 along the radial direction of the nanorods 4 to obtain a second light emitting structure 7 .

[0152] In one embodiment, step 4 includes step 41 and step 42 .

[0153] Step 41 : growing a second quantum well layer 71 along the radial direction of the nanorod 4 on at least part of the side surface of the nanorod 4 by MOCVD.

[0154] Because the top surface of the nanopillars 4 is covered by the protective layer 6, the second quantum well layer 71 grows only on the exposed sidewalls of the nanopillars 4. The second quantum well layer 71 includes multiple second quantum well structures stacked and grown sequentially along the sides of the nanopillars 4. The material composition and components of the second quantum well structures can be set according to the requirements of the emission wavelength.

[0155] In one embodiment, the second quantum well structure emits green light, and the second quantum well structure includes a stacked second In b Ga 1-b The N-well layer and the second GaN barrier layer. The growth cycle of the first quantum well structure is 1 to 10. The second quantum well structure is grown using the following scheme:

[0156] A1) Under the first growth condition, a second In is grown on at least part of the side surface of the nanorod 4 along the radial direction of the nanorod 4. b Ga 1-b N-well layer.

[0157] Second In b Ga 1-b The N-well layer is grown to a thickness of 2 to 3 nm. The first growth conditions include: a growth temperature of 700 to 800°C, a growth pressure of 200 to 600 mbar, a V-III ratio of 10,000 to 40,000, and a carrier gas of N2.

[0158] It should be noted that 0.12 <b<0.3。

[0159] A2) Under the second growth condition, a second GaN barrier layer is grown on the side of the second InGaN well layer along the radial direction of the nanorods 4 .

[0160] The second GaN barrier layer is grown to a thickness of 8 to 15 nm. The second growth conditions include: a growth temperature of 830 to 950°C, a growth pressure of 200 to 600 mbar, a V-III ratio of 5000 to 20000, and N2 as a carrier gas.

[0161] In another embodiment, the second quantum well structure emits ultraviolet light, and the second quantum well structure includes a stacked second Al x2 Ga 1-x2 N well layer and the second Al y2 Ga 1-y2 The growth cycle of the N barrier layer and the second quantum well structure is 1 to 10. The second quantum well structure is grown using the following scheme:

[0162] B1) Under the third growth condition, a second Al2O3 layer is grown on at least part of the side surface of the nanorod 4 along the radial direction of the nanorod 4. x2 Ga 1-x2 N-well layer.

[0163] Second Al x2 Ga 1-x2 The N-well layer is grown to a thickness of 1 to 3 nm. The third growth conditions include: a growth temperature of 1100 to 1250°C, a growth pressure of 50 to 200 mbar, a V-III ratio of 500 to 3000, and a carrier gas of H2.

[0164] B2) Under the fourth growth condition, the second Al x2 Ga 1-x2 A second Al layer is grown on the side of the N-well layer y2 Ga 1-y2 N layers.

[0165] Second Al y2 Ga 1-y2 The N barrier layer is grown to a thickness of 5 to 15 nm. The fourth growth conditions include: a growth temperature of 1100 to 1250°C, a growth pressure of 50 to 200 mbar, a V-III ratio of 100 to 3000, and a carrier gas of H2.

[0166] It should be noted that 0.3 <x2<0.6,0.4<y2<0.8。

[0167] Step 42 : growing a second P-type layer 72 on the side of the first quantum well layer 51 by MOCVD.

[0168] In one embodiment, the material of the second P-type layer 72 can be p-type GaN; the growth thickness of the second P-type layer 72 is 50~300nm; the growth conditions of the second P-type layer 72 include: temperature of 950~1100ºC, growth pressure of 100~400mbar, V / III ratio of 5000~20000, and carrier gas of H2 (or a mixture of H2 and N2).

[0169] In another embodiment, the material of the second P-type layer 72 can be p-type Al z Ga 1-z N; the growth thickness of the second P-type layer 72 is 50~300nm; the growth conditions of the second P-type layer 72 include: a growth temperature of 1100~1250ºC, a growth pressure of 50~200mbar, a V-III ratio of 500~3000, and a carrier gas of H2.

[0170] It should be noted that 0.15 <z<0.65。

[0171] The above solution uses MOCVD technology to grow the second light-emitting structure 7 and second P-type layer 72 on the sidewalls of the nanopillars 4, achieving radial growth of the second light-emitting structure 7. Because the tops of the nanopillars 4 are protected by the protective layer 6, the quantum well material grows only in the exposed areas of the sidewalls. By adjusting the material composition and growth parameters, different wavelengths of light can be emitted from the first light-emitting structure 5, resulting in a richer color combination for the dual-color LED.

[0172] The above steps allow for the integration of two color light-emitting structures: the first light-emitting structure 5 and the second light-emitting structure 7. Different electrode preparation schemes can be employed depending on the application requirements. For example, if each nanopillar 4 needs to be independently controlled, the nanopillars 4 can be isolated from each other and non-interconnected electrodes can be prepared. If a dual-color LED is to be used for full-chip illumination or to control the simultaneous operation of multiple nanopillars 4, interconnected electrodes can be prepared to control the nanopillars 4. The following uses interconnected electrodes as an example to illustrate electrode preparation.

[0173] Step 5: depositing a conductive layer 8 on the surface of the mask layer 3 to cover the surface of the second light emitting structure 7 .

[0174] In one embodiment, step 5 includes step 51a and step 52a.

[0175] Step 51a: forming a conductive layer 8 on the surface of the mask layer 3 and the protective layer 6 by magnetron sputtering. Figure 7a shown.

[0176] The material of the conductive layer 8 can be ITO (Indium Tin Oxide, tin-doped indium oxide), and the thickness of the conductive layer 8 is not less than the height of the second light-emitting structure 7. For example, the thickness of the conductive layer 8 is 700~2500nm. The magnetron sputtering conditions of the conductive layer 8 include: sputtering temperature of 300~400℃, flow ratio of oxygen and argon of 1:60~90, sputtering pressure of 0.2~0.5 Pa, and sputtering power density of 0.1~0.3W / cm 2 .

[0177] Step 52a: remove part of the conductive layer 8 on the surface of the second light emitting structure 7 by standard photolithography and etching processes, so that the remaining conductive layer 8 covers the second light emitting structure 7 and the top surface of the conductive layer 8 covering the second light emitting structure 7 does not exceed the top surface of the first light emitting structure 5.

[0178] In another embodiment, step 5 includes steps 51b and 52b. Figure 7b shown.

[0179] Step 51b: forming a conductive layer 8 on the surface of the mask layer 3 by magnetron sputtering.

[0180] Step 51 b : removing a portion of the conductive layer 8 by standard photolithography and etching processes, so that the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7 does not exceed the top surface of the protective layer 6 .

[0181] Furthermore, the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7 is flush with the top surface of the protective layer 6 .

[0182] The conductive layer 8 is used to realize electrode interconnection between the nano-pillars 4 and to realize light emission control of the second light-emitting structure 7 and the first light-emitting structure 5 on the plurality of nano-pillars 4 .

[0183] Step 6: forming an N electrode 12 , a first P electrode 10 corresponding to each first light emitting structure 5 , and a second P electrode 11 corresponding to each second light emitting structure 7 .

[0184] The first P-electrode 10 is disposed on each first light emitting structure 5 , the second P-electrode 11 is disposed on the conductive layer 8 , and the N-electrode 12 is disposed on the N-type layer 2 .

[0185] In one embodiment, step 6 includes steps 61a to 64a.

[0186] Step 61a: Form a second P-electrode 11 by electron beam evaporation on the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7. Figure 8c 、 Figure 8b or Figure 8a shown.

[0187] The second P electrodes 11 are connected to each other and are led out through metal wires; preferably, the second P electrodes 11 are mesh-shaped to enhance the current spreading effect.

[0188] Further, if Figure 8c As shown, the top surface of the second P electrode 11 is lower than the top surface of the protective layer 6. Alternatively, as shown in FIG. Figure 8b As shown, the top surface of the second P electrode 11 is higher than the top surface of the protective layer 6. Alternatively, the top surface of the second P electrode 11 can be flush with the top surface of the protective layer 6. Alternatively, as shown Figure 8a As shown, a conductive layer 8 is provided on the top surface of the protective layer 6 , and the top surface of the second P-electrode 11 is lower than the top surface of the conductive layer 8 .

[0189] Step 62a: deposit a first dielectric layer 9 on the surface of the conductive layer 8 by PECVD, ALD or magnetron sputtering process, and the first dielectric layer 9 at least covers the side surface of the second P electrode 11. Figure 9e 、 9b , 9c or 9b.

[0190] The material of the first dielectric layer 9 can be one or more of SiNx, SiO2, or Al2O3, and the deposition thickness of the first dielectric layer 9 is 80-200 nm. The function of the first dielectric layer 9 is to effectively isolate adjacent nanopillars 4 and reduce optical crosstalk between the light-emitting structures of the nanopillars 4.

[0191] Further, if Figure 9e As shown, the first dielectric layer 9 covers the side surface of the second P electrode 11, the top surface of the second P electrode 11, the top surface of the protective layer 6, and part of the side surface of the protective layer 6. Alternatively, as shown Figure 9b As shown, the first dielectric layer 9 covers the side surface of the second P electrode 11, the top surface of the second P electrode 11 and part of the side surface of the protective layer 6. Alternatively, as shown Figure 9c As shown, the first dielectric layer 9 covers part of the side surface of the second P electrode 11, the top surface of the protective layer 6 and part of the side surface of the protective layer 6. Alternatively, as shown Figure 9d As shown, the first dielectric layer 9 covers part of the side surface of the second P electrode 11 and part of the side surface of the protective layer 6. Alternatively, as shown Figure 9a As shown, a conductive layer 8 is provided on the top surface of the protective layer 6 , and the first dielectric layer 9 covers the side and top surfaces of the second P electrode 11 , part of the side surfaces of the protective layer 6 , and the top and side surfaces of the conductive layer 8 on the protective layer 6 .

[0192] Step 63a: sequentially remove a portion of the first dielectric layer 9, a portion of the conductive layer 8 and a portion of the protective layer 6 on the top surface of the first light emitting structure 5 until the first light emitting structure 5 is exposed; and form a first P electrode 10 on the first light emitting structure 5. Figure 10e 、 Figure 10b 、 Figure 10c 、 Figure 10d or Figure 10a shown.

[0193] Part of the first dielectric layer 9, part of the conductive layer 8 and part of the protective layer 6 on the top surface of the first light-emitting structure 5 are removed in sequence by standard photolithography and etching until the first light-emitting structure 5 is exposed; then, a first P-electrode 10 is deposited on the exposed first light-emitting structure 5 by electron beam evaporation.

[0194] Further, Figure 9e After the structure shown above is processed, we get Figure 10e The structure shown. Figure 9b After the structure shown above is processed, we get Figure 10b The structure shown. Figure 9c After the structure shown above is processed, we get Figure 10c The structure shown. Figure 9d After the structure shown above is processed, we get Figure 10d The structure shown. Figure 10d After the structure shown above is processed, we get Figure 10a The structure shown.

[0195] Step 64a: sequentially remove a portion of the first dielectric layer 9, a portion of the conductive layer 8, and a portion of the mask layer 3 until the N-type layer 2 is exposed; and form an N-electrode 12 on the N-type layer 2. Figure 11e 、 11b , 11c, 11d or 11e.

[0196] Part of the first dielectric layer 9 , part of the conductive layer 8 and part of the mask layer 3 are removed in sequence by standard photolithography and etching processes until the N-type layer 2 is exposed; then, an N-electrode 12 is formed on the exposed N-type layer 2 by electron beam evaporation.

[0197] Specifically, the material of the first P-electrode 10 and the second P-electrode 11 can be Ni / Au or Ti / Au, and the thickness of the first P-electrode 10 and the second P-electrode 11 can be preferably 200 nm. The material of the N-electrode 12 can be Ti / Al / Ni / Au or Cr / Al / Ni / Au, and the thickness of the N-electrode 12 can be preferably 350 nm.

[0198] Conductive layer 8 is deposited via magnetron sputtering, and standard photolithography and etching processes are used to connect the second light-emitting structure 7 and the first light-emitting structure 5 of each nanopillar 4, achieving electrode interconnection and fabrication. Combined with electron beam evaporation and deposition of the first dielectric layer 9, the P-electrodes (including the first P-electrode 10 and the second P-electrode 11) and N-electrode 12 effectively connect the two-color LEDs in series or parallel, providing a reliable electrode structure for various optical control applications.

[0199] The above embodiment realizes interconnected electrodes to control the nanopillars 4 through the conductive layer 8 prepared by the above steps, uses the chip to emit light as a whole or controls multiple nanopillars 4 to work simultaneously, and realizes the integration of LEDs of different colors in the axial and radial directions of the nanopillars 4.

[0200] In another embodiment, electrodes that are not interconnected can be prepared. The difference from the above embodiment is that step 6 is different. Step 6 of this embodiment includes steps 61b to 63b. Figures 12 to 18 shown.

[0201] Step 61 b ​​: removing a portion of the conductive layer 8 until the mask layer 3 is exposed, so as to form a second blank area on the surface of the mask layer 3 between the conductive layers 8 corresponding to two adjacent second light-emitting structures 7 .

[0202] A portion of the conductive layer 8 is removed by standard photolithography and etching processes until the mask layer 3 is exposed. The second blank area is used as a growth window for the insulating layer 13 to be grown subsequently.

[0203] Step 62b: forming an insulating layer 13 in the second blank area, wherein the top surface of the insulating layer 13 is flush with the top surface of the conductive layer 8. Figure 12 shown.

[0204] In this embodiment, the insulating layer 13 is a transparent insulating layer. The material of the insulating layer 13 can be SiO2, SiN x Or photoresist, wherein the photoresist can be SU-8 photoresist, which is an epoxy-type near-ultraviolet negative photoresist.

[0205] Step 63b: remove another portion of the conductive layer 8 until the top surface of the second light emitting structure 7 is exposed, so that a third blank area is formed on the top surface of the second light emitting structure 7. Figure 13 shown.

[0206] Another portion of the conductive layer 8 is removed by standard photolithography and etching processes until the top surface of the second light emitting structure 7 is exposed. The third blank area is used as a growth window for the second dielectric layer 14 to be grown subsequently.

[0207] Step 64b: Form a second dielectric layer 14 in the third blank area by PECVD, ALD or magnetron sputtering process, and the top surface of the second dielectric layer 14 is flush with the top surface of the conductive layer 8. Figure 14 shown.

[0208] The material of the second dielectric layer 14 can be one or more of SiNx, SiO2 or Al2O3. The function of the second dielectric layer 14 is to effectively isolate adjacent nanorods 4 and reduce optical crosstalk of the light-emitting structures between the nanorods 4.

[0209] Step 65 b : forming an N electrode 12 , a first P electrode 10 corresponding to each first light emitting structure 5 , and a second P electrode 11 corresponding to each second light emitting structure 7 .

[0210] The first P-electrode 10 is disposed on each first light emitting structure 5 , the second P-electrode 11 is disposed on the conductive layer 8 , and the N-electrode 12 is disposed on the N-type layer 2 .

[0211] In one embodiment, step 65b includes steps 651 to 654.

[0212] Step 651: Remove another portion of the conductive layer 8 by standard photolithography and etching processes, so that the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7 is flush with the top surface of the second light emitting structure 7. Figure 15 shown.

[0213] Step 652: Form a second P-electrode 11 by electron beam evaporation on the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7. Figure 16 shown.

[0214] The second P-electrode 11 is in a mesh shape and is used to enhance the current spreading effect.

[0215] Step 653: sequentially remove a portion of the conductive layer 8 and a portion of the protective layer 6 on the top surface of the first light emitting structure 5 until the first light emitting structure 5 is exposed; and form a first P electrode 10 on the first light emitting structure 5. Figure 17 shown.

[0216] Part of the conductive layer 8 and part of the protective layer 6 on the top surface of the first light-emitting structure 5 are removed in sequence by standard photolithography and etching until the first light-emitting structure 5 is exposed; then, a first P-electrode 10 is deposited on the exposed first light-emitting structure 5 by electron beam evaporation.

[0217] Step 654: sequentially remove a portion of the conductive layer 8 and a portion of the mask layer 3 until the N-type layer 2 is exposed, and form an N-electrode 12 on the N-type layer 2. Figure 18 shown.

[0218] First, a portion of the conductive layer 8 and a portion of the mask layer 3 are removed in sequence by standard photolithography and etching processes until the N-type layer 2 is exposed; then, an N-electrode 12 is formed on the exposed N-type layer 2 by electron beam evaporation.

[0219] The insulating layer 13 prepared by the above steps realizes independent control of each nanocolumn 4 without interconnected electrodes, and realizes the integration of different color LEDs of the nanocolumns 4 in the axial and radial directions, that is, the light-emitting structures (the first light-emitting structure 5 and the second light-emitting structure 7).

[0220] The dual-color LED prepared by the above embodiment has the characteristics of high integration and high luminous efficiency, wavelength tunability, material applicability and control flexibility.

[0221] High integration and high luminous efficiency: A dual-color LED with a first quantum well layer 51 and a second quantum well layer 71 is grown on GaN nanopillars 4 using MOCVD technology, integrating two light-emitting structures with different orientations on the same nanopillar 4. While reducing device size, the high specific surface area and light extraction efficiency of the nanopillars 4 significantly improve the overall integration and optical performance of the dual-color LED.

[0222] Wavelength tunability: The first light-emitting structure 5 and the second light-emitting structure 7 are grown in the axial and radial directions of the nanopillar 4, respectively. By controlling the different growth materials and growth conditions of the first quantum well layer 51 and the second quantum well layer 71, the emission wavelength can be independently adjusted in the axial and radial directions, achieving more flexible two-color light output on the same nanopillar 4. This wavelength adjustment feature greatly broadens the application areas of two-color LEDs. For example, in the medical field, two-color wavelength LEDs can be used for imaging and diagnosis at specific wavelengths; different wavelengths of light energy can be used to detect oxygen content in the blood and tissue lesions, respectively, to provide support for precision medicine; in the field of sensing and environmental monitoring, two-color wavelength LEDs can be used to identify and detect the light absorption characteristics of different substances, thereby achieving rapid monitoring of air and water quality, etc., and provide a rich color selection for multi-wavelength lighting and display devices.

[0223] Material Applicability: Unlike conventional designs that rely solely on InGaN as the active region, this invention utilizes GaN nanopillars (4) as the core. By growing different materials in the axial and radial directions, the composition and structure of the grown materials can be adjusted to achieve emission across diverse spectral ranges, whether InGaN for blue light or AlGaN for ultraviolet light. The integration of the AlGaN structure, in particular, enables applications in ultraviolet lighting and sterilization, enhancing the diverse applications of dual-color LEDs.

[0224] Control Flexibility: The nanopillar structure can be controlled independently or interconnected through different electrode designs. Isolating and independently controlling each nanopillar provides greater flexibility for precise tuning and light mixing of the dual-color LED. Controlling the nanopillars with interconnected electrodes allows for large-scale, simultaneous illumination across the entire chip. This flexibility makes dual-color LEDs suitable for a wide range of applications in display, lighting, and biomedical fields.

[0225] The present invention also provides a product embodiment of a dual-color LED. The dual-color LED provided in this embodiment is prepared using the above-mentioned preparation method. Figure 11a-Figure 11e 、 Figure 18 as well as Figure 19 As shown, the dual-color LED includes a substrate 1 , an N-type layer 2 , a mask layer 3 , a plurality of nanorods 4 , a conductive layer 8 , a second P-electrode 11 and an N-electrode 12 .

[0226] The N-type layer 2 and the mask layer 3 are sequentially arranged on the surface of the substrate 1 . The mask layer 3 has a plurality of spaced blank areas exposing the N-type layer 2 . A nanorod 4 is arranged in each blank area.

[0227] A first light emitting structure 5 is disposed on the top surface of the nanorod 4 , and a second light emitting structure 7 located on the surface of the mask layer 3 is disposed on at least part of the side surface of the nanorod 4 . The first light emitting structure 5 and the second light emitting structure 7 emit different colors.

[0228] A first P-electrode 10 is provided on the top surface of the first light-emitting structure 5 , and a completely covering protection layer 6 is provided on the side surface of the first light-emitting structure 5 .

[0229] The conductive layer 8 is disposed on the surface of the mask layer 3 and covers the surface of the second light emitting structure 7 .

[0230] The second P-electrode 11 is located on the surface of the conductive layer 8 .

[0231] The N-electrode 12 is disposed on the surface of the N-type layer 2 and is located on the other outer side of the outermost nanorod 4 .

[0232] In one embodiment, the dual-color LED further includes a first dielectric layer 9 , which is disposed on the surface of the conductive layer 8 . It should be noted that the first dielectric layer 9 at least covers the side surface of the second P-electrode 11 .

[0233] In another embodiment, if Figure 18 As shown, the bi-color LED further includes an insulating layer 13, which is disposed on the surface of the mask layer 3 and between the conductive layers 8 corresponding to two adjacent second light-emitting structures 7. A second dielectric layer 14 is disposed around the protective layer 6. It should be noted that the insulating layer 13 covers the surface of the conductive layer 8 and the surface of the second light-emitting structure 7.

[0234] In another embodiment, if Figure 19 As shown, the top surface of the conductive layer 8 is flush with the top surface of the protective layer 6. Furthermore, a first dielectric layer may be provided on the conductive layer 8, and the first dielectric layer at least covers the side surfaces of the first P-electrode 10 and / or the second P-electrode 11.

[0235] The technical solution of the present application will be described in more detail below. However, it should be understood that the following examples are merely for the purpose of explaining and illustrating the technical solution and do not limit the scope of the present application. Furthermore, unless otherwise specified, the various raw materials, reaction equipment, detection equipment, and methods used in the following examples are all known in the art. Example 1

[0236] like Figures 1-6 as well as Figure 7a-Figure 11a This embodiment provides a method for preparing a dual-color LED, comprising the following steps:

[0237] Step 101: Provide a substrate 1 made of Si.

[0238] Step 102: Under the conditions of a temperature of 1000°C, a growth pressure of 100 mbar, a V / III ratio of 500, and a carrier gas of H2, an N-type layer 2 of n-type GaN with a thickness of 500 nm is epitaxially grown on the top surface of the substrate 1 by MOCVD. Figure 1 shown.

[0239] Step 103: SiN is deposited on the top surface of the N-type layer 2 by PECVD. x And the mask layer 3 with a thickness of 30nm, such as Figure 1 shown.

[0240] The deposition conditions of the mask layer 3 include: a deposition pressure of 200 mbar, a radio frequency power of 30 W, an N2O flow rate of 100 sccm, and an NH3 flow rate of 10 sccm.

[0241] Step 104 : removing a portion of the mask layer 3 by standard photolithography and etching processes, so that the mask layer 3 forms a plurality of spaced first blank areas exposing the N-type layer 2 .

[0242] The etching depth of the mask layer 3 is consistent with the thickness of the mask layer 3, that is, its thickness is 30 nm. The first blank area is used as a growth window for the nanorods 4, and its diameter is 300 nm. The distance between two adjacent first blank areas is 500 nm.

[0243] Step 105: Under the conditions of a growth temperature of 850°C, a growth pressure of 50 mbar, a V / III ratio of 50, and a carrier gas of H2, a GaN nanorod 4 with a thickness of 500 nm and doped with Si is grown in each first blank area by MOCVD. Figure 2 shown.

[0244] Step 106: grow the first quantum well layer 51 on the top surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 3 shown.

[0245] The first quantum well layer 51 includes a plurality of first quantum well structures that are stacked and grown in sequence along the top surface of the nanorod 4; the first quantum well structure includes a stacked first In a Ga 1-a The N well layer and the first GaN barrier layer have a growth cycle of one first quantum well structure.

[0246] Furthermore, the first quantum well structure is grown using the following scheme:

[0247] A1) A first In layer with a thickness of 2 nm was grown on the top surface of the nanorod 4 under the conditions of a growth temperature of 700°C, a growth pressure of 200 mbar, a V-III ratio of 10000, and N2 as the carrier gas. a Ga 1-a N-well layer, a=0.1.

[0248] A2) Under the conditions of growth temperature of 830°C, growth pressure of 200 mbar, V-III ratio of 5000 and carrier gas of N2, in the first In a Ga1-a A first GaN barrier layer with a thickness of 8 nm is grown on the top surface of the N-well layer.

[0249] Step 107: Under the conditions of a growth temperature of 950°C, a growth pressure of 100 mbar, a V / III ratio of 5000, and a carrier gas of H2, a first P-type layer 52 made of p-type GaN and having a thickness of 50 nm is grown on the top surface of the first quantum well layer 51 by MOCVD. Figure 3 shown.

[0250] Step 108: forming a protective layer 6 of SiNx with a thickness of 20 nm on the top surface of the first light emitting structure 5 and extending to the side surface of the corresponding nanocolumn 4. Figure 4 shown.

[0251] After the first light-emitting structure 5 is grown by MOCVD, SiH4 and NH3 are simultaneously introduced into the MOCVD reaction chamber to grow a protective layer 6 on the top surface of the first P-type layer 52 of the first light-emitting structure 5, extending to the side of the corresponding nanopillar 4. The growth conditions of the protective layer 6 include a growth temperature of 1050°C, a growth pressure of 50 mbar, an NH3 flow rate of 3000 sccm, a SiH4 flow rate of 20 sccm, and a carrier gas of H2.

[0252] Step 109: etching away a portion of the protective layer 6 at a preset etching angle to expose a portion of the side surfaces of the nanorods 4, so that the remaining protective layer 6 covers the top surface and side surfaces of the first light emitting structure 5, as shown in FIG. Figure 5 shown.

[0253] A portion of the protective layer 6 is removed by a standard photolithography and etching process, wherein the etching depth of the portion of the protective layer 6 is consistent with the thickness of the protective layer 6, which is 20 nm. The preset etching angle is 30°.

[0254] Step 110: grow the second quantum well layer 71 along the radial direction of the nanorod 4 on the exposed side surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 6 shown.

[0255] The second quantum well layer 71 includes a plurality of second quantum well structures sequentially stacked and grown along the side of the nanorod 4. The second quantum well structure includes stacked second In b Ga 1-b The N well layer and the second GaN barrier layer have a growth cycle of one first quantum well structure.

[0256] Furthermore, the second quantum well structure is grown using the following scheme:

[0257] A1) Under the conditions of growth temperature of 700°C, growth pressure of 200 mbar, V-III ratio of 1000 and N2 as carrier gas, a second In layer with a thickness of 2 nm is grown along the radial direction of the nano-pillar 4 on the exposed side of the nano-pillar 4. b Ga 1-b N-well layer, b=0.2.

[0258] A2) Under the conditions of growth temperature of 830°C, growth pressure of 200 mbar, V-III ratio of 5000 and carrier gas of N2, in the second In b Ga 1-b A second GaN barrier layer with a thickness of 8 nm is grown on the side of the N-well layer along the radial direction of the nano-pillars 4 .

[0259] Step 111: Under the conditions of a growth temperature of 950°C, a growth pressure of 100 mbar, a V / III ratio of 5000, and a carrier gas of H2, a second P-type layer 72 made of p-type GaN and having a thickness of 50 nm is grown on the side of the first quantum well layer 51 by MOCVD. Figure 6 shown.

[0260] Step 112: Deposit a conductive layer 8 on the surface of the mask layer 3 to cover the surface of the second light emitting structure 7, such as Figure 7a shown.

[0261] First, a conductive layer 8 made of ITO with a thickness of 700 nm is formed on the surface of the mask layer 3 and the protective layer 6 by magnetron sputtering. The magnetron sputtering conditions of the conductive layer 8 include: sputtering temperature of 300 °C, flow ratio of oxygen to argon of 1:60, sputtering pressure of 0.2 Pa, sputtering power density of 0.1 W / cm 2 .

[0262] Then, part of the conductive layer 8 on the surface of the second light emitting structure 7 is removed by standard photolithography and etching processes, so that the remaining conductive layer 8 covers the second light emitting structure 7 and the top surface of the conductive layer 8 covering the second light emitting structure 7 does not exceed the top surface of the first light emitting structure 5.

[0263] Step 113: Deposit a mesh-shaped second P-electrode 11 on the top surface of the conductive layer 8 covering the surface of the second light-emitting structure 7 by electron beam evaporation. Figure 8a shown.

[0264] The second P electrodes 11 are connected to each other and led out through metal wires.

[0265] Step 114: A first dielectric layer 9 made of SiO2 and having a thickness of 80 nm is formed on the surface of the conductive layer 8 by PECVD process. The first dielectric layer 9 covers the side and top surfaces of the second P electrode 11. Figure 9a shown.

[0266] Step 115: sequentially remove a portion of the first dielectric layer 9, a portion of the conductive layer 8 and a portion of the protective layer 6 on the top surface of the first light emitting structure 5 until the first light emitting structure 5 is exposed; form a first P electrode 10 on the first light emitting structure 5, as shown in FIG. Figure 10a shown.

[0267] Part of the first dielectric layer 9, part of the conductive layer 8 and part of the protective layer 6 on the top surface of the first light-emitting structure 5 are removed in sequence by standard photolithography and etching until the first light-emitting structure 5 is exposed; then, a first P-electrode 10 is deposited on the exposed first light-emitting structure 5 by electron beam evaporation.

[0268] Step 116: sequentially remove a portion of the first dielectric layer 9, a portion of the conductive layer 8, and a portion of the mask layer 3 until the N-type layer 2 is exposed; and form an N-electrode 12 on the N-type layer 2, as shown in FIG. Figure 11a shown.

[0269] Part of the first dielectric layer 9 , part of the conductive layer 8 and part of the mask layer 3 are removed in sequence by standard photolithography and etching processes until the N-type layer 2 is exposed; then, an N-electrode 12 is formed on the exposed N-type layer 2 by electron beam evaporation.

[0270] Specifically, the first and second P electrodes 10 and 11 are made of Ni / Au, and their thicknesses are preferably 200 nm, respectively. The N electrode 12 is made of Ti / Al / Ni / Au, and its thickness is preferably 350 nm. Example 2

[0271] like Figures 1-6 as well as Figure 7a-Figure 11a This embodiment provides a method for preparing a dual-color LED, comprising the following steps:

[0272] Step 101: Provide a substrate 1 made of Si.

[0273] Step 102: Under the conditions of a growth temperature of 1050°C, a growth pressure of 250 mbar, a V / III ratio of 1800, and a carrier gas of H2, an N-type layer 2 of n-type GaN with a thickness of 1800 nm is epitaxially grown on the top surface of the substrate 1 by MOCVD. Figure 1 shown.

[0274] Step 103: SiN is deposited on the top surface of the N-type layer 2 by PECVD. x And the mask layer 3 with a thickness of 120nm, such as Figure 1 shown.

[0275] The deposition conditions of the mask layer 3 include: a deposition pressure of 400 mbar, a radio frequency power of 50 W, an N2O flow rate of 300 sccm, and an NH3 flow rate of 30 sccm.

[0276] Step 104 : removing a portion of the mask layer 3 by standard photolithography and etching processes, so that the mask layer 3 forms a plurality of spaced first blank areas exposing the N-type layer 2 .

[0277] The etching depth of the mask layer 3 is consistent with the thickness of the mask layer 3, that is, its thickness is 120 nm. The first blank area is used as a growth window for the nanorods 4, and its diameter is 1200 nm. The distance between two adjacent first blank areas is 1800 nm.

[0278] Step 105: Under the conditions of a growth temperature of 930°C, a growth pressure of 130 mbar, a V / III ratio of 230, and a carrier gas of H2, a GaN nanorod 4 with a thickness of 3000 nm and doped with Ge is grown in each first blank area by MOCVD, as shown in FIG. Figure 2 shown.

[0279] Step 106: grow the first quantum well layer 51 on the top surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 3 shown.

[0280] The first quantum well layer 51 includes a plurality of first quantum well structures that are stacked and grown in sequence along the top surface of the nanorod 4; the first quantum well structure includes a stacked first In a Ga 1-a The N well layer and the first GaN barrier layer have five growth cycles for the first quantum well structure.

[0281] Further, growing the first quantum well structure includes:

[0282] A1) Under the conditions of growth temperature of 750°C, growth pressure of 400 mbar, V-III ratio of 25000 and N2 as carrier gas, a first In layer with a thickness of 2.5 nm is grown on the top surface of the nanorod 4. a Ga 1-a N-well layer, a=0.12.

[0283] A2) Under the conditions of growth temperature 890°C, growth pressure 400mbar, V-III ratio 13000, and carrier gas N2, in the first In a Ga 1-a A first GaN barrier layer with a thickness of 12 nm is grown on the top surface of the N-well layer.

[0284] Step 107: Under the conditions of a growth temperature of 1030°C, a growth pressure of 250 mbar, a V / III ratio of 18000, and a carrier gas of H2, a first P-type layer 52 of p-type GaN and a thickness of 180 nm is grown on the top surface of the first quantum well layer 51 by MOCVD. Figure 3 shown.

[0285] Step 108: forming a protective layer 6 on the top surface of the first light emitting structure 5, which is made of SiNx and has a thickness of 110 nm and extends to the side surface of the corresponding nanocolumn 4. Figure 4 shown.

[0286] Furthermore, after the first light-emitting structure 5 is grown by MOCVD, SiH4 and NH3 are simultaneously introduced into the MOCVD reaction chamber to grow a protective layer 6 extending from the top surface of the first P-type layer 52 of the first light-emitting structure 5 to the side surfaces of the corresponding nanopillars 4. The growth conditions of the protective layer 6 include:

[0287] Step 109: etching away a portion of the protective layer 6 at a preset etching angle to expose a portion of the side surfaces of the nanorods 4, so that the remaining protective layer 6 covers the top surface and side surfaces of the first light emitting structure 5, as shown in FIG. Figure 5 shown.

[0288] A portion of the protective layer 6 is removed by a standard photolithography and etching process, and the etching depth of the portion of the protective layer 6 is consistent with the thickness of the protective layer 6, which is 110 nm. The preset etching angle range is 45°.

[0289] Step 110: grow the second quantum well layer 71 along the radial direction of the nanorod 4 on the exposed side surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 6 shown.

[0290] The second quantum well layer 71 includes a plurality of second quantum well structures sequentially stacked and grown along the side of the nanorod 4. The second quantum well structure includes stacked second In b Ga 1-b The N well layer and the second GaN barrier layer have five growth cycles for the first quantum well structure.

[0291] In one embodiment, growing the second quantum well structure includes:

[0292] A1) Under the conditions of growth temperature of 750°C, growth pressure of 400 mbar, V-III ratio of 25000 and N2 as carrier gas, a second In layer with a thickness of 2.5 nm was grown along the radial direction of the nano-pillar 4 on the exposed side of the nano-pillar 4. b Ga 1-b N-well layer, b=0.21.

[0293] A2) Under the conditions of growth temperature 890°C, growth pressure 400mbar, V-III ratio 13000 and carrier gas N2, in the second In b Ga 1-b A second GaN barrier layer with a thickness of 12 nm is grown on the side of the N-well layer along the radial direction of the nano-pillars 4 .

[0294] Step 111: Under the conditions of a growth temperature of 1030°C, a growth pressure of 250 mbar, a V / III ratio of 13000, and a carrier gas of H2, a second P-type layer 72 of p-type GaN with a thickness of 180 nm is grown on the side of the first quantum well layer 51 by MOCVD. Figure 6 shown.

[0295] Step 112: Deposit a conductive layer 8 on the surface of the mask layer 3 to cover the surface of the second light emitting structure 7, such as Figure 7a shown.

[0296] First, a conductive layer 8 made of ITO with a thickness of 1600 nm is formed on the surface of the mask layer 3 and the protective layer 6 by magnetron sputtering. The magnetron sputtering conditions of the conductive layer 8 include: sputtering temperature of 350°C, flow ratio of oxygen to argon of 1:70, sputtering pressure of 0.35 Pa, sputtering power density of 0.2 W / cm 2 .

[0297] Then, part of the conductive layer 8 on the surface of the second light emitting structure 7 is removed by standard photolithography and etching processes, so that the remaining conductive layer 8 covers the second light emitting structure 7 and the top surface of the conductive layer 8 covering the second light emitting structure 7 does not exceed the top surface of the first light emitting structure 5.

[0298] Step 113: Deposit a mesh-shaped second P-electrode 11 on the top surface of the conductive layer 8 covering the surface of the second light-emitting structure 7 by electron beam evaporation. Figure 8a shown.

[0299] The second P electrodes 11 are connected to each other and led out through metal wires.

[0300] Step 114: A first dielectric layer 9 made of SiO2 and having a thickness of 140 nm is formed on the surface of the conductive layer 8. The first dielectric layer 9 covers the side and top surfaces of the second P-electrode 11. Figure 9a shown.

[0301] Step 115: sequentially remove a portion of the first dielectric layer 9, a portion of the conductive layer 8 and a portion of the protective layer 6 on the top surface of the first light emitting structure 5 until the first light emitting structure 5 is exposed; form a first P electrode 10 on the first light emitting structure 5, as shown in FIG. Figure 10a shown.

[0302] Part of the first dielectric layer 9, part of the conductive layer 8 and part of the protective layer 6 on the top surface of the first light-emitting structure 5 are removed in sequence by standard photolithography and etching until the first light-emitting structure 5 is exposed; then, a first P-electrode 10 is deposited on the exposed first light-emitting structure 5 by electron beam evaporation.

[0303] Step 116: sequentially remove a portion of the first dielectric layer 9, a portion of the conductive layer 8, and a portion of the mask layer 3 until the N-type layer 2 is exposed; and form an N-electrode 12 on the N-type layer 2, as shown in FIG. Figure 11a shown.

[0304] Part of the first dielectric layer 9 , part of the conductive layer 8 and part of the mask layer 3 are removed in sequence by standard photolithography and etching processes until the N-type layer 2 is exposed; then, an N-electrode 12 is formed on the exposed N-type layer 2 by electron beam evaporation.

[0305] Specifically, the first and second P electrodes 10 and 11 are made of Cr / Al / Ni / Au, and have a thickness of 200 nm, respectively. The N electrode 12 is made of Ti / Au, and has a thickness of 350 nm. Example 3

[0306] like Figures 1-6 as well as Figure 7a-Figure 11a This embodiment provides a method for preparing a dual-color LED, comprising the following steps:

[0307] Step 101: Provide a substrate 1 made of Si.

[0308] Step 102: Under the conditions of a growth temperature of 1100°C, a growth pressure of 400 mbar, a V / III ratio of 3000, and a carrier gas of H2, an N-type layer 2 of n-type GaN with a thickness of 2 μm is epitaxially grown on the top surface of the substrate 1 by MOCVD, as shown in FIG. Figure 1 shown.

[0309] Step 103: SiN is deposited on the top surface of the N-type layer 2 by PECVD. x And the mask layer 3 with a thickness of 200nm, such as Figure 1 shown.

[0310] The deposition conditions of the mask layer 3 include: a deposition pressure of 600 mbar, a radio frequency power of 70 W, an N2O flow rate of 500 sccm, and an NH3 flow rate of 50 sccm.

[0311] Step 104 : removing a portion of the mask layer 3 by standard photolithography and etching processes, so that the mask layer 3 forms a plurality of spaced first blank areas exposing the N-type layer 2 .

[0312] The etching depth of the mask layer 3 is consistent with the thickness of the mask layer 3, that is, its thickness is 200 nm. The first blank area is used as a growth window for the nanorods 4, and its diameter is 2000 nm. The distance between two adjacent first blank areas is 3000 nm.

[0313] Step 105: Under the conditions of a growth temperature of 1000°C, a growth pressure of 200 mbar, a V / III ratio of 400, and a carrier gas of H2, a GaN nanorod 4 with a thickness of 5000 nm and doped with Ge is grown in each first blank area by MOCVD, as shown in FIG. Figure 2 shown.

[0314] Step 106: grow the first quantum well layer 51 on the top surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 3 shown.

[0315] The first quantum well layer 51 includes a plurality of first quantum well structures that are stacked and grown in sequence along the top surface of the nanorod 4; the first quantum well structure includes a stacked first In a G a1-a The N well layer and the first GaN barrier layer have 10 growth cycles for the first quantum well structure.

[0316] Further, growing the first quantum well structure includes:

[0317] A1) Under the conditions of growth temperature 800°C, growth pressure 600 mbar, V-III ratio 40000 and N2 as carrier gas, a first In layer with a thickness of 3 nm is grown on the top surface of the nanorod 4. a G a1-a N-well layer, a=0.14.

[0318] A2) Under the conditions of growth temperature 950°C, growth pressure 600mbar, V-III ratio 20000, and carrier gas N2, in the first In a G a1-a A first GaN barrier layer with a thickness of 15 nm is grown on the top surface of the N-well layer.

[0319] Step 107: Under the conditions of a growth temperature of 1100°C, a growth pressure of 400 mbar, a V / III ratio of 20,000, and a carrier gas of H2, a first P-type layer 52 made of p-type GaN and having a thickness of 300 nm is grown on the top surface of the first quantum well layer 51 by MOCVD. Figure 3 shown.

[0320] Step 108: forming a protective layer 6 of SiNx with a thickness of 200 nm on the top surface of the first light emitting structure 5 and extending to the side surface of the corresponding nanocolumn 4. Figure 4 shown.

[0321] Furthermore, after the first light-emitting structure 5 is grown by MOCVD, SiH4 and NH3 are simultaneously introduced into the MOCVD reaction chamber to grow a protective layer 6 extending from the top surface of the first P-type layer 52 of the first light-emitting structure 5 to the side of the corresponding nanopillar 4. The growth conditions of the protective layer 6 include: growth temperature of 1150 ºC, growth pressure of 200 mbar, NH3 flow rate of 5000 sccm, SiH4 flow rate of 50 sccm, and carrier gas of H2.

[0322] Step 109: etching away a portion of the protective layer 6 at a preset etching angle to expose a portion of the side surfaces of the nanorods 4, so that the remaining protective layer 6 covers the top surface and side surfaces of the first light emitting structure 5, as shown in FIG. Figure 5 shown.

[0323] A portion of the protective layer 6 is removed by a standard photolithography and etching process, and the etching depth of the portion of the protective layer 6 is consistent with the thickness of the protective layer 6, which is 200 nm. The preset etching angle range is 60°.

[0324] Step 110: grow the second quantum well layer 71 along the radial direction of the nanorod 4 on the exposed side surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 6 shown.

[0325] The second quantum well layer 71 includes a plurality of second quantum well structures sequentially stacked and grown along the side of the nanorod 4. The second quantum well structure includes stacked second In b Ga 1-b The N well layer and the second GaN barrier layer have 10 growth cycles for the first quantum well structure.

[0326] In one embodiment, growing the second quantum well structure includes:

[0327] A1) Under the conditions of growth temperature of 800°C, growth pressure of 600 mbar, V-III ratio of 40000 and N2 as carrier gas, a second In layer with a thickness of 3 nm was grown along the radial direction of the nano-pillar 4 on the exposed side of the nano-pillar 4. b Ga 1-b N-well layer, b=0.23.

[0328] A2) Under the conditions of growth temperature of 950°C, growth pressure of 600mbar, V-III ratio of 20000 and carrier gas of N2, in the second In b Ga 1-b A second GaN barrier layer with a thickness of 15 nm is grown on the side of the N-well layer along the radial direction of the nano-pillars 4 .

[0329] Step 111: Under the conditions of a growth temperature of 1100°C, a growth pressure of 400 mbar, a V / III ratio of 20,000, and a carrier gas of H2, a second P-type layer 72 made of p-type GaN and having a thickness of 300 nm is grown on the side of the first quantum well layer 51 by MOCVD. Figure 6 shown.

[0330] Step 112: Deposit a conductive layer 8 on the surface of the mask layer 3 to cover the surface of the second light emitting structure 7, such as Figure 7a shown.

[0331] First, a conductive layer 8 made of ITO with a thickness of 2500 nm is formed on the surface of the mask layer 3 and the protective layer 6 by magnetron sputtering. The magnetron sputtering conditions of the conductive layer 8 include: sputtering temperature of 400°C, flow ratio of oxygen to argon of 1:90, sputtering pressure of 0.5 Pa, and sputtering power density of 0.3 W / cm 2 .

[0332] Then, part of the conductive layer 8 on the surface of the second light emitting structure 7 is removed by standard photolithography and etching processes, so that the remaining conductive layer 8 covers the second light emitting structure 7 and the top surface of the conductive layer 8 covering the second light emitting structure 7 does not exceed the top surface of the first light emitting structure 5.

[0333] Step 113: Deposit a mesh-shaped second P-electrode 11 on the top surface of the conductive layer 8 covering the surface of the second light-emitting structure 7 by electron beam evaporation. Figure 8a shown.

[0334] The second P electrodes 11 are connected to each other and led out through metal wires.

[0335] Step 114: a first dielectric layer 9 made of SiO2 and having a thickness of 200 nm is formed on the surface of the conductive layer 8. The first dielectric layer 9 covers the side and top surfaces of the second P electrode 11. Figure 9a shown.

[0336] Step 115: sequentially remove a portion of the first dielectric layer 9, a portion of the conductive layer 8 and a portion of the protective layer 6 on the top surface of the first light emitting structure 5 until the first light emitting structure 5 is exposed; form a first P electrode 10 on the first light emitting structure 5, as shown in FIG. Figure 10a shown.

[0337] Part of the first dielectric layer 9, part of the conductive layer 8 and part of the protective layer 6 on the top surface of the first light-emitting structure 5 are removed in sequence by standard photolithography and etching until the first light-emitting structure 5 is exposed; then, a first P-electrode 10 is deposited on the exposed first light-emitting structure 5 by electron beam evaporation.

[0338] Step 116: sequentially remove a portion of the first dielectric layer 9, a portion of the conductive layer 8, and a portion of the mask layer 3 until the N-type layer 2 is exposed; and form an N-electrode 12 on the N-type layer 2, as shown in FIG. Figure 11a shown.

[0339] Part of the first dielectric layer 9 , part of the conductive layer 8 and part of the mask layer 3 are removed in sequence by standard photolithography and etching processes until the N-type layer 2 is exposed; then, an N-electrode 12 is formed on the exposed N-type layer 2 by electron beam evaporation.

[0340] Specifically, the materials of the first P-electrode 10 and the second P-electrode 11 can be Cr / Al / Ni / Au, and the thickness of the first P-electrode 10 and the second P-electrode 11 can be preferably 200 nm. The material of the N-electrode 12 can be Ti / Al / Ni / Au, and the thickness of the N-electrode 12 can be preferably 350 nm. Example 4

[0341] like Figures 1-6 as well as Figure 7a-Figure 11a The difference between this embodiment and embodiment 1 is that step 106, step 107, step 110 and step 111 are different, and the rest are the same and will not be repeated here.

[0342] Step 106: grow the first quantum well layer 51 on the top surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 3 shown.

[0343] The first quantum well layer 51 includes a plurality of first quantum well structures that are sequentially stacked and grown along the top surface of the nanorod 4; the first quantum well structure includes a stacked first Al x1 Ga 1-x1 N and the first Al y1 Ga 1-y1 N barrier layer. The growth cycle of the first quantum well structure is 1.

[0344] The first quantum well structure is grown using the following scheme:

[0345] B1) Under the conditions of growth temperature 1100°C, growth pressure 50 mbar, V-III ratio 500 and H2 as carrier gas, a first Al layer with a thickness of 1 nm is grown on the top surface of the nanorod 4. x1 Ga 1-x1 N-well layer.

[0346] B2) Under the conditions of growth temperature 1100°C, growth pressure 50mbar, V-III ratio 100 and carrier gas H2, x1 Ga 1-x1 The first Al2O3 layer with a thickness of 5 nm is grown on the top surface of the N-well layer. y1 Ga 1-y1 N layers.

[0347] Among them, x1=0.18, y1=0.35.

[0348] Step 107: Under the conditions of a growth temperature of 1100°C, a growth pressure of 50 mbar, a V-III ratio of 500, and a carrier gas of H2, a p-type Al is grown on the top surface of the first quantum well layer 51 by MOCVD. z1 Ga 1-z1 N and a first P-type layer 52 with a thickness of 50 nm, such as Figure 3 shown.

[0349] It should be noted that z1=0.26.

[0350] Step 110: grow the second quantum well layer 71 along the radial direction of the nanorod 4 on the exposed side surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 6 shown.

[0351] The second quantum well layer 71 includes a plurality of second quantum well structures that are sequentially stacked and grown along the side of the nanorod 4. The second quantum well structure includes a stacked second Al x2 Ga 1-x2 N well layer and the second Al y2 Ga 1-y2 N barrier layer. The growth cycle of the first quantum well structure is 1.

[0352] The second quantum well structure is grown using the following scheme:

[0353] B1) Under the conditions of growth temperature of 1100°C, growth pressure of 50 mbar, V-III ratio of 500 and H2 as carrier gas, a second Al layer with a thickness of 1 nm is grown along the radial direction of the nano-pillar 4 on the exposed side surface of the nano-pillar 4. x2 Ga 1-x2 N-well layer.

[0354] B2) Under the conditions of growth temperature 1100°C, growth pressure 50mbar, V-III ratio 100, and carrier gas H2, in the second Al x2 Ga 1-x2 A second Al2O3 layer with a thickness of 5 nm is grown on the side of the N-well layer. y2 Ga 1-y2 N layers.

[0355] Step 111: Under the conditions of a growth temperature of 1100°C, a growth pressure of 50 mbar, a V / III ratio of 500, and a carrier gas of H2, a p-type Al2O3 layer is grown on the side of the first quantum well layer 51 by MOCVD. z2 Ga 1-z2 N and a second P-type layer 72 with a thickness of 50 nm, such as Figure 6 shown.

[0356] It should be noted that x2=0.4, y2=0.55, and z2=0.45. Example 5

[0357] like Figures 1-6 as well as Figure 7a-Figure 11a The difference between this embodiment and embodiment 2 is that step 106, step 107, step 110 and step 111 are different, and the rest are the same and will not be repeated here.

[0358] Step 106: grow the first quantum well layer 51 on the top surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 3 shown.

[0359] The first quantum well layer 51 includes a plurality of first quantum well structures that are sequentially stacked and grown along the top surface of the nanorod 4; the first quantum well structure includes a stacked first Al x1 Ga 1-x1 N well layer and the first Al y1 Ga 1-y1 The N barrier layer and the first quantum well structure have five growth cycles.

[0360] The first quantum well structure is grown using the following scheme:

[0361] B1) Under the conditions of growth temperature 1180°C, growth pressure 130 mbar, V-III ratio 1800 and H2 as carrier gas, a first Al layer with a thickness of 2 nm is grown on the top surface of the nanorod 4. x1 Ga 1-x1 N-well layer.

[0362] B2) Under the conditions of growth temperature 1180°C, growth pressure 130mbar, V-III ratio 1600 and carrier gas H2, in the first Al x1 Ga 1-x1 The first Al2O3 layer with a thickness of 10 nm is grown on the top surface of the N-well layer. y1 Ga 1-y1 N layers.

[0363] Among them, x1=0.2, y1=0.35.

[0364] Step 107: Under the conditions of a growth temperature of 1180°C, a growth pressure of 130 mbar, a V-III ratio of 1800, and a carrier gas of H2, a p-type Al2O3 is grown on the top surface of the first quantum well layer 51 by MOCVD. z1 Ga 1-z1 N and a first P-type layer 52 with a thickness of 180 nm, such as Figure 3 shown.

[0365] It should be noted that z1=0.28.

[0366] Step 110: grow the second quantum well layer 71 along the radial direction of the nanorod 4 on the exposed side surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 6 shown.

[0367] The second quantum well layer 71 includes a plurality of second quantum well structures that are sequentially stacked and grown along the side of the nanorod 4. The second quantum well structure includes a stacked second Al x2 Ga 1-x2 N well layer and the second Al y2 Ga 1-y2 The N barrier layer and the first quantum well structure have five growth cycles.

[0368] The second quantum well structure is grown using the following scheme:

[0369] B1) Under the conditions of growth temperature of 1180°C, growth pressure of 130 mbar, V-III ratio of 1800 and H2 as carrier gas, a second Al layer with a thickness of 2 nm was grown along the radial direction of the nanopillar 4 on the exposed side of the nanopillar 4. x2 Ga 1-x2 N-well layer.

[0370] B2) Under the conditions of growth temperature 1180°C, growth pressure 130mbar, V-III ratio 1600, and carrier gas H2, in the second Al x2 Ga 1-x2 A second Al2O3 layer with a thickness of 10 nm is grown on the side of the N-well layer. y2 Ga 1-y2 N layers.

[0371] Among them, x2=0.45, y2=0.6.

[0372] Step 111: Under the conditions of a growth temperature of 1180°C, a growth pressure of 130 mbar, a V / III ratio of 1800, and a carrier gas of H2, a p-type Al2O3 layer is grown on the side of the first quantum well layer 51 by MOCVD. z2 Ga 1-z2 N and a second P-type layer 72 with a thickness of 180 nm, such as Figure 6 shown.

[0373] It should be noted that z2=0.5. Example 6

[0374] like Figure 1-6 as well as Figure 7a-Figure 11aThe difference between this embodiment and embodiment 3 is that step 106, step 107, step 110 and step 111 are different, and the rest are the same and will not be repeated here.

[0375] Step 106: grow the first quantum well layer 51 on the top surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 3 shown.

[0376] The first quantum well layer 51 includes a plurality of first quantum well structures that are sequentially stacked and grown along the top surface of the nanorod 4; the first quantum well structure includes a stacked first Al x1 Ga 1-x1 The N well layer and the first Al y1 Ga 1-y1 The first quantum well structure has 10 growth cycles.

[0377] The first quantum well structure is grown using the following scheme:

[0378] B1) Under the conditions of growth temperature of 1250°C, growth pressure of 200 mbar, V-III ratio of 3000 and H2 as carrier gas, a first Al layer with a thickness of 3 nm is grown on the top surface of the nanorod 4. x1 Ga 1-x1 N-well layer.

[0379] B2) Under the conditions of growth temperature 1250°C, growth pressure 200mbar, V-III ratio 3000 and carrier gas H2, x1 Ga 1-x1 The first Al2O3 layer with a thickness of 15 nm is grown on the top surface of the N-well layer. y1 Ga 1-y1 N layers.

[0380] Among them, x1=0.22, y1=0.38.

[0381] Step 107: Under the conditions of a growth temperature of 1250°C, a growth pressure of 200 mbar, a V-III ratio of 3000, and a carrier gas of H2, a p-type Al2O3 is grown on the top surface of the first quantum well layer 51 by MOCVD. z1 Ga 1-z1 N and a first P-type layer 52 with a thickness of 300 nm, such as Figure 3 shown.

[0382] It should be noted that z1=0.31.

[0383] Step 110: grow the second quantum well layer 71 along the radial direction of the nanorod 4 on the exposed side surface of the nanorod 4 by MOCVD, as shown in FIG. Figure 6 shown.

[0384] The second quantum well layer 71 includes a plurality of second quantum well structures that are sequentially stacked and grown along the side of the nanorod 4. The second quantum well structure includes a stacked second Al x2 Ga 1-x2 N well layer and the second Al y2 Ga 1-y2 The first quantum well structure has 10 growth cycles.

[0385] The second quantum well structure is grown using the following scheme:

[0386] B1) Under the conditions of growth temperature of 1250°C, growth pressure of 200 mbar, V-III ratio of 3000 and H2 as carrier gas, a second Al layer with a thickness of 3 nm was grown along the radial direction of the nanopillar 4 on the exposed side surface of the nanopillar 4. x2 Ga 1-x2 N-well layer.

[0387] B2) Under the conditions of growth temperature 1250°C, growth pressure 200mbar, V-III ratio 3000, and carrier gas H2, in the second Al x2 Ga 1-x2 A second Al layer with a thickness of 15 nm is grown on the side of the N-well layer. y2 Ga 1-y2 N layers.

[0388] Among them, x2=0.46, y2=0.7.

[0389] Step 111: Under the conditions of a growth temperature of 1250°C, a growth pressure of 200 mbar, a V / III ratio of 3000, and a carrier gas of H2, a p-type Al2O3 layer is grown on the side of the first quantum well layer 51 by MOCVD. z2 Ga 1-z2 N and a second P-type layer 72 with a thickness of 300 nm, such as Figure 6 shown.

[0390] It should be noted that z2=0.55. Example 7

[0391] like Figures 1-6 as well as Figure 7b-Figure 11b The difference between this embodiment and embodiment 2 is that the following steps are performed, and the rest are similar and will not be described again.

[0392] Step 112: Figure 7b As shown, a conductive layer 8 is formed on the surface of the mask layer 3 by magnetron sputtering, and the top surface of the conductive layer 8 is flush with the top surface of the protective layer 6. Figure 8bAs shown, part of the conductive layer 8 is removed by standard photolithography and etching processes, so that the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7 is lower than the top surface of the protective layer 6 .

[0393] Step 113: Figure 8b As shown, a mesh-shaped second P-electrode 11 is deposited on the top surface of the conductive layer 8 covering the surface of the second light-emitting structure 7 by electron beam evaporation.

[0394] Step 114: Figure 9b As shown, a first dielectric layer 9 made of SiO2 and having a thickness of 140 nm is deposited on the surface of the conductive layer 8. The first dielectric layer 9 covers the side and top surfaces of the second P electrode 11, and the top surface of the first dielectric layer 9 is flush with the top surface of the protective layer 6.

[0395] Step 115: Figure 10b As shown, part of the protection layer 6 on the top surface of the first light emitting structure 5 is removed until the first light emitting structure 5 is exposed; and a first P-electrode 10 is formed on the first light emitting structure 5 . Example 8

[0396] like Figures 1-6 、 Figure 7b 、 Figures 8c to 11c The difference between this embodiment and embodiment 2 is that the following steps are performed, and the rest are the same and will not be described again.

[0397] Step 112: Figure 7b As shown, a conductive layer 8 is formed on the surface of the mask layer 3 by magnetron sputtering, and the top surface of the conductive layer 8 is flush with the top surface of the protective layer 6. Figure 8c As shown, part of the conductive layer 8 is removed by standard photolithography and etching processes, so that the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7 is lower than the top surface of the protective layer 6 .

[0398] Step 113: Figure 8c As shown, the second P-electrode 11 is deposited on the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7 by electron beam evaporation, and the top surface of the second P-electrode 11 exceeds the top surface of the protective layer 6 .

[0399] Step 114: Figure 9c As shown, a first dielectric layer 9 made of SiO2 and having a thickness of 140 nm is deposited on the surface of the conductive layer 8. The first dielectric layer 9 covers part of the side surface of the second P electrode 11, and the top surface of the second P electrode 11 is higher than the top surface of the first dielectric layer 9.

[0400] Step 115: Figure 10c As shown, part of the protection layer 6 on the top surface of the first light emitting structure 5 is removed until the first light emitting structure 5 is exposed; and a first P-electrode 10 is formed on the first light emitting structure 5 . Example 9

[0401] like Figures 1-6 as well as Figures 12-18 The difference between this embodiment and embodiment 2 is that step 113 is as follows:

[0402] Step 1131 : removing a portion of the conductive layer 8 by standard photolithography and etching processes until the mask layer 3 is exposed, so as to form a second blank area on the surface of the mask layer 3 between the conductive layers 8 corresponding to two adjacent second light emitting structures 7 .

[0403] Step 1132: Figure 12 As shown, an insulating layer 13 flush with the top surface of the conductive layer 8 is formed in the second blank area.

[0404] The insulating layer 13 is a transparent insulating layer. The material of the insulating layer 13 can be SiO2, SiN x Or photoresist, wherein the photoresist can be SU-8 photoresist, which is an epoxy-type near-ultraviolet negative photoresist.

[0405] Step 1133: Figure 13 As shown, another portion of the conductive layer 8 is removed by standard photolithography and etching processes until the top surface of the second light emitting structure 7 is exposed, so that a third blank area is formed on the top surface of the second light emitting structure 7 .

[0406] The third blank area is used as a growth window for the second dielectric layer 14 that is subsequently grown.

[0407] Step 1134: Figure 13 and Figure 14 As shown, a second dielectric layer 14 is formed in the third blank area, and the top surface of the second dielectric layer 14 is flush with the top surface of the conductive layer 8 .

[0408] The material of the second dielectric layer 14 can be one or more of SiNx, SiO2 or Al2O3.

[0409] Step 1135: Figure 15 As shown, another portion of the conductive layer 8 is removed by standard photolithography and etching processes, so that the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7 is flush with the top surface of the second light emitting structure 7 .

[0410] Step 1136: Figure 16 As shown, the second P-electrode 11 is formed by deposition on the top surface of the conductive layer 8 covering the surface of the second light emitting structure 7 by electron beam evaporation.

[0411] Step 1137: Figure 17As shown, part of the conductive layer 8 and part of the protective layer 6 on the top surface of the first light-emitting structure 5 are removed in sequence by standard photolithography and etching until the first light-emitting structure 5 is exposed; then, the first P electrode 10 is deposited on the exposed first light-emitting structure 5 by electron beam evaporation.

[0412] Step 1138: Figure 18 As shown, first, a portion of the conductive layer 8 and a portion of the mask layer 3 are removed in sequence by standard photolithography and etching processes until the N-type layer 2 is exposed; then, an N-electrode 12 is formed on the exposed N-type layer 2 by electron beam evaporation. Comparative Example 1

[0413] See also Figure 20 This comparative example provides a method for preparing a dual-color LED. Steps 101 to 105 are the same as those in Example 2 and will not be repeated here. The difference lies in the following steps:

[0414] Step 106 : growing a quantum well layer 91 on the top surface of the nanorod 4 by MOCVD.

[0415] The quantum well layer 91 includes five quantum well structures that are stacked and grown in sequence along the top surface of the nanorod 4. The quantum well structure includes stacked In a Ga 1-a N well layer and GaN barrier layer, a=0.12.

[0416] Furthermore, the growth conditions of the quantum well structure are the same as the growth conditions of the first quantum well structure in Example 2, and are not described again here.

[0417] Step 107 : growing a quantum well layer 92 on the top surface of the quantum well layer 91 by MOCVD.

[0418] The quantum well layer 92 includes five quantum well structures that are stacked and grown in sequence along the top surface of the quantum well layer 91; the quantum well structure includes stacked In b Ga 1-b N well layer and GaN barrier layer, b=0.21.

[0419] Furthermore, the growth conditions of the quantum well structure are the same as the growth conditions of the second quantum well structure in Example 2, and are not described again here.

[0420] Step 108: Under the conditions of a growth temperature of 1030°C, a growth pressure of 250 mbar, a V / III ratio of 18000, and H2 as a carrier gas, a P-type layer 93 made of p-type GaN and having a thickness of 180 nm is grown on the top surface of the quantum well layer 92 by MOCVD.

[0421] Step 109 : forming a P electrode 20 on the P-type layer 93 and forming an N electrode 12 on the N-type layer 2 . Comparative Example 2

[0422] See also Figure 20 This comparative example provides a method for preparing a dual-color LED. Steps 101 to 105 are the same as those in Example 2 and will not be repeated here. The difference lies in the following steps:

[0423] Step 106 : growing a quantum well layer 91 on the top surface of the nanorod 4 by MOCVD.

[0424] The quantum well layer 91 includes five quantum well structures that are stacked and grown in sequence along the top surface of the nanorod 4. The quantum well structure includes stacked Al x1 Ga 1-x1 N well layer and Al y1 Ga 1-y1 N layers.

[0425] Furthermore, Al2O3 with a thickness of 1 nm was grown under the conditions of growth temperature of 1100°C, growth pressure of 50 mbar, V-III ratio of 500 and carrier gas of H2. x1 Ga 1-x1 N well layer; Al with a thickness of 5nm was grown at a growth temperature of 1100°C, a growth pressure of 50mbar, a V-III ratio of 100, and a carrier gas of H2. y1 Ga 1-y1 N layers; where x1=0.2 and y1=0.35.

[0426] Step 107 : growing a quantum well layer 92 on the top surface of the quantum well layer 91 by MOCVD.

[0427] The quantum well layer 92 includes five quantum well structures that are stacked and grown in sequence along the top surface of the quantum well layer 91. The quantum well structure includes stacked Al x2 Ga 1-x2 N well layer and Al y2 Ga 1-y2 N layers.

[0428] Furthermore, Al2O3 with a thickness of 1 nm was grown under the conditions of growth temperature of 1100°C, growth pressure of 50 mbar, V-III ratio of 500 and carrier gas of H2. x2 Ga 1-x2 N well layer; Al with a thickness of 5nm was grown at a growth temperature of 1100°C, a growth pressure of 50mbar, a V-III ratio of 100, and a carrier gas of H2. y2 Ga 1-y2 N layers; where x2=0.45 and y2=0.6.

[0429] Step 108: Under the conditions of a growth temperature of 1180°C, a growth pressure of 130 mbar, a V-III ratio of 1800, and a carrier gas of H2, a p-type Al is grown on the top surface of the quantum well layer 92 by MOCVD. z Ga 1-z N and a P-type layer 93 with a thickness of 180 nm, z=0.5.

[0430] Step 108 : forming a P electrode 20 on the P-type layer 93 and forming an N electrode 12 on the N-type layer 2 .

[0431] The thickness and material of the P-electrode 20 and the N-electrode 12 are the same as those in the second embodiment and are not described again here.

[0432] The dual-color LED devices of the same size prepared in the above Examples 1-9 and the comparative example were tested by EL (electroluminescent) testing, and the test results shown in Table 1 were obtained:

[0433] Table 1: Test results of dual-color LED devices of Examples 1-9 and Comparative Example

[0434]

[0435] Specifically, the luminous efficiency is calculated by collecting single-color light emission using an integrating sphere; the turn-on voltage is calculated from the curve collected by the IV test. This is a conventional technical means of testing the performance parameters of LED devices and will not be described in detail here.

[0436] By comparing Examples 1-3 and Examples 7-9 with Comparative Example 1, it can be seen that the solution provided by the present invention can achieve higher luminous efficiency, lower turn-on voltage, and more superior performance. By comparing Examples 4-6 with Comparative Example 2, it can be seen that the solution provided by the present invention can achieve higher luminous efficiency, lower turn-on voltage, and more superior performance.

[0437] In summary, the technical solution provided by the present invention has higher flexibility and wide material applicability, and provides an integrated, efficient and flexible new method for dual-color LEDs.

[0438] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limiting the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the invention without departing from the principles and purpose of the present invention. All such changes shall fall within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a dual-color LED, characterized in that: include: Providing a substrate (1), and sequentially stacking an N-type layer (2) and a mask layer (3) on a surface of the substrate (1); removing a portion of the mask layer (3) so that the mask layer (3) forms a plurality of spaced first blank areas exposing the N-type layer (2), and forming a nanocolumn (4) in each of the first blank areas; A first light-emitting structure (5) is formed on the top surface of each of the nanopillars (4), and a protective layer (6) is formed to cover the side surfaces of the first light-emitting structure (5); wherein the forming of the protective layer (6) to cover the side surfaces of the first light-emitting structure (5) comprises: forming a protective layer (6) on the top surface of the first light-emitting structure (5) extending to the side surfaces corresponding to the nanopillars (4); etching away a portion of the protective layer (6) at a preset etching angle to expose at least a portion of the side surfaces of the nanopillars (4), so that the remaining protective layer (6) at least covers the top surface and the side surfaces of the first light-emitting structure (5); A second light-emitting structure (7) is formed on at least part of the side surface of each of the nanocolumns (4); wherein the first light-emitting structure (5) and the second light-emitting structure (7) emit light of different colors; forming a conductive layer (8) on the surface of the mask layer (3) to cover the surface of the second light-emitting structure (7); forming an N electrode (12), a first P electrode (10) corresponding to each of the first light-emitting structures (5), and a second P electrode (11) corresponding to each of the second light-emitting structures (7); The first P-electrode (10) is arranged on each of the first light-emitting structures (5), the second P-electrode (11) is arranged on the conductive layer (8), and the N-electrode (12) is arranged on the N-type layer (2).

2. The preparation method according to claim 1, characterized in that The preset etching angle ranges from 30° to 60°.

3. The preparation method according to claim 1, characterized in that A conductive layer (8) covering the surface of the second light-emitting structure (7) is formed on the surface of the mask layer (3), comprising: forming the conductive layer (8) on the surface of the mask layer (3) and the protective layer (6); removing a portion of the conductive layer (8) on the surface of the second light-emitting structure (7), so that the remaining conductive layer (8) covers the second light-emitting structure (7) and the top surface of the conductive layer (8) covering the second light-emitting structure (7) does not exceed the top surface of the first light-emitting structure (5); Alternatively, the conductive layer (8) is formed on the surface of the mask layer (3), so that the top surface of the conductive layer (8) covering the surface of the second light-emitting structure (7) is not higher than the top surface of the protective layer (6).

4. The preparation method according to claim 3, characterized in that The forming of the N electrode (12), the first P electrode (10) corresponding to each of the first light-emitting structures (5), and the second P electrode (11) corresponding to each of the second light-emitting structures (7) includes: forming a second P-electrode (11) on the top surface of the conductive layer (8) covering the surface of the second light-emitting structure (7); A first dielectric layer (9) is formed on the surface of the conductive layer (8), wherein the first dielectric layer (9) at least covers the side surface of the second P-electrode (11); Sequentially removing a portion of the first dielectric layer (9), a portion of the conductive layer (8), and a portion of the protective layer (6) on the top surface of the first light-emitting structure (5) until the first light-emitting structure (5) is exposed, and forming the first P-electrode (10) on the first light-emitting structure (5); Part of the first dielectric layer (9), part of the conductive layer (8), and part of the mask layer (3) are removed in sequence until the N-type layer (2) is exposed, and the N-electrode (12) is formed on the N-type layer (2).

5. The preparation method according to any one of claims 1 to 4, characterized in that Forming a first light-emitting structure (5) on the top surface of the nanocolumn (4) includes: sequentially growing a stacked first quantum well layer (51) and a first P-type layer (52) on the top surface of the nanocolumn (4) to obtain the first light-emitting structure (5); and / or, Forming a second light-emitting structure (7) on at least part of the side surface of the nanocolumn (4) comprises: sequentially growing a stacked second quantum well layer (71) and a second P-type layer (72) along the radial direction of the nanocolumn (4) on at least part of the side surface of the nanocolumn (4) to obtain the second light-emitting structure (7); and / or, The first quantum well layer (51) comprises a plurality of first quantum well structures that are sequentially stacked and grown along the top surface of the nanocolumn (4); the first quantum well structure comprises a stacked first In a Ga 1-a N well layer and the first GaN barrier layer, growing the first quantum well layer (51) on the top surface of the nanocolumn (4) includes: growing the first In under the first growth condition a Ga 1-a N well layer, the first GaN barrier layer is grown under the second growth condition; or the first quantum well structure includes a stacked first Al x1 Ga 1- x1 The N well layer and the first Al y1 Ga 1-y1 N barrier layer, growing a first quantum well layer (51) on the top surface of the nanocolumn (4) includes: growing the first Al x1 Ga 1-x1 The N well layer is grown under the fourth growth condition. y1 Ga 1-y1 N-barrier layer; and / or, The second quantum well layer (71) comprises a plurality of second quantum well structures sequentially stacked and grown along the side of the nanocolumn (4), wherein the second quantum well structure comprises a stacked second In b Ga 1-b N well layer and a second GaN barrier layer; growing a second quantum well layer (71) on at least part of the side of the nanocolumn (4) includes: growing the second In under the first growth condition b Ga 1-b N layer, growing the second GaN barrier layer under the second growth condition; or the second quantum well structure includes a stacked second Al x2 Ga 1-x2 N well layer and the second Al x2 Ga 1-x2 N well layer, growing a second quantum well layer (71) on at least part of the side of the nano column (4) includes: growing the second Al x2 Ga 1-x2 N well layer, growing the second Al under the fourth growth condition y2 Ga 1-y2 N barrier layer; Among them, 0.08 <a<0.3,0.12<b<0.3,0.1<x1<0.5,0.2<y1<0.6,0.3<x2<0.6,0.4<y2<0.8。 6. The preparation method according to claim 5, characterized in that The first growth conditions include: a growth thickness of 2-3 nm, a growth temperature of 700-800° C., a growth pressure of 200-600 mbar, a V-III ratio of 10,000-40,000, and a carrier gas of N 2 ; and / or The second growth conditions include a growth thickness of 8-15 nm, a growth temperature of 830-950° C., a growth pressure of 200-600 mbar, a V-III ratio of 5000-20000, and a carrier gas of N 2 ; and / or, The third growth condition includes: a growth thickness of 1-3 nm, a growth temperature of 1100-1250° C., a growth pressure of 50-200 mbar, a V-III ratio of 500-3000, and a carrier gas of H2; and / or the fourth growth condition includes: a growth thickness of 5-15 nm, a growth temperature of 1100-1250° C., a growth pressure of 50-200 mbar, a V-III ratio of 100-3000, and a carrier gas of H2; The growth period of the first quantum well structure is 1 to 10, and the growth period of the second quantum well structure is 1 to 10.

7. The preparation method according to claim 6, characterized in that The material of the first P-type layer (52) and / or the second P-type layer (72) is GaN or Al z Ga 1-z N, where z < y1 or z < y2; When the material of the first P-type layer (52) and / or the second P-type layer (72) is GaN, the growth conditions include: a growth thickness of 50-300 nm, a growth temperature of 950-1100°C, a growth pressure of 100-400 mbar, a V-III ratio of 5000-20000, and a carrier gas of H2 or a mixture of H2 and N2; When the material of the first P-type layer (52) and / or the second P-type layer (72) is Al z Ga 1-z When N, the growth conditions include: growth thickness of 50~300nm, growth temperature of 1100~1250ºC, growth pressure of 50~200mbar, V-III ratio of 500~3000, and carrier gas of H2; Among them, 0.15 <z<0.65。 8. The preparation method according to claim 3, characterized in that After forming a conductive layer (8) on the surface of the mask layer (3), the preparation method further comprises: removing a portion of the conductive layer (8) until the mask layer (3) is exposed, so that a second blank area located between the conductive layers (8) corresponding to two adjacent second light-emitting structures (7) is formed on the surface of the mask layer (3); forming an insulating layer (13) in the second blank area, wherein the top surface of the insulating layer (13) is flush with the top surface of the conductive layer (8); removing another portion of the conductive layer (8) until the top surface of the second light-emitting structure (7) is exposed, so that a third blank area is formed on the top surface of the second light-emitting structure (7); A second dielectric layer (14) is formed in the third blank area, and the top surface of the second dielectric layer (14) is flush with the top surface of the conductive layer (8).

9. The preparation method according to claim 8, characterized in that The forming of the N electrode (12), the first P electrode (10) corresponding to each of the first light-emitting structures (5), and the second P electrode (11) corresponding to each of the second light-emitting structures (7) includes: forming a second P-electrode (11) on the top surface of the conductive layer (8) covering the surface of the second light-emitting structure (7); Sequentially removing a portion of the conductive layer (8) and a portion of the protective layer (6) on the top surface of the first light-emitting structure (5) until the first light-emitting structure (5) is exposed, and forming the first P-electrode (10) on the first light-emitting structure (5); Part of the conductive layer (8) and part of the mask layer (3) are removed in sequence until the N-type layer (2) is exposed, and the N-electrode (12) is formed on the N-type layer (2).

10. A dual-color LED, characterized in that: include: substrate (1); An N-type layer (2) and a mask layer (3) are sequentially arranged on the surface of the substrate (1), and the mask layer (3) has a plurality of spaced blank areas exposing the N-type layer (2); A plurality of nanopillars (4), with one nanopillar (4) being provided in each blank area; A first light-emitting structure (5) is provided on the top surface of the nanocolumn (4), and a second light-emitting structure (7) located on the surface of the mask layer (3) is provided on at least part of the side surface of the nanocolumn (4), wherein the first light-emitting structure (5) and the second light-emitting structure (7) emit light of different colors; A first P-electrode (10) is provided on the top surface of the first light-emitting structure (5), and a completely covering protective layer (6) is provided on the side surface of the first light-emitting structure (5); wherein the protective layer (6) extends to a portion of the side surface corresponding to the nanocolumn (4); a conductive layer (8), arranged on the surface of the mask layer (3) and covering the surface of the second light-emitting structure (7); A second P electrode (11) is located on the surface of the conductive layer (8); An N-electrode (12) is provided on the surface of the N-type layer (2) and is located on the other outer side of the outermost nanocolumn (4).

11. The dual-color LED according to claim 10, characterized in that: The bi-color LED further comprises an insulating layer (13) and a second dielectric layer (14), wherein the insulating layer (13) is arranged on the surface of the mask layer (3) and is located between the conductive layers (8) corresponding to two adjacent second light-emitting structures (7), and the second dielectric layer (14) is arranged around the protective layer (6); and / or The dual-color LED further comprises a first dielectric layer (9), the first dielectric layer (9) being arranged on the surface of the conductive layer (8), the first dielectric layer (9) at least covering the side surfaces of the first P-electrode (10) and / or the second P-electrode (11); and / or The top surface of the conductive layer (8) is flush with the top surface of the protective layer (6).

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