Light emitting diode epitaxial wafer and preparation method thereof

Abstract

The present invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and relates to the field of semiconductor optoelectronic devices. The light-emitting diode epitaxial wafer comprises a substrate, a buffer layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer in sequence; the buffer layer comprises a first AlN layer, a second AlN layer, a third AlN layer, a first superlattice layer, a first AlGaN layer, a second superlattice layer and a first GaN layer in sequence; the first superlattice layer comprises an alternately stacked fourth AlN layer and a second AlGaN layer, and the second superlattice layer comprises an alternately stacked third AlGaN layer and a second GaN layer; a first V-pit extending to the second superlattice layer is formed on the third AlN layer, a second V-pit is formed on the first superlattice layer, and the second V-pit is filled by the first AlGaN layer; a third V-pit is formed on the second superlattice layer, and the first V-pit and the third V-pit are filled by the first GaN layer. The implementation of the present invention can improve the luminous efficiency.

Description

Technical Field

[0001] The invention relates to the field of semiconductor optoelectronic devices, and in particular to a light emitting diode epitaxial wafer and a preparation method thereof. Background Art

[0002] Currently, GaN-based light-emitting diodes all use heterogeneous substrates (including sapphire substrates, silicon carbide substrates, silicon substrates, etc.), which have large lattice mismatches and thermal mismatches with the epitaxial materials. As a result, the epitaxial materials are subjected to greater stress during the growth process and are prone to dislocation defects. These dislocation defects will extend to the active area, reducing the radiation recombination efficiency and the luminescence efficiency.

[0003] On the other hand, external quantum efficiency is also a factor that limits the improvement of the luminous efficiency of GaN-based light-emitting diodes. Taking blue light GaN-based LEDs as an example, the external quantum efficiency of high-power LED chips is usually only about 40%. This is because the refractive index of GaN material (n=2.5) is quite different from the refractive index of air (n=1) and the refractive index of sapphire substrate (n=1.75), resulting in the critical angles of total reflection at the air-GaN interface and the sapphire-GaN interface being only 23.6° and 44.4° respectively, and only a small amount of light generated in the active area can escape from the bulk material. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a light emitting diode epitaxial wafer and a preparation method thereof, which can improve the light emitting efficiency of the light emitting diode.

[0005] In order to solve the above problems, the present invention discloses a light-emitting diode epitaxial wafer, comprising a substrate, a buffer layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate; the buffer layer comprises a first AlN layer, a second AlN layer, a third AlN layer, a first superlattice layer, a first AlGaN layer, a second superlattice layer and a first GaN layer sequentially stacked on the substrate;

[0006] Wherein, the first superlattice layer comprises a fourth AlN layer and a second AlGaN layer which are alternately stacked, and the second superlattice layer comprises a third AlGaN layer and a second GaN layer which are alternately stacked;

[0007] A first V-pit is formed on the third AlN layer, the first V-pit extends to the second superlattice layer and is filled by the first GaN layer;

[0008] The first superlattice layer further forms a second V-pit, and the second V-pit is filled by the first AlGaN layer; and / or

[0009] The second superlattice layer also forms a third V-pit, and the third V-pit is filled by the first GaN layer.

[0010] As an improvement of the above technical solution, the thickness of the first AlN layer is 2nm~50nm; and / or

[0011] The thickness of the second AlN layer is 1 nm to 20 nm; and / or

[0012] The thickness of the third AlN layer is 1 nm to 20 nm; and / or

[0013] The period number of the first superlattice layer is 2 to 25; and / or

[0014] The thickness of the fourth AlN layer is 0.5 nm to 8 nm; and / or

[0015] The thickness of the second AlGaN layer is 0.5 nm to 8 nm, and the Al component ratio is 0.4 to 0.85; and / or

[0016] The thickness of the first AlGaN layer is 3nm-80nm, and the Al component ratio is 0.25-0.75; and / or

[0017] The number of periods of the second superlattice layer is 3 to 50; and / or

[0018] The thickness of the third AlGaN layer is 0.8 nm to 10 nm, and the Al component ratio is 0.15 to 0.6; and / or

[0019] The thickness of the second GaN layer is 0.8 nm to 10 nm; and / or

[0020] The first GaN layer is 5nm~200nm.

[0021] As an improvement of the above technical solution, the size of the second V-pit is smaller than the size of the first V-pit; and / or

[0022] The size of the third V-pit is smaller than the size of the first V-pit; and / or

[0023] The distribution density of the second V-pits is greater than the distribution density of the first V-pits; and / or

[0024] The distribution density of the third V-pits is greater than the distribution density of the first V-pits.

[0025] As an improvement of the above technical solution, the distribution density of the first V pits is 1.18×10 8 cm -2 ~5.78×10 11 cm -2 ; and / or

[0026] The distribution density of the second V pit is 2.35×10 8 cm -2 ~1.95×10 12 cm -2 ; and / or

[0027] The distribution density of the third V pit is 5.07×10 8 cm -2 ~6.98×10 12 cm -2 .

[0028] As an improvement of the above technical solution, the first GaN layer is doped with Si, and its doping concentration is 2.8×10 17 cm -3 ~1.9×10 19 cm -3 ; and / or

[0029] The second GaN layer is doped with Si, and the doping concentration is 2.5×10 17 cm -3 ~1.6×10 19 cm -3 .

[0030] Correspondingly, the present invention also discloses a method for preparing a light-emitting diode epitaxial wafer, which is used to prepare the above-mentioned light-emitting diode epitaxial wafer, and comprises:

[0031] Providing a substrate, and sequentially growing a buffer layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate;

[0032] The buffer layer includes a first AlN layer, a second AlN layer, a third AlN layer, a first superlattice layer, a first AlGaN layer, a second superlattice layer and a first GaN layer sequentially stacked on the substrate;

[0033] The first superlattice layer includes a fourth AlN layer and a second AlGaN layer that are alternately stacked, and the second superlattice layer includes a third AlGaN layer and a second GaN layer that are alternately stacked;

[0034] After the growth of the second AlN layer is completed, a first H2 etching process is performed to form a first V-pit extending from the third AlN layer to the second superlattice layer, wherein the first V-pit is filled by the first GaN layer;

[0035] After the growth of the third AlN layer is completed, a second H2 etching process is performed to form a second V-pit in the first superlattice layer, and the second V-pit is filled by the first AlGaN layer; and / or

[0036] After the growth of the second AlGaN layer is completed, a third H2 etching process is performed to form a third V-pit in the second superlattice layer, and the third V-pit is filled by the first GaN layer.

[0037] As an improvement of the above technical solution, the first AlN layer is grown by PVD, and its growth temperature is 500°C~680°C, the sputtering power is 2kW~7kW, the Ar flow rate is 10sccm~80sccm, the N2 flow rate is 50sccm~300sccm, and the O2 flow rate is 0.3sccm~5sccm; and / or

[0038] The second AlN layer is grown by MOCVD at a growth temperature of 650° C. to 920° C. and a growth pressure of 20 torr to 500 torr; and / or

[0039] The third AlN layer is grown by MOCVD at a growth temperature of 780° C. to 980° C. and a growth pressure of 30 torr to 300 torr; and / or

[0040] The fourth AlN layer is grown by MOCVD at a growth temperature of 800° C. to 1050° C. and a growth pressure of 30 torr to 320 torr; and / or

[0041] The second AlGaN layer is grown by MOCVD at a growth temperature of 800° C. to 1050° C. and a growth pressure of 30 torr to 320 torr; and / or

[0042] The first AlGaN layer is grown by MOCVD at a growth temperature of 900° C. to 1180° C. and a growth pressure of 30 torr to 320 torr; and / or;

[0043] The third AlGaN layer is grown by MOCVD at a growth temperature of 820° C. to 1080° C. and a growth pressure of 30 torr to 320 torr; and / or

[0044] The second GaN layer is grown by MOCVD at a growth temperature of 820° C. to 1080° C. and a growth pressure of 30 torr to 320 torr; and / or

[0045] The first GaN layer is grown by MOCVD, with a growth temperature of 900° C. to 1180° C. and a growth pressure of 30 torr to 320 torr.

[0046] As an improvement of the above technical solution, the etching time of the first H2 etching process is greater than or equal to the etching time of the second H2 etching process, and the H2 flow rate of the first H2 etching process is greater than or equal to the H2 flow rate of the second H2 etching process; and / or

[0047] The etching time of the second H2 etching process is greater than or equal to the etching time of the third H2 etching process, and the H2 flow rate of the second H2 etching process is greater than or equal to the H2 flow rate of the third H2 etching process.

[0048] As an improvement of the above technical solution, the conditions of the first H2 etching treatment include: etching temperature of 920°C to 1250°C, etching pressure of 20torr to 360torr, etching time of 15s to 360s, and H2 flow rate of 50slm to 500slm; and / or

[0049] The conditions of the second H2 etching treatment include: etching temperature of 920° C. to 1250° C., etching pressure of 20 torr to 360 torr, etching time of 10 s to 300 s, and H2 flow rate of 30 slm to 390 slm; and / or

[0050] The conditions of the third H2 etching treatment include: etching temperature of 920° C. to 1250° C., etching pressure of 20 torr to 360 torr, etching time of 5 s to 250 s, and H2 flow rate of 20 slm to 350 slm.

[0051] As an improvement of the above technical solution, after the growth of the first AlN layer is completed, an annealing treatment is performed in MOCVD;

[0052] The annealing conditions include: annealing temperature of 600° C. to 1200° C., annealing pressure of 30 torr to 650 torr, annealing time of 10 s to 360 s, annealing atmosphere of a mixture of H 2 and NH 3, and a volume ratio of H 2 to NH 3 of 1:0.2 to 1:5.

[0053] The implementation of the present invention has the following beneficial effects:

[0054] In the light-emitting diode epitaxial wafer in one embodiment of the present invention, a first AlN layer, a second AlN layer, a third AlN layer, a first superlattice layer, a first AlGaN layer, a second superlattice layer and a first GaN layer are sequentially stacked between the substrate and the N-type GaN layer as a buffer layer. Among them, the first superlattice layer includes a fourth AlN layer and a second AlGaN layer stacked alternately, and the second superlattice layer includes a third AlGaN layer and a second GaN layer stacked alternately; a first V-pit is formed on the third AlN layer, the first V-pit extends to the second superlattice layer and is filled by the first GaN layer; a second V-pit is also formed on the first superlattice layer, the second V-pit is filled by the first AlGaN layer; a third V-pit is also formed on the second superlattice layer, and the third V-pit is filled by the first GaN layer. Based on the above buffer layer structure, on the one hand, by designing the first V-pit, the second V-pit and the third V-pit, stress can be fully released, stress-induced defects can be reduced, and the crystal quality of each layer subsequently grown can be improved. Second, by filling the second V-pit with the first AlGaN layer; the first V-pit and the third V-pit are filled with the first GaN layer, so that the dislocation defects are deflected and merged multiple times, the dislocation density is reduced, and the crystal quality of each layer subsequently grown is improved. Third, through the above-mentioned buffer layer design, the in-plane total reflection of the buffer layer can also be reduced, the photon overflow ratio is increased, and the light extraction efficiency is improved. Therefore, the light-emitting diode epitaxial wafer in this embodiment can improve the crystal quality and the radiation recombination efficiency, that is, the internal quantum efficiency; it can also improve the light extraction efficiency, that is, the external quantum efficiency. The combination of the two effectively improves the luminous efficiency of the light-emitting diode epitaxial wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 is a schematic structural diagram of a light emitting diode epitaxial wafer in one embodiment of the present invention;

[0056] Figure 2 is a schematic structural diagram of a buffer layer in one embodiment of the present invention;

[0057] Figure 3 is a schematic structural diagram of a first superlattice layer in one embodiment of the present invention;

[0058] Figure 4 is a schematic structural diagram of a second superlattice layer in one embodiment of the present invention;

[0059] Figure 5 is a schematic structural diagram of a light emitting diode epitaxial wafer in another embodiment of the present invention;

[0060] Figure 6 is a flow chart of a method for preparing a light emitting diode epitaxial wafer in one embodiment of the present invention;

[0061] In the figure, 100 is a substrate, 200 is a buffer layer, 210 is a first AlN layer, 220 is a second AlN layer, 230 is a third AlN layer, 231 is a first V-pit, 231a is a first sub-V-pit, 231b is a second sub-V-pit, 231c is a third sub-V-pit, 231d is a fourth sub-V-pit, 240 is a first superlattice layer, 241 is a fourth AlN layer, 242 is a second AlGaN layer, 243 is a second V-pit, 250 is a first AlGaN layer, 260 is a second superlattice layer, 261 is a third AlGaN layer, 262 is a second GaN layer, 263 is a third V-pit, 270 is a first GaN layer, 300 is an N-type GaN layer, 400 is a stress release layer, 500 is a multiple quantum well layer, 600 is an electron blocking layer, and 700 is a P-type GaN layer. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0063] See also Figure 1 The present invention discloses a light emitting diode epitaxial wafer, which includes a substrate 100, a buffer layer 200, an N-type GaN layer 300, a multi-quantum well layer 500, an electron blocking layer 600 and a P-type GaN layer 700 sequentially stacked on the substrate 100.

[0064] The substrate 100 may be a sapphire substrate, a silicon substrate, a silicon carbide substrate or a gallium oxide substrate, but is not limited thereto. A sapphire substrate is preferred.

[0065] Among them, see Figure 2~Figure 4 , the buffer layer 200 includes a first AlN layer 210, a second AlN layer 220, a third AlN layer 230, a first superlattice layer 240, a first AlGaN layer 250, a second superlattice layer 260 and a first GaN layer 270 sequentially stacked on the substrate 100; the first superlattice layer 240 includes a fourth AlN layer 241 and a second AlGaN layer 242 alternately stacked, and the second superlattice layer 260 includes a third AlGaN layer 261 and a second GaN layer 262 alternately stacked. Based on the above buffer layer 200, not only the crystal quality of each layer grown subsequently can be improved, but also the internal quantum efficiency can be improved. It can also improve the light extraction efficiency and the external quantum efficiency, thereby effectively improving the luminous efficiency.

[0066] Specifically, the thickness of the first AlN layer 210 is 2nm~50nm, exemplarily 3nm, 15nm, 27nm, 39nm or 45nm, but not limited thereto. Preferably, it is 10nm~30nm. The first AlN layer 210 can be grown by MOCVD or PVD, but not limited thereto. Preferably, in one embodiment, the first AlN layer 210 is grown by PVD, which has few side reactions, and the grown first AlN layer 210 has higher crystal quality and relatively better uniformity, which lays a good foundation for the subsequent reduction of dislocation defects.

[0067] Specifically, the thickness of the second AlN layer 220 is 1nm~20nm, exemplarily 4nm, 8nm, 12nm or 16nm, but not limited thereto. Preferably, it is 5nm~15nm. It can be grown by MOCVD or PVD, but not limited thereto. Preferably, in one embodiment, the second AlN layer 220 is grown by MOCVD, which can serve as a crystal nucleus layer for the subsequent growth of each layer to induce its growth; and the second AlN layer 220 grown by MOCVD has a relatively low structural density and poor crystal quality, and presents a porous structure after the first H2 etching treatment, which lays a good foundation for the subsequent induction of the first V pit 231.

[0068] Specifically, the thickness of the third AlN layer 230 is 1nm~20nm, and is exemplarily 4nm, 8nm, 12nm or 16nm, but is not limited thereto. Preferably, it is 10nm~20nm. The third AlN layer 230 is a porous structure, and there are multiple first V pits 231 inside it. The design of this porous structure material is conducive to fully releasing the stress of the epitaxial layer material, and can effectively reduce the defects caused by the large stress of the epitaxial layer material during the growth process, thereby improving the quality of the epitaxial layer material. Specifically, the distribution density of the first V pit 231 is 1×10 8 cm -2 ~6×10 11 cm -2 , an exemplary value is 2.5×10 8 cm -2 , 8×10 8 cm -2 , 5×10 9 cm -2 ,7×10 10 cm -2 or 3×10 11 cm -2 , but not limited thereto. Preferably 1.18×10 8 cm -2 ~5.78×10 11 cm -2 .

[0069] Specifically, in one embodiment, the first V-pit 231 extends from the third AlN layer 230 to the second superlattice layer 260. In the direction from the third AlN layer 230 to the second superlattice layer 260, the first V-pit 231 includes a first sub-V-pit 231a, a second sub-V-pit 231b, a third sub-V-pit 231c and a fourth sub-V-pit 231d in sequence. The first sub-V-pit 231a is formed on the third AlN layer 230, the second sub-V-pit 231b is formed on the first superlattice layer 240, the third sub-V-pit 231c is formed on the first AlGaN layer 250, and the fourth sub-V-pit 231d is formed on the second superlattice layer 260. The vertices of the first sub-V-pit 231a, the second sub-V-pit 231b, the third sub-V-pit 231c and the fourth sub-V-pit 231d are located on the same straight line.

[0070] Specifically, the number of periods of the first superlattice layer 240 is 2 to 25, and exemplary periods are 3, 8, 13, 20 or 24, but not limited thereto. Preferably, the number is 5 to 15. The first superlattice layer 240 grows on the porous third AlN layer 230. The first superlattice layer 240 is formed with a second sub-V pit 231b and a second V pit 243. The second V pit 243 is staggered with the second sub-V pit 231b. The first superlattice layer 240 is a porous material, which can reduce the defect density and improve the crystal quality. Moreover, the first superlattice layer 240 also realizes the transition between AlN material and AlGaN material, further reduces stress accumulation and improves the crystal quality. Specifically, the distribution density of the second V pit 243 is 2×10 8 cm -2 ~2×10 12 cm -2 , exemplarily 5×10 8 cm -2 , 3×10 9 cm -2 ,7×10 10 cm -2 or 5×10 11 cm -2 , but not limited thereto. Preferably, it is 2.35×10 8 cm -2 ~1.95×10 12 cm -2 .

[0071] The thickness of a single fourth AlN layer 241 in the first superlattice layer 240 is 0.5 nm to 8 nm, exemplarily 0.8 nm, 1.5 nm, 3 nm, 4.5 nm, 6 nm or 7 nm, but not limited thereto, preferably 1 nm to 3 nm.

[0072] The thickness of a single second AlGaN layer 242 in the first superlattice layer 240 is 0.5 nm to 8 nm, and is exemplarily 0.8 nm, 1.5 nm, 3 nm, 4.5 nm, 6 nm or 7 nm, but not limited thereto. Preferably, it is 1 nm to 3 nm. The proportion of Al component in the second AlGaN layer 242 is 0.4 to 0.9, and is exemplarily 0.48, 0.55, 0.67, 0.74, 0.82 or 0.88, but not limited thereto. Preferably, it is 0.4 to 0.8, and more preferably, it is 0.7 to 0.8.

[0073] Specifically, the thickness of the first AlGaN layer 250 is 3nm~80nm, exemplarily 5nm, 22nm, 34nm, 50nm, 62nm or 75nm, but not limited thereto. Preferably, it is 10nm~50nm. The proportion of Al component in the first AlGaN layer 250 is less than the proportion of Al component in the second AlGaN layer 242. Specifically, the proportion of Al component in the first AlGaN layer 250 is 0.25~0.75, exemplarily 0.28, 0.35, 0.44, 0.6, 0.7 or 0.72, but not limited thereto. Preferably, it is 0.5~0.75. Through the first AlGaN layer 250, one can fill the second V pit 243, realize the twisting and annihilation of dislocations, and improve the crystal quality. Second, it can achieve a good transition with the second superlattice layer 260 in the future, reduce stress accumulation, and improve crystal quality. In addition, the first AlGaN layer 250 is further formed with a third sub-V pit 231 c . Therefore, the first AlGaN layer 250 is also a porous material, which can also reduce defect density and improve crystal quality.

[0074] Specifically, the number of periods of the second superlattice layer 260 is 3 to 50, and exemplary periods are 4, 8, 10, 15, 30, 40 or 45, but not limited thereto. Preferably, it is 10 to 20. The second superlattice layer 260 grows on the porous first AlGaN layer 250. The second superlattice layer 260 is formed with a fourth sub-V pit 231d and a third V pit 263. The third V pit 263 is staggered with the fourth sub-V pit 231d. The second superlattice layer 260 is a porous material, which can reduce the defect density and improve the crystal quality. Moreover, the second superlattice layer 260 also realizes the transition between AlGaN material and GaN material, further reduces stress accumulation and improves the crystal quality. Specifically, the distribution density of the third V pit 263 is 5×10 8 cm -2 ~8×10 12 cm -2 , exemplarily 6×10 8 cm -2 , 3×10 9 cm -2 ,7×10 10 cm-2 , 5×10 11 cm -2 , or 3 × 10 12 cm -2 But not limited to this. Preferably, it is 5.07×10 8 cm -2 ~6.98×10 12 cm -2 .

[0075] The thickness of a single third AlGaN layer 261 in the second superlattice layer 260 is 0.8nm~10nm, and is exemplarily 0.9nm, 1.5nm, 3nm, 4.5nm, 6nm, 7nm or 9nm, but not limited thereto. Preferably, it is 2nm~5nm. The proportion of Al component in the third AlGaN layer 261 is less than the proportion of Al component in the first AlGaN layer 250. Specifically, the proportion of Al component in the third AlGaN layer 261 is 0.15~0.6, and is exemplarily 0.2, 0.4, 0.5 or 0.55, but not limited thereto. Preferably, it is 0.2~0.5.

[0076] The thickness of a single second GaN layer 262 in the second superlattice layer 260 is 0.8 nm to 10 nm, exemplarily 0.9 nm, 1.5 nm, 3 nm, 4.5 nm, 6 nm, 7 nm or 9 nm, but not limited thereto, preferably 3 nm to 6 nm.

[0077] Specifically, the thickness of the first GaN layer 270 is 5nm to 200nm, and is exemplarily 20nm, 40nm, 60nm or 80nm, but is not limited thereto. Preferably, it is 40nm to 120nm. Through the first GaN layer 270, the first V-pit 231 and the third V-pit 263 can be filled, the dislocation can be twisted and annihilated, the crystal quality can be improved, and a good transition with the subsequent N-type GaN layer 300 can be achieved, further improving the crystal quality.

[0078] The N-type doping element of the N-type GaN layer 300 is Si, but is not limited thereto. The N-type doping concentration of the N-type GaN layer 300 is 5×10 18 cm -3 ~5×10 19 cm -3 , and its thickness is 1μm~5μm.

[0079] Among them, the multi-quantum well layer 500 is a periodic structure, and its period number is 3 to 15. Each period includes an InGaN quantum well layer and a GaN quantum barrier layer stacked in sequence. The thickness of the InGaN quantum well layer is 3nm to 5nm, and its In component accounts for 0.1 to 0.5. Preferably, the In component accounts for 0.35 to 0.5. In this embodiment, the stress buffering effect is strong and can be better applied to yellow-green LEDs. The thickness of the GaN quantum barrier layer is 5nm to 15nm.

[0080] The electron blocking layer 600 is an AlGaN layer or an InAlGaN layer, but is not limited thereto, preferably an AlGaN layer, and the thickness of the electron blocking layer 600 is 30 nm to 100 nm.

[0081] The P-type doping element in the P-type GaN layer 700 is Mg, but is not limited thereto. The P-type doping concentration in the P-type GaN layer 700 is 1×10 19 cm -3 ~1×10 21 cm -3 , and its thickness is 200nm~500nm.

[0082] Preferably, see Figure 5 In some embodiments, the light-emitting diode epitaxial wafer further includes a stress release layer 400, a P-type contact layer and other structures, but is not limited thereto. Preferably, in one embodiment, the light-emitting diode epitaxial wafer further includes a stress release layer 400, which is disposed between the N-type GaN layer 300 and the multi-quantum well layer 500. Specifically, the stress release layer 400 is a periodic structure formed by alternating InGaN layers and low-doped N-GaN layers, and the number of periods is 3 to 10. Among them, the thickness of the InGaN layer is 1nm to 5nm, and the In component accounts for 0.05 to 0.2. The thickness of the low-doped N-GaN layer is 5nm to 10nm, and its doping element is Si, but is not limited thereto. Its doping concentration is 1×10 17 cm -3 ~1×10 18 cm -3 .

[0083] Preferably, in some embodiments, the size of the second V-pit 243 is smaller than the size of the first V-pit 231. Specifically, the size of the V-pit refers to its opening size. After the growth of the V-pit is completed, the cross-section of the top of the V-pit is hexagonal, and its opening size refers to the side length of the top hexagonal cross-section or the diameter of its circumscribed circle. Based on the control of the above opening size, the annihilation effect on dislocations can be further enhanced.

[0084] Preferably, in some embodiments, the size of the third V-pit 263 is smaller than that of the first V-pit 231. Based on the control of the opening size described above, the annihilation effect on dislocations can be further enhanced.

[0085] More preferably, in some embodiments, the size of the third V-pit 263 is smaller than the size of the second V-pit 243 and smaller than the size of the first V-pit 231. Based on the control of the opening size described above, the annihilation effect on dislocations can be further enhanced.

[0086] Preferably, in some embodiments, the distribution density of the second V-pits 243 is greater than the distribution density of the first V-pits 231 ; this can better improve the crystal quality.

[0087] Preferably, in some embodiments, the distribution density of the third V-pits 263 is greater than the distribution density of the first V-pits 231 ; this can better improve the crystal quality.

[0088] More preferably, in some embodiments, the distribution density of the third V-pits 263 is greater than the distribution density of the second V-pits 243 and greater than the distribution density of the first V-pits 231. Based on the control of the distribution density, the annihilation effect on dislocations can be further enhanced, and the crystal quality can be better improved.

[0089] Preferably, in some embodiments, the first GaN layer 270 is doped with Si, and the doping concentration is 2.8×10 17 cm -3 ~1.9×10 19 cm -3 The second GaN layer 262 is doped with Si, and its doping concentration is 2.5×10 17 cm -3 ~1.6×10 19 cm -3 .

[0090] Accordingly, see Figure 6 The present invention also provides a method for preparing a light emitting diode epitaxial wafer, which is used to prepare the light emitting diode epitaxial wafer, and specifically comprises the following steps:

[0091] S1: providing a substrate;

[0092] S2: sequentially growing a buffer layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate;

[0093] Specifically, step S2 includes:

[0094] S21: growing a buffer layer on the substrate;

[0095] Specifically, step S21 includes:

[0096] S211: growing a first AlN layer on the substrate;

[0097] Specifically, in one embodiment, the first AlN layer is grown by PVD, and its growth temperature is 500°C~680°C, the sputtering power is 2kW~7kW, the Ar flow rate is 10sccm~80sccm, the N2 flow rate is 50sccm~300sccm, and the O2 flow rate is 0.3sccm~5sccm.

[0098] Preferably, in one embodiment, after the growth of the first AlN layer is completed, an annealing treatment is performed in MOCVD; the conditions of the annealing treatment include: an annealing temperature of 600°C to 1200°C, an annealing pressure of 30torr to 650torr, an annealing time of 10s to 360s, an annealing atmosphere of a mixture of H2 and NH3, and a volume ratio of H2 to NH3 of 1:0.2 to 1:5. Through the above annealing treatment, the poorly crystalline portion of the surface of the first AlN layer can be removed.

[0099] S212: growing a second AlN layer on the first AlN layer;

[0100] Specifically, in one embodiment, the second AlN layer is grown by MOCVD, and the growth temperature is 650° C. to 920° C. and the growth pressure is 20 torr to 500 torr.

[0101] Specifically, after the second AlN layer is grown, a first H2 etching process is performed to form a first V-pit extending from the third AlN layer to the second superlattice layer. Specifically, the first H2 etching process is performed in MOCVD, and its conditions include: etching temperature of 920°C to 1250°C, etching pressure of 20torr to 360torr, etching time of 15s to 360s, and H2 flow rate of 50slm to 500slm.

[0102] S213: growing a third AlN layer on the second AlN layer;

[0103] Specifically, in one embodiment, the third AlN layer is grown by MOCVD, and the growth temperature is 780° C. to 980° C. and the growth pressure is 30 torr to 300 torr.

[0104] Specifically, after the third AlN layer is grown, a second H2 etching process is performed to form a second V-pit in the first superlattice layer. Specifically, the second H2 etching process is performed in MOCVD, and its conditions include: etching temperature of 920°C to 1250°C, etching pressure of 20torr to 360torr, etching time of 10s to 300s, and H2 flow rate of 30slm to 390slm.

[0105] S214: growing a first superlattice layer on the third AlN layer;

[0106] Specifically, in one embodiment, the fourth AlN layer and the second AlGaN layer are periodically grown by MOCVD until the first superlattice layer is obtained. The growth temperature of the fourth AlN layer is 800°C to 1050°C, and the growth pressure is 30 torr to 320 torr; the growth temperature of the second AlGaN layer is 800°C to 1050°C, and the growth pressure is 30 torr to 320 torr.

[0107] S215: growing a first AlGaN layer on the first superlattice layer;

[0108] Specifically, in one embodiment, the first AlGaN layer is grown by MOCVD, with a growth temperature of 900° C. to 1180° C. and a growth pressure of 30 torr to 320 torr.

[0109] S216: growing a second superlattice layer on the first AlGaN layer;

[0110] Specifically, in one embodiment, a third AlGaN layer and a second GaN layer are periodically grown by MOCVD until a second superlattice layer is obtained, wherein the growth temperature of the third AlGaN layer is 820°C to 1080°C and the growth pressure is 30 torr to 320 torr; the growth temperature of the second GaN layer is 820°C to 1080°C and the growth pressure is 30 torr to 320 torr.

[0111] Specifically, after the second superlattice layer is grown, a third H2 etching process is performed to form a third V-pit in the second superlattice layer. Specifically, the third H2 etching process is performed in MOCVD, and its conditions include: etching temperature of 920° C. to 1250° C., etching pressure of 20 torr to 360 torr, etching time of 5 s to 250 s, and H2 flow rate of 20 slm to 350 slm.

[0112] S217: growing a first GaN layer on the second superlattice layer to obtain a buffer layer;

[0113] Specifically, in one embodiment, the first GaN layer is grown by MOCVD, and the growth temperature is 900° C. to 1180° C. and the growth pressure is 30 torr to 320 torr.

[0114] Preferably, in some embodiments, the etching time of the first H2 etching treatment is greater than or equal to the etching time of the second H2 etching treatment, and the H2 flow rate of the first H2 etching treatment is greater than or equal to the H2 flow rate of the second H2 etching treatment; so that the size of the first V-pit is larger than the size of the second V-pit.

[0115] Preferably, in some embodiments, the etching time of the second H2 etching treatment is greater than or equal to the etching time of the third H2 etching treatment, and the H2 flow rate of the second H2 etching treatment is greater than or equal to the H2 flow rate of the third H2 etching treatment; so that the size of the second V-pit is larger than that of the third V-pit.

[0116] S22: growing an N-type GaN layer on the buffer layer;

[0117] In one embodiment of the present invention, the N-type GaN layer is grown by MOCVD, the growth temperature is 1100° C. to 1150° C., and the growth pressure is 100 torr to 500 torr.

[0118] S23: growing a stress release layer on the N-type GaN layer;

[0119] Specifically, in one embodiment of the present invention, an InGaN layer and a low-doped N-GaN layer are periodically grown by MOCVD until a stress release layer is obtained. The growth temperature of the InGaN layer is 750°C to 850°C, and the growth pressure is 100 torr to 200 torr. The growth temperature of the low-doped N-GaN layer is 850°C to 900°C, and the growth pressure is 100 torr to 200 torr.

[0120] S24: growing a multi-quantum well layer on the stress release layer;

[0121] Specifically, in one embodiment of the present invention, an InGaN quantum well layer and a GaN quantum barrier layer are periodically grown by MOCVD until a multi-quantum well layer is obtained, wherein the growth temperature of the InGaN quantum well layer is 730°C to 820°C, the growth pressure is 100 torr to 300 torr, and the growth temperature of the GaN quantum barrier layer is 850°C to 950°C, and the growth pressure is 100 torr to 300 torr.

[0122] S25: growing an electron blocking layer on the multi-quantum well layer;

[0123] Specifically, in one embodiment of the present invention, an AlGaN layer is grown by MOCVD as an electron blocking layer, and the growth temperature is 1000° C. to 1100° C. and the growth pressure is 100 torr to 300 torr.

[0124] S26: growing a P-type GaN layer on the electron blocking layer;

[0125] Specifically, in one embodiment of the present invention, a P-type GaN layer is grown by MOCVD, and the growth temperature is 900° C. to 1000° C. and the growth pressure is 100 torr to 300 torr.

[0126] The present invention will be further described below with specific embodiments:

[0127] Example 1

[0128] The present embodiment provides a light emitting diode epitaxial wafer, which includes a sapphire substrate, a buffer layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the sapphire substrate.

[0129] The buffer layer includes a first AlN layer, a second AlN layer, a third AlN layer, a first superlattice layer, a first AlGaN layer, a second superlattice layer and a first GaN layer sequentially stacked on the substrate; wherein the first superlattice layer includes a fourth AlN layer and a second AlGaN layer alternately stacked, and the number of periods is 12. The second superlattice layer includes a third AlGaN layer and a second GaN layer alternately stacked, and the number of periods is 20.

[0130] Among them, the thickness of the first AlN layer is 10nm, the thickness of the second AlN layer is 12nm, the thickness of the third AlN layer is 15nm, and the thickness of the fourth AlN layer is 2nm. The thickness of the second AlGaN layer is 2.5nm, and its Al component accounts for 0.75. The thickness of the first AlGaN layer is 50nm, and its Al component accounts for 0.55. The thickness of the third AlGaN layer is 2nm, and its Al component accounts for 0.3, and the thickness of the second GaN layer is 3nm. The thickness of the first GaN layer is 120nm.

[0131] The first V-pit is formed on the third AlN layer, extending to the second superlattice layer and filled by the first GaN layer; the distribution density of the first V-pit is 3.52×10 9 cm -2 The first superlattice layer also forms a second V-pit, which is filled by the first AlGaN layer. The distribution density of the second V-pit is 2.44×10 10 cm -2 The size of the first V-pit is larger than that of the second V-pit.

[0132] The thickness of the N-type GaN layer is 2 μm, and the Si doping concentration is 8.3×10 18 cm -3 .

[0133] The stress release layer is a periodic structure formed by alternating InGaN layers and low-doped N-GaN layers, with a period number of 8. The thickness of the InGaN layer is 2nm, and its In component ratio is 0.08. The thickness of the low-doped N-GaN layer is 8nm, and its Si doping concentration is 5×10 17 cm -3 .

[0134] Among them, the multi-quantum well layer is a periodic structure formed by alternating the growth of InGaN quantum well layers and GaN quantum barrier layers, with a period number of 10. The thickness of the InGaN quantum well layer is 4nm, of which the In component accounts for 0.35, and the thickness of the GaN quantum barrier layer is 12nm.

[0135] The electron blocking layer is an AlGaN layer with a thickness of 65 nm. The doping element of the P-type GaN layer is Mg with a doping concentration of 3×10 20 cm -3 , and its thickness is 220nm.

[0136] The method for preparing the light emitting diode epitaxial wafer in this embodiment comprises the following steps:

[0137] (1) Provide a sapphire substrate.

[0138] (2) growing the first AlN layer on a sapphire substrate;

[0139] Specifically, the first AlN layer is grown by PVD, with a growth temperature of 550° C., a sputtering power of 3 kW, an Ar flow rate of 35 sccm, a N2 flow rate of 100 sccm, and an O2 flow rate of 5 sccm.

[0140] After the growth of the first AlN layer is completed, an annealing treatment is performed in MOCVD; the annealing conditions include: an annealing temperature of 800° C., an annealing pressure of 500 torr, an annealing time of 200 s, an annealing atmosphere of a mixture of H2 and NH3, and a volume ratio of H2 to NH3 of 1:2.

[0141] (3) growing a second AlN layer on the first AlN layer;

[0142] Specifically, the second AlN layer is grown by MOCVD, with a growth temperature of 820° C. and a growth pressure of 300 torr.

[0143] After the growth of the second AlN layer is completed, a first H2 etching treatment is performed to form a first V-pit extending from the third AlN layer to the second superlattice layer, wherein the first H2 etching treatment is performed in MOCVD, and its conditions include: etching temperature of 1200°C, etching pressure of 300 torr, etching time of 300s, and H2 flow rate of 380slm.

[0144] (4) growing a third AlN layer on the second AlN layer;

[0145] Specifically, the third AlN layer is grown by MOCVD, and the growth temperature is 880° C. and the growth pressure is 300 torr. After the growth of the third AlN layer is completed, a second H2 etching process is performed to form a second V pit. The second H2 etching process is performed in MOCVD, and the conditions include: etching temperature of 1050° C., etching pressure of 200 torr, etching time of 200 s, and H2 flow rate of 300 slm.

[0146] (5) growing a first superlattice layer on the third AlN layer;

[0147] Specifically, the fourth AlN layer and the second AlGaN layer are periodically grown by MOCVD until the first superlattice layer is obtained. The growth temperature of the fourth AlN layer is 1020° C. and the growth pressure is 200 torr; the growth temperature of the second AlGaN layer is 1050° C. and the growth pressure is 200 torr.

[0148] (6) growing a first AlGaN layer on the first superlattice layer;

[0149] Specifically, the first AlGaN layer is grown by MOCVD, with a growth temperature of 1120° C. and a growth pressure of 300 torr.

[0150] (7) growing a second superlattice layer on the first AlGaN layer;

[0151] Specifically, the third AlGaN layer and the second GaN layer are periodically grown by MOCVD until the second superlattice layer is obtained. The growth temperature of the third AlGaN layer is 1050°C and the growth pressure is 200 torr; the growth temperature of the second GaN layer is 1020°C and the growth pressure is 200 torr.

[0152] (8) growing a first GaN layer on the second superlattice layer to obtain a buffer layer;

[0153] Specifically, the first GaN layer is grown by MOCVD, with a growth temperature of 1150° C. and a growth pressure of 200 torr.

[0154] (9) Growing an N-type GaN layer on the buffer layer;

[0155] Specifically, the N-type GaN layer is grown by MOCVD, with a growth temperature of 1120° C. and a growth pressure of 300 torr.

[0156] (10) growing a stress release layer on the N-type GaN layer;

[0157] Specifically, an InGaN layer and a low-doped N-GaN layer are periodically grown by MOCVD until a stress release layer is obtained. The growth temperature of the InGaN layer is 820°C and the growth pressure is 200 torr. The growth temperature of the low-doped N-GaN layer is 880°C and the growth pressure is 200 torr.

[0158] (11) Growing a multi-quantum well layer on the stress release layer

[0159] Specifically, InGaN quantum well layers and GaN quantum barrier layers are periodically grown by MOCVD until a multi-quantum well layer is obtained, wherein the growth temperature of the InGaN quantum well layer is 760°C and the growth pressure is 200 torr, and the growth temperature of the GaN quantum barrier layer is 880°C and the growth pressure is 200 torr.

[0160] (12) growing an electron blocking layer on the multi-quantum well layer;

[0161] Specifically, an AlGaN layer is grown by MOCVD as an electron blocking layer, and the growth temperature is 1040° C. and the growth pressure is 200 torr.

[0162] (13) growing a P-type GaN layer on the electron blocking layer;

[0163] Specifically, the P-type GaN layer is grown by MOCVD at a growth temperature of 980° C. and a growth pressure of 200 torr.

[0164] Example 2

[0165] This embodiment provides a light emitting diode epitaxial wafer, which is different from the embodiment 1 in that:

[0166] A third V-pit is also formed in the second superlattice layer, and the third V-pit is filled by the first GaN layer. The distribution density of the third V-pit is 6.55×10 11 cm -2 .

[0167] In the preparation method, after the growth of the second superlattice layer is completed, a third H2 etching treatment is performed to form a third V-pit. The third H2 etching treatment is performed in MOCVD, and its conditions include: etching temperature of 1120°C, etching pressure of 200torr, etching time of 100s, and H2 flow rate of 280slm.

[0168] The rest are the same as in Example 1.

[0169] Example 3

[0170] This embodiment provides a light emitting diode epitaxial wafer, which is different from the embodiment 2 in that:

[0171] The first GaN layer is doped with Si, and its doping concentration is 5.6×10 17 cm -3 ; The second GaN layer is doped with Si, and its doping concentration is 3.3×10 17 cm -3 .

[0172] The rest are the same as in Example 2.

[0173] Comparative Example 1

[0174] This comparative example provides a light-emitting diode epitaxial wafer, which is different from Example 1 in that the buffer layer is an AlN layer, which is made by PVD and has a thickness of 50 nm.

[0175] The rest are the same as in Example 1.

[0176] The light emitting diode epitaxial wafer obtained in Example 1 to Example 3 was used to prepare a 10 mil×24 mil vertical structure chip. The luminous brightness was measured at a current of 20 mA, and the luminous brightness improvement rate was calculated based on the comparative example 1. The specific test results are shown in the following table:

[0177]

[0178] It can be seen from the table that when the buffer layer in the conventional light-emitting diode epitaxial wafer (Comparative Example 1) is replaced with the buffer layer of the present invention, the light-emitting brightness of the light-emitting diode epitaxial wafer is effectively improved.

[0179] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A light-emitting diode epitaxial wafer, comprising a substrate, a buffer layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate; characterized in that: The buffer layer includes a first AlN layer, a second AlN layer, a third AlN layer, a first superlattice layer, a first AlGaN layer, a second superlattice layer and a first GaN layer sequentially stacked on the substrate; Wherein, the first superlattice layer comprises a fourth AlN layer and a second AlGaN layer which are alternately stacked, and the second superlattice layer comprises a third AlGaN layer and a second GaN layer which are alternately stacked; A first V-pit is formed on the third AlN layer, the first V-pit extends to the second superlattice layer and is filled by the first GaN layer; The first superlattice layer is further formed with a second V-pit, and the second V-pit is filled by the first AlGaN layer; and The second superlattice layer also forms a third V-pit, and the third V-pit is filled by the first GaN layer.

2. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the first AlN layer is 2nm-50nm; and / or The thickness of the second AlN layer is 1 nm to 20 nm; and / or The thickness of the third AlN layer is 1 nm to 20 nm; and / or The period number of the first superlattice layer is 2 to 25; and / or The thickness of the fourth AlN layer is 0.5 nm to 8 nm; and / or The thickness of the second AlGaN layer is 0.5 nm to 8 nm, and the Al component ratio is 0.4 to 0.85; and / or The thickness of the first AlGaN layer is 3nm-80nm, and the Al component ratio is 0.25-0.75; and / or The number of periods of the second superlattice layer is 3 to 50; and / or The thickness of the third AlGaN layer is 0.8 nm to 10 nm, and the Al component ratio is 0.15 to 0.6; and / or The thickness of the second GaN layer is 0.8 nm to 10 nm; and / or The first GaN layer is 5nm~200nm.

3. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The size of the second V-pit is smaller than the size of the first V-pit; and / or The size of the third V-pit is smaller than the size of the first V-pit; and / or The distribution density of the second V-pits is greater than the distribution density of the first V-pits; and / or The distribution density of the third V-pits is greater than the distribution density of the first V-pits.

4. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The distribution density of the first V pits is 1.18×10 8 cm -2 ~5.78×10 11 cm -2 ; and / or The distribution density of the second V pit is 2.35×10 8 cm -2 ~1.95×10 12 cm -2 ; and / or The distribution density of the third V pit is 5.07×10 8 cm -2 ~6.98×10 12 cm -2 .

5. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The first GaN layer is doped with Si, and the doping concentration is 2.8×10 17 cm -3 ~1.9×10 19 cm -3 ; and / or The second GaN layer is doped with Si, and the doping concentration is 2.5×10 17 cm -3 ~1.6×10 19 cm -3 .

6. A method for preparing a light emitting diode epitaxial wafer, for preparing the light emitting diode epitaxial wafer according to any one of claims 1 to 5, characterized in that: include: Providing a substrate, and sequentially growing a buffer layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate; The buffer layer includes a first AlN layer, a second AlN layer, a third AlN layer, a first superlattice layer, a first AlGaN layer, a second superlattice layer and a first GaN layer sequentially stacked on the substrate; The first superlattice layer includes a fourth AlN layer and a second AlGaN layer that are alternately stacked, and the second superlattice layer includes a third AlGaN layer and a second GaN layer that are alternately stacked; After the growth of the second AlN layer is completed, a first H2 etching process is performed to form a first V-pit extending from the third AlN layer to the second superlattice layer, wherein the first V-pit is filled by the first GaN layer; After the growth of the third AlN layer is completed, a second H2 etching process is performed to form a second V-pit in the first superlattice layer, and the second V-pit is filled by the first AlGaN layer; and After the growth of the second AlGaN layer is completed, a third H2 etching process is performed to form a third V-pit in the second superlattice layer, and the third V-pit is filled by the first GaN layer.

7. The method for preparing a light emitting diode epitaxial wafer according to claim 6, characterized in that: The first AlN layer is grown by PVD, with a growth temperature of 500° C. to 680° C., a sputtering power of 2 kW to 7 kW, an Ar flow rate of 10 sccm to 80 sccm, an N2 flow rate of 50 sccm to 300 sccm, and an O2 flow rate of 0.3 sccm to 5 sccm; and / or The second AlN layer is grown by MOCVD at a growth temperature of 650° C. to 920° C. and a growth pressure of 20 torr to 500 torr; and / or The third AlN layer is grown by MOCVD at a growth temperature of 780° C. to 980° C. and a growth pressure of 30 torr to 300 torr; and / or The fourth AlN layer is grown by MOCVD at a growth temperature of 800° C. to 1050° C. and a growth pressure of 30 torr to 320 torr; and / or The second AlGaN layer is grown by MOCVD at a growth temperature of 800° C. to 1050° C. and a growth pressure of 30 torr to 320 torr; and / or The first AlGaN layer is grown by MOCVD at a growth temperature of 900° C. to 1180° C. and a growth pressure of 30 torr to 320 torr; and / or; The third AlGaN layer is grown by MOCVD at a growth temperature of 820° C. to 1080° C. and a growth pressure of 30 torr to 320 torr; and / or The second GaN layer is grown by MOCVD at a growth temperature of 820° C. to 1080° C. and a growth pressure of 30 torr to 320 torr; and / or The first GaN layer is grown by MOCVD, with a growth temperature of 900° C. to 1180° C. and a growth pressure of 30 torr to 320 torr.

8. The method for preparing a light emitting diode epitaxial wafer according to claim 6, characterized in that: The etching time of the first H2 etching process is greater than or equal to the etching time of the second H2 etching process, and the H2 flow rate of the first H2 etching process is greater than or equal to the H2 flow rate of the second H2 etching process; and / or The etching time of the second H2 etching process is greater than or equal to the etching time of the third H2 etching process, and the H2 flow rate of the second H2 etching process is greater than or equal to the H2 flow rate of the third H2 etching process.

9. The method for preparing a light emitting diode epitaxial wafer according to claim 6, characterized in that: The conditions of the first H2 etching treatment include: etching temperature of 920° C. to 1250° C., etching pressure of 20 torr to 360 torr, etching time of 15 s to 360 s, and H2 flow rate of 50 slm to 500 slm; and / or The conditions of the second H2 etching treatment include: etching temperature of 920° C. to 1250° C., etching pressure of 20 torr to 360 torr, etching time of 10 s to 300 s, and H2 flow rate of 30 slm to 390 slm; and / or The conditions of the third H2 etching treatment include: etching temperature of 920° C. to 1250° C., etching pressure of 20 torr to 360 torr, etching time of 5 s to 250 s, and H2 flow rate of 20 slm to 350 slm.

10. The method for preparing a light emitting diode epitaxial wafer according to claim 7, characterized in that: After the growth of the first AlN layer is completed, an annealing treatment is performed in MOCVD; The annealing conditions include: annealing temperature of 600° C. to 1200° C., annealing pressure of 30 torr to 650 torr, annealing time of 10 s to 360 s, annealing atmosphere of a mixture of H 2 and NH 3, and a volume ratio of H 2 to NH 3 of 1:0.2 to 1:5.

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