Method and device for DC voltage conversion

Abstract

The invention relates to a method and an apparatus for DC voltage conversion. The apparatus includes a buck converter coupled with a direct current (DC) input voltage source, and the buck converter is configured to output a buck output voltage at an output node thereof. The apparatus further includes an LLC resonant converter coupled with the Buck converter and configured to output a DC output voltage to provide power to a load, where the LLC resonant converter includes a controlled switching network, an output node of the Buck converter being connected between a lower switch in the controlled switching network and ground.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of electronic circuits, and in particular, to a direct current (DC) voltage conversion method and apparatus. Background Art

[0002] The 48V bus architecture is becoming more and more popular in data center power supply design. Compared with the 12V bus, the 48V bus architecture can support higher power with higher efficiency. At the same time, it can reduce rack costs and have better deployment flexibility.

[0003] The power supply voltage from the 48V bus is usually first converted to a power supply level that can be input to, for example, a processor by a buck converter or regulator. In one example, a multi-stage buck voltage converter is used to convert the 48V power supply to the input power supply of the processor. Summary of the invention

[0004] According to an embodiment of the present disclosure, a device is provided, which includes: a step-down (Buck) converter, which is coupled to a DC input voltage source and configured to output a Buck output voltage at an output node of the Buck converter; an LLC resonant converter, which is coupled to the Buck converter and configured to output a DC output voltage to provide power to a load, wherein the LLC resonant converter includes a controlled switch network, wherein the output node of the Buck converter is connected between a lower switch in the controlled switch network and ground.

[0005] According to an embodiment of the present disclosure, a method is provided, the method comprising: connecting a Buck converter to an LLC resonant converter, the LLC resonant converter comprising a controlled switch network, wherein an output node of the Buck converter is connected between a lower switch in the controlled switch network of the LLC resonant converter and ground.

[0006] According to an embodiment of the present disclosure, a voltage converter is provided, comprising the device described above.

[0007] According to an embodiment of the present disclosure, a system is provided, which includes: a DC voltage source; a voltage converter including the device described above; a processor coupled to the output of the voltage converter, wherein the voltage converter is used to provide power to the processor; and a memory coupled to the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present disclosure will be described by way of example and not limitation with reference to the figures of the accompanying drawings in which like reference numerals refer to like elements and in which:

[0009] Figure 1Exemplary hybrid topologies for DC voltage conversion according to various embodiments of the present disclosure are shown.

[0010] Figure 2 An exemplary hybrid topology for DC voltage conversion and an exemplary dual-loop feedback module for the hybrid topology according to various embodiments of the present disclosure are shown.

[0011] Figure 3 Key stable waveforms of the LLC resonant stage in a hybrid topology for DC voltage conversion during simulation verification are shown.

[0012] Figure 4 The key stable waveforms of the Buck stage in a hybrid topology for DC voltage conversion during simulation verification are shown.

[0013] Figure 5 The load transient waveforms of the hybrid topology used for DC voltage conversion during simulation verification are shown.

[0014] Figure 6 A smart device or computer system or SoC (system on chip) receiving power from a hybrid topology for DC voltage conversion according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0015] The features and exemplary embodiments of various aspects of the application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the application. However, it is obvious to those skilled in the art that the application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the application by illustrating the example of the application. The application is by no means limited to any specific configuration proposed below, but covers any modification, replacement and improvement of elements, parts and algorithms without departing from the spirit of the application. In the accompanying drawings and the following description, known structures and technologies are not shown to avoid causing unnecessary ambiguity to the application.

[0016] Furthermore, various operations will be described as multiple discrete operations in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations do not need to be performed in the order presented.

[0017] The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. The phrase generally does not refer to the same embodiment; however, it may. The terms "comprising," "having," and "including" are synonymous unless the context dictates otherwise. The phrases "A or B" and "A / B" mean "(A), (B), or (A and B)."

[0018] The present disclosure provides a new Buck and LLC hybrid topology with higher power delivery efficiency and higher transient response to directly convert voltage from, for example, 48V to 1.8V.

[0019] Specifically, according to various embodiments of the present disclosure, the present disclosure provides a hybrid Buck and LLC topology for DC voltage conversion. The hybrid topology includes a Buck stage and an LLC stage, wherein the Buck stage can be inserted into the LLC stage.

[0020] The Buck level can be implemented with a universal Buck converter, which may include two switches, an output inductor, and an output capacitor. In some embodiments, both switches of the Buck converter are metal oxide semiconductor field effect transistors (MOSFETs). In some embodiments, one of the two switches may be a MOSFET, and the other switch may be a diode. In some embodiments, the input source of the Buck level may be, for example, a 48V bus. In other embodiments, the input source may be any other voltage source with a fixed DC voltage output. The Buck level outputs an output voltage at the Buck level output node V_Buck, wherein the output voltage may range from the input voltage to 0V.

[0021] The LLC stage can be implemented with a general LLC resonant converter. The LLC stage may include: a controlled switch network, a resonant cavity, a transformer, a rectifier filter, and a load. The controlled switch network may be a full-bridge switch network or a half-bridge switch network. The LLC resonant converter implemented in the LLC stage may operate in a DC transformer (DCX) mode like an ideal DC transformer, which converts voltage with a fixed turns ratio (N:1).

[0022] In some embodiments, the output voltage of the LLC stage may be, for example, 1.8 V. In other embodiments, the output voltage of the LLC stage may be 3.3 V, 2.5 V, 1 V, or 0.9 V. The output voltage may be appropriately selected according to the load.

[0023] In some embodiments, the Buck output node of the Buck stage can be inserted between the lower switch in the controlled switch network of the LLC stage and the ground. When the LLC stage has a half-bridge switch network, the Buck output node is inserted between the lower switch of the half-bridge switch network and the ground. When the LLC stage has a full-bridge switch network, the Buck output node is inserted between one of the two lower switches of the full-bridge switch network and the ground.

[0024] In some embodiments, multi-phase interleaved coupled inductors may be implemented in the Buck converter stage to achieve higher transient response and reduce the ripple current of the Buck inductor.

[0025] Figure 1 An exemplary hybrid topology for DC voltage conversion according to various embodiments of the present disclosure is shown. Figure 1 As shown, S1 and S2 are switches of the Buck converter in the Buck stage, which are shown as MOSFETs, and D1 and D2 are the parasitic diodes of the two MOSFETs. L1 is the output inductor of the Buck converter, and C2 is the output capacitor of the Buck converter. A full-bridge LLC resonant converter is implemented behind the Buck converter, which provides the main power to the load. In the LLC resonant converter of the LLC stage, S3, S4, S5 and S6 are full-bridge MOSFET switches, D3, D4, D5 and D6 are the parasitic diodes of the four MOSFETs, Lr is the resonant inductor, Cr is the resonant capacitor, TX1 is the main transformer, D7 and D8 are diode rectifiers, and D7 and D8 can be replaced by MOSFETs to improve efficiency when using a synchronous rectification scheme.

[0026] like Figure 1 As shown, the Buck stage is inserted into the LLC stage by inserting the Buck output node V_buck between the lower switch S4 and ground. In another example, the Buck output node V_buck can be inserted between the lower switch S6 and ground.

[0027] The Buck stage adjusts the voltage of the V_buck node when the load changes, and the voltage of the V_buck node will adjust the input voltage of the LLC resonant cavity, which is one of the control variables for load regulation. The voltage of the V_buck node can vary from the input voltage (e.g., 48V) to 0V, so the converter gain of the LLC can vary from 0.5 to 1 using the V_buck voltage adjustment. The LLC stage can be used as an ideal transformer with a fixed switching frequency equal to the resonant frequency (e.g., 1MHz) of the resonant inductor Lr and the resonant capacitor Cr. With a hybrid topology, the Buck stage does not need to transfer higher power from its input to the output, so the Buck stage can use a small inductor and a small output capacitor, which helps with high transient response. In one example, the Buck inductor can be 100nH or 200nH, and the output capacitor can be 22uF or 47uF. In order to obtain higher transient response and reduce the ripple current of the Buck inductor, a multi-phase interleaved coupled inductor can be used in the Buck converter stage to replace the inductor L1.

[0028] Figure 2 An exemplary hybrid topology for DC voltage conversion and a dual-loop feedback module for the hybrid topology according to various embodiments of the present disclosure are shown.

[0029] exist Figure 2The upper part of the diagram shows an exemplary hybrid Buck and LLC topology, where the Buck stage is inserted into the LLC stage as mentioned above. Figure 2 Those elements in the drawings having the same reference numbers (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited thereto.

[0030] exist Figure 2 The lower part of FIG. 4 shows a dual-loop feedback module for a hybrid topology. One of the dual loops is a voltage outer loop, and the other is a current inner loop.

[0031] In some embodiments, the input of the voltage outer loop is the output voltage of the LLC stage, and the voltage outer loop can be used to adjust the output voltage of the LLC stage by using a compensation circuit or a control circuit, the compensation circuit is, for example, a Type I or Type II or Type III compensation circuit, and the control circuit is, for example, a digital control circuit or a nonlinear control circuit.

[0032] like Figure 2 As shown, in the voltage outer loop, the output voltage from the LLC stage is fed back to V OUT-FB It is input into the type II compensation circuit, specifically, into the error amplifier X1 in the type II compensation circuit, and the output of the error amplifier X1 in the voltage outer loop is input into the current inner loop.

[0033] In some embodiments, the current inner loop can be implemented with a simple proportional compensation circuit. One input of the current inner loop is the current of the resonant inductor Lr in the LLC stage, and the other input of the current inner loop is the output of the voltage outer loop. In some embodiments, the current I of the resonant inductor Lr can be sensed by a current sensing circuit. lr_sense For example, the current sensing circuit may be a current transformer. The current of the resonant inductor Lr may be sensed by any other method, which is not limited herein.

[0034] like Figure 2 As shown, the current sensed from the LLC stage I lr_sense The output signal of the current inner loop can be used to adjust the Buck PWM of the Buck converter in the Buck stage, where the Buck PWM is configured to control the on and off of the switches (e.g., S1 and S2) in the Buck converter. Figure 2 As shown, an exemplary BUCK PWM modulation circuit is shown to control the on and off of S1 and S2. In other embodiments, BUCK PWM can be implemented with any general PWM modulation circuit with dead time control.

[0035] Figure 4 Also shown is an exemplary LLC PWM modulation circuit configured to control the on and off of switches (eg, S3, S4, S5, and S6) in the LLC stage. In other embodiments, LLC PWM can be implemented with any general PWM modulation circuit with dead time control.

[0036] In order to verify the present disclosure, the Buck+LLC hybrid topology model and the related dual-loop control circuit were simulated in Simplis. Figure 2 The main key parameters are shown in Table 1.

[0037] Table 1. Key parameters in simulation verification

[0038] parameter value parameter value Input voltage (Vin) 48V Transformer (TX1) 19:1(Lp=6uH) Output voltage (Vout) 1.8V Resonant capacitor (Cr) 100nF Buck switching frequency (fsw) 1MHz Resonant inductance (Lr) 253nH Buck inductor (L_buck / L1) 100nH Load current step 50A(50A-100A) Buck output capacitor (C2) 47uF Load current slew rate 50A / us LLC switching frequency (fsw) 1MHz Output capacitor (C3+C4) 2400uF(470uF*5+10uF*5)

[0039] In the simulation verification, S3 / S6 and S4 / S5 have complementary 50% duty cycle PWM with a fixed switching frequency (1MHz) that is equal to the resonant frequency Fr of Lr and Cr:

[0040]

[0041] Figure 3 The key stable waveforms of LLC stage in simulation verification are shown, including i Lr , Iupper / MOSFET S3, Ilower / MOSFET S4, Id1 / Id2 and V OUT The waveform of Lr is the current of the resonant inductor Lr, Iupper is the current of MOSFETS3, Ilower is the current of MOSFET S4, Id1 and Id2 are the currents of rectifiers D7 and D8 respectively, V OUT is the output voltage of the LLC stage.

[0042] like Figure 3 As shown, MOSFET S3 is turned on or off when Iupper is close to a negative value, thereby realizing zero voltage switching (ZVS) of MOSFET S3. Similarly, MOSFET S4 is turned on or off when Ilower is close to a negative value, thereby realizing ZVS of MOSFETS4. When D7 and D8 are turned on or off, Id1 and Id2 are close to zero current, thereby also realizing zero current switching (ZCS) of the rectifier.

[0043] Figure 4The key stable waveforms of the Buck stage in the simulation verification are shown, including the waveforms of V_buck voltage, MOSFET S1, MOSFET S2, iL, SW_buck / S2 and Vds1 / S. V_buck voltage is the output voltage of the Buck stage, iL is the current of the output inductor L1, Figure 6 SW_buck and Vds1 indicated by dotted lines are the voltage waveforms at the drain and source terminals of MOSFET S1 / S2. Figure 4 As shown on the right side of , both S1 and S2 achieve ZVS turn-on.

[0044] Figure 5 Figure 2 shows the load transient waveform of the hybrid topology in simulation verification. Figure 5 As shown, when the load current increases from 50A to 100A (50A / us slew rate, @1ms simulation time), the feedback loop will adjust the duty cycle of S1, and the v_buck voltage will decrease from 25.5V to 11V, so that Vout can be regulated at 1.8V with a small undershoot (1.664V). In the same way, when the load current decreases from 100A to 50A (50A / us slew rate, @1.3ms simulation time), the feedback loop will adjust the duty cycle of S1, and the v_buck voltage will increase from 11V to 25.5V, so that Vout can be regulated at 1.8V with a small overshoot (1.937V).

[0045] As described above, through a hybrid Buck and LLC topology for DC voltage conversion and a dual-loop feedback module for the hybrid topology, the present invention provides a solution with higher efficiency power delivery and higher transient response for converting voltage (e.g., directly from 48V to 1.8V).

[0046] Figure 6 The figure illustrates a smart device or computer system or SoC (system on chip) from a hybrid topology for DC voltage conversion according to some embodiments of the present disclosure. It should be noted that, Figure 6 Those elements in the drawings having the same reference numbers (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited thereto.

[0047] In some embodiments, device 600 represents a suitable computing device, such as a computing tablet device, a mobile phone or smart phone, a laptop, a desktop computer, an Internet of Things (IOT) device, a server, a wearable device, a set-top box, an e-reader with wireless capabilities, etc. It will be understood that certain components are generally shown, and not all components of such devices are shown in device 600. Some embodiments of the present disclosure may be implemented in a system package design including multiple chips rather than in a SoC. In some embodiments, a system package design including multiple chips may receive power from a hybrid buck and LLC topology according to some embodiments of the present invention.

[0048] In an example, the device 600 includes a SoC (System on Chip) 601. Figure 6 Example boundaries of SOC 601 are illustrated in FIG. 6 using dashed lines, with some example components illustrated as included within SOC 601—however, SOC 601 may include any suitable components of device 600 .

[0049] In some embodiments, the device 600 includes a processor 604. The processor 604 may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, a processing core, or other processing means. The processing operations performed by the processor 604 include the execution of an operating platform or operating system on which applications and / or device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or with other devices, operations related to power management, operations related to connecting the computing device 600 to another device, and the like. The processing operations may also include operations related to audio I / O or display I / O.

[0050] In some embodiments, processor 604 includes multiple processing cores (also referred to as cores) 608a, 608b, 608c. Figure 6 Only three cores 608a, 608b, 608c are shown in the figure. However, the processor 604 may include any other suitable number of processing cores, for example, dozens or even hundreds of processing cores. The processor cores 608a, 608b, 608c may be implemented on a single integrated circuit (IC) chip. In addition, the chip may include one or more shared and / or private caches, buses or interconnects, graphics and / or memory controllers, or other components.

[0051] In some embodiments, the processor 604 includes a cache 606. In an example, portions of the cache 606 may be dedicated to individual cores 608 (e.g., a first portion of the cache 606 is dedicated to core 608a, a second portion of the cache 606 is dedicated to core 608b, etc.). In an example, one or more portions of the cache 606 may be shared between two or more cores 608. The cache 606 may be divided into different levels, such as a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, etc.

[0052] In some embodiments, the processor core 604 may include an acquisition unit for acquiring instructions (including instructions with conditional branches) for execution by the core 604. The instructions may be acquired from any storage device such as the memory 603. The processor core 604 may also include a decoding unit for decoding the acquired instructions. For example, the decoding unit may decode the acquired instructions into a plurality of micro-operations. The processor core 604 may include a scheduling unit for performing various operations associated with storing the decoded instructions. For example, the scheduling unit may save data from the decoding unit until the instructions are ready for dispatch, for example, until all source values ​​of the decoded instructions become available. In one embodiment, the scheduling unit may schedule and / or issue (or dispatch) the decoded instructions to the execution unit for execution.

[0053] After the instructions are decoded (e.g., by a decode unit) and dispatched (e.g., by a scheduling unit), the execution unit may execute the dispatched instructions. In an embodiment, the execution unit may include more than one execution unit (such as an imaging computing unit, a graphics computing unit, a general computing unit, etc.). The execution unit may also perform various arithmetic operations such as addition, subtraction, multiplication, and / or division, and may include one or more arithmetic logic units (ALUs). In an embodiment, a coprocessor (not shown) may be combined with the execution unit to perform various arithmetic operations.

[0054] In addition, the execution unit can execute instructions out of order. Therefore, in one embodiment, the processor core 604 can be an out-of-order processor core. The processor core 604 can also include a retirement unit. The retirement unit can retire the executed instruction after the instruction is submitted. In an embodiment, the retirement of the executed instruction can cause the physical state submitted when the instruction is executed, the physical register used by the instruction to be de-allocated, etc. The processor core 604 can also include a bus unit to enable communication between the components of the processor core 604 and other components via one or more buses. The processor core 604 can also include one or more registers to store data accessed by various components of the core 604 (such as, values ​​associated with the assigned application priority and / or subsystem state (mode)).

[0055] In some embodiments, device 600 includes connection circuitry 631. For example, connection circuitry 631 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and / or software components (e.g., drivers, protocol stacks, etc.), for example, to enable device 600 to communicate with external devices. Device 600 can be separate from external devices such as other computing devices, wireless access points, or base stations.

[0056] In the example, the connection circuit 631 may include a variety of different types of connections. In general, the connection circuit 631 may include a cellular connection circuit, a wireless connection circuit, etc. The cellular connection circuit of the connection circuit 631 generally refers to a cellular network connection provided by a wireless operator, such as via GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variants or derivatives, the Third Generation Partnership Project (3GPP) Universal Mobile Telecommunications System (UMTS) or variants or derivatives, 3GPP Long Term Evolution (LTE) system or variants or derivatives, 3GPP LTE-Advanced (LTE-A) system or variants or derivatives, fifth generation (5G) wireless system or variants or derivatives, 5G mobile network system or variants or derivatives, 5G new radio (NR) system or variants or derivatives, 6G, or other cellular service standards. The wireless connection circuit (or wireless interface) of the connection circuit 631 refers to a non-cellular wireless connection and may include a personal area network (such as Bluetooth, near field, etc.), a local area network (such as Wi-Fi), and / or a wide area network and / or other wireless communications. In an example, the connection circuit 631 may include a network interface such as a wired or wireless interface, for example, so that the system embodiment can be incorporated into a wireless device such as a mobile phone or a personal digital assistant.

[0057] In some embodiments, the device 600 includes a controller 632, which represents a hardware device and / or software component related to the interaction with one or more I / O devices. For example, the processor 604 can communicate with one or more of the display 622, one or more peripheral devices 624, a storage device 628, one or more other external devices 629, etc. via the controller 632. The controller 632 can be a chipset, a platform controller, etc.

[0058] For example, controller 632 illustrates one or more connection points for additional devices connected to device 600, through which, for example, a user may interact with the system. For example, devices (e.g., device 629) that may be attached to device 600 include a microphone device, a speaker or stereo system, an audio device, a video system or other display device, a keyboard or keypad device, or other I / O devices for specific applications such as a card reader or other device.

[0059] As described above, the controller 632 can interact with audio devices, display 622, and the like. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the device 600. In addition, audio output can be provided instead of or in addition to display output. In another example, if the display 622 includes a touch screen, the display 622 also acts as an input device, which can be managed at least in part by the controller 632. There can also be additional buttons or switches on the computing device 600 to provide I / O functions managed by the controller 632. In one embodiment, the controller 632 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware devices that may be included in the device 600. The input can be part of a direct user interaction, or environmental input can be provided to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, applying a flash to the camera, or other features).

[0060] In some embodiments, the controller 632 can be coupled to various devices using any suitable communication protocol, such as PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High-Definition Multimedia Interface (HDMI), Firewire, etc.

[0061] In some embodiments, the display 622 represents hardware (e.g., display device) and software (e.g., driver) components that provide a user with a visual and / or tactile display for interaction with the device 600. The display 622 may include a display interface, a display screen, and / or a hardware device for providing a display to a user. In some embodiments, the display 622 includes a touch screen (or touchpad) device that provides output and input to the user. In an example, the display 622 can communicate directly with the processor 604. The display 622 may be one or more of an internal display device in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display 622 may be a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) applications or augmented reality (AR) applications.

[0062] In some embodiments, although not illustrated in the figure, in addition to (or in place of) the processor 604, the device 600 may also include a graphics processing unit (GPU), which includes one or more graphics processing cores that can control one or more aspects of the displayed content on the display 622.

[0063] The controller 632 (or platform controller) may include hardware interfaces and connectors as well as software components (eg, drivers, protocol stacks) to make peripheral connections with the peripheral devices 624 , for example.

[0064] It will be understood that device 600 can be a peripheral device of other computing devices or can have peripheral devices connected to it. Device 600 can have a "docking" connector that connects to other computing devices for purposes such as managing (e.g., downloading and / or uploading, modifying, synchronizing) content on device 600. In addition, the docking connector can allow device 600 to connect to certain peripheral devices that allow computing device 600 to control, for example, the output of content to an audio-visual system or other system.

[0065] In addition to proprietary docking connectors or other proprietary connection hardware, device 600 may also connect peripherals via universal connectors or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a variety of different hardware interfaces), DisplayPort including Mini DisplayPort (MiniDisplayPort, MDP), High Definition Multimedia Interface (HDMI), FireWire, or other types.

[0066] In some embodiments, for example, in addition to or instead of being directly coupled to the processor 604, the connection circuit 631 can also be coupled to the controller 632. In some embodiments, for example, in addition to or instead of being directly coupled to the processor 604, the display 622 can also be coupled to the controller 632.

[0067] In some embodiments, device 600 includes memory 630 coupled to processor 604 via memory interface 634. Memory 630 includes a memory device for storing information in device 600.

[0068] In some embodiments, memory 630 includes means for maintaining stable timing as described with reference to various embodiments. Memory may include non-volatile (if power to the memory device is interrupted, the state does not change) and / or volatile (if power to the memory device is interrupted, the state is uncertain) memory devices. Memory device 630 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance for use as processing memory. In one embodiment, memory 630 may operate as system memory of device 600 to store data and instructions for use by one or more processors 604 when executing applications or processes. Memory 630 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to executing applications and functions of device 600.

[0069] Elements of various embodiments and examples are also provided as machine-readable media (e.g., memory 630) for storing computer-executable instructions (e.g., instructions for implementing any other process discussed herein). The machine-readable medium (e.g., memory 630) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memories (PCMs), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS), which may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) in the form of a data signal via a communication link (e.g., a modem or a network connection).

[0070] In some embodiments, the device 600 includes a temperature measurement circuit 640, for example, for measuring the temperature of various components of the device 600. In an example, the temperature measurement circuit 640 can be embedded in, coupled to, or attached to various components whose temperatures are to be measured or monitored. For example, the temperature measurement circuit 640 can measure the temperature of one or more of (or within) the cores 608a, 608b, 608c, the voltage regulator 614, the memory 630, the motherboard of the SOC 601, and / or any suitable component of the device 600.

[0071] In some embodiments, the device 600 includes a power measurement circuit 642, for example, for measuring the power consumed by one or more components of the device 600. In an example, in addition to measuring power or instead of measuring power, the power measurement circuit 642 can also measure voltage and / or current. In an example, the power measurement circuit 642 can be embedded, coupled, or attached to various components whose power, voltage, and / or current consumption will be measured or monitored. For example, the power measurement circuit 642 can measure the power, current, and / or voltage provided by one or more voltage regulators 614, the power provided to the SOC 601, the power provided to the device 600, the power consumed by the processor 604 (or any other component) of the device 600, etc.

[0072] In some embodiments, the device 600 includes one or more voltage regulator circuits, which are collectively referred to as voltage regulators (VRs) 614. VR 614 generates a signal at an appropriate voltage level that can be provided to operate any appropriate component of the device 600. By way of example only, VR 614 is illustrated as providing a signal to a processor 604 of the device 600. In some embodiments, VR 614 receives one or more voltage identification (VID) signals and generates a voltage signal at an appropriate level based on the VID signals. Different types of VRs can be utilized for VR 614. For example, VR 614 can include a "buck" VR, a "boost" VR, a combination of buck and boost VRs, a low dropout (LDO) regulator, a switching DC-DC regulator, and the like. Buck VRs are typically used in power transmission applications where an input voltage needs to be converted to an output voltage at a ratio less than 1. Boost VRs are typically used in power transmission applications where an input voltage needs to be converted to an output voltage at a ratio greater than 1. In some embodiments, each processor core has its own VR, which is controlled by PCU 610a / b and / or PMIC 612. In some embodiments, each core has a distributed LDO network to provide efficient control for power management. The LDO can be a digital LDO, an analog LDO, or a combination of digital or analog LDOs.

[0073] Each voltage regulator of the device 600 receives an input power supply Vin and generates a regulated power supply voltage for a specific power domain. In various embodiments, in various embodiments, the input power supply Vin is generated by a hybrid Buck and LLC topology that receives a high voltage (e.g., 48V) from an external source such as a 48V bus.

[0074] In some embodiments, the device 600 includes one or more clock generator circuits, collectively referred to as clock generators 616. The clock generators 616 generate clock signals at appropriate frequency levels, which may be provided to any appropriate component of the device 600. By way of example only, the clock generators 616 are illustrated as providing clock signals to the processor 604 of the device 600. In some embodiments, the clock generators 616 receive one or more frequency identification (FID) signals and generate clock signals at appropriate frequencies based on the FID signals.

[0075] In some embodiments, device 600 includes an input voltage source 618 that powers various components of device 600 via a converter 619 .

[0076] In some embodiments, the device 600 includes a power control unit (PCU) 610 (also referred to as a power management unit (PMU), a power controller, etc.). In an example, some parts of the PCU 610 may be implemented by one or more processing cores 608, and these parts of the PCU 610 are symbolically illustrated using dashed boxes and labeled as PCU 610a. In an example, some other parts of the PCU 610 may be implemented outside the processing core 608, and these parts of the PCU 610 are symbolically illustrated using dashed boxes and labeled as PCU 610b. The PCU 610 may implement various power management operations for the device 600. The PCU 610 may include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) to implement various power management operations for the device 600.

[0077] In some embodiments, the device 600 includes a power management integrated circuit (PMIC) 612, for example, to implement various power management operations for the device 600. In some embodiments, the PMIC 612 is a reconfigurable power management IC (RPMIC) and / or an IMVP ( Mobile voltage positioning). In an example, the PMIC is located in an IC chip separate from the processor 604. The PMIC can implement various power management operations for the device 600. The PMIC 612 can include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) to implement various power management operations for the device 600.

[0078] In the example, the device 600 includes one or both of the PCU 610 or the PMIC 612. In the example, neither the PCU 610 or the PMIC 612 may be present in the device 600, and thus, these components are illustrated using dashed lines.

[0079] Various power management operations of the device 600 may be performed by the PCU 610, the PMIC 612, or a combination of the PCU 610 and the PMIC 612. For example, the PCU 610 and / or the PMIC 612 may select power states (e.g., P-states) of various components of the device 600. For example, the PCU 610 and / or the PMIC 612 may select power states (e.g., according to the ACPI (Advanced Configuration and Power Interface) specification) of various components of the device 600. By way of example only, the PCU 610 and / or the PMIC 612 may cause various components of the device 600 to transition to a sleep state, an active state, an appropriate C-state (e.g., a C0 state or another appropriate C-state according to the ACPI specification), etc. In an example, the PCU 610 and / or the PMIC 612 may control the voltage output by the VR 614 and / or the frequency of the clock signal output by the clock generator, for example, by outputting a VID signal and / or a FID signal, respectively.

[0080] The clock generator 616 may include a phase-locked loop (PLL), a frequency-locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor 604 has its own clock source. In this way, each core can operate at a frequency independent of the operating frequency of other cores. In some embodiments, the PCU 610 and / or the PMIC 612 perform adaptive or dynamic frequency scaling or adjustment. For example, if the processor core is not operating at its maximum power consumption threshold or limit, the clock frequency of the processor core can be increased. In some embodiments, the PCU 610 and / or the PMIC 612 determine the operating conditions of each core of the processor, and when the PCU 610 and / or the PMIC 612 determine that the core is running below the target performance level, the core clock source (e.g., the PLL of the core) is not lost. The core frequency and / or supply voltage are opportunistically adjusted. For example, if a core is drawing less current from the power rail than the total current allocated to the core or processor 604, the PCU 610 and / or PMIC 612 may temporarily increase the power drawn for the core or processor 604 (e.g., by increasing the clock frequency and / or the power supply voltage level) so that the core or processor 604 may operate at a higher performance level. In this way, the voltage and / or frequency may be temporarily increased for the processor 604 without violating product reliability.

[0081] In an example, the PCU 610 and / or PMIC 612 may perform power management operations, for example, based at least in part on measurements received from the power measurement circuit 642 and the temperature measurement circuit 640 and / or any other appropriate information that may be used for power management. To this end, the PMIC 612 is communicatively coupled to one or more sensors to sense / detect various values / changes of one or more factors that have an impact on the power / thermal behavior of the system / platform. Examples of the one or more factors include current, voltage drop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be provided in physical proximity (and / or thermal contact / coupling) to one or more components or logic / IP blocks of the computing system. In addition, in at least one embodiment, one or more sensors may be directly coupled to the PCU 610 and / or PMIC 612 to allow the PCU 610 and / or PMIC 612 to manage processor core energy based at least in part on values ​​detected by the one or more sensors.

[0082] Also illustrated is an example software stack for device 600 (although not all elements of the software stack are illustrated). By way of example only, processor 604 may execute application 650, operating system 652, one or more power management (PM) specific applications (e.g., collectively referred to as PM applications 658), etc. PM applications 658 may also be executed by PUC 610 and / or PMIC 612. OS 652 may also include one or more PM applications 656a, 656b, 656c. OS 652 may also include various drivers 654a, 654b, 654c, etc., some of which may be dedicated to power management purposes. In some embodiments, device 600 may also include a basic input / output system (BIOS) 620. BIOS 620 may communicate with OS 652 (e.g., via one or more drivers 654), communicate with processor 604, etc.

[0083] For example, one or more of the PM applications 658, 656, driver 654, BIOS 620, etc. may be used to implement power management specific tasks, such as to control the voltage and / or frequency of various components of the device 600, control the wake state, sleep state, and / or any other appropriate power state of various components of the device 600, and so on.

[0084] References in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least some embodiments, but not necessarily in all embodiments. Various appearances of "an embodiment," "one embodiment," or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not necessarily included. If the specification or claims refer to "a" or "an" element, it does not mean that there is only one element. If the specification or claims refer to "an additional" element, it does not exclude that there is more than one additional element.

[0085] In addition, specific features, structures, functions, or characteristics can be combined in any suitable manner in one or more embodiments. For example, in any case where the specific features, structures, functions, or characteristics associated with the first embodiment and the second embodiment are not mutually exclusive, the first embodiment can be combined with the second embodiment.

[0086] Although the present disclosure has been described in conjunction with the specific embodiments of the present disclosure, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. The embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims.

[0087] In addition, to simplify the description and discussion and to avoid obscuring the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. In addition, to avoid obfuscating the present disclosure, and in view of the fact that the details of the implementation of this block diagram arrangement are highly dependent on the platform on which the present disclosure is implemented (i.e., these details should be within the capabilities of those skilled in the art), the arrangement can be shown in block diagram form. Where specific details (e.g., circuits) are stated to describe example embodiments of the present disclosure, it will be apparent to those skilled in the art that the present disclosure may be implemented without these specific details or with variations of these specific details. Therefore, the present description is considered to be illustrative rather than restrictive.

[0088] The following examples are provided to illustrate various embodiments. These examples may be dependent upon each other in any suitable manner.

[0089] Example 1 includes a device including a step-down (Buck) converter and an LLC resonant converter. The Buck converter is coupled to a direct current (DC) input voltage source and is configured to output a Buck output voltage at its output node. The LLC resonant converter is coupled to the Buck converter and is configured to output a DC output voltage to provide power to a load, wherein the LLC resonant converter includes a controlled switch network, and the output node of the Buck converter is connected between a lower switch in the controlled switch network and ground.

[0090] Example 2 includes the apparatus of Example 1, wherein the controlled switching network is a full-bridge switch network.

[0091] Example 3 includes the apparatus of Example 1 or 2, wherein the controlled switching network is a half-bridge switching network.

[0092] Example 4 includes the apparatus of any one of Examples 1-3, wherein a multi-phase interleaved coupled inductor is implemented in the Buck converter.

[0093] Example 5 includes the apparatus described in any one of Examples 1-4, wherein the Buck output voltage of the Buck converter is adjusted by a dual-loop feedback module according to the output of the LLC resonant converter, and the dual-loop feedback module includes a voltage outer loop and a current inner loop.

[0094] Example 6 includes the apparatus described in any one of Examples 1-5, wherein an input signal of the voltage outer loop is the output voltage of the LLC resonant converter, and one input signal of the current inner loop is the current of the resonant inductor Lr in the LLC resonant converter, and another input signal of the current inner loop is the output signal of the voltage outer loop.

[0095] Example 7 includes the apparatus of any one of Examples 1-6, wherein the output signal of the inner current loop is used to adjust the Buck PWM of the Buck converter, wherein the Buck PWM is configured to control the on and off of a switch in the Buck converter.

[0096] Example 8 includes the apparatus of any of Examples 1-7, wherein the current of the resonant inductor Lr is sensed by a current sensing circuit.

[0097] Example 9 includes the apparatus of any one of Examples 1-8, wherein the current of the resonant inductor Lr is sensed by a current transformer.

[0098] Example 10 includes the apparatus of any of Examples 1-9, wherein the voltage outer loop is implemented by a compensation circuit.

[0099] Example 11 includes the apparatus of any one of Examples 1-10, wherein the voltage outer loop is implemented by a Type I, Type II, or Type III compensation circuit.

[0100] Example 12 includes the apparatus of any of Examples 1-11, wherein the voltage outer loop is implemented by a control circuit.

[0101] Example 13 includes the apparatus of any of Examples 1-12, wherein the voltage outer loop is implemented by a digital control circuit.

[0102] Example 14 includes the apparatus of any of Examples 1-13, wherein the voltage outer loop is implemented by a nonlinear control circuit.

[0103] Example 15 includes the apparatus of any of Examples 1-14, wherein the inner current loop is implemented using a proportional compensation circuit.

[0104] Example 16 includes the apparatus of any one of Examples 1-15, wherein the Buck PWM of the Buck converter is implemented by a Buck PWM modulation circuit with dead time control.

[0105] Example 17 includes the apparatus of any of Examples 1-16, wherein LLC PWM of the LLC resonant converter is implemented by an LLC PWM modulation circuit with dead time control.

[0106] Example 18 includes the apparatus of any one of Examples 1-17, wherein the DC input voltage source has a DC voltage of 48V.

[0107] Example 19 includes the apparatus of any of Examples 1-18, wherein the output voltage of the LLC resonant converter is 2.5V, 1.8V, 1V, or 0.9V.

[0108] Example 20 includes a method comprising: connecting a Buck converter to an LLC resonant converter, the LLC resonant converter including a controlled switch network, wherein an output node of the Buck converter is connected between a lower switch in the controlled switch network of the LLC resonant converter and ground.

[0109] Example 21 includes the method of Example 20, wherein the controlled switching network is a full-bridge switch network.

[0110] Example 22 includes the method of Example 20 or 21, wherein the controlled switching network is a half-bridge switching network.

[0111] Example 23 includes the method of any one of Examples 20-22, wherein a multi-phase interleaved coupled inductor is implemented in the Buck converter.

[0112] Example 24 includes the method described in any one of Examples 20-23, further comprising: adjusting the Buck output voltage at the output node of the Buck converter according to the output of the LLC resonant converter by a dual-loop feedback module, wherein the dual-loop feedback module includes a voltage outer loop and a current inner loop.

[0113] Example 25 includes the method described in any one of Examples 20-24, wherein an input signal of the voltage outer loop is the output voltage of the LLC resonant converter, and one input signal of the current inner loop is the current of the resonant inductor Lr in the LLC resonant converter, and another input signal of the current inner loop is the output signal of the voltage outer loop.

[0114] Example 26 includes the method of any of Examples 20-25, wherein the output signal of the inner current loop is used to adjust the Buck PWM of the Buck converter, wherein the Buck PWM is configured to control the on and off of a switch in the Buck converter.

[0115] Example 27 includes the method of any one of Examples 20-26, wherein the current of the resonant inductor Lr is sensed by a current sensing circuit.

[0116] Example 28 includes the method of any one of Examples 20-27, wherein the current of the resonant inductor Lr is sensed by a current transformer.

[0117] Example 29 includes the method of any of Examples 20-28, wherein the voltage outer loop is implemented by a compensation circuit.

[0118] Example 30 includes the method of any one of Examples 20-29, wherein the voltage outer loop is implemented by a Type I, Type II, or Type III compensation circuit.

[0119] Example 31 includes the method of any of Examples 20-230, wherein the voltage outer loop is implemented by a control circuit.

[0120] Example 32 includes the method of any of Examples 20-31, wherein the voltage outer loop is implemented by a digital control circuit.

[0121] Example 33 includes the method of any of Examples 20-32, wherein the voltage outer loop is implemented by a nonlinear control circuit.

[0122] Example 34 includes the method of any of Examples 20-33, wherein the current inner loop is implemented using a proportional compensation circuit.

[0123] Example 35 includes the method of any of Examples 20-34, wherein the Buck PWM of the Buck converter is implemented by a Buck PWM modulation circuit with dead time control.

[0124] Example 36 includes the method of any of Examples 20-35, wherein LLC PWM of the LLC resonant converter is implemented by an LLC PWM modulation circuit with dead time control.

[0125] Example 37 includes the method of any one of Examples 20-36, wherein the DC voltage of the DC input voltage source is 48V.

[0126] Example 38 includes the method of any of Examples 20-37, wherein the output voltage of the LLC resonant converter is 2.5V, 1.8V, 1V, or 0.9V.

[0127] Example 39 includes a voltage converter comprising the apparatus of any of Examples 1-19.

[0128] Example 40 includes a system comprising: a DC voltage source; a voltage converter comprising a device according to any one of claims 1-14; a processor coupled to an output of the voltage converter, wherein the voltage converter is used to provide power to the processor; and a memory coupled to the processor.

[0129] The above detailed description includes references to the accompanying drawings that form a part of the detailed description. The accompanying drawings show specific embodiments that can be put into practice by way of illustration. These embodiments are also referred to as "examples" in this article. Such examples may include elements other than those shown or described. However, the inventors also consider examples that only provide those elements shown or described. In addition, with respect to the specific examples (or one or more aspects thereof) shown and described herein or with respect to other examples (or one or more aspects thereof), the inventors also consider examples of any combination or arrangement of those elements (or one or more aspects thereof) shown or described.

[0130] All publications, patents, and patent documents mentioned in this document are incorporated herein by reference in their entirety, as if individually incorporated by reference. In the event of an inconsistency between the usage of this document and those documents incorporated by reference, the usage in the cited references should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0131] In this document, as is common in patent documents, the terms "a" or "an" are used to include one or more, independent of any other instances or uses of "at least one" or "one or more." In this document, unless otherwise stated, the term "or" is used to refer to a non-exclusive or, for example, "A or B" includes "A but not B," "B but not A," and "A and B." In the appended claims, the terms "including" and "wherein" are used as simple equivalents of the respective terms "comprising" and "wherein." In addition, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include elements other than the elements listed after such terms in the claim are also considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first," "second," "third," etc. are used merely as labels and do not impose numerical requirements on their objects.

[0132] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, for example, by a person of ordinary skill in the art after reading the above description. The abstract is intended to allow the reader to quickly determine the essence of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the disclosure. This should not be interpreted as intending that the disclosed features that are not claimed for protection are essential to any claim. On the contrary, the subject matter of the present invention may lie in less than all the features of a particular disclosed embodiment. Therefore, the claims are hereby incorporated into the detailed description, and each claim is independent as a separate embodiment. The scope of the embodiment should be determined with reference to the appended claims and the full scope of equivalents to which these claims are assigned.

Claims

1. A device comprising: A step-down Buck converter coupled to a DC input voltage source and configured to output a Buck output voltage at an output node of the Buck converter; An LLC resonant converter coupled to the Buck converter and configured to output a DC output voltage to provide power to a load, wherein the LLC resonant converter includes a controlled switch network; The output node of the Buck converter is connected between the lower switch in the controlled switch network and the ground.

2. The device according to claim 1, wherein: The controlled switching network is a full-bridge switching network.

3. The device of claim 1, wherein: The controlled switching network is a half-bridge switching network.

4. The device according to any one of claims 1 to 3, wherein: A multi-phase interleaved coupled inductor is implemented in the Buck converter.

5. The device according to any one of claims 1 to 3, wherein: The Buck output voltage of the Buck converter is adjusted by a dual-loop feedback module according to the output of the LLC resonant converter, and the dual-loop feedback module includes a voltage outer loop and a current inner loop.

6. The device according to claim 5, wherein: An input signal of the voltage outer loop is the output voltage of the LLC resonant converter, and one input signal of the current inner loop is the current of the resonant inductor Lr in the LLC resonant converter, and another input signal of the current inner loop is the output signal of the voltage outer loop.

7. The device according to claim 6, wherein: The output signal of the current inner loop is used to adjust the Buck pulse width modulation (PWM) of the Buck converter, wherein the Buck PWM is configured to control the on and off of the switch in the Buck converter.

8. The device of claim 6, wherein: The current of the resonant inductor Lr is sensed by a current sensing circuit.

9. The device of claim 8, wherein: The current of the resonant inductor Lr is sensed by a current transformer.

10. The device according to claim 5, wherein: The voltage outer loop is implemented by a compensation circuit, or a digital or nonlinear control circuit.

11. The device according to claim 5, wherein: The current inner loop is implemented by a proportional compensation circuit.

12. The device of claim 7, wherein: The Buck PWM of the Buck converter is implemented by a Buck PWM modulation circuit with dead time control.

13. The device of claim 1, wherein: The LLC PWM of the LLC resonant converter is implemented by an LLC PWM modulation circuit with dead time control.

14. The device of claim 1, wherein: The DC input voltage source has a DC voltage of 48V, and the output voltage of the LLC resonant converter is 2.5V, 1.8V, 1V or 0.9V.

15. A method comprising: A buck converter is connected to an LLC resonant converter, the LLC resonant converter comprising a controlled switch network, The output node of the Buck converter is connected between the lower switch in the controlled switch network of the LLC resonant converter and the ground.

16. The method of claim 15, further comprising: The Buck output voltage at the output node of the Buck converter is adjusted by a dual-loop feedback module according to the output of the LLC resonant converter, wherein the dual-loop feedback module includes a voltage outer loop and a current inner loop.

17. The method of claim 16, wherein: An input signal of the voltage outer loop is the output voltage of the LLC resonant converter, and one input signal of the current inner loop is the current of the resonant inductor Lr in the LLC resonant converter, and another input signal of the current inner loop is the output signal of the voltage outer loop.

18. The method of claim 17, wherein: The output signal of the current inner loop is used to adjust the Buck pulse width modulation (PWM) of the Buck converter, wherein the Buck PWM is configured to control the on and off of the switch in the Buck converter.

19. A voltage converter comprising the device according to any one of claims 1-14.

20. A system, comprising: Direct current (DC) voltage source; A voltage converter comprising a device according to any one of claims 1 to 14; a processor coupled to an output of the voltage converter, wherein the voltage converter is used to provide power to the processor; and A memory is coupled to the processor.

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