Integrated circuit device and oscillator

Abstract

Provided are an integrated circuit device and an oscillator capable of reducing the possibility of a decrease in current flowing through a transistor due to parasitic resistance between a land and the transistor. The integrated circuit device includes: a first land to which one of a power supply voltage and a ground voltage is supplied; a second terminal pad to which the other of the power supply voltage and the ground voltage is supplied; a first transistor having a first gate to which a temperature control signal is input, a first drain electrically connected to the first land, and a first source electrically connected to the second land; a first drain connection via wiring that is a via wiring that electrically connects the first land and the first drain to each other; and a first source connection via wiring that electrically connects the second land and the first source, in which, in a plan view, the first drain overlaps the first land, and the first source overlaps the second land.

Description

Technical Field

[0001] The present invention relates to an integrated circuit device and an oscillator. Background Art

[0002] Patent document 1 describes an integrated circuit device having a heating circuit, which includes a heating transistor connected between a power connection plate and a ground connection plate. By configuring the resistance value of the source of the heating transistor to be smaller than the resistance value of the drain, the reduction in heating performance caused by the parasitic resistance of the heating transistor is suppressed.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2022-138842

[0004] In the integrated circuit device described in Patent Document 1, the current flowing through the heating transistor may decrease due to the parasitic resistance of the diffusion layer between the power connection pad and the drain of the heating transistor and the parasitic resistance of the diffusion layer between the source of the heating transistor and the ground connection pad. Summary of the invention

[0005] One embodiment of the integrated circuit device of the present invention includes: a first connection pad, which is provided with one of a power supply voltage and a ground voltage; a second connection pad, which is provided with the other of the power supply voltage and the ground voltage; a first transistor, which has a first gate to which a temperature control signal is input, a first drain electrically connected to the first connection pad, and a first source electrically connected to the second connection pad; a through-hole wiring for connecting the first drain, which is a through-hole wiring that electrically connects the first connection pad and the first drain; and a through-hole wiring for connecting the first source, which is a through-hole wiring that electrically connects the second connection pad and the first source, and when viewed from above, the first drain overlaps with the first connection pad, and the first source overlaps with the second connection pad.

[0006] One embodiment of an oscillator of the present invention comprises: an integrated circuit device; a vibration element, which is temperature-controlled by the integrated circuit device; and an oscillation circuit, which causes the vibration element to oscillate, the integrated circuit device including: a first connection pad, which is provided with one of a power supply voltage and a ground voltage; a second connection pad, which is provided with the other of the power supply voltage and the ground voltage; a first transistor, which has a first gate to which a temperature control signal is input, a first drain electrically connected to the first connection pad, and a first source electrically connected to the second connection pad; a through-hole wiring for connecting the first drain, which is a through-hole wiring that electrically connects the first connection pad and the first drain; and a through-hole wiring for connecting the first source, which is a through-hole wiring that electrically connects the second connection pad and the first source, and when viewed from above, the first drain overlaps with the first connection pad, and the first source overlaps with the second connection pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a functional block diagram of the integrated circuit device of this embodiment.

[0008] Figure 2 It is a diagram showing the circuit configuration of the heat generating section in the first embodiment.

[0009] Figure 3 It is a plan view showing an example of the layout of an integrated circuit device.

[0010] Figure 4 It is a diagram showing the layout of the heat generating parts in the first embodiment.

[0011] Figure 5 It is a perspective view of a region A1 of the integrated circuit device according to the first embodiment.

[0012] Figure 6 It is a diagram showing a circuit configuration of a heat generating unit in the second embodiment.

[0013] Figure 7 It is a diagram showing the layout of the heat generating section in the second embodiment.

[0014] Figure 8 It is a perspective view of a region A1 of the integrated circuit device according to the second embodiment.

[0015] Fig. 9 It is a cross-sectional view of the oscillator according to this embodiment.

[0016] Fig.10 It is a top view of the oscillator of this embodiment.

[0017] Fig.11 This is a cross-sectional view showing the inner package of the oscillator and its interior.

[0018] Fig.12 It is a cross-sectional view showing a voltage controlled oscillator included in the oscillator.

[0019] Fig.13 is the functional block diagram of the oscillator.

[0020] Description of symbols

[0021] 1: oscillator; 2: outer package; 3: inner package; 4: control IC; 5: voltage controlled oscillator; 6: vibration element; 7: integrated circuit device; 8: oscillation IC; 10: digital signal processing circuit; 11: temperature control circuit; 12: temperature compensation circuit; 21: outer base, 21a: upper surface; 21b: lower surface; 22: outer cover; 23: sealing component; 25: internal wiring; 27: substrate; 28: wall; 29: foot; 31: inner base; 31a: upper surface; 31b: lower surface; 32: inner cover; 33: sealing component; 41: selector, 42: temperature sensor; 43: A / D converter; 44: D / A converter; 45: fractional-N-PLL circuit; 46: PLL circuit; 47: switch circuit; 48: power supply circuit; 49: interface circuit; 51: package; 52: base; 52a: upper surface; 52b: lower surface; 53: cover; 54: sealing member; 55: vibration element; 59: oscillation IC; 71: heating part; 72: temperature sensor; 73: electrostatic protection circuit; 74: electrostatic protection circuit; 75-1 to 75-N: transistor; 76-1 to 76-N: transistor; 81: oscillation circuit; 82: temperature sensor; 90: memory; 91: temperature control data; 92: temperature compensation data; 94: register; 100: external device 211: upper recess; 211a: first upper recess; 211b: second upper recess; 211c: third upper recess; 212: lower recess; 241: internal terminal; 242: internal terminal; 243: internal terminal; 244: external terminal; 245: side terminal; 311: recess; 311a: first recess; 311b: second recess, 311c: third recess; 341: internal terminal; 342: internal terminal; 343: internal terminal; 344: external terminal; 400: semiconductor substrate; 401: connection pad; 402: connection pad; 403: connection pad; 404: connection pad; 410: well; 411: metal Wiring; 412: metal wiring; 421: through-hole wiring; 422: through-hole wiring; 431: through-hole wiring; 432: through-hole wiring; 521: recess; 521a: 1st recess; 521b: 2nd recess; 521c: 3rd recess; 561: internal terminal; 562: internal terminal; 564: external terminal; B1: bonding component; B2: bonding component; B3: bonding component; B4: bonding component; BW1: bonding wire; BW2: bonding wire; BW3: bonding wire; BW4: bonding wire; BW5: bonding wire; BW6: bonding wire; H: solder; S1: storage space; S2: storage space; S3: storage space; S5: storage space. DETAILED DESCRIPTION

[0022] Hereinafter, preferred embodiments of the present invention will be described in detail using the accompanying drawings. In addition, the embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, the structures described below may not all be essential components of the present invention.

[0023] 1. Integrated circuit devices

[0024] 1-1. First Embodiment

[0025] Figure 1 FIG. 1 is a functional block diagram of an integrated circuit device according to this embodiment. Figure 1 As shown, the integrated circuit device 7 of this embodiment includes a heat generating portion 71 and may further include a temperature sensor 72 .

[0026] The integrated circuit device 7 has connection pads 401, 402, 403, 404 as electrodes for external connection. The connection pads 401, 402, 403, 404 can be connection pads for wire bonding installation or connection pads for flip chip installation. The connection pad 401 is connected to the power supply and is provided with a power supply voltage VDD. The connection pad 402 is grounded and is provided with a ground voltage VSS. The connection pads 403 and 404 are connected to, for example, a control device not shown. Moreover, the connection pad 403 is input with a temperature control signal TC, and the connection pad 404 outputs a temperature detection signal TS as an output signal from the temperature sensor 72.

[0027] The heating portion 71 is connected between the power supply and the ground via the connection pads 401 and 402, and generates heat by the current flowing from the power supply to the ground. The amount of heat generated by the heating portion 71 varies according to the voltage level of the temperature control signal TC. Thus, the integrated circuit device 7 is a heating IC (Integrated Circuit) that generates heat through the heating portion 71.

[0028] The temperature sensor 72 is connected between the power supply and the ground via the connection pads 401 and 402, detects the temperature of the integrated circuit device 7, and outputs a temperature detection signal TS of a voltage level corresponding to the detected temperature. Since the integrated circuit device 7 has a built-in heating portion 71, the temperature sensor 72 detects the internal temperature of the integrated circuit device 7 that changes according to the heat generated by the heating portion 71. The temperature sensor 72 may be, for example, a sensor that utilizes the temperature dependency of the forward voltage of the PN junction of a diode. The temperature detection signal TS output from the temperature sensor 72 is output to the outside of the integrated circuit device 7 via the connection pad 404.

[0029] Figure 2 2 is a diagram showing a circuit configuration of the heating unit 71 in the first embodiment. Figure 2As shown, the heat generating unit 71 includes a transistor 75-1. The transistor 75-1 is an N-channel MOS (Metal-Oxide-Semiconductor) transistor having a gate G, a drain D, and a source S. The gate G of the transistor 75-1 is input with a temperature control signal TC, the drain D is electrically connected to the connection pad 401, and the source S is electrically connected to the connection pad 402. In fact, a parasitic resistor RD-1 is formed between the drain D of the transistor 75-1 and the connection pad 401, and a parasitic resistor RS-1 is formed between the source S of the transistor 75-1 and the connection pad 402. The parasitic resistors RD-1 and RS-1 are formed by the resistance of each wiring layer, the resistance of the N+ diffusion layer, and the like.

[0030] like Figure 2 As shown, the heat generating unit 71 may further include transistors 75-2 to 75-N. N is an integer greater than or equal to 2.

[0031] For each integer i greater than or equal to 2 and less than or equal to N, the transistor 75-i is an N-channel MOS transistor having a gate G, a drain D, and a source S. The temperature control signal TC is input to the gate G of the transistor 75-i, the drain D is electrically connected to the connection pad 401, and the source S is electrically connected to the connection pad 402. In fact, a parasitic resistance RD-i is formed between the drain D of the transistor 75-i and the connection pad 401, and a parasitic resistance RS-i is formed between the source S of the transistor 75-i and the connection pad 402. The parasitic resistances RD-i and RS-i are formed by the resistance of each wiring layer, the resistance of the N+ diffusion layer, and the like.

[0032] That is, the heat generating unit 71 may be configured such that N transistors 75 - 1 to 75 -N are connected in parallel between the connection pad 401 and the connection pad 402 , and the temperature control signal TC is commonly input to the gates G of the transistors 75 - 1 to 75 -N.

[0033] The transistors 75-1 to 75-N are N-channel MOS transistors, respectively. Therefore, the higher the voltage level of the temperature control signal TC input to the gate G, the smaller the on-resistance and the larger the drain current. The power consumption of each of the transistors 75-1 to 75-N is represented by the product of the square of the drain current and the on-resistance, and is released as heat. Therefore, the higher the voltage level of the temperature control signal TC, the larger the heat generated by each of the transistors 75-1 to 75-N.

[0034] However, when the parasitic resistances RD-1 to RD-N and RS-1 to RS-N are large, the drain current of the transistors 75-1 to 75-N becomes small, and the heat generated by the heat generating portion 71 including the transistors 75-1 to 75-N decreases. Therefore, in this embodiment, by studying the layout of the integrated circuit device 7, the parasitic resistances RD-1 to RD-N and RS-1 to RS-N are reduced, and the heat generation efficiency of the heat generating portion 71 is improved.

[0035] Figure 3 is a plan view showing an example of the layout of the integrated circuit device 7. Figure 4 is a diagram showing the detailed layout of the heat generating unit 71. Figure 4 In FIG. 4 , the connection plates 401 and 402 are also shown by dotted lines. Figure 5 yes Figure 3 The area A1 of the integrated circuit device 7 is shown in FIG. Figure 3 , Figure 4 as well as Figure 5 In order to determine the direction of observation, three mutually orthogonal directions, namely, the X direction, the Y direction, and the Z direction, are shown. Figure 4 and Figure 5 , exemplified Figure 2 The case where the integer N in is 16, that is, the case where the heat generating unit 71 includes 16 transistors 75 - 1 to 75 - 16.

[0036] like Figure 3 As shown, the integrated circuit device 7 is rectangular in a plan view, and has a first side E1 as a short side, a second side E2 as a short side opposite to the first side E1, a third side E3 as a long side, and a fourth side E4 as a long side opposite to the third side E3. The first side E1 and the second side E2 are parallel to the Y axis, and the third side E3 and the fourth side E4 are parallel to the X axis.

[0037] The integrated circuit device 7 has a semiconductor substrate 400, and various elements and wirings are stacked on the semiconductor substrate 400. In the present embodiment, the semiconductor substrate 400 is an N-type semiconductor substrate formed by mixing impurities such as phosphorus (P) into a silicon substrate. Alternatively, the semiconductor substrate 400 is rectangular, and the four sides of the semiconductor substrate 400 correspond to the first side E1, the second side E2, the third side E3, and the fourth side E4 of the integrated circuit device 7.

[0038] like Figure 3 As shown, in the second direction intersecting the first direction which is the length direction of the gate G, drain D and source S of the transistor 75-1, one of the connection pads 401 and 402 is arranged in parallel with the connection pad 404. In addition, in the second direction, the other of the connection pads 401 and 402 is arranged in parallel with the connection pad 403. Figure 3 In the figure, the first direction is the Y direction, the second direction is the X direction, and in the second direction, the connection pads 401 and 404 are arranged in a row, and the connection pads 402 and 403 are arranged in a row. However, it is also possible that in the second direction, the connection pads 402 and 404 are arranged in a row, and the connection pads 401 and 403 are arranged in a row.

[0039] like Figure 3 and Figure 4 As shown, in the second direction, the temperature sensor 72, the connection pad 404, and the transistors 75-1 to 75-16 included in the heat generating portion 71 are arranged in this order.

[0040] like Figure 3 As shown in FIG. 1 , the temperature sensor 72 is disposed at a position closer to the first side E1 than the second side E2. Specifically, the temperature sensor 72 is disposed along the first side E1 and the third side E3. Figure 3 and Figure 4 As shown, the transistors 75 - 1 to 75 - 16 included in the heat generating portion 71 are arranged at positions closer to the second side E2 than to the first side E1 .

[0041] Furthermore, an electrostatic protection circuit 73 for the lands 401 and 402 is disposed between the land 401 and the land 404 , and an electrostatic protection circuit 74 for the lands 403 and 404 is disposed between the land 403 and the first side E1 .

[0042] In addition, if Figure 3 As shown, the heat generating portion 71 is disposed in the region A1 , and a portion of the heat generating portion 71 overlaps with the connection land 401 , and another portion of the heat generating portion 71 overlaps with the connection land 402 in a plan view.

[0043] like Figure 4 and Figure 5 As shown, the connection pads 401 and 402 are arranged along the length direction of the gate G, drain D and source S of the transistor 75-1, that is, the first direction. For example, the first direction may also be the Y direction. Figure 4 As shown, the transistors 75-1 to 75-16 are arranged side by side in a second direction intersecting the first direction. For example, the second direction may be the X direction.

[0044] like Figure 5 As shown, in the region A1, a P-type well 410 is formed in the semiconductor substrate 400, and transistors 75-1 to 75-16 are formed in the well 410. The gates G of the transistors 75-1 to 75-16 are formed in the polysilicon layer, and the drains D and sources S of the transistors 75-1 to 75-16 are formed in the N+ diffusion layer. The gates G of the transistors 75-1 to 75-16 are electrically connected to each other through polysilicon wiring or metal wiring (not shown).

[0045] like Figure 4 as well as Figure 5As shown, the drain D of transistor 75-1 is formed in the same region as the drain D of transistor 75-2. Similarly, the drain D of transistor 75-3 is formed in the same region as the drain D of transistor 75-4. Similarly, the drain D of transistor 75-5 is formed in the same region as the drain D of transistor 75-6. Similarly, the drain D of transistor 75-7 is formed in the same region as the drain D of transistor 75-8. Similarly, the drain D of transistor 75-9 is formed in the same region as the drain D of transistor 75-10. Similarly, the drain D of transistor 75-11 is formed in the same region as the drain D of transistor 75-12. Similarly, the drain D of transistor 75-13 is formed in the same region as the drain D of transistor 75-14. Similarly, the drain D of transistor 75-15 is formed in the same region as the drain D of transistor 75-16.

[0046] In addition, the source S of the transistor 75-2 is formed in the same region as the source S of the transistor 75-3. Similarly, the source S of the transistor 75-4 is formed in the same region as the source S of the transistor 75-5. Similarly, the source S of the transistor 75-6 is formed in the same region as the source S of the transistor 75-7. Similarly, the source S of the transistor 75-8 is formed in the same region as the source S of the transistor 75-9. Similarly, the source S of the transistor 75-10 is formed in the same region as the source S of the transistor 75-11. Similarly, the source S of the transistor 75-12 is formed in the same region as the source S of the transistor 75-13. Similarly, the source S of the transistor 75-14 is formed in the same region as the source S of the transistor 75-15.

[0047] like Figure 4 As shown, when the integrated circuit device 7 is viewed from above, the drain D of the transistor 75-1 overlaps with the connection pad 401, and the source S of the transistor 75-1 overlaps with the connection pad 402. Specifically, when the integrated circuit device 7 is viewed from above, the gate G, the drain D, and the source S of the transistor 75-1 overlap with the connection pad 401 and the connection pad 402. When the integrated circuit device 7 is viewed from above, a plurality of via wirings (via wires) 421 that electrically connect the connection pad 401 and the drain D of the transistor 75-1 are formed in the region where the connection pad 401 overlaps with the drain D of the transistor 75-1. In addition, when the integrated circuit device 7 is viewed from above, a plurality of via wirings 422 that electrically connect the connection pad 402 and the source S of the transistor 75-1 are formed in the region where the connection pad 402 overlaps with the source S of the transistor 75-1.

[0048] Similarly, for each integer i greater than or equal to 2 and less than or equal to 16, when the integrated circuit device 7 is viewed from above, the drain D of the transistor 75-i overlaps with the connection pad 401, and the source S of the transistor 75-i overlaps with the connection pad 402. Specifically, when the integrated circuit device 7 is viewed from above, the gate G, drain D, and source S of the transistor 75-i overlap with the connection pad 401 and the connection pad 402. When the integrated circuit device 7 is viewed from above, a plurality of through-hole wirings 421 that electrically connect the connection pad 401 and the drain D of the transistor 75-i are formed in the region where the connection pad 401 overlaps with the drain D of the transistor 75-i. In addition, when the integrated circuit device 7 is viewed from above, a plurality of through-hole wirings 422 that electrically connect the connection pad 402 and the source S of the transistor 75-i are formed in the region where the connection pad 402 overlaps with the source S of the transistor 75-i.

[0049] like Figure 5 As shown, the connection pads 401 and 402 are formed, for example, by metal wirings of the third wiring layer which is the uppermost layer. In addition, for example, each metal wiring 411 of the second wiring layer is formed so as to overlap with each drain D of the transistors 75-1 to 75-16 when viewed from above. Moreover, for each integer j which is greater than or equal to 1 and less than or equal to 16, a plurality of via wirings 431 are formed so as to connect the drain D of the transistor 75-j and the metal wiring 411, and a plurality of via wirings 421 are formed so as to connect the metal wiring 411 and the connection pad 401. Therefore, when the integrated circuit device 7 is viewed from above, a plurality of via wirings 421 and a part of a plurality of via wirings 431 are formed in the region where the connection pad 401 overlaps with the drain D of the transistor 75-i.

[0050] In addition, if Figure 5 As shown, for example, each metal wiring 412 of the second wiring layer is formed so as to overlap with each source S of the transistors 75-1 to 75-16 in a plan view. Furthermore, for each integer j greater than 1 and less than N, a plurality of via wirings 432 are formed so as to connect the source S of the transistor 75-i and the metal wiring 412, and a plurality of via wirings 422 are formed so as to connect the metal wiring 412 and the connection pad 402. Therefore, when the integrated circuit device 7 is viewed from above, a plurality of via wirings 422 and a portion of a plurality of via wirings 432 are formed in a region where the connection pad 402 overlaps with the source S of the transistor 75-i.

[0051] In such Figure 3 , Figure 4 and Figure 5In the integrated circuit device 7 constructed in this way, the current flows from the connection pad 401 to the drains D of the transistors 75-1 to 75-16 through the wiring path formed by the plurality of through-hole wirings 421, the metal wiring 411 and the plurality of through-hole wirings 431. The wiring path through which the current flows is very short, so the parasitic resistance of the wiring path is very small. In addition, the current flows from the drains D of the transistors 75-1 to 75-16 to the sources S along their short sides, so the parasitic resistance of the drains D of the transistors 75-1 to 75-16 and the parasitic resistance of the sources S are also small. Furthermore, the current flows from the sources S of the transistors 75-1 to 75-16 to the connection pad 402 through the wiring path formed by the plurality of through-hole wirings 432, the metal wiring 412 and the plurality of through-hole wirings 422. The wiring path through which the current flows is very short, so the parasitic resistance of the wiring path is also very small. Therefore, Figure 2 The parasitic resistances RD-1 to RD-16 and RS-1 to RS-16 shown are reduced, so the current flowing through the transistors 75-1 to 75-16 increases, and the heat generation efficiency of the heat generating portion 71 improves.

[0052] In the first embodiment, the connection pad 401 is an example of the "first connection pad", the connection pad 402 is an example of the "second connection pad", and the connection pad 404 is an example of the "third connection pad". In addition, the transistor 75-1 is an example of the "first transistor", and the gate G, drain D, and source S of the transistor 75-1 are examples of the "first gate", "first drain", and "first source", respectively. In addition, the transistors 75-2 to 75-N are examples of the "second to N-th transistors", and for each integer i greater than 2 and less than N, the gate G, drain D, and source S of the i-th transistor 75-i are examples of the "i-th gate", "i-th drain", and "i-th source", respectively. In addition, the plurality of through-hole wirings 421 electrically connecting the connection pad 401 to the drain D of the transistor 75-1 are each an example of the “first drain connection through-hole wiring”, and the plurality of through-hole wirings 422 electrically connecting the connection pad 402 to the source S of the transistor 75-1 are each an example of the “first source connection through-hole wiring”. In addition, for each integer i greater than or equal to 2 and less than or equal to N, the plurality of through-hole wirings 421 electrically connecting the connection pad 401 to the drain D of the i-th transistor 75-i are each an example of the “i-th drain connection through-hole wiring”, and the plurality of through-hole wirings 422 electrically connecting the connection pad 402 to the source S of the i-th transistor 75-i are each an example of the “i-th source connection through-hole wiring”.

[0053] As described above, according to the integrated circuit device 7 of the first embodiment, the current flows from the connection pad 401 to the drain D of the transistors 75-1 to 75-N via the plurality of via wirings 421, the plurality of metal wirings 411, and the plurality of via wirings 431 in a very short path. The current flows from the drain D to the source S of the transistors 75-1 to 75-N in a relatively short path, and flows from the source S of the transistors 75-1 to 75-N in a very short path via the plurality of via wirings 432, the plurality of metal wirings 412, and the plurality of via wirings 422 to the connection pad 402. Therefore, the path of the current flowing from the connection pad 401 to the connection pad 402 is short. Moreover, since the current flows between the connection pads 401 and 402 and the transistors 75-1 to 75-N in a direction orthogonal to the connection pads 401 and 402, the cross-sectional area of ​​the wiring through which the current flows becomes larger. Therefore, according to the integrated circuit device 7 of the first embodiment, the parasitic resistance between the connection pads 401 and 402 and the transistors 75 - 1 to 75 -N is reduced, and the possibility of a decrease in the current flowing through the transistors 75 - 1 to 75 -N due to the parasitic resistance can be reduced.

[0054] Furthermore, according to the integrated circuit device 7 of the first embodiment, since the cross-sectional area of ​​the wiring through which current flows between the connection pads 401 and 402 and the transistors 75 - 1 to 75 -N is large, it is also resistant to electromigration.

[0055] Furthermore, according to the integrated circuit device 7 of the first embodiment, the transistors 75-1 to 75-N having a large drain D and source S can be arranged in the region overlapping with the lands 401 and 402 in a plan view, so that the current flowing through the transistors 75-1 to 75-N can be increased. Therefore, a small integrated circuit device 7 that can flow a sufficient current can be realized.

[0056] In addition, according to the integrated circuit device 7 of the first embodiment, the connection pads 401 and 402 are arranged along the length direction of the gate G of the transistor 75-1, that is, the first direction, and in the second direction intersecting the first direction, the connection pads 401 and 402 and the connection pads 404 and 403 are arranged respectively. Therefore, no dead space is generated between the connection pads 401 and 404 and the third side E3, and between the connection pads 402 and 403 and the fourth side E4, and bonding of the connection pads 401, 402, 403, and 404 can be easily performed.

[0057] In the integrated circuit device 7 of the first embodiment, the temperature sensor is arranged at a position close to the first side E1, and the transistors 75-1 to 75-N are arranged at a position close to the second side E2. In the second direction, the temperature sensor 72, the connection pad 404, the electrostatic protection circuit 73, and the transistors 75-1 to 75-N are arranged in this order. That is, since the temperature sensor 72 is arranged at a place far away from the transistors 75-1 to 75-N, the temperature detected by the temperature sensor 72 can be prevented from changing sharply due to the change in the heat generated by the transistors 75-1 to 75-N.

[0058] 1-2. Second Embodiment

[0059] Hereinafter, regarding the second embodiment, the same reference numerals are used for the same structures as those in the first embodiment, and the same description as that in the first embodiment is omitted or simplified, and the contents different from the first embodiment are mainly described.

[0060] The functional block diagram of the integrated circuit device 7 of the second embodiment is similar to Figure 1 The same, therefore, their illustration and description are omitted.

[0061] Figure 6 2 is a diagram showing a circuit configuration of the heating unit 71 in the second embodiment. Figure 6 As shown, the heat generating unit 71 includes a transistor 76-1. The transistor 76-1 is a P-channel MOS transistor having a gate G, a drain D, and a source S. The gate G of the transistor 76-1 is input with a temperature control signal TC, the drain D is electrically connected to the connection pad 402, and the source S is electrically connected to the connection pad 401. In fact, a parasitic resistor RD-1 is formed between the drain D of the transistor 76-1 and the connection pad 402, and a parasitic resistor RS-1 is formed between the source S of the transistor 76-1 and the connection pad 401. The parasitic resistors RD-1 and RS-1 are formed by the resistance of each wiring layer, the resistance of the P+ diffusion layer, and the like.

[0062] like Figure 6 As shown, the heat generating unit 71 may further include transistors 76-2 to 76-N. N is an integer greater than or equal to 2.

[0063] For each integer i greater than or equal to 2 and less than or equal to N, the transistor 76-i is a P-channel MOS transistor having a gate G, a drain D, and a source S. The gate G of the transistor 76-i is input with a temperature control signal TC, the drain D is electrically connected to the connection pad 402, and the source S is electrically connected to the connection pad 401. In fact, a parasitic resistance RD-i is formed between the drain D of the transistor 76-i and the connection pad 402, and a parasitic resistance RS-i is formed between the source S of the transistor 76-i and the connection pad 401. The parasitic resistances RD-i and RS-i are formed by the resistances of each wiring layer, the resistance of the P+ diffusion layer, and the like.

[0064] That is, the heat generating unit 71 may be configured such that N transistors 76 - 1 to 76 -N are connected in parallel between the connection pad 401 and the connection pad 402 , and the temperature control signal TC is commonly input to the gates G of the transistors 76 - 1 to 76 -N.

[0065] Each of the transistors 76-1 to 76-N is a P-channel MOS transistor. Therefore, the lower the voltage level of the temperature control signal TC input to the gate G, the smaller the on-resistance and the larger the drain current. The power consumption of each of the transistors 76-1 to 76-N is represented by the product of the square of the drain current and the on-resistance, and is released as heat. Therefore, the lower the voltage level of the temperature control signal TC, the larger the heat generated by each of the transistors 76-1 to 76-N.

[0066] However, when the parasitic resistances RD-1 to RD-N and RS-1 to RS-N are large, the drain current of the transistors 76-1 to 76-N becomes small, and the heat generated by the heat generating portion 71 including the transistors 76-1 to 76-N decreases. Therefore, in this embodiment, by studying the layout of the integrated circuit device 7, the parasitic resistances RD-1 to RD-N and RS-1 to RS-N are reduced, and the heat generation efficiency of the heat generating portion 71 is improved.

[0067] A plan view showing an example of the layout of the integrated circuit device 7 according to the second embodiment Figure 3 The same, therefore, their illustration and description are omitted. Figure 7 FIG. 2 is a diagram showing a detailed layout of the heat generating section 71 in the second embodiment. Figure 7 In FIG. 4 , the connection plates 401 and 402 are also shown by dotted lines. Figure 8 yes Figure 3 The area A1 of the integrated circuit device 7 is shown in FIG. Figure 3 , Figure 7 as well as Figure 8 In order to determine the direction of observation, three mutually orthogonal directions, namely, the X direction, the Y direction, and the Z direction, are shown. Figure 7 and Figure 8 , exemplified Figure 6 The case where the integer N in is 16, that is, the case where the heat generating unit 71 includes 16 transistors 76 - 1 to 76 - 16.

[0068] like Figure 3 and Figure 7 As shown, in the second direction intersecting the first direction which is the length direction of the gate G, drain D and source S of the transistor 76-1, one of the connection pads 401 and 402 is arranged in parallel with the connection pad 404. In addition, in the second direction, the other of the connection pads 401 and 402 is arranged in parallel with the connection pad 403. Figure 3In the figure, the first direction is the Y direction, the second direction is the X direction, and in the second direction, the connection pads 401 and 404 are arranged in a row, and the connection pads 402 and 403 are arranged in a row. However, it is also possible that in the second direction, the connection pads 402 and 404 are arranged in a row, and the connection pads 401 and 403 are arranged in a row.

[0069] like Figure 3 and Figure 7 As shown, in the second direction, the temperature sensor 72, the connection pad 404, and the transistors 76-1 to 76-16 included in the heat generating portion 71 are arranged in this order.

[0070] like Figure 3 and Figure 7 As shown, the transistors 76 - 1 to 76 - 16 included in the heat generating portion 71 are arranged at positions closer to the second side E2 than to the first side E1 .

[0071] like Figure 7 and Figure 8 As shown, the connection pads 401 and 402 are arranged along the length direction of the gate G, drain D and source S of the transistor 76-1, that is, the first direction. For example, the first direction may also be the Y direction. Figure 7 As shown, the transistors 76-1 to 76-16 are arranged side by side in a second direction intersecting the first direction. For example, the second direction may be the X direction.

[0072] like Figure 8 As shown, in region A1, transistors 76-1 to 76-16 are formed in semiconductor substrate 400. Gates G of transistors 76-1 to 76-16 are formed in a polysilicon layer, and drains D and sources S of transistors 76-1 to 76-16 are formed in a P+ diffusion layer. Gates G of transistors 76-1 to 76-16 are electrically connected to each other through polysilicon wiring or metal wiring (not shown).

[0073] like Figure 7 as well as Figure 8As shown, the source S of transistor 76-1 is formed in the same region as the source S of transistor 76-2. Similarly, the source S of transistor 76-3 is formed in the same region as the source S of transistor 76-4. Similarly, the source S of transistor 76-5 is formed in the same region as the source S of transistor 76-6. Similarly, the source S of transistor 76-7 is formed in the same region as the source S of transistor 76-8. Similarly, the source S of transistor 76-9 is formed in the same region as the source S of transistor 76-10. Similarly, the source S of transistor 76-11 is formed in the same region as the source S of transistor 76-12. Similarly, the source S of transistor 76-13 is formed in the same region as the source S of transistor 76-14. Similarly, the source S of transistor 76-15 is formed in the same region as the source S of transistor 76-16.

[0074] In addition, the drain D of the transistor 76-2 and the drain D of the transistor 76-3 are formed in the same region. Similarly, the drain D of the transistor 76-4 and the drain D of the transistor 76-5 are formed in the same region. Similarly, the drain D of the transistor 76-6 and the drain D of the transistor 76-7 are formed in the same region. Similarly, the drain D of the transistor 76-8 and the drain D of the transistor 76-9 are formed in the same region. Similarly, the drain D of the transistor 76-10 and the drain D of the transistor 76-11 are formed in the same region. Similarly, the drain D of the transistor 76-12 and the drain D of the transistor 76-13 are formed in the same region. Similarly, the drain D of the transistor 76-14 and the drain D of the transistor 76-15 are formed in the same region.

[0075] like Figure 7 As shown, when the integrated circuit device 7 is viewed from above, the drain D of the transistor 76-1 overlaps with the connection pad 402, and the source S of the transistor 76-1 overlaps with the connection pad 401. Specifically, when the integrated circuit device 7 is viewed from above, the gate G, the drain D, and the source S of the transistor 76-1 overlap with the connection pad 402 and the connection pad 401. When the integrated circuit device 7 is viewed from above, a plurality of through-hole wirings 422 that electrically connect the connection pad 402 and the drain D of the transistor 76-1 are formed in the region where the connection pad 402 overlaps with the drain D of the transistor 76-1. In addition, when the integrated circuit device 7 is viewed from above, a plurality of through-hole wirings 421 that electrically connect the connection pad 401 and the source S of the transistor 76-1 are formed in the region where the connection pad 401 overlaps with the source S of the transistor 76-1.

[0076] Similarly, for each integer i greater than or equal to 2 and less than or equal to 16, when viewed from above, the drain D of the transistor 76-i overlaps with the connection pad 402, and the source S of the transistor 76-i overlaps with the connection pad 401. Specifically, when the integrated circuit device 7 is viewed from above, the gate G, drain D, and source S of the transistor 76-i overlap with the connection pad 402 and the connection pad 401. When the integrated circuit device 7 is viewed from above, a plurality of through-hole wirings 422 that electrically connect the connection pad 402 and the drain D of the transistor 76-i are formed in the region where the connection pad 402 overlaps with the drain D of the transistor 76-i. In addition, when the integrated circuit device 7 is viewed from above, a plurality of through-hole wirings 421 that electrically connect the connection pad 401 and the source S of the transistor 76-i are formed in the region where the connection pad 401 overlaps with the source S of the transistor 76-i.

[0077] like Figure 8 As shown, for example, each metal wiring 411 of the second wiring layer is formed so as to overlap with each source S of the transistors 76-1 to 76-16 in a plan view. Furthermore, for each integer j greater than 1 and less than N, a plurality of via wirings 431 are formed so as to connect the source S of the transistor 76-i and the metal wiring 411, and a plurality of via wirings 421 are formed so as to connect the metal wiring 411 and the connection pad 401. Therefore, when the integrated circuit device 7 is viewed from above, a plurality of via wirings 421 and a part of a plurality of via wirings 431 are formed in a region where the connection pad 401 overlaps with the source S of the transistor 75-i.

[0078] In addition, if Figure 8 As shown, the connection pads 401 and 402 are formed, for example, by metal wirings of the third wiring layer which is the uppermost layer. In addition, for example, each metal wiring 412 of the second wiring layer is formed so as to overlap with each drain D of the transistors 76-1 to 76-16 when viewed from above. Moreover, for each integer j which is greater than or equal to 1 and less than or equal to 16, a plurality of via wirings 432 are formed so as to connect the drain D of the transistor 76-j and the metal wiring 412, and a plurality of via wirings 422 are formed so as to connect the metal wiring 412 and the connection pad 402. Therefore, when the integrated circuit device 7 is viewed from above, a plurality of via wirings 422 and a portion of a plurality of via wirings 432 are formed in the region where the connection pad 402 overlaps with the drain D of the transistor 76-i.

[0079] In such Figure 3 , Figure 7 and Figure 8In the integrated circuit device 7 constructed in this way, the current flows from the connection pad 401 to the source S of the transistors 76-1 to 76-16 through the wiring path formed by the multiple through-hole wirings 421, the metal wiring 411 and the multiple through-hole wirings 431. The wiring path through which the current flows is very short, so the parasitic resistance of the wiring path is very small. In addition, the current flows from the source S of the transistors 76-1 to 76-16 to the drain D along their short sides, so the parasitic resistance of the source S of the transistors 76-1 to 76-16 and the parasitic resistance of the drain D are also small. Furthermore, the current flows from the drain D of the transistors 76-1 to 76-16 to the connection pad 402 through the wiring path formed by the multiple through-hole wirings 432, the metal wiring 412 and the multiple through-hole wirings 422. The wiring path through which the current flows is very short, so the parasitic resistance of the wiring path is also very small. Therefore, Figure 6 The parasitic resistances RS- 1 to RS- 16 and RD- 1 to RD- 16 shown are reduced, so that the current flowing through the transistors 76 - 1 to 76 - 16 increases, and the heat generation efficiency of the heat generating portion 71 improves.

[0080] In the second embodiment, the connection pad 402 is an example of the "first connection pad", the connection pad 401 is an example of the "second connection pad", and the connection pad 404 is an example of the "third connection pad". In addition, the transistor 76-1 is an example of the "first transistor", and the gate G, drain D, and source S of the transistor 76-1 are examples of the "first gate", "first drain", and "first source", respectively. In addition, the transistors 76-2 to 76-N are examples of the "second to Nth transistors", and for each integer i greater than 2 and less than N, the gate G, drain D, and source S of the i-th transistor 76-i are examples of the "i-th gate", "i-th drain", and "i-th source", respectively. In addition, the plurality of through-hole wirings 422 electrically connecting the connection pad 402 to the drain D of the transistor 76-1 are each an example of the “first drain connection through-hole wiring”, and the plurality of through-hole wirings 421 electrically connecting the connection pad 401 to the source S of the transistor 76-1 are each an example of the “first source connection through-hole wiring”. In addition, for each integer i greater than or equal to 2 and less than or equal to N, the plurality of through-hole wirings 422 electrically connecting the connection pad 402 to the drain D of the i-th transistor 76-i are each an example of the “i-th drain connection through-hole wiring”, and the plurality of through-hole wirings 421 electrically connecting the connection pad 401 to the source S of the i-th transistor 76-i are each an example of the “i-th source connection through-hole wiring”.

[0081] As described above, according to the integrated circuit device 7 of the second embodiment, the current flows from the connection pad 401 to the source S of the transistors 76-1 to 76-N via the plurality of via wirings 421, the plurality of metal wirings 411, and the plurality of via wirings 431 in a very short path. The current flows from the source S to the drain D of the transistors 76-1 to 76-N in a relatively short path, and then flows from the drain D of the transistors 76-1 to 76-N in a very short path via the plurality of via wirings 432, the plurality of metal wirings 412, and the plurality of via wirings 422 to the connection pad 402. Therefore, the path for the current to flow from the connection pad 401 to the connection pad 402 is short. Moreover, since the current flows between the connection pads 401 and 402 and the transistors 76-1 to 76-N in a direction orthogonal to the connection pads 401 and 402, the cross-sectional area of ​​the wiring through which the current flows becomes larger. Therefore, according to the integrated circuit device 7 of the second embodiment, the parasitic resistance between the connection pads 401 and 402 and the transistors 76 - 1 to 76 -N is reduced, and the possibility of a decrease in the current flowing through the transistors 76 - 1 to 76 -N due to the parasitic resistance can be reduced.

[0082] Furthermore, according to the integrated circuit device 7 of the second embodiment, since the cross-sectional area of ​​the wiring through which current flows between the connection pads 401 and 402 and the transistors 76 - 1 to 76 -N is large, it is also resistant to electromigration.

[0083] Furthermore, according to the integrated circuit device 7 of the second embodiment, the transistors 76-1 to 76-N having a large source S and a drain D can be arranged in the region overlapping with the lands 401 and 402 in a plan view, so that the current flowing through the transistors 76-1 to 76-N can be increased. Therefore, a small integrated circuit device 7 that can flow a sufficient current can be realized.

[0084] In addition, according to the integrated circuit device 7 of the second embodiment, the connection pads 401 and 402 are arranged along the length direction of the gate G of the transistor 76-1, that is, the first direction, and in the second direction intersecting the first direction, the connection pads 401 and 402 and the connection pads 404 and 403 are arranged respectively. Therefore, no invalid space is generated between the connection pads 401 and 404 and the third side E3, and between the connection pads 402 and 403 and the fourth side E4, and the connection pads 401, 402, 403, and 404 can be easily joined.

[0085] In the integrated circuit device 7 of the second embodiment, the temperature sensor is arranged at a position close to the first side E1, and the transistors 76-1 to 76-N are arranged at a position close to the second side E2. In the second direction, the temperature sensor 72, the connection pad 404, the electrostatic protection circuit 73 and the transistors 76-1 to 76-N are arranged in sequence. That is, since the temperature sensor 72 is arranged at a position away from the transistors 76-1 to 76-N, the temperature detected by the temperature sensor 72 can be prevented from changing sharply due to the change in the heat generated by the transistors 76-1 to 76-N.

[0086] 2. Oscillator

[0087] 2-1. Oscillator structure

[0088] Fig. 9 It is a cross-sectional view showing the oscillator according to the present embodiment. Fig.10 This is a top view of the oscillator as viewed from the upper surface side. Fig.11 This is a cross-sectional view showing the inner package of the oscillator and its interior. Fig.12 It is a cross-sectional view showing a voltage controlled oscillator included in the oscillator.

[0089] Fig. 9 and Fig.10 The oscillator 1 shown is an oven-controlled quartz oscillator, and includes an outer package 2, an inner package 3, a control IC 4, and a voltage-controlled oscillator 5. The inner package 3, the control IC 4, and the voltage-controlled oscillator 5 are housed in the outer package 2.

[0090] like Fig. 9 As shown, the outer package 2 has an outer base 21 and an outer cover 22. The outer base 21 has: a substrate 27; a frame-shaped wall portion 28, which is erected from the edge of the upper surface of the substrate 27 toward the upper side; and a frame-shaped leg portion 29, which is erected from the edge of the lower surface of the substrate 27 toward the lower side. An upper side recess 211 opened on the upper surface 21a of the outer base 21 as a storage space S1 is formed by the upper surface of the substrate 27 and the wall portion 28, and a lower side recess 212 opened on the lower surface 21b of the outer base 21 as a storage space S2 is formed by the lower surface of the substrate 27 and the leg portion 29. Therefore, the outer base 21 is substantially H-shaped when viewed in section.

[0091] The upper recess 211 includes a first upper recess 211a opened on the upper surface 21a, a second upper recess 211b opened on the bottom of the first upper recess 211a and having an opening smaller than the first upper recess 211a, and a third upper recess 211c opened on the bottom of the second upper recess 211b and having an opening smaller than the second upper recess 211b. The control IC 4 is arranged on the bottom of the first upper recess 211a, and the inner package 3 is arranged on the bottom of the third upper recess 211c.

[0092] The outer cover 22 is bonded to the upper surface 21a of the outer base 21 via a sealing member 23 such as a sealing ring or low-melting-point glass in a manner that blocks the opening of the upper recess 211. As a result, the upper recess 211 as the storage space S1 is hermetically sealed. In addition, the storage space S1 stores an integrated circuit device 7, a vibration element 6, and an oscillation IC 8 as a heat generating IC, and also stores a control IC 4. Specifically, as described later, the integrated circuit device 7, the vibration element 6, and the oscillation IC 8 are stored in the inner package 3, and the inner package 3 and the control IC 4 are stored in the storage space S1. On the other hand, the opening of the lower recess 212 as the storage space S1 is not sealed, and is open to the outside of the outer package 2. In addition, the voltage-controlled oscillator 5 is stored in the storage space S2.

[0093] The outer base 21 is provided with: a plurality of internal terminals 241 disposed on the bottom surface of the first upper recess 211a; a plurality of internal terminals 242 disposed on the bottom surface of the second upper recess 211b; a plurality of internal terminals 243 disposed on the bottom surface of the lower recess 212; and a plurality of external terminals 244 disposed on the lower surface 21b, i.e., the top surface of the leg 29. Each internal terminal 241 is electrically connected to the control IC 4 via a bonding wire BW1, each internal terminal 242 is electrically connected to the inner package 3 via a bonding wire BW2, and each internal terminal 243 is electrically connected to the voltage controlled oscillator 5 via a conductive bonding member B1.

[0094] These terminals 241, 242, 243, and 244 are appropriately electrically connected via the internal wiring 25 formed in the outer base 21, and the control IC 4, the inner package 3, the voltage-controlled oscillator 5, and the external terminal 244 are electrically connected. The internal wiring 25 is connected to the external terminal 244 through the inside of the foot 29. In addition, the connection with the external device not shown is made at the external terminal 244. A side terminal 245 connected to the external terminal 244 is arranged on the side of the foot 29. The side terminal 245 is a castellation structure. Therefore, the solder H infiltrates and spreads in the side terminal 245 to form a solder foot, and the mechanical and electrical connection with the external device becomes stronger. However, it is not limited to this, for example, the side terminal 245 can also be omitted.

[0095] like Fig.11 As shown, the inner package 3 has an inner base 31 and an inner cover 32. The inner base 31 has a recess 311 opened in a lower surface 31b.

[0096] The recess 311 includes a first recess 311a opened on the lower surface 31b, a second recess 311b opened on the bottom surface of the first recess 311a and having a smaller opening than the first recess 311a, and a third recess 311c opened on the bottom surface of the second recess 311b and having a smaller opening than the second recess 311b. The vibration element 6 is arranged on the bottom surface of the first recess 311a, and the integrated circuit device 7 and the oscillation IC 8 are arranged side by side along the X-axis direction on the bottom surface of the third recess 311c.

[0097] The inner cover 32 is bonded to the lower surface 31b of the inner base 31 via a sealing member 33 such as a sealing ring or low-melting-point glass so as to block the opening of the recess 311. As a result, the recess 311 is hermetically sealed, and a storage space S3 is formed in the inner package 3. The vibration element 6, the integrated circuit device 7, and the oscillation IC 8 are stored in the storage space S3.

[0098] Such a storage space S3 is airtight and is in a reduced pressure state, preferably a state closer to a vacuum. Thus, the viscous resistance of the storage space S3 is reduced, and the vibration characteristics of the vibration element 6 are improved. However, the atmosphere of the storage space S3 is not particularly limited.

[0099] The inner base 31 is provided with: a plurality of internal terminals 341 disposed on the bottom surface of the first recess 311a; a plurality of internal terminals 342 and 343 disposed on the bottom surface of the second recess 311b; and a plurality of external terminals 344 disposed on the upper surface 31a of the inner base 31. Each internal terminal 341 is electrically connected to the vibration element 6 via a conductive bonding member B2 and a bonding wire BW3, each internal terminal 342 is electrically connected to the integrated circuit device 7 via a bonding wire BW4, and each internal terminal 343 is electrically connected to the oscillation IC 8 via a bonding wire BW5.

[0100] The terminals 341, 342, 343, and 344 are appropriately electrically connected via internal wiring (not shown) formed in the inner package 3, and the vibration element 6, the integrated circuit device 7, the oscillation IC 8, and the external terminal 344 are electrically connected. In such an inner package 3, the inside and outside are electrically connected via the external terminal 344.

[0101] The inner package 3 as described above is fixed to the bottom surface of the third upper recess 211 c at the inner cover 32 via a bonding member B3 having a sufficiently low thermal conductivity.

[0102] like Fig.11As shown, the integrated circuit device 7 is arranged on the bottom surface of the third recess 311c with its active surface facing downward (inner cover 32 side), and is electrically connected to the plurality of internal terminals 342 via bonding wires BW4. The oscillator IC 8 is arranged on the bottom surface of the third recess 311c with its active surface facing downward (inner cover 32 side), and is electrically connected to the plurality of internal terminals 343 via bonding wires BW5.

[0103] The voltage controlled oscillator 5 is an oscillator that outputs an oscillation signal whose frequency varies according to an input voltage. Fig.12 As shown, the voltage controlled oscillator 5 includes a package 51 , and a vibration element 55 and an oscillation IC 59 housed in the package 51 .

[0104] The package 51 includes a base 52 and a cover 53. The base 52 includes a recess 521 opened on a lower surface 52b. The recess 521 includes a first recess 521a opened on the lower surface 52b, a second recess 521b opened on the bottom surface of the first recess 521a and having an opening smaller than the first recess 521a, and a third recess 521c opened on the bottom surface of the second recess 521b and having an opening smaller than the second recess 521b. In addition, a vibration element 55 is arranged on the bottom surface of the first recess 521a, and an oscillation IC 59 is arranged on the bottom surface of the third recess 521c.

[0105] The cover 53 is bonded to the lower surface 52b of the base 52 via a sealing member 54 such as a sealing ring or low-melting-point glass in a manner that blocks the opening of the recess 521. As a result, the recess 521 is hermetically sealed, and a storage space S5 is formed in the package 51. In addition, a vibration element 55 and an oscillation IC 59 are stored in the storage space S5. The storage space S5 is airtight and is in a decompressed state, preferably a state closer to a vacuum. As a result, the viscous resistance of the storage space S5 is reduced, and the vibration characteristics of the vibration element 55 are improved. However, the atmosphere of the storage space S5 is not particularly limited.

[0106] The base 52 is provided with: a plurality of internal terminals 561 disposed on the bottom surface of the first recess 521a; a plurality of internal terminals 562 disposed on the bottom surface of the second recess 521b; and a plurality of external terminals 564 disposed on the upper surface 52a of the base 52. Each internal terminal 561 is electrically connected to the vibration element 55 via a conductive bonding member B4, and each internal terminal 562 is electrically connected to the oscillation IC 59 via a bonding wire BW6. These terminals 561, 562, 564 are appropriately electrically connected via an internal wiring (not shown) formed in the base 52, and the vibration element 55, the oscillation IC 59, and the external terminal 564 are electrically connected. In such a package 51, the inside and the outside are electrically connected via the external terminal 564.

[0107] The vibration element 55 is an AT-cut quartz vibration element. However, the vibration element 55 may not be an AT-cut quartz vibration element, but may be an SC-cut quartz vibration element, a BT-cut quartz vibration element, a tuning fork-type quartz vibration element, a surface acoustic wave resonator, other piezoelectric vibration elements, a MEMS resonance element, etc.

[0108] The oscillation IC 59 is arranged on the bottom surface of the third recess 521 c with its active surface facing downward, and is electrically connected to the plurality of internal terminals 562 via bonding wires BW6 .

[0109] like Fig.12 As shown, the voltage controlled oscillator 5 is fixed to the bottom surface of the lower recessed portion 212 via a conductive bonding member B1. In addition, the external terminal 564 and the internal terminal 243 are electrically connected via the bonding member B1.

[0110] In addition, the outer package 2 is an example of a "first container", and the inner package 3 is an example of a "second container". In addition, the upper surface of the substrate 27 is an example of a "first surface", and the lower surface of the substrate 27 is an example of a "second surface". In addition, the storage space S1 is an example of a "first storage space", and the storage space S2 is an example of a "second storage space".

[0111] 2-2. Functional structure of oscillator

[0112] Fig.13 1 is a functional block diagram of the oscillator 1 of this embodiment. Fig.13 In, with Figures 9 to 12 The same components as shown in the figure are marked with the same reference numerals. Fig.13 As shown, the oscillator 1 of the present embodiment includes a control IC 4 , a voltage controlled oscillator 5 , a vibration element 6 , the integrated circuit device 7 of the above-mentioned embodiment as a heat generating IC, and an oscillation IC 8 .

[0113] The oscillation IC 8 includes an oscillation circuit 81 and a temperature sensor 82, and operates by receiving a power supply voltage VOSC from the control IC 4. The oscillation circuit 81 is a circuit that is electrically connected to both ends of the vibration element 6, amplifies the output signal of the vibration element 6, and feeds it back to the vibration element 6, thereby causing the vibration element 6 to oscillate and output an oscillation signal OSCO. For example, the oscillation circuit 81 may be an oscillation circuit using an inverter as an amplification element, or may be an oscillation circuit using a bipolar transistor as an amplification element. The oscillation signal OSCO output from the oscillation circuit 81 is input to the control IC 4.

[0114] The temperature sensor 82 is a temperature sensing element that detects temperature and outputs a temperature detection signal TS1 having a voltage level corresponding to the detected temperature. The temperature sensor 82 is built into the oscillation IC 8 and detects the temperature of the oscillation IC 8. The temperature detection signal TS1 output from the temperature sensor 82 is input to the control IC 4. The temperature sensor 82 may be, for example, a sensor that utilizes the temperature dependency of the forward voltage of the PN junction of a diode.

[0115] As described above, the integrated circuit device 7 includes a heating portion 71 and a temperature sensor 72. The temperature control signal OVC output from the control IC 4 is input to the heating portion 71 as the aforementioned temperature control signal TC. The amount of heat generated by the heating portion 71 varies according to the voltage level of the temperature control signal OVC. The greater the amount of heat generated by the heating portion 71, the higher the temperature of the vibration element 6. That is, the vibration element 6 is temperature-controlled by the integrated circuit device 7. In practice, the amount of heat generated by the heating portion 71 is controlled by the control IC 4 so that the temperature of the vibration element 6 is constant at a set temperature as a target. For example, the set temperature may be a fixed value such as 80°C, or may be arbitrarily set within a specified range such as a range above 70°C and 125°C.

[0116] As described above, the temperature sensor 72 detects the temperature of the heat generating portion 71 and outputs the temperature detection signal TS having a voltage level corresponding to the detected temperature. The temperature detection signal TS is input to the control IC 4 as the temperature detection signal TS2.

[0117] like Fig.11As shown, the vibration element 6, the integrated circuit device 7, and the oscillation IC 8 are housed in the inner package 3, and the heat generation of the integrated circuit device 7 is controlled by the control IC 4 so that the temperature of the vibration element 6 is kept constant. The integrated circuit device 7 is a heat source, and the radiant heat from the integrated circuit device 7 is transferred to the vibration element 6 and the oscillation IC 8, so that a difference occurs between the temperature of the vibration element 6 and the oscillation IC 8 and the temperature of the integrated circuit device 7. In contrast, the vibration element 6 and the oscillation IC 8 are arranged separately from the integrated circuit device 7, and when the thermal distance between the integrated circuit device 7 and the vibration element 6 and the thermal distance between the integrated circuit device 7 and the oscillation IC 8 are considered to be approximately the same, it can be said that the temperature of the oscillation IC 8 is close to the temperature of the vibration element 6. That is, the temperature detected by the temperature sensor 82 built into the oscillation IC 8 is closer to the temperature of the vibration element 6 than the temperature detected by the temperature sensor 72 built into the integrated circuit device 7. Therefore, the control IC 4 controls the heat generation of the integrated circuit device 7 based on the temperature detection signal TS1 output from the temperature sensor 82. However, depending on the configuration of the vibration element 6, the integrated circuit device 7 and the oscillation IC 8, sometimes the temperature of the integrated circuit device 7 is closer to the temperature of the vibration element 6 than the temperature of the oscillation IC 8. In this case, the control IC 4 can also control the heating of the integrated circuit device 7 based on the temperature detection signal TS2 output from the temperature sensor 72.

[0118] The control IC 4 includes a digital signal processing circuit 10, a selector 41, a temperature sensor 42, an A / D converter 43, a D / A converter 44, a fractional N-PLL circuit (FN-PLL circuit) 45, a PLL (Phase Locked Loop) circuit 46, a switch circuit 47, a power supply circuit 48, an interface circuit (I / F circuit) 49, a memory 90 and a register 94.

[0119] The power supply circuit 48 generates a power supply voltage VOSC which is a constant voltage lower than the power supply voltage VDD based on the power supply voltage VDD and the ground voltage VSS supplied from the outside of the oscillator 1. For example, the power supply circuit 48 generates the power supply voltage VOSC as a constant voltage based on the output voltage of the bandgap reference circuit. The power supply voltage VOSC is supplied to the oscillation IC 8.

[0120] The fractional-N-PLL circuit 45 receives the oscillation signal OSCO output from the oscillation IC 8 and outputs a frequency f of the oscillation signal OSCO. OSCO The frequency f is converted to the frequency corresponding to the frequency division ratio indicated by the frequency division ratio control signal DIVC. CK1The fractional N-PLL circuit 45 generates the clock signal CK1 by performing feedback control so that the phase of the oscillation signal OSCO matches the phase of the signal obtained by dividing the clock signal CK1 according to the division ratio specified by the division ratio control signal DIVC. The division ratio control signal DIVC is Δ-Σ modulated, and the division ratio specified by the division ratio control signal DIVC switches between multiple integer division ratios, which, when averaged, become a fractional division ratio. Therefore, the frequency f CK1 is the frequency f OSCO The fractional N-PLL circuit 45 can also output a frequency f according to the frequency division ratio control signal DIVC. OSCO The frequency f is different and is approximately constant regardless of the outside air temperature. CK1 The clock signal CK1.

[0121] The PLL circuit 46 receives the clock signal CK1 output from the fractional-N-PLL circuit 45 and outputs a clock signal having a frequency f that is the same as the clock signal CK1. CK1 The same frequency is the frequency f CK2 The PLL circuit 46 generates the clock signal CK2 by feedback-controlling the input voltage of the voltage-controlled oscillator 5 so that the phase of the clock signal CK1 matches the phase of the clock signal CK2 output from the voltage-controlled oscillator 5.

[0122] The frequency f of the clock signal CK1 output from the fractional-N-PLL circuit 45 is CK1 is the frequency f of the oscillation signal OSCO OSCO In contrast, the frequency f of the clock signal CK2 output from the PLL circuit 46 is larger. CK2 The frequency f of the clock signal CK1 CK1 The same as the clock signal CK1, and output from the voltage controlled oscillator 5 using the vibration element 55 with high frequency stability, the jitter is smaller than that of the clock signal CK1.

[0123] The switch circuit 47 outputs the clock signal CK which selects either the clock signal CK1 or the clock signal CK2 according to the logic level of the switch control signal SWC output from the register 94. The clock signal CK is output to the outside of the oscillator 1. The clock signal CK may be provided to the external device 100 or to a device different from the external device 100. For example, during the normal operation of the oscillator 1, the clock signal CK2 with small jitter may be selected as the clock signal CK, and when the clock signal CK1 is checked, the clock signal CK1 may be selected as the clock signal CK.

[0124] The temperature sensor 42 is a temperature sensing element that detects temperature and outputs a temperature detection signal TS3 having a voltage level corresponding to the detected temperature. The temperature sensor 42 is built into the control IC 4 and detects the temperature of the control IC 4. Fig. 9 As shown in FIG. 1 , the control IC 4 is arranged at a position close to the outer cover 22, and the distance between the vibration element 6 and the temperature sensor 42 is greater than the distance between the vibration element 6 and the temperature sensor 82 included in the oscillation IC 8. The temperature of the control IC 4 is easily affected by the temperature of the air outside the oscillator 1. Therefore, when the heat generated by the control IC 4 is substantially constant, the temperature sensor 42 can detect the temperature change of the air outside the oscillator 1. The temperature detection signal TS2 output from the temperature sensor 72 is input to the control IC 4. The temperature sensor 72 may be a sensor that utilizes the temperature dependence of the forward voltage of the PN junction of a diode, for example.

[0125] The selector 41 selects and outputs any one of the temperature detection signal TS1 output from the oscillation IC 8, the temperature detection signal TS2 output from the integrated circuit device 7, and the temperature detection signal TS3 output from the temperature sensor 42. In the present embodiment, the selector 41 selects the temperature detection signals TS1, TS2, and TS3 in a time-division manner and periodically outputs them.

[0126] The A / D converter 43 converts the temperature detection signals TS1, TS2, TS3, which are analog signals outputted from the selector 41 in time division, into digital signals, namely, temperature codes DTS1, DTS2, DTS3. The A / D converter 43 may convert the temperature detection signals TS1, TS2, TS3 into temperature codes DTS1, DTS2, DTS3 after performing voltage level conversion on the temperature detection signals TS1, TS2, TS3 by resistor voltage division or the like.

[0127] The digital signal processing circuit 10 includes a temperature control circuit 11 and a temperature compensation circuit 12 .

[0128] The temperature control circuit 11 generates a control signal for controlling the operation of the heating unit 71 built into the integrated circuit device 7. Specifically, the temperature control circuit 11 outputs a temperature control code DOVC for controlling the amount of heat generated by the heating unit 71 based on the temperature code DTS1 or the temperature code DTS2 and the temperature control data 91 stored in the non-volatile memory 90. For example, the temperature control data 91 may also include information on a set temperature as a temperature target of the vibration element 6 and information on a gain for controlling the amount of heat generated by the heating unit 71. Alternatively, in a case where the set temperature as the temperature target of the vibration element 6 varies according to the outside air temperature, the temperature control data 91 may also include information indicating the relationship between the temperature code DTS3 and the set temperature. In this case, the temperature control circuit 11 outputs the temperature control code DOVC based on the temperature code DTS1 or the temperature codes DTS2, DTS3 and the temperature control data 91.

[0129] The temperature compensation circuit 12 performs temperature compensation on the frequency of the oscillation signal OSCO generated by the oscillation circuit 81 built into the oscillation IC 8 causing the vibration element 6 to oscillate. Specifically, the temperature compensation circuit 12 outputs a frequency division ratio control signal DIVC to the fractional N-PLL circuit 45 based on the temperature code DTS3 and the temperature compensation data 92 stored in the memory 90. The frequency division ratio control signal DIVC is used to output the clock signal CK1 having a constant frequency and being independent of the temperature. For example, the temperature compensation data 92 may be table information indicating the relationship between the temperature code DTS3 and the frequency of the oscillation signal OSCO, or may be information on coefficient values ​​of each order of a mathematical formula indicating the relationship. Alternatively, the temperature compensation data 92 may be information indicating the relationship between the temperature code DTS3 and the value of the fractional frequency division ratio of the fractional N-PLL circuit 45 calculated based on the relationship between the temperature code DTS3 and the frequency of the oscillation signal OSCO.

[0130] In addition, the temperature control circuit 11 may also be a hardware circuit that performs temperature control processing for controlling the operation of the heating unit 71. Similarly, the temperature compensation circuit 12 may also be a hardware circuit that performs temperature compensation processing for temperature compensation of the frequency of the oscillation signal OSCO. Alternatively, the digital signal processing circuit 10 may also include a CPU (Central Processing Unit) and a non-volatile memory, and the CPU performs temperature control processing for controlling the operation of the heating unit 71 according to a temperature control program stored in the memory. That is, the CPU may also function as the temperature control circuit 11 by executing the temperature control program. Similarly, the CPU may also perform temperature compensation processing for temperature compensation of the frequency of the oscillation signal OSCO according to a temperature compensation program stored in the memory. That is, the CPU may also function as the temperature compensation circuit 12 by executing the temperature compensation program.

[0131] The D / A converter 44 converts the temperature control code DOVC outputted from the temperature control circuit 11 as a digital signal into a temperature control signal OVC as an analog signal. The temperature control signal OVC is supplied to the heat generating portion 71 of the integrated circuit device 7.

[0132] The interface circuit 49 is a circuit for performing data communication with the external device 100 connected to the oscillator 1. Specifically, the interface circuit 49 writes and reads data to and from the memory 90 or the register 94 according to a request from the external device 100. The interface circuit 49 may be, for example, an I 2 The interface circuit may be an interface circuit corresponding to a C (Inter-Integrated Circuit) bus, or may be an interface circuit corresponding to a SPI (Serial Peripheral Interface) bus.

[0133] In the inspection process when manufacturing the oscillator 1, the inspection device as the external device 100 may set the switch control signal SWC for causing the switch circuit 47 to select the clock signal CK1 via the interface circuit 49, and inspect the clock signal CK1. In addition, the inspection device as the external device 100 writes the temperature control data 91 and the temperature compensation data 92 to the memory 90 via the interface circuit 49. In addition, the temperature control data 91 and the temperature compensation data 92 may be set in the register 94 by the external device 100 when the oscillator 1 is started.

[0134] According to the oscillator 1 of the present embodiment described above, by using a small integrated circuit device 7 that can flow a sufficient current through the heat generating portion 71, the integrated circuit device 7, the vibration element 6, and the oscillation IC 8 can be housed in the inner package 3. Therefore, it is possible to realize a small oscillator 1 that can perform temperature control of the vibration element 6 with high accuracy and output a clock signal CK with high frequency accuracy.

[0135] The present invention is not limited to the present embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0136] The above-mentioned embodiments and modifications are merely examples, and the present invention is not limited thereto. For example, the embodiments and modifications may be appropriately combined.

[0137] The present invention includes structures that are substantially the same as the structures described in the embodiments, such as structures with the same functions, methods and results, or structures with the same purposes and effects. In addition, the present invention includes structures that replace non-essential parts of the structures described in the embodiments. In addition, the present invention includes structures that play the same role and effect as the structures described in the embodiments or structures that can achieve the same purpose. In addition, the present invention includes structures that add known technology to the structures described in the embodiments.

[0138] The following contents are derived from the above-mentioned embodiments and modifications.

[0139] One method of an integrated circuit device includes: a first connection pad, which is provided with one of a power supply voltage and a ground voltage; a second connection pad, which is provided with the other of the power supply voltage and the ground voltage; a first transistor, which has a first gate to which a temperature control signal is input, a first drain electrically connected to the first connection pad, and a first source electrically connected to the second connection pad; a through-hole wiring for connecting the first drain, which is a through-hole wiring that electrically connects the first connection pad to the first drain; and a through-hole wiring for connecting the first source, which is a through-hole wiring that electrically connects the second connection pad to the first source, and when viewed from above, the first drain overlaps with the first connection pad, and the first source overlaps with the second connection pad.

[0140] In the integrated circuit device, when a power supply voltage is provided to the first connection pad and a ground voltage is provided to the second connection pad, a current flows from the first connection pad to the drain of the first transistor via the first drain connection through-hole wiring in a very short path. The current flows from the drain of the first transistor to the source in a relatively short path, and flows from the source of the first transistor to the second connection pad via the first source connection through-hole wiring in a very short path. Therefore, the path for the current to flow from the first connection pad to the second connection pad is short. When a power supply voltage is provided to the second connection pad and a ground voltage is provided to the first connection pad, the path for the current to flow from the second connection pad to the first connection pad is also short. Moreover, since the current flows in a direction orthogonal to the first connection pad and the second connection pad through the first drain connection through-hole wiring and the first source connection through-hole wiring between the first connection pad and the second connection pad and the first transistor, the cross-sectional area of ​​the wiring for the current flow becomes larger. Therefore, according to the integrated circuit device, the parasitic resistance between the first and second lands and the first transistor is reduced, and the possibility of a decrease in the current flowing to the first transistor due to the parasitic resistance between the first and second lands and the transistor can be reduced.

[0141] Furthermore, according to this integrated circuit device, since the cross-sectional area of ​​the wiring through which current flows between the first connection pad and the second connection pad and the first transistor is large, it is also resistant to electromigration.

[0142] In one aspect of the integrated circuit device, the first gate, the first drain, and the first source may overlap with the first connection land and the second connection land in a plan view.

[0143] According to this integrated circuit device, since the first transistor having a large drain and source area can be arranged in the region overlapping the first connection pad and the second connection pad in a plan view, the current flowing through the first transistor can be increased. Therefore, a small integrated circuit device capable of sufficiently flowing current can be realized.

[0144] In one aspect of the integrated circuit device, the first connection pad and the second connection pad may be arranged side by side along a first direction which is a longitudinal direction of the first gate.

[0145] In one embodiment of the integrated circuit device, N may be an integer greater than or equal to 2, the integrated circuit device may include second to N-th transistors, second to N-th drain connection through-hole wirings, and second to N-th source connection through-hole wirings, the first to N-th transistors are arranged along a second direction intersecting the first direction, for each integer i greater than or equal to 2 and less than or equal to N, the i-th transistor has an i-th gate to which the temperature control signal is input, an i-th drain electrically connected to the first connection pad, and an i-th source electrically connected to the second connection pad, the i-th drain connection through-hole wiring is a through-hole wiring that electrically connects the first connection pad to the i-th drain, the i-th source connection through-hole wiring is a through-hole wiring that electrically connects the second connection pad to the i-th source, and when viewed from above, the i-th drain overlaps with the first connection pad, and the i-th source overlaps with the second connection pad.

[0146] According to the integrated circuit device, when a power supply voltage is provided to the first connection pad and a ground voltage is provided to the second connection pad, a current flows from the first connection pad to the drain of the i-th transistor via the i-th drain connection through-hole wiring in a very short path. The current flows from the drain of the i-th transistor to the source in a relatively short path, and flows from the source of the i-th transistor to the second connection pad via the i-th source connection through-hole wiring in a very short path. Therefore, the path for the current to flow from the first connection pad to the second connection pad is short. When a power supply voltage is provided to the second connection pad and a ground voltage is provided to the first connection pad, the path for the current to flow from the second connection pad to the first connection pad is also short. Moreover, since the current flows in a direction orthogonal to the first connection pad and the second connection pad through the i-th drain connection through-hole wiring and the i-th source connection through-hole wiring between the first connection pad and the second connection pad and the i-th transistor, the cross-sectional area of ​​the wiring for the current flow becomes larger. Therefore, according to the integrated circuit device, the parasitic resistance between the first connection pad and the second connection pad and the i-th transistor becomes smaller, and the possibility of the current flowing through the i-th transistor decreasing due to the parasitic resistance between the first connection pad and the second connection pad and the i-th transistor can be reduced. In addition, according to the integrated circuit device, a large current can flow between the first connection pad and the second connection pad through N transistors.

[0147] Furthermore, according to this integrated circuit device, since the cross-sectional area of ​​the wiring through which current flows between the first connection pad and the second connection pad and the first transistor is large, the device is also resistant to electromigration.

[0148] One embodiment of the integrated circuit device may also include: a temperature sensor; and a third connection pad that outputs a signal from the temperature sensor, wherein one of the first connection pad and the second connection pad is arranged with the third connection pad in a second direction intersecting the first direction.

[0149] According to this integrated circuit device, in the first direction, no ineffective space is generated near the first land and the second land due to the arrangement of the third land, and the first land and the second land can be easily bonded.

[0150] One embodiment of the integrated circuit device may also include: a temperature sensor; and a third connection pad that outputs a signal from the temperature sensor, wherein the temperature sensor, the third connection pad, and the first transistor are arranged in this order in a second direction intersecting the first direction.

[0151] According to this integrated circuit device, since the temperature sensor is disposed at a location away from the first transistor, the temperature detected by the temperature sensor can be prevented from rapidly changing due to a change in the amount of heat generated by the first transistor.

[0152] One embodiment of the integrated circuit device may also include a temperature sensor, wherein the integrated circuit device is rectangular when viewed from above, has a first side as a short side and a second side as a short side opposite to the first side, the temperature sensor is arranged at a position closer to the first side than the second side, and the first transistor is arranged at a position closer to the second side than the first side.

[0153] According to this integrated circuit device, since the temperature sensor is disposed at a location away from the first transistor, the temperature detected by the temperature sensor can be prevented from rapidly changing due to a change in the amount of heat generated by the first transistor.

[0154] In one aspect of the integrated circuit device, the power supply voltage may be supplied to the first connection pad, the ground voltage may be supplied to the second connection pad, and the first transistor may be an N-channel MOS transistor.

[0155] Since an N-channel MOS transistor has a higher current-flowing capability than a P-channel MOS transistor, according to this integrated circuit device, a sufficient current can flow through the first transistor.

[0156] One form of an oscillator comprises: an integrated circuit device; a vibration element, which is temperature-controlled by the integrated circuit device; and an oscillation circuit, which causes the vibration element to oscillate, the integrated circuit device including: a first connection pad, which is provided with one of a power supply voltage and a ground voltage; a second connection pad, which is provided with the other of the power supply voltage and the ground voltage; a first transistor, which has a first gate to which a temperature control signal is input, a first drain electrically connected to the first connection pad, and a first source electrically connected to the second connection pad; a through-hole wiring for connecting the first drain, which is a through-hole wiring that electrically connects the first connection pad to the first drain; and a through-hole wiring for connecting the first source, which is a through-hole wiring that electrically connects the second connection pad to the first source, when viewed from above, the first drain overlaps with the first connection pad, and the first source overlaps with the second connection pad.

[0157] According to this oscillator, the integrated circuit device capable of causing a sufficient current to flow through the first transistor can control the temperature of the vibration element with high accuracy, and thus can output an oscillation signal with high frequency accuracy.

[0158] One embodiment of the oscillator may include a first container that accommodates the integrated circuit device, the vibration element, and the oscillation circuit.

[0159] In one embodiment of the oscillator, the first container may include: a substrate; a wall portion upright on the first surface of the substrate; and a foot portion upright on the second surface of the substrate, wherein a first storage space is formed by the first surface of the substrate and the wall portion, and a second storage space is formed by the second surface of the substrate and the foot portion, and the integrated circuit device, the vibration element, and the oscillation circuit are stored in the first storage space.

[0160] In one aspect of the oscillator, the first storage space may be airtightly sealed, and the second storage space may be open.

[0161] According to this oscillator, the integrated circuit device, the vibration element and the oscillation circuit are not easily affected by the external air, and the heat released from the integrated circuit device is efficiently transferred to the vibration element. Therefore, the temperature of the vibration element can be controlled with high precision, and an oscillation signal with high frequency accuracy can be output.

[0162] One embodiment of the oscillator may include a second container that accommodates the integrated circuit device, the vibration element, and the oscillation circuit, wherein the second container is accommodated in the first container.

[0163] According to this oscillator, since heat released from the integrated circuit device is efficiently transferred to the vibration element, the temperature of the vibration element can be controlled with high accuracy, and an oscillation signal with high frequency accuracy can be output.

Claims

1. An integrated circuit device comprising: a first connection pad to which one of a power supply voltage and a ground voltage is supplied; a second connection pad to which the other of the power supply voltage and the ground voltage is supplied; a first transistor having a first gate to which a temperature control signal is input, a first drain electrically connected to the first connection pad, and a first source electrically connected to the second connection pad; a first drain connection through-hole wiring, which is a through-hole wiring that electrically connects the first connection pad and the first drain; a first source-connecting through-hole wiring, which is a through-hole wiring that electrically connects the second connection pad and the first source, In a plan view, the first drain electrode overlaps with the first connection pad, and the first source electrode overlaps with the second connection pad.

2. The integrated circuit device according to claim 1, wherein: The first gate, the first drain, and the first source overlap with the first connection pad and the second connection pad in a plan view.

3. The integrated circuit device according to claim 1, wherein: The first connection pad and the second connection pad are arranged side by side along a first direction which is a length direction of the first grid.

4. The integrated circuit device according to claim 3, wherein: Let N be an integer greater than 2, The integrated circuit device includes second to N-th transistors, second to N-th drain connection via wirings, and second to N-th source connection via wirings. The first to N-th transistors are arranged along a second direction intersecting the first direction. For each integer i greater than or equal to 2 and less than or equal to N, The i-th transistor has an i-th gate to which the temperature control signal is input, an i-th drain electrically connected to the first connection pad, and an i-th source electrically connected to the second connection pad. The i-th drain connecting via wiring is a via wiring that electrically connects the first connection pad to the i-th drain. The i-th source connecting via wiring is a via wiring that electrically connects the second connection pad to the i-th source. In a plan view, the i-th drain electrode overlaps with the first connection pad, and the i-th source electrode overlaps with the second connection pad.

5. The integrated circuit device according to claim 3, wherein: The integrated circuit device comprises: temperature sensor; and A third connection pad, which outputs a signal from the temperature sensor, In a second direction intersecting the first direction, one of the first land and the second land and the third land are arranged side by side.

6. The integrated circuit device according to claim 3, wherein: The integrated circuit device comprises: temperature sensor; and A third connection pad, which outputs a signal from the temperature sensor, The temperature sensor, the third land, and the first transistor are arranged in this order in a second direction intersecting the first direction.

7. The integrated circuit device according to claim 1, wherein: The integrated circuit device comprises a temperature sensor, The integrated circuit device is rectangular in a plan view and has a first side as a short side and a second side as a short side opposite to the first side. The temperature sensor is arranged at a position closer to the first side than to the second side. The first transistor is arranged at a position closer to the second side than to the first side.

8. The integrated circuit device according to claim 1, wherein: supplying the power supply voltage to the first connection pad, supplying the ground voltage to the second connection pad, The first transistor is an N-channel MOS transistor.

9. An oscillator comprising: Integrated circuit devices; a vibrating element that is temperature controlled by the integrated circuit device; and an oscillation circuit which causes the vibration element to oscillate, The integrated circuit device comprises: a first connection pad to which one of a power supply voltage and a ground voltage is supplied; a second connection pad to which the other of the power supply voltage and the ground voltage is supplied; a first transistor having a first gate to which a temperature control signal is input, a first drain electrically connected to the first connection pad, and a first source electrically connected to the second connection pad; a first drain connection through-hole wiring, which is a through-hole wiring that electrically connects the first connection pad and the first drain; a first source-connecting through-hole wiring, which is a through-hole wiring that electrically connects the second connection pad and the first source, In a plan view, the first drain electrode overlaps with the first connection pad, and the first source electrode overlaps with the second connection pad.

10. The oscillator according to claim 9, wherein The oscillator includes a first container that accommodates the integrated circuit device, the vibration element, and the oscillation circuit.

11. The oscillator according to claim 10, wherein The first container comprises: a base plate; a wall portion disposed upright on a first surface of the base plate; and a leg portion disposed upright on a second surface of the base plate. The first surface of the substrate and the wall portion form a first storage space, The second surface of the base plate and the leg portion form a second storage space. The integrated circuit device, the vibration element, and the oscillation circuit are accommodated in the first accommodation space.

12. The oscillator according to claim 11, wherein The first storage space is hermetically sealed, and the second storage space is open.

13. The oscillator according to claim 10, wherein: The oscillator includes a second container for storing the integrated circuit device, the vibration element, and the oscillation circuit. The second container is accommodated in the first container.

Images