Method and circuit for reducing mixer harmonic conversion gain and local oscillator fundamental and harmonic feedthrough

Abstract

Relates to a method and circuit for reducing mixer harmonic conversion gain and local oscillator fundamental and harmonic feedthrough. The mixer circuit may include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal; a second pair of transistors coupled to the second tail node and configured to receive a local oscillator signal; a first digital-to-analog converter; a second DAC coupled between the first DAC and the first pair of transistors; and a third DAC coupled between the first DAC and the second pair of transistors. During the first phase, the control circuit may scan the first DAC to trim the first order local oscillator feedthrough and / or other odd order local oscillator feedthrough. During the second phase, the control circuit may scan the second DAC to trim the second order local oscillator feedthrough and / or other even order local oscillator feedthrough. During the third phase, the control circuit may scan the second DAC and the third DAC to suppress a signal associated with a second harmonic conversion gain of the mixer circuit.

Description

[0001] This application claims priority to U.S. patent application No. 18 / 336,786, filed on June 16, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure relates generally to electronic devices and, more particularly, to electronic devices having wireless communications circuitry. Background Art

[0003] Electronic devices often have wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless communication circuits with one or more antennas for sending and receiving radio frequency signals.

[0004] Wireless communication circuits may include a transceiver having one or more mixers. A mixer in the transmit path may be used to modulate a signal from a baseband frequency to a radio frequency, while a mixer in the receive path may be used to demodulate a signal from a radio frequency to a baseband frequency. The mixer receives a clock signal generated from a local oscillator circuit. Designing satisfactory mixer and local oscillator circuits for electronic devices can be challenging. Summary of the invention

[0005] The electronic device may include a wireless circuit. The wireless circuit may include one or more mixers that receive an oscillating signal. The oscillator may generate the oscillating signal, and the oscillator drive circuit may be used to transmit the oscillating signal to the one or more mixers.

[0006] One aspect of the present disclosure provides a mixer circuit, the mixer circuit comprising: a first mixer transistor, the first mixer transistor configured to receive a first oscillation signal and coupled to a first tail node; a second mixer transistor, the second mixer transistor configured to receive a second oscillation signal and coupled to the first tail node; a first digital-to-analog converter (DAC); and a second digital-to-analog converter (DAC), the second digital-to-analog converter (DAC) coupled between the first DAC and the first mixer transistor. The second DAC may include a first output terminal coupled to a gate terminal of the first mixer transistor and a second output terminal coupled to a gate terminal of the second mixer transistor. The mixer circuit may also include: a third mixer transistor, the third mixer transistor configured to receive the first oscillation signal and coupled to the second tail node; a fourth mixer transistor, the fourth mixer transistor configured to receive the second oscillation signal and coupled to the second tail node; and a third digital-to-analog converter (DAC), the third digital-to-analog converter (DAC) coupled between the first DAC and the third mixer transistor. The first DAC may include a first output terminal coupled to the second DAC and a second output terminal coupled to the third DAC. The third DAC may include a first output coupled to a gate terminal of the third mixer transistor and a second output coupled to a gate terminal of the fourth mixer transistor. The mixer circuit may also include a control circuit configured to trim the first DAC during a first calibration phase, trim the second DAC during a second calibration phase after the first calibration phase, and trim the second DAC and the third DAC during a third calibration phase after the second calibration phase.

[0007] One aspect of the present disclosure provides a mixer circuit, the mixer circuit comprising: a first pair of transistors, the first pair of transistors coupled to a first tail node and having a first gate terminal configured to receive a local oscillator signal; a second pair of transistors, the second pair of transistors coupled to a second tail node and having a second gate terminal configured to receive a local oscillator signal; a first digital-to-analog converter (DAC); a second digital-to-analog converter (DAC), the second digital-to-analog converter (DAC) coupled between the first DAC and the first gate terminal of the first pair of transistors; and a third digital-to-analog converter (DAC), the third digital-to-analog converter (DAC) coupled between the first DAC and the second gate terminal of the second pair of transistors. The mixer circuit may include a control circuit configured to trim a direct current (DC) mismatch between the first tail node and the second tail node by adjusting the first DAC, trim an impedance at the first tail node by adjusting the second DAC, and trim a DC level of the local oscillator signal by adjusting the second DAC together with the third DAC.

[0008] One aspect of the present disclosure provides a method of operating a mixer circuit, the method comprising: receiving a first oscillating signal at a gate terminal of a first mixer transistor; receiving a second oscillating signal at a gate terminal of a second mixer transistor, the first mixer transistor and the second mixer transistor being coupled to a first tail node; and receiving a bias voltage from a first digital-to-analog converter (DAC) using a second digital-to-analog converter (DAC), outputting a first bias voltage to a gate terminal of the first mixer transistor, and outputting a second bias voltage to a gate terminal of the second mixer transistor. The method may also include: receiving the first oscillating signal at a gate terminal of a third mixer transistor; receiving a second oscillating signal at a gate terminal of a fourth mixer transistor, the third mixer transistor and the fourth mixer transistor being coupled to a second tail node; and receiving another bias voltage from a first digital-to-analog converter (DAC) using a third digital-to-analog converter (DAC), outputting a third bias voltage to a gate terminal of the third mixer transistor, and outputting a fourth bias voltage to a gate terminal of the fourth mixer transistor.

[0009] The method may also include trimming an offset of the first DAC during the first stage, trimming an offset of the second DAC relative to an offset of the third DAC during the second stage, and trimming an offset of the second DAC together with an offset of the third DAC during the third stage. During the first stage, a DC mismatch between the first tail node and the second tail node may be trimmed. During the second stage, an impedance at the first node may be trimmed relative to an impedance at the second tail node. During the third stage, a DC level of the first oscillating signal may be trimmed relative to a DC level of the second oscillating signal. During the first stage, the first DAC may be scanned to trim a first order LO feedthrough. During the second stage, the second DAC may be scanned to trim a second order LO feedthrough. During the third stage, the second DAC and the third DAC may be scanned to suppress a signal associated with a second harmonic gain of the mixer circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram of an illustrative electronic device with wireless circuitry according to some embodiments.

[0011] Figure 2 is a diagram of an illustrative wireless circuit having transceiver circuitry according to some implementations.

[0012] Figure 3A is a diagram of an illustrative mixer in a receive path according to some implementations.

[0013] Figure 3B is a diagram illustrating how a RF blocker according to some embodiments can down-convert to an intermediate frequency of interest via the second harmonic conversion gain of a receive mixer.

[0014] Figure 4A is a diagram of an illustrative mixer in a transmit path according to some implementations.

[0015] Figure 4B is a diagram illustrating how a blocker signal at an intermediate frequency is up-converted to a radio frequency range of interest by the second harmonic conversion gain of a transmit mixer caused by a second harmonic component of a local oscillator circuit feeding the transmit mixer, according to some embodiments.

[0016] Figure 5 is a diagram of an illustrative mixer circuit including a harmonic shaping circuit and a current reuse input transformer, according to some embodiments.

[0017] Figure 6 is a diagram of an illustrative mixer circuit including a harmonic shaping circuit and an active input transformer, according to some embodiments.

[0018] Figure 7 is a diagram of an illustrative mixer circuit including a harmonic shaping circuit and a passive input, according to some implementations.

[0019] Figure 8 is a circuit diagram illustrating one specific implementation of a differentially biased digital-to-analog converter (DAC) according to some embodiments.

[0020] Fig. 9 is a circuit diagram illustrating another specific implementation of a differential biased digital-to-analog converter (DAC) according to some embodiments.

[0021] Fig.10 According to some embodiments, Figures 5 to 7 Flowchart of illustrative steps for a mixer circuit of the type shown in FIG.

[0022] Fig.11 is a diagram of an illustrative mixer circuit including a harmonic shaping circuit with four single-ended biased DACs, according to some implementations.

[0023] Fig.12 According to some embodiments, Fig.11 Flowchart of illustrative steps for a mixer circuit of the type shown in FIG. DETAILED DESCRIPTION

[0024] Electronic devices such as Figure 1The electronic device 10 may be provided with wireless circuitry. The wireless circuitry may include one or more mixers, such as a mixer in a transmit path for up-converting (modulating) a signal from a lower frequency to a higher frequency, and a mixer in a receive path for down-converting (demodulating) a signal from a higher frequency to a lower frequency. The mixer may receive an oscillating (clock) signal from a local oscillator circuit. The local oscillator (LO) circuit may exhibit nonlinearity, thereby generating a second harmonic component. The second harmonic component of the LO circuit may mix with a blocking signal, thereby interfering with an in-band signal of interest at the output of the mixer. This effect is sometimes collectively referred to as the second harmonic conversion gain of the mixer.

[0025] The mixer may include four mixer transistors configured to receive the LO signal. The first mixer transistor and the second mixer transistor may have a gate configured to receive a positive local oscillator signal LO+. The third mixer transistor and the fourth mixer transistor may have a gate configured to receive a negative local oscillator signal LO-. The four mixer transistors may have a gate coupled to a set of at least three differential bias DACs, such as DAC1, DAC2, and DAC3. DAC1 may have a first (+) output coupled to an input of DAC2 and a second (-) output coupled to an input of DAC3. DAC2 may have a first (+) output coupled to a gate of the first mixer transistor and a second (-) output coupled to a gate of the third mixer transistor. DAC3 may have a first (+) output coupled to a gate of the second mixer transistor and a second (-) output coupled to a gate of the fourth mixer transistor.

[0026] The three DACs may be trimmed to reduce undesirable spurious emissions at the mixer circuit. The trimming operation may include: (1) calibrating the offset of DAC1 to trim the DC mismatch between the first tail node at the source terminal of the first mixer transistor and the third mixer transistor and the second tail node at the source terminal of the second mixer transistor and the fourth mixer transistor; (2) calibrating the offset of DAC2 relative to the offset of DAC3 to trim the impedance at the first tail node relative to the impedance at the second tail node at the fundamental and / or LO harmonic frequency; and (3) calibrating the offset of DAC2 together with DAC3 to trim LO+ relative to LO-differential. Operating the mixer circuit in this manner is technically advantageous and beneficial due to at least the following results. Step (1) minimizes the first order LO feedthrough. Step (2) minimizes the second order LO feedthrough. Step (3) minimizes the (2LO-IF) blocker generated due to the mixer second harmonic conversion gain. In other words, undesirable in-band spurious or spectral emissions can be suppressed.

[0027] Figure 1The electronic device 10 may be: a computing device, such as a laptop computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch device, a hanging device, a headset or earpiece device, a device embedded in glasses; or other equipment worn on the user's head; or other wearable or miniature devices, televisions, computer displays that do not contain embedded computers, gaming devices, navigation devices, embedded systems (such as systems in which electronic equipment with displays is installed in kiosks or cars), voice-controlled speakers connected to wireless Internet, home entertainment equipment, remote control devices, game controllers, peripheral user input devices, wireless base stations or access points, equipment that implements the functions of two or more of these devices; or other electronic equipment.

[0028] like Figure 1 As shown in the functional block diagram in , device 10 may include components located on or within an electronic device housing such as housing 12. Housing 12 (which may sometimes be referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloy, etc.), other suitable materials, or combinations of these materials. In some embodiments, part or all of housing 12 may be formed of a dielectric or other low conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing 12 or at least some of the structures that make up housing 12 may be formed of metal elements.

[0029] Device 10 may include control circuitry 14. Control circuitry 14 may include storage, such as storage circuitry 16. Storage circuitry 16 may include hard drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 may include storage integrated within device 10 and / or removable storage media.

[0030] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). The software code may sometimes be referred to as program instructions, software, data, instructions, or code. The software code stored on storage circuitry 16 may be executed by processing circuitry 18.

[0031] Control circuitry 14 may be used to run software on device 10, such as satellite navigation applications, Internet browsing applications, Voice over Internet Protocol (VOIP) phone call applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 may be used to implement communication protocols. Communication protocols that may be implemented using control circuitry 14 include: Internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols—sometimes referred to as ), protocols for other short-range wireless communication links such as Protocol or other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., global positioning system (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based space ranging protocols (e.g., radio detection and ranging (RADAR) protocols or other desired distance detection protocols for signals transmitted at millimeter and centimeter wave frequencies), or any other desired communication protocols. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies a physical connection method for implementing the protocol.

[0032] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touch pads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice, and joysticks, and other input-output devices may be coupled to device 10 using wired or wireless connections (e.g., some of input-output devices 22 may be peripheral devices coupled to a main processing unit or other portion of device 10 via a wired or wireless link).

[0033] Input-output circuitry 20 may include wireless circuitry 24 to support wireless communications. Wireless circuitry 24 (sometimes referred to herein as wireless communications circuitry 24) may include one or more antennas. Wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, radio frequency transmission lines, and / or any other circuitry for transmitting and / or receiving radio frequency signals using an antenna.

[0034] Wireless circuitry 24 may transmit and / or receive radio frequency signals within a corresponding band of radio frequencies (sometimes referred to herein as a communication band or simply a “band”). The bands processed by wireless circuitry 24 may include wireless local area network (WLAN) bands (e.g., (IEEE 802.11) or other WLAN communication bands) such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925 MHz to 7125 MHz) and / or other frequency bands (e.g., 1875 MHz to 5160 MHz); wireless personal area network (WPAN) bands such as 2.4 GHz frequency band or other WPAN communication band; cellular telephone frequency band (for example, frequency band of about 600 MHz to about 5 GHz, 3G frequency band, 4G LTE frequency band, 5G new air interface frequency range 1 (FR1) frequency band below 10 GHz, 5G new air interface frequency range 2 (FR2) frequency band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave frequency bands between 10 GHz and 300 GHz; near field communication frequency band (for example, 13.56 MHz); satellite navigation frequency band (for example, GPS frequency band of 1565 MHz to 1610 MHz, global satellite navigation system (GLONASS) frequency band, Beidou satellite navigation system (BDS) frequency band, etc.); ultra-wideband (UWB) frequency band operating under IEEE802.15.4 protocol and / or other ultra-wideband communication protocols; communication frequency band under 3GPP wireless communication standard family; communication frequency band under IEEE 802.XX standard family, and / or any other desired frequency band of interest.

[0035] Figure 2 2 is a diagram showing illustrative components within wireless circuitry 24. Figure 2 As shown, the wireless circuit 24 may include one or more processors such as a processor 26, a radio frequency (RF) transceiver circuit such as an RF transceiver 28, an RF front-end circuit such as an RF front-end module (FEM) 40, and an antenna 42. The processor 26 may be a baseband processor, an application processor, a digital signal processor, a microcontroller, a microprocessor, a central processing unit (CPU), a programmable device, a combination of these circuits, and / or one or more processors within the circuit 18. The processor 26 may be configured to generate a digital (transmit or baseband) signal. The processor 26 may be coupled to the transceiver 28 via a path 34 (sometimes referred to as a baseband path). The transceiver 28 may be coupled to the antenna 42 via an RF transmit line path 36. The RF front-end module 40 may be inserted on the RF transmit line path 36 between the transceiver 28 and the antenna 42.

[0036] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 may be formed using any desired antenna structure. For example, antenna 42 may be an antenna having a resonant element formed by a loop antenna structure, a patch antenna structure, an inverted-F antenna structure, a slot antenna structure, a planar inverted-F antenna structure, a helical antenna structure, a monopole antenna, a dipole, a mixture of these designs, and the like. Two or more antennas 42 may be arranged into one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports an antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0037] exist Figure 2In the example of FIG. 2 , for the sake of clarity, the wireless circuit 24 is shown as including only a single processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. In general, the wireless circuit 24 may include any desired number of processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processor 26 may be coupled to one or more transceivers 28 via a corresponding path 34. Each transceiver 28 may include a transmitter circuit configured to output an uplink signal to the antenna 42, may include a receiver circuit configured to receive a downlink signal from the antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmission line path 36. Each RF transmission line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmission line path 36. If desired, one or more of the RF transmission line paths 36 in the wireless circuit 24 may be implemented without any front-end module inserted thereon.

[0038] The front end module (FEM) 40 may include RF front end circuitry that operates on RF signals transmitted (transmitted and / or received) via the RF transmit line path 36. The front end module may, for example, include front end module (FEM) components such as RF filter circuitry 44 (e.g., low pass filter, high pass filter, notch filter, band pass filter, multiplexing circuit, duplexer circuit, diplexer circuit, triplexer circuit, etc.), switching circuitry 46 (e.g., one or more RF switches), RF amplifier circuitry 48 (e.g., one or more power amplifiers and one or more low noise amplifiers), impedance matching circuitry (e.g., circuitry that helps match the impedance of the antenna 42 to the impedance of the RF transmit line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of the antenna 42), RF coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on RF signals transmitted and / or received by the antenna 42. Each of the front end module components may be mounted to a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit substrate. If desired, the various front-end module components may also be integrated into a single integrated circuit chip.

[0039] Filter circuits 44, switching circuits 46, amplifier circuits 48, and other circuits may be interposed within RF transmit line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuitry 14) to adjust the frequency response and wireless performance of antenna 42 over time.

[0040] The RF transmission line path 36 may be coupled to an antenna feed on the antenna 42. The antenna feed may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmission line path 36 may have a positive transmission line signal path that is coupled to the positive antenna feed terminal on the antenna 42. The RF transmission line path 36 may have a ground transmission line signal path that is coupled to the ground antenna feed terminal on the antenna 42. This example is illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feeds coupled to one or more RF transmission line paths 36.

[0041] The RF transmission line path 36 may include a Figure 1 ) for routing RF antenna signals within the device 10. The transmission lines in the device 10 may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed by combinations of these types of transmission lines, and the like. Transmission lines in the device 10, such as the transmission lines in the RF transmission line path 36, may be integrated into a rigid and / or flexible printed circuit board. In a suitable arrangement, the RF transmission line path (such as the RF transmission line path 36) may also include transmission line conductors that are integrated into a multilayer laminate structure (e.g., layers of conductive material (such as copper) and dielectric material (such as resin) laminated together without intervening adhesives). If desired, the multilayer laminate structure may be folded or bent in multiple dimensions (e.g., two or three dimensions), and may maintain a bent or folded shape after bending (e.g., the multilayer laminate structure may be folded into a specific three-dimensional structural shape to route around other device components and may be rigid enough to maintain its shape after folding without reinforcements or other structures to hold it in place). All of the multiple layers of the laminated structure may be laminated together in batches (eg, in a single pressing process) without an adhesive (eg, as opposed to performing multiple pressing processes to laminate the multiple layers together with an adhesive).

[0042] Transceiver circuitry 28 may include processors that handle WLAN communication bands (e.g., (IEEE 802.11) or other WLAN communication bands) such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925 MHz to 7125 MHz) and / or other Wireless LAN transceiver circuits for frequency bands (e.g., 1875MHz to 5160MHz); handles 2.4GHz Wireless personal area network transceiver circuits for processing cellular telephone frequency bands or other WPAN communication frequency bands; cellular telephone transceiver circuits for processing cellular telephone frequency bands (e.g., frequency bands from about 600 MHz to about 5 GHz, 3G frequency bands, 4G LTE frequency bands, 5G new radio frequency range 1 (FR1) frequency bands below 10 GHz, 5G new radio frequency range 2 (FR2) frequency bands between 20 GHz and 60 GHz, etc.); near field communication (NFC) transceiver circuits for processing near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits for processing satellite navigation frequency bands (e.g., GPS frequency bands from 1565 MHz to 1610 MHz, global satellite navigation system (GLONASS) frequency bands, Beidou satellite navigation system (BDS) frequency bands, etc.); ultra-wideband (UWB) transceiver circuits for processing communications using the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuits for covering any other desired communication frequency bands of interest.

[0043] When performing wireless transmission, the processor 26 can provide a digital signal to the transceiver 28 via the path 34. The transceiver 28 may also include a circuit for converting a baseband signal received from the processor 26 into a corresponding intermediate frequency or radio frequency signal. For example, the transceiver circuit 28 may include a mixer circuit 50 for up-converting (or modulating) the baseband signal to an intermediate frequency or radio frequency before transmission through the antenna 42. The transceiver circuit 28 may also include a digital-to-analog converter (DAC) circuit and / or an analog-to-digital converter (ADC) circuit for converting signals between the digital domain and the analog domain. The transceiver 28 may include a transmitter component to transmit a radio frequency signal through the antenna 42 via the radio frequency transmission line path 36 and the front-end module 40. The antenna 42 can transmit the radio frequency signal to the external wireless equipment by radiating the radio frequency signal into free space.

[0044] When performing wireless reception, the antenna 42 can receive a radio frequency signal from an external wireless device. The received radio frequency signal can be transmitted to the transceiver 28 via the radio frequency transmission line path 36 and the front-end module 40. The transceiver 28 may include a circuit for converting the received radio frequency signal to a corresponding intermediate frequency or baseband signal. For example, the transceiver 28 may use a mixer circuit 50 to down-convert (or demodulate) the received radio frequency signal to a baseband frequency before transmitting the received signal to the processor 26 via the path 34. The mixer circuit 50 may include a local oscillator circuit, such as a local oscillator (LO) circuit 52. The local oscillator circuit 52 can generate an oscillator signal, and the mixer circuit 50 can use the oscillator signal to modulate the transmit signal from the baseband frequency to the radio frequency and / or demodulate the received signal from the radio frequency to the baseband frequency.

[0045] Figure 3Ais a diagram of an exemplary mixer in a receive (RX) path of a wireless circuit. Figure 3A As shown, antenna 42 can feed the received RF signal to mixer 51. Mixer 51 in the receive (downlink) path can be referred to as a receive mixer. Mixer 51 can represent Figure 2 4 and 5. The mixer 51 may have a first input configured to receive a radio frequency signal from the antenna 42, a second input configured to receive an oscillating signal LO, and an output at which a demodulated signal (as an example) down-converted to an intermediate frequency (IF) range is generated. One or more components (such as a radio frequency coupler, a filter circuit, an antenna tuning element, a matching network, a switching circuit, an amplifier circuit, other radio frequency front-end components, other transceiver components, and / or other wireless components) may be arranged in a receiving path between the antenna 42 and the mixer 51. The receiving mixer 51 that receives a radio frequency signal may be referred to as a radio frequency mixer.

[0046] Figure 3B is a diagram illustrating how the second harmonic conversion gain of mixer 51 can generate undesired in-band emissions at the mixer output if care is not taken. Figure 3B As shown, the radio frequency signal received at the first input terminal of the mixer 51 may be at a frequency f RF ; Adjacent channel or in-band blockers can be located at f RFB The LO signal received at the second input of the mixer 51 may be located at a frequency f LO ; and the demodulated signal generated at the output of the mixer 51 may be located at the intermediate frequency f IF In implementation, the local oscillator circuit feeding the second input of the mixer 51 may exhibit non-linear behavior, which results in a generated frequency of 2*f LO Such second harmonic components can be combined with the RF signal of the adjacent channel or f RFB The in-band blocker mixes at and generates a frequency of f B The down-converted blocker signal, where the blocker frequency f B Equal to 2*f LO Subtract f RFB (See, for example, arrow 60 .) This phenomenon is sometimes referred to as being caused by the second harmonic conversion gain of mixer 51 .

[0047] If the radio frequency f RF and the local oscillator frequency f LO The choice of leads to the corresponding f B In the intermediate frequency (IF) range of interest or close to it, the blocker frequency f B The placement of may be problematic. For example, consider the frequency f RFEqual to 37GHz, frequency f RFB is equal to 38 GHz and the frequency f LO The intermediate frequency f is equal to 25 GHz. IF will be equal to 12 GHz (for example, f RF -f LO =37-25=12 GHz). In this example, the down-converted blocker frequency f B will also be equal to 12 GHz (e.g., 2*f LO -f RFB =2*25-38=12GHz). In other words, f B The blocker signal at the output of mixer 51 may interfere with the intermediate frequency f IF This can cause self-desensitization and reduce the overall signal-to-noise ratio of the receive path.

[0048] Figure 4A is a diagram of an exemplary mixer in the transmit (TX) path of a wireless circuit. Figure 4A As shown, the mixer 51 can output RF signals, which are ultimately radiated by the antenna 42. The mixer 51 in the transmit (uplink) path can be referred to as a transmit mixer. The mixer 51 can represent Figure 2 42. The transmit mixer 51 may have a first input configured to receive a signal in an intermediate frequency (IF) range, a second input configured to receive an oscillating signal LO, and an output on which a modulated signal (as an example) up-converted to a radio frequency (RF) range is generated. One or more components (such as a radio frequency coupler, a filter circuit, an antenna tuning element, a matching network, a switching circuit, an amplifier circuit, other radio frequency front-end components, other transceiver components, and / or other wireless components) may be disposed in a transmit path between the transmit mixer 51 and the antenna 42. The transmit mixer 51 that outputs a radio frequency signal may be referred to as a radio frequency mixer.

[0049] Figure 4B is a diagram illustrating how the second harmonic conversion gain of the transmit mixer 51 can generate undesirable in-band emissions at the mixer output if care is not taken. Figure 4B As shown, the intermediate frequency signal received at the first input terminal of the mixer 51 may be located at a frequency f IF The LO signal received at the second input of the mixer 51 may be located at a frequency f LO ; and the modulated signal generated at the output of the mixer 51 may be located at a radio frequency f RF In implementation, the local oscillator circuit feeding the second input of the transmit mixer 51 may exhibit non-linear behavior, which results in a generated frequency of 2*f LOSuch second harmonic components can be combined with adjacent channel signals or f B The in-band IF blocker mixes at and generates an up-converted interference signal 63 that may fall within the RF range of interest (see, for example, falling within frequency f RFB The arrow 62 at which f RFB Equal to 2*f LO Subtract f B ). This phenomenon is sometimes said to be caused by the second harmonic conversion gain of the mixer 51.

[0050] If the radio frequency f RFB and the local oscillator frequency f LO If the selection of causes the interference signal to fall within or close to the radio frequency (RF) range of interest, the frequency f of the interference signal 63 is RF For example, consider the above scenario where the frequency f RF is equal to 37 GHz, and the frequency f LO =25GHz. Intermediate frequency f IF will be equal to 12 GHz (for example, f RF -f LO =37-25=12GHz). In this example, the frequency f B The in-band blocker equal to 13 GHz can also be used with 2*f LO Mix to reconstruct the frequency f RFB The up-converted interfering signal 63 (eg, 2*f LO -f B =2*25-13=37 GHz). In other words, the signal 63 may interfere with f at the output of the transmit mixer 51. RF This may cause the transmit path to violate performance standards.

[0051] According to one embodiment, a mixer circuit 50 is provided that includes a harmonic shaping circuit configured to reduce or suppress the combination of Figure 3B and Figure 4B Describes various unwanted spurious emissions. Figure 5 is a circuit diagram of an illustrative mixer circuit 50 that includes a harmonic shaping circuit, such as harmonic shaping circuit 98. Mixer circuit 50 may represent a transmit mixer (eg, a mixer in a transmit path) or a receive mixer (eg, a mixer in a receive path).

[0052] like Figure 5As shown, the mixer circuit 50 may include a first input transistor 80-1 and a second input transistor 80-2, which are coupled to an input transformer, such as a transformer 82. The transformer 82 may include a primary coil (winding) Lp and a secondary coil (winding) Ls. The primary coil Lp may have a center tap shorted to the center tap of the secondary coil Ls. Connecting the center tap terminals of the coils Lp and Ls together in this manner allows current to be shared or reused between the two coils. Therefore, the transformer 82 configured in this manner is sometimes referred to as a "current reuse" transformer.

[0053] Input transistors 80-1 and 80-2 may be n-channel devices such as n-type metal oxide semiconductor (NMOS) transistors. Input transistor 80-1 may have a drain terminal coupled to a first terminal of coil Lp, a source terminal coupled to ground power supply line 68 (e.g., a ground line on which a ground voltage is provided), and a gate terminal configured to receive an input voltage Vin+. Input transistor 80-2 may have a drain terminal coupled to a second terminal of coil Lp, a source terminal coupled to ground line 68, and a gate terminal configured to receive an input voltage Vin-. The increment of voltages Vin+ and Vin- can represent a differential RF input voltage of mixer circuit 50. The terms "source" and "drain" terminals used to refer to current-carrying terminals in transistors are used interchangeably and are sometimes referred to as "source-drain" terminals. Therefore, the drain terminal of transistor 80-1 may sometimes be referred to as a first source-drain terminal, and the source terminal of transistor 80-1 may be referred to as a second source-drain terminal (or vice versa).

[0054] The transformer 82 may be coupled to the mixer subcircuits 53-1 and 53-2. The mixer subcircuit 53-1 may include a first pair of mixer transistors 76-1a and 76-1b (e.g., a first transistor pair). The mixer transistor 76-1a may have a source terminal coupled to the secondary coil Ls, a gate terminal configured to receive a signal LO+, and a drain terminal coupled to the first output terminal o1. The mixer transistor 76-1b may have a source terminal also coupled to the secondary coil Ls, a gate terminal configured to receive a signal LO-, and a drain terminal coupled to the second output terminal o2. The source terminals of the mixer transistors 76-1a and 76-1b may be coupled to the first tail node Tp. The signals LO+ and LO- represent the positive and negative polarities of the differential signal and may be collectively referred to as local oscillator signals or oscillation signals. The gate terminals of the mixer transistors 76-1a and 76-1b together form a differential input port for receiving the oscillation signal. The output terminals o1 and o2 together form a differential output port OUT of the mixer circuit 50. An output inductor Lout may be coupled across the differential output ports of the mixer circuit 50. Specifically, the output inductor Lout may have a first terminal coupled to the output terminal o1, a second terminal coupled to the output terminal o2, and a center tap terminal coupled to a positive power supply line 78 (e.g., a positive power supply terminal on which a positive power supply voltage Vdd is provided).

[0055] The mixer subcircuit 53-2 may include a second pair of mixer transistors 76-2a and 76-2b (e.g., a second transistor pair). The mixer transistor 76-2a may have a source terminal coupled to the secondary coil Ls, a gate terminal configured to receive the signal LO+, and a drain terminal coupled to the second output terminal o2. The mixer transistor 76-2b may have a source terminal also coupled to the secondary coil Ls, a gate terminal configured to receive the signal LO-, and a drain terminal coupled to the first output terminal o1. The source terminals of the mixer transistors 76-2a and 76-2b may be coupled to the second tail node Tm. The gate terminals of the mixer transistors 76-2a and 76-2b together form a differential input terminal for receiving an oscillation signal.

[0056] To help reduce undesirable spurious emissions associated with the operation of the mixer circuit 50, the four mixer transistors (e.g., transistors 76-1a, 76-1b, 76-2a, and 76-2b) can be configured to receive bias voltages from a harmonic shaping circuit 98. The harmonic shaping circuit 98 can include a plurality of differential direct current (DC) bias digital-to-analog converters, such as a first DAC 100-1, a second DAC 100-2, and a third DAC 100-3. The first DAC 100-1 can have a first (positive) output terminal coupled to the second DAC 100-2, and can have a second (negative) output terminal coupled to the third DAC 100-3. The second DAC 100-2 can have a first (positive) output terminal coupled to the gate terminal of the mixer transistor 76-1a via a resistor 102, and can have a second (negative) output terminal coupled to the gate terminal of the mixer transistor 76-1b via a resistor 104. The third DAC 100-3 may have a first (positive) output coupled to the gate terminal of the mixer transistor 76-2a via a resistor 108, and may have a second (negative) output coupled to the gate terminal of the mixer transistor 76-2b via a resistor 106. The three DACs 100-1, 100-2, and 100-3 may be configured (calibrated or trimmed) to provide appropriate bias voltages to the gate terminals of the mixer transistors to achieve optimal LO feedthrough reduction and harmonic gain suppression.

[0057] The input portion of mixer circuit 50 is implemented using current reuse transformer 82. Figure 5 The embodiments are exemplary. Figure 6 Another embodiment of a mixer circuit 50 having an input section implemented using an active transformer 82' is shown. Figure 6 As shown, the transformer 82' includes a primary coil Lp, the center tap of which is coupled to a power supply line, such as the positive power supply line 78. The transformer 82' also includes a secondary coil Ls, the center tap of which is coupled to a power supply line, such as the ground line 68. This example in which the center tap of the coil Lp is coupled to the power supply line 78 and the center tap of the coil Ls is coupled to the ground line 68 is illustrative. As another example, the center tap of the coil Lp may be coupled to the ground line 68, and the center tap of the coil Ls may be coupled to the power supply line 78. As another example, the center taps of the coils Lp and Ls may be coupled to different voltage lines. As another example, the center taps of the coils Lp and Ls may be coupled to the same or different power supply lines.

[0058] Active transformer 82' is used to implement the input portion of mixer circuit 50. Figure 6 The embodiments are exemplary. Figure 7Another embodiment of a mixer circuit 50 having an input section implemented using passive components is shown. Figure 7 As shown, the input portion of the mixer circuit 50 may include passive electronic components, such as passive components 90-1, 90-2, 92-1, and 92-2. Component 90-1 (e.g., a first input coupling capacitor) may have a first terminal configured to receive an input voltage Vin+ and a second terminal coupled to a first tail node Tp of the mixer subcircuit 53-1. Component 90-2 (e.g., a second input coupling capacitor) may have a first terminal configured to receive an input voltage Vin- and a second terminal coupled to a second tail node Tm of the mixer subcircuit 53-2. Component 92-1 (e.g., a resistor, capacitor, inductor, or other passive load) may be coupled between capacitor 90-1 and ground line 68. Similarly, component 92-2 (e.g., a resistor, capacitor, inductor, or other passive load) may be coupled between capacitor 90-2 and ground line 68. There are no active input transistors (see, e.g., Figure 5 and Figure 6 The input transistors 80-1 and 80-2 in the Figure 7 The embodiments of the mixer circuit 50 are sometimes referred to as mixer circuits 50 with passive input stages. Figures 5 to 7 The embodiment of is exemplary. If desired, mixer circuit 50 can be implemented in other ways.

[0059] The differential DC bias DAC 100 (eg, DACs 100 - 1 , 100 - 2 , and 100 - 3 ) may be implemented in various ways. Figure 8 1 is a circuit diagram showing a specific implementation of the DAC circuit 100. Figure 8 As shown, DAC 100 may include a differential buffer (such as buffer 110), resistors R1 and R2, and current sources I1 and I2. Buffer 110 may have a first (positive) input terminal configured to receive an input bias voltage Vbias_in, a second (negative) input terminal, and an output terminal shorted to the second input terminal via a feedback path 112. The input bias voltage Vbias_in may be fixed (static) or adjustable (tunable). Buffer 110 configured in this manner is sometimes referred to as a "unit gain buffer" and may exhibit a gain of one. The output terminal of buffer 110 is coupled to node 116. The bias voltage Vbias may be generated at node 116 and may have a voltage level equal to Vbias_in.

[0060] Resistor R1 may have a first terminal coupled to node 116 and a second terminal coupled to node 114. Current source I1 may have a first terminal coupled to positive power supply line 78 and a second terminal coupled to node 114. Current source I1 may be an adjustable current source (e.g., a current source with an adjustable current amount, such as a current source DAC). Resistor R2 may have a first terminal coupled to node 116 and a second terminal coupled to node 118. Resistors R1 and R2 may optionally have adjustable resistances. Current source I2 may have a first terminal coupled to node 118 and a second terminal coupled to ground line 68. Current source I2 may be an adjustable current sink (e.g., a current sink with an adjustable current amount, such as a current sink DAC). Configured in this manner, a first bias voltage equal to (Vbias+I1*R1) may be generated at the first (positive) output node 114, while a second bias voltage equal to (Vbias-I2*R2) may be generated at the second (negative) output node 118. The voltage levels at output nodes 114 and 118 may be adjusted by tuning Vbias (eg, by adjusting input bias voltage Vbias_in, by adjusting currents I1 or I2 , and / or by adjusting the resistances of R1 and R2 ).

[0061] Fig. 9 is a circuit diagram showing another specific implementation of the DAC circuit 100. Fig. 9 As shown, DAC 100 may include a differential buffer (such as buffer 120), resistors R1 and R2, and current sources I1 and I2. Buffer 120 may have a first (negative) input terminal configured to receive an input bias voltage Vbias_in, a second (positive) input terminal coupled to node 116, and an output terminal for controlling current source I2. The input bias voltage Vbias_in may be fixed (static) or adjustable (tunable). The bias voltage Vbias may be generated at node 116 and may have a voltage level equal to Vbias_in.

[0062] Resistor R1 may have a first terminal coupled to node 116 and a second terminal coupled to node 114. Current source I1 may have a first terminal coupled to positive power supply line 78 and a second terminal coupled to node 114. Current source I1 may be an adjustable current source (e.g., a current source with an adjustable current amount, such as a current source DAC). Resistor R2 may have a first terminal coupled to node 116 and a second terminal coupled to node 118. Resistors R1 and R2 may optionally have adjustable resistances. Current source I2 may have a first terminal coupled to node 118 and a second terminal coupled to ground line 68. Current source I2 may be an adjustable current sink (e.g., a current sink with an adjustable current amount, such as a current sink DAC). Configured in this manner, a first bias voltage equal to (Vbias+I1*R1) may be generated at the first (positive) output node 114, while a second bias voltage equal to (Vbias-I2*R2) may be generated at the second (negative) output node 118. The voltage levels at output nodes 114 and 118 may be adjusted by tuning Vbias (eg, by adjusting input bias voltage Vbias_in, by adjusting currents I1 or I2 , and / or by adjusting the resistances of R1 and R2 ). Figure 8 and Fig. 9 The embodiments are exemplary. In general, the mixer circuit may be provided with a differential bias DAC having any suitable DAC architecture.

[0063] Fig.10 According to some embodiments, Figures 5 to 7 2 is a flow chart of illustrative steps of a mixer circuit 50 of the type shown in FIG. During operation of block 200, the first DAC 100-1 (sometimes referred to and defined herein as "DAC1") may be scanned to trim or minimize the DC mismatch between the tail nodes Tp and Tm. This may be accomplished by adjusting the current sources I1 and I2 (see, e.g., Figure 8 and Fig. 9 ) to sweep DAC1 so that the voltages at the two output nodes are adjusted within its tuning range. DAC1 calibrates the DC currents flowing into the tail nodes Tp and Tm, which have an approximately 1:1 relationship with the first order LO feedthrough and the third order LO feedthrough (and other higher order odd LO feedthroughs in general). Trimming DAC1 in this manner establishes a DC offset of DAC1 (referred to and defined herein as "OS1") that calibrates or minimizes the first order LO feedthrough and other higher odd order LO feedthroughs. Block 200 is sometimes referred to as the first calibration phase.

[0064] During the operation of block 202, the second DAC 100-2 (sometimes referred to and defined herein as "DAC2") can be swept to trim the LO impedance at the tail node Tp relative to the impedance at the tail node Tm at the LO frequency. The signal at the LO frequency is up-converted to the differential mode second harmonic frequency by the fundamental mixer gain, so trimming DAC2 can be used to trim the second harmonic ("2LO") feedthrough. However, trimming DAC2 does not affect the amount of DC current flowing to the tail node Tp, and therefore does not affect the LO feedthrough trimming of block 202. Therefore, the operation of block 202 can be said to be orthogonal or independent of the operation of block 200. Trimming DAC2 in this manner can establish an increment between the DC offset of DAC2 (referred to and defined herein as "OS2") and the DC offset of DAC3 (referred to and defined herein as "OS3"), which increment calibrates or minimizes the 2LO feedthrough. Block 202 is sometimes referred to as the second calibration stage.

[0065] During operation of block 204, DAC2 and a third DAC 100-3 (sometimes referred to and defined herein as “DAC3”) may be swept together (i.e., in parallel in the same direction) while maintaining the DC offset increment established from block 202 to shift the DC level of signal LO+ relative to the DC level of signal LO-. Scanning DAC2 in series with DAC3 may cause the DC offsets of OS2 and DAC3 (referred to and defined herein as “OS3”) to move in the same direction, which may help minimize IF (intermediate frequency) feedthrough and any blocker signal components at (2LO-IF). However, trimming DAC2+DAC3 together does not affect the DC offset increment established during block 204. Thus, the operation of block 204 may be said to be orthogonal to the operation of block 202. Thus, trimming DAC2 and DAC3 in this manner to minimize the (2LO-IF) blocker signal may be said to calibrate or minimize the mixer second harmonic conversion gain. Thus, DAC1, DAC2, and DAC3 are sometimes collectively referred to as harmonic suppression circuit 98. The control circuit 14 (see Figure 1 ), processing circuitry 18, logic or other controller to trim, adjust or calibrate these different DACs. Block 204 is sometimes referred to as the third calibration phase.

[0066] Fig.10The operations are exemplary. In some embodiments, DAC2 may be set equal to DAC3, and the two may be trimmed together to trim the (2LO-IF) component alone. In other embodiments, DAC3 may be set to zero and DAC2 may be trimmed alone to minimize the 2LO feedthrough component. If necessary, the operation of box 202 may be performed before box 200. If necessary, the operation of box 204 may be performed before box 202 or before box 200. In some embodiments, one or more of the operations described may be modified, replaced, or omitted. In some embodiments, one or more of the operations described may be performed in parallel. In some embodiments, additional processes may be added or inserted between the operations described. If necessary, the order of certain operations may be reversed or changed, and / or the timing of the operations described may be adjusted so that they occur at slightly different times.

[0067] The mixer circuit 50 is provided with a harmonic suppression circuit 98 including three DACs. Figures 5 to 7 The embodiments are exemplary. Fig.11 Another embodiment of a mixer circuit 50 including a harmonic rejection circuit 98 having four single-ended DC bias DACs is shown. Fig.11 As shown, the harmonic suppression circuit 98 may include a first DAC 101-1 (sometimes referred to herein as "DACa"), a second DAC 101-2 (sometimes referred to herein as "DACb"), a third DAC 101-3 (sometimes referred to herein as "DACc"), and a fourth DAC 101-4 (sometimes referred to herein as "DACd"). The first DACa may have an output terminal coupled to the gate terminal of the mixer transistor 76-1a via a resistor 102. The second DACb may have an output terminal coupled to the gate terminal of the mixer transistor 76-1b via a resistor 104. The third DACc may have an output terminal coupled to the gate terminal of the mixer transistor 76-2a via a resistor 108. The fourth DACd may have an output terminal coupled to the gate terminal of the mixer transistor 76-2b via a resistor 106. The four DACs may be configured (trimmed or calibrated) to provide appropriate bias voltages to the gate terminals of the mixer transistors to achieve optimal harmonic gain suppression. The offset associated with DACa may be referred to as "OSa"; the offset associated with DACb may be referred to as "OSb"; the offset associated with DACc may be referred to as "OSc"; and the offset associated with DACd may be referred to as "OSd".

[0068] Fig.11 The mixer circuit 50 includes a current reuse transformer 82. This is exemplary. As another example, Fig.11The mixer circuit 50 may use an active transformer 82' (see, for example, Figure 6 As another example, Fig.11 The mixer circuit 50 may use a passive input stage (see, for example, Figure 7 Generally speaking, a mixer circuit 50 having any type of input stage may be used.

[0069] Fig.12 Is used for operation Fig.11 Flowchart of illustrative steps of mixer circuit 50 of the type shown in FIG. During operation of block 210, DACa and DACb may be swept together (e.g., OSa and OSb may be swept in the same direction) to trim or minimize the DC mismatch between tail nodes Tp and Tm. Trimming DACa in series with DACb while keeping DACc and DACd fixed may trim OSa and OSb relative to OSc and OSd to calibrate or minimize first order LO feedthrough and other higher odd order LO feedthroughs.

[0070] During the operation of block 212, DACa and DACb may be swept in opposite directions while maintaining the same midamble from block 212 to trim the LO impedance at the tail node Tp at the LO frequency. The signal at the LO frequency is upconverted to the differential mode second harmonic frequency by the fundamental mixer gain, so trimming DACa and DACb may be used to trim the second harmonic ("2LO") feedthrough. Trimming DACa and DACb in opposite directions in this manner may tune the increments of (OSa relative to OSb) and (OSc relative to OSd) to calibrate or minimize 2LO feedthrough. The operation of block 212 may be said to be orthogonal or independent of the operation of block 210.

[0071] During operation of block 214, DACa and DACc may be swept in a first direction, while DACb and DACd may be swept in a second (opposite) direction, while maintaining the same offset increment established from block 212 to offset the DC level of signal LO+ relative to the DC level of signal LO-. This can help minimize IF (intermediate frequency) feedthrough in a transmit mixer where the input signal is in the IF band, RF feedthrough in a receive mixer where the input signal is in the RF band, and any blocker signal components at (2LO-IF). The operation of block 214 can be said to be orthogonal to the operation of block 212. Therefore, trimming the DACs in this manner to minimize the (2LO-IF) blocker signal can be said to be calibrating or minimizing the mixer second harmonic conversion gain. The control circuit 14 (see Figure 1 ), processing circuitry 18, logic or other controller to trim, adjust or calibrate these different DACs.

[0072] Fig.12The operations are exemplary. In some embodiments, DAC1 may be set equal to DAC3, and DAC2 may be set equal to DAC4, and these DACs may be trimmed to minimize the (2LO-IF) component. In other embodiments, DAC3 may be set equal to DAC4, and DAC1 may be scanned opposite to DAC2 to trim the 2LO feedthrough component. If necessary, the operation of box 212 may be performed before box 210. If necessary, the operation of box 214 may be performed before box 212 or before box 210. In some embodiments, one or more of the described operations may be modified, replaced, or omitted. In some embodiments, one or more of the described operations may be performed in parallel. In some embodiments, additional processes may be added or inserted between the described operations. If necessary, the order of certain operations may be reversed or changed, and / or the timing of the described operations may be adjusted so that they occur at slightly different times.

[0073] Combination of the above Figures 1 to 12 The methods and operations described may be performed by the components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuits or hardware). Software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more of the components of device 10 (e.g., a computer-readable storage medium). Figure 1 The software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include a drive, non-volatile memory such as non-volatile random access memory (NVRAM), a removable flash drive or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be executed by processing circuits on one or more of the components of device 10 (e.g., processing circuits in wireless communication circuit 24, Figure 1 The processing circuit may include a microprocessor, an application processor, a digital signal processor, a central processing unit (CPU), a dedicated integrated circuit with a processing circuit, or other processing circuits.

[0074] According to one embodiment, a mixer circuit is provided, which includes: a first mixer transistor, which is configured to receive a first oscillation signal and is coupled to a first tail node; a second mixer transistor, which is configured to receive a second oscillation signal and is coupled to the first tail node; a first digital-to-analog converter (DAC); and a second digital-to-analog converter (DAC), which is coupled between the first DAC and the first mixer transistor.

[0075] According to another embodiment, the second DAC includes a first output coupled to the gate terminal of the first mixer transistor and a second output coupled to the gate terminal of the second mixer transistor.

[0076] According to another embodiment, the mixer circuit includes: a first resistor, which is coupled between a first output terminal of a second DAC and a gate terminal of a first mixer transistor; and a second resistor, which is coupled between a second output terminal of the second DAC and a gate terminal of a second mixer transistor.

[0077] According to another embodiment, the mixer circuit includes: a third mixer transistor, which is configured to receive the first oscillation signal and coupled to the second tail node; a fourth mixer transistor, which is configured to receive the second oscillation signal and coupled to the second tail node; and a third digital-to-analog converter (DAC) coupled between the first DAC and the third mixer transistor.

[0078] According to another embodiment, the first DAC includes a first output terminal coupled to the second DAC and a second output terminal coupled to the third DAC.

[0079] According to another embodiment, the third DAC includes a first output coupled to the gate terminal of the third mixer transistor and a second output coupled to the gate terminal of the fourth mixer transistor.

[0080] According to another embodiment, the mixer circuit includes: a first resistor, which is coupled between a first output terminal of a third DAC and a gate terminal of a third mixer transistor; and a second resistor, which is coupled between a second output terminal of the third DAC and a gate terminal of a fourth mixer transistor.

[0081] According to another embodiment, the mixer circuit includes a transformer coupled to the first tail node and the second tail node.

[0082] According to another embodiment, the first mixer transistor has a drain terminal coupled to the first mixer output, the second mixer transistor has a drain terminal coupled to the second mixer output, the third mixer transistor has a drain terminal coupled to the first mixer output, and the fourth mixer transistor has a drain terminal coupled to the second mixer output.

[0083] According to another embodiment, the mixer circuit includes a control circuit configured to trim the first DAC during a first calibration phase, trim the second DAC during a second calibration phase after the first calibration phase, and trim the second DAC and the third DAC during a third calibration phase after the second calibration phase.

[0084] According to one embodiment, a mixer circuit is provided, the mixer circuit comprising: a first pair of transistors, the first pair of transistors coupled to a first tail node and having a first gate terminal configured to receive a local oscillator signal; a second pair of transistors, the second pair of transistors coupled to a second tail node and having a second gate terminal configured to receive the local oscillator signal; a first digital-to-analog converter (DAC); a second digital-to-analog converter (DAC), the second digital-to-analog converter (DAC), coupled between the first DAC and the first gate terminals of the first pair of transistors; and a third digital-to-analog converter (DAC), the third digital-to-analog converter (DAC), coupled between the first DAC and the second gate terminals of the second pair of transistors.

[0085] According to another embodiment, a mixer circuit includes a coil having a first terminal coupled to a first tail node and having a second terminal coupled to a second tail node.

[0086] According to another embodiment, the first DAC includes a first output terminal coupled to the second DAC and a second output terminal coupled to the third DAC.

[0087] According to another embodiment, the mixer circuit includes a control circuit configured to tune the first DAC during a first calibration phase, tune the second DAC during a second calibration phase after the first calibration phase, and tune the second DAC and the third DAC during a third calibration phase after the second calibration phase.

[0088] According to another embodiment, a mixer circuit includes a control circuit configured to trim a direct current (DC) mismatch between a first tail node and a second tail node by adjusting a first DAC, to trim an impedance at the first tail node by adjusting a second DAC, and to trim a DC level of a local oscillator signal by adjusting the second DAC together with a third DAC.

[0089] According to one embodiment, a method of operating a mixer circuit is provided, the method comprising: receiving a first oscillating signal at a gate terminal of a first mixer transistor; receiving a second oscillating signal at a gate terminal of a second mixer transistor, the first mixer transistor and the second mixer transistor being coupled to a first tail node; and receiving a bias voltage from a first digital-to-analog converter (DAC) with a second digital-to-analog converter (DAC), outputting a first bias voltage to a gate terminal of the first mixer transistor, and outputting a second bias voltage to a gate terminal of the second mixer transistor.

[0090] According to another embodiment, the method includes: receiving a first oscillating signal at a gate terminal of a third mixer transistor; receiving a second oscillating signal at a gate terminal of a fourth mixer transistor, the third mixer transistor and the fourth mixer transistor being coupled to a second tail node; and receiving another bias voltage from the first digital-to-analog converter (DAC) with a third digital-to-analog converter (DAC), outputting a third bias voltage to a gate terminal of the third mixer transistor, and outputting a fourth bias voltage to a gate terminal of the fourth mixer transistor.

[0091] According to another embodiment, the method includes trimming an offset of a first DAC during a first phase, trimming an offset of a second DAC relative to an offset of a third DAC during a second phase different from the first phase, and trimming an offset of the second DAC together with an offset of the third DAC during a third phase different from the second phase.

[0092] According to another embodiment, the method includes: during a first phase, trimming a direct current (DC) mismatch between a first tail node and a second tail node; during a second phase different from the first phase, trimming an impedance at the first tail node relative to an impedance at the second tail node; and during a third phase different from the second phase, trimming a DC level of the first oscillating signal relative to a DC level of the second oscillating signal.

[0093] According to another embodiment, the method includes: during a first phase, scanning a first DAC to trim a first-order local oscillator feedthrough; during a second phase different from the first phase, scanning a second DAC to trim a second-order local oscillator feedthrough; and during a third phase different from the second phase, scanning the second DAC and the third DAC to suppress a signal associated with a second harmonic gain of a mixer circuit.

[0094] The foregoing is exemplary and various modifications may be made to the embodiments described. The foregoing embodiments may be implemented independently or in any combination.

Claims

1. Mixer circuit, including: a first mixer transistor configured to receive a first oscillating signal and coupled to a first tail node; a second mixer transistor configured to receive a second oscillating signal and coupled to the first tail node; a first digital-to-analog converter (DAC); and A second digital-to-analog converter (DAC) is coupled between the first DAC and the first mixer transistor.

2. The mixer circuit according to claim 1, wherein the second DAC comprises: a first output terminal coupled to a gate terminal of the first mixer transistor; and A second output terminal is coupled to a gate terminal of the second mixer transistor.

3. The mixer circuit according to claim 2, further comprising: a first resistor coupled between the first output of the second DAC and the gate terminal of the first mixer transistor; and A second resistor is coupled between the second output of the second DAC and the gate terminal of the second mixer transistor.

4. The mixer circuit according to claim 1, further comprising: a third mixer transistor configured to receive the first oscillating signal and coupled to a second tail node; a fourth mixer transistor configured to receive the second oscillating signal and coupled to the second tail node; and A third digital-to-analog converter (DAC) is coupled between the first DAC and the third mixer transistor.

5. The mixer circuit according to claim 4, wherein the first DAC comprises: a first output terminal, the first output terminal being coupled to the second DAC; and A second output terminal is coupled to the third DAC.

6. The mixer circuit according to claim 4, wherein the third DAC comprises: a first output terminal coupled to a gate terminal of the third mixer transistor; and A second output terminal is coupled to a gate terminal of the fourth mixer transistor.

7. The mixer circuit according to claim 6, further comprising: a first resistor coupled between the first output of the third DAC and the gate terminal of the third mixer transistor; and A second resistor is coupled between the second output terminal of the third DAC and the gate terminal of the fourth mixer transistor.

8. The mixer circuit according to claim 4, further comprising: A transformer is coupled to the first tail node and the second tail node.

9. The mixer circuit according to claim 4, wherein: The first mixer transistor has a drain terminal coupled to a first mixer output; the second mixer transistor having a drain terminal coupled to a second mixer output; the third mixer transistor having a drain terminal coupled to the first mixer output; and The fourth mixer transistor has a drain terminal coupled to the second mixer output.

10. The mixer circuit according to claim 4, further comprising a control circuit, wherein the control circuit is configured to: trimming the first DAC during a first calibration phase; trimming the second DAC during a second calibration phase following the first calibration phase; and The second DAC and the third DAC are trimmed during a third calibration phase following the second calibration phase.

11. Mixer circuit, comprising: a first pair of transistors coupled to the first tail node and having first gate terminals configured to receive a local oscillator signal; a second pair of transistors coupled to the second tail node and having second gate terminals configured to receive the local oscillator signal; a first digital-to-analog converter (DAC); a second digital-to-analog converter (DAC) coupled between the first DAC and the first gate terminals of the first pair of transistors; and A third digital-to-analog converter (DAC) is coupled between the first DAC and the second gate terminals of the second pair of transistors.

12. The mixer circuit according to claim 11, further comprising: A coil has a first terminal coupled to the first tail node and has a second terminal coupled to the second tail node.

13. The mixer circuit of claim 11 , wherein the first DAC comprises: a first output terminal, the first output terminal being coupled to the second DAC; and A second output terminal is coupled to the third DAC.

14. The mixer circuit according to claim 11, further comprising a control circuit, wherein the control circuit is configured to: tuning the first DAC during a first calibration phase; tuning the second DAC during a second calibration phase following the first calibration phase; and The second DAC and the third DAC are tuned during a third calibration phase following the second calibration phase.

15. The mixer circuit according to claim 11, further comprising a control circuit, wherein the control circuit is configured to: trimming a direct current (DC) mismatch between the first tail node and the second tail node by adjusting the first DAC; trimming the impedance at the first tail node by adjusting the second DAC; and The DC level of the local oscillator signal is trimmed by adjusting the second DAC together with the third DAC.

16. A method of operating a mixer circuit, comprising: receiving a first oscillating signal at a gate terminal of a first mixer transistor; receiving a second oscillating signal at a gate terminal of a second mixer transistor, the first mixer transistor and the second mixer transistor being coupled to a first tail node; as well as With a second digital-to-analog converter (DAC), a bias voltage is received from the first digital-to-analog converter (DAC), a first bias voltage is output to the gate terminal of the first mixer transistor, and a second bias voltage is output to the gate terminal of the second mixer transistor.

17. The method according to claim 16, further comprising: receiving the first oscillating signal at a gate terminal of a third mixer transistor; receiving the second oscillating signal at a gate terminal of a fourth mixer transistor, the third mixer transistor and the fourth mixer transistor being coupled to a second tail node; as well as With a third digital-to-analog converter (DAC), another bias voltage is received from the first digital-to-analog converter (DAC), a third bias voltage is output to the gate terminal of the third mixer transistor, and a fourth bias voltage is output to the gate terminal of the fourth mixer transistor.

18. The method according to claim 17, further comprising: During a first phase, trimming an offset of the first DAC; trimming the offset of the second DAC relative to the offset of the third DAC during a second phase different from the first phase; as well as During a third phase different from the second phase, the offset of the second DAC is trimmed together with the offset of the third DAC.

19. The method according to claim 17, further comprising: During a first phase, a direct current (DC) mismatch between the first tail node and the second tail node is trimmed; trimming an impedance at the first tail node relative to an impedance at the second tail node during a second phase different from the first phase; as well as During a third phase different from the second phase, a DC level of the first oscillating signal is trimmed relative to a DC level of the second oscillating signal.

20. The method of claim 17, further comprising: During a first phase, scanning the first DAC to trim a first-order local oscillator feedthrough; During a second phase different from the first phase, scanning the second DAC to trim second-order local oscillator feedthrough; as well as During a third phase different from the second phase, the second DAC and the third DAC are scanned to suppress a signal associated with a second harmonic gain of the mixer circuit.

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